kernel/drivers/media/i2c/adv7604.c

   1 /*
   2  * adv7604 - Analog Devices ADV7604 video decoder driver
   3  *
   4  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
  24  *              Revision 2.5, June 2010
  25  * REF_02 - Analog devices, Register map documentation, Documentation of
  26  *              the register maps, Software manual, Rev. F, June 2010
  27  * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
  28  */
  29
  30 #include <linux/delay.h>
  31 #include <linux/gpio/consumer.h>
  32 #include <linux/i2c.h>
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/slab.h>
  36 #include <linux/v4l2-dv-timings.h>
  37 #include <linux/videodev2.h>
  38 #include <linux/workqueue.h>
  39
  40 #include <media/adv7604.h>
  41 #include <media/v4l2-ctrls.h>
  42 #include <media/v4l2-device.h>
  43 #include <media/v4l2-dv-timings.h>
  44 #include <media/v4l2-of.h>
  45
  46 static int debug;
  47 module_param(debug, int, 0644);
  48 MODULE_PARM_DESC(debug, "debug level (0-2)");
  49
  50 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
  51 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  52 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  53 MODULE_LICENSE("GPL");
  54
  55 /* ADV7604 system clock frequency */
  56 #define ADV76XX_FSC (28636360)
  57
  58 #define ADV76XX_RGB_OUT                                 (1 << 1)
  59
  60 #define ADV76XX_OP_FORMAT_SEL_8BIT                      (0 << 0)
  61 #define ADV7604_OP_FORMAT_SEL_10BIT                     (1 << 0)
  62 #define ADV76XX_OP_FORMAT_SEL_12BIT                     (2 << 0)
  63
  64 #define ADV76XX_OP_MODE_SEL_SDR_422                     (0 << 5)
  65 #define ADV7604_OP_MODE_SEL_DDR_422                     (1 << 5)
  66 #define ADV76XX_OP_MODE_SEL_SDR_444                     (2 << 5)
  67 #define ADV7604_OP_MODE_SEL_DDR_444                     (3 << 5)
  68 #define ADV76XX_OP_MODE_SEL_SDR_422_2X                  (4 << 5)
  69 #define ADV7604_OP_MODE_SEL_ADI_CM                      (5 << 5)
  70
  71 #define ADV76XX_OP_CH_SEL_GBR                           (0 << 5)
  72 #define ADV76XX_OP_CH_SEL_GRB                           (1 << 5)
  73 #define ADV76XX_OP_CH_SEL_BGR                           (2 << 5)
  74 #define ADV76XX_OP_CH_SEL_RGB                           (3 << 5)
  75 #define ADV76XX_OP_CH_SEL_BRG                           (4 << 5)
  76 #define ADV76XX_OP_CH_SEL_RBG                           (5 << 5)
  77
  78 #define ADV76XX_OP_SWAP_CB_CR                           (1 << 0)
  79
  80 enum adv76xx_type {
  81         ADV7604,
  82         ADV7611,
  83 };
  84
  85 struct adv76xx_reg_seq {
  86         unsigned int reg;
  87         u8 val;
  88 };
  89
  90 struct adv76xx_format_info {
  91         u32 code;
  92         u8 op_ch_sel;
  93         bool rgb_out;
  94         bool swap_cb_cr;
  95         u8 op_format_sel;
  96 };
  97
  98 struct adv76xx_chip_info {
  99         enum adv76xx_type type;
 100
 101         bool has_afe;
 102         unsigned int max_port;
 103         unsigned int num_dv_ports;
 104
 105         unsigned int edid_enable_reg;
 106         unsigned int edid_status_reg;
 107         unsigned int lcf_reg;
 108
 109         unsigned int cable_det_mask;
 110         unsigned int tdms_lock_mask;
 111         unsigned int fmt_change_digital_mask;
 112         unsigned int cp_csc;
 113
 114         const struct adv76xx_format_info *formats;
 115         unsigned int nformats;
 116
 117         void (*set_termination)(struct v4l2_subdev *sd, bool enable);
 118         void (*setup_irqs)(struct v4l2_subdev *sd);
 119         unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
 120         unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
 121
 122         /* 0 = AFE, 1 = HDMI */
 123         const struct adv76xx_reg_seq *recommended_settings[2];
 124         unsigned int num_recommended_settings[2];
 125
 126         unsigned long page_mask;
 127 };
 128
 129 /*
 130  **********************************************************************
 131  *
 132  *  Arrays with configuration parameters for the ADV7604
 133  *
 134  **********************************************************************
 135  */
 136
 137 struct adv76xx_state {
 138         const struct adv76xx_chip_info *info;
 139         struct adv76xx_platform_data pdata;
 140
 141         struct gpio_desc *hpd_gpio[4];
 142
 143         struct v4l2_subdev sd;
 144         struct media_pad pads[ADV76XX_PAD_MAX];
 145         unsigned int source_pad;
 146
 147         struct v4l2_ctrl_handler hdl;
 148
 149         enum adv76xx_pad selected_input;
 150
 151         struct v4l2_dv_timings timings;
 152         const struct adv76xx_format_info *format;
 153
 154         struct {
 155                 u8 edid[256];
 156                 u32 present;
 157                 unsigned blocks;
 158         } edid;
 159         u16 spa_port_a[2];
 160         struct v4l2_fract aspect_ratio;
 161         u32 rgb_quantization_range;
 162         struct workqueue_struct *work_queues;
 163         struct delayed_work delayed_work_enable_hotplug;
 164         bool restart_stdi_once;
 165
 166         /* i2c clients */
 167         struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
 168
 169         /* controls */
 170         struct v4l2_ctrl *detect_tx_5v_ctrl;
 171         struct v4l2_ctrl *analog_sampling_phase_ctrl;
 172         struct v4l2_ctrl *free_run_color_manual_ctrl;
 173         struct v4l2_ctrl *free_run_color_ctrl;
 174         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 175 };
 176
 177 static bool adv76xx_has_afe(struct adv76xx_state *state)
 178 {
 179         return state->info->has_afe;
 180 }
 181
 182 /* Supported CEA and DMT timings */
 183 static const struct v4l2_dv_timings adv76xx_timings[] = {
 184         V4L2_DV_BT_CEA_720X480P59_94,
 185         V4L2_DV_BT_CEA_720X576P50,
 186         V4L2_DV_BT_CEA_1280X720P24,
 187         V4L2_DV_BT_CEA_1280X720P25,
 188         V4L2_DV_BT_CEA_1280X720P50,
 189         V4L2_DV_BT_CEA_1280X720P60,
 190         V4L2_DV_BT_CEA_1920X1080P24,
 191         V4L2_DV_BT_CEA_1920X1080P25,
 192         V4L2_DV_BT_CEA_1920X1080P30,
 193         V4L2_DV_BT_CEA_1920X1080P50,
 194         V4L2_DV_BT_CEA_1920X1080P60,
 195
 196         /* sorted by DMT ID */
 197         V4L2_DV_BT_DMT_640X350P85,
 198         V4L2_DV_BT_DMT_640X400P85,
 199         V4L2_DV_BT_DMT_720X400P85,
 200         V4L2_DV_BT_DMT_640X480P60,
 201         V4L2_DV_BT_DMT_640X480P72,
 202         V4L2_DV_BT_DMT_640X480P75,
 203         V4L2_DV_BT_DMT_640X480P85,
 204         V4L2_DV_BT_DMT_800X600P56,
 205         V4L2_DV_BT_DMT_800X600P60,
 206         V4L2_DV_BT_DMT_800X600P72,
 207         V4L2_DV_BT_DMT_800X600P75,
 208         V4L2_DV_BT_DMT_800X600P85,
 209         V4L2_DV_BT_DMT_848X480P60,
 210         V4L2_DV_BT_DMT_1024X768P60,
 211         V4L2_DV_BT_DMT_1024X768P70,
 212         V4L2_DV_BT_DMT_1024X768P75,
 213         V4L2_DV_BT_DMT_1024X768P85,
 214         V4L2_DV_BT_DMT_1152X864P75,
 215         V4L2_DV_BT_DMT_1280X768P60_RB,
 216         V4L2_DV_BT_DMT_1280X768P60,
 217         V4L2_DV_BT_DMT_1280X768P75,
 218         V4L2_DV_BT_DMT_1280X768P85,
 219         V4L2_DV_BT_DMT_1280X800P60_RB,
 220         V4L2_DV_BT_DMT_1280X800P60,
 221         V4L2_DV_BT_DMT_1280X800P75,
 222         V4L2_DV_BT_DMT_1280X800P85,
 223         V4L2_DV_BT_DMT_1280X960P60,
 224         V4L2_DV_BT_DMT_1280X960P85,
 225         V4L2_DV_BT_DMT_1280X1024P60,
 226         V4L2_DV_BT_DMT_1280X1024P75,
 227         V4L2_DV_BT_DMT_1280X1024P85,
 228         V4L2_DV_BT_DMT_1360X768P60,
 229         V4L2_DV_BT_DMT_1400X1050P60_RB,
 230         V4L2_DV_BT_DMT_1400X1050P60,
 231         V4L2_DV_BT_DMT_1400X1050P75,
 232         V4L2_DV_BT_DMT_1400X1050P85,
 233         V4L2_DV_BT_DMT_1440X900P60_RB,
 234         V4L2_DV_BT_DMT_1440X900P60,
 235         V4L2_DV_BT_DMT_1600X1200P60,
 236         V4L2_DV_BT_DMT_1680X1050P60_RB,
 237         V4L2_DV_BT_DMT_1680X1050P60,
 238         V4L2_DV_BT_DMT_1792X1344P60,
 239         V4L2_DV_BT_DMT_1856X1392P60,
 240         V4L2_DV_BT_DMT_1920X1200P60_RB,
 241         V4L2_DV_BT_DMT_1366X768P60_RB,
 242         V4L2_DV_BT_DMT_1366X768P60,
 243         V4L2_DV_BT_DMT_1920X1080P60,
 244         { },
 245 };
 246
 247 struct adv76xx_video_standards {
 248         struct v4l2_dv_timings timings;
 249         u8 vid_std;
 250         u8 v_freq;
 251 };
 252
 253 /* sorted by number of lines */
 254 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
 255         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 256         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 257         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 258         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 259         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 260         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 261         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 262         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 263         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 264         /* TODO add 1920x1080P60_RB (CVT timing) */
 265         { },
 266 };
 267
 268 /* sorted by number of lines */
 269 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
 270         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 271         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 272         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 273         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 274         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 275         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 276         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 277         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 278         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 279         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 280         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 281         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 282         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 283         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 284         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 285         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 286         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 287         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 288         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 289         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 290         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 291         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 292         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 293         { },
 294 };
 295
 296 /* sorted by number of lines */
 297 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
 298         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 299         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 300         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 301         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 302         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 303         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 304         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 305         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 306         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 307         { },
 308 };
 309
 310 /* sorted by number of lines */
 311 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
 312         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 313         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 314         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 315         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 316         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 317         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 318         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 319         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 320         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 321         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 322         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 323         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 324         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 325         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 326         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 327         { },
 328 };
 329
 330 /* ----------------------------------------------------------------------- */
 331
 332 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
 333 {
 334         return container_of(sd, struct adv76xx_state, sd);
 335 }
 336
 337 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 338 {
 339         return V4L2_DV_BT_FRAME_WIDTH(t);
 340 }
 341
 342 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 343 {
 344         return V4L2_DV_BT_FRAME_HEIGHT(t);
 345 }
 346
 347 /* ----------------------------------------------------------------------- */
 348
 349 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
 350                 u8 command, bool check)
 351 {
 352         union i2c_smbus_data data;
 353
 354         if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 355                         I2C_SMBUS_READ, command,
 356                         I2C_SMBUS_BYTE_DATA, &data))
 357                 return data.byte;
 358         if (check)
 359                 v4l_err(client, "error reading %02x, %02x\n",
 360                                 client->addr, command);
 361         return -EIO;
 362 }
 363
 364 static s32 adv_smbus_read_byte_data(struct adv76xx_state *state,
 365                                     enum adv76xx_page page, u8 command)
 366 {
 367         return adv_smbus_read_byte_data_check(state->i2c_clients[page],
 368                                               command, true);
 369 }
 370
 371 static s32 adv_smbus_write_byte_data(struct adv76xx_state *state,
 372                                      enum adv76xx_page page, u8 command,
 373                                      u8 value)
 374 {
 375         struct i2c_client *client = state->i2c_clients[page];
 376         union i2c_smbus_data data;
 377         int err;
 378         int i;
 379
 380         data.byte = value;
 381         for (i = 0; i < 3; i++) {
 382                 err = i2c_smbus_xfer(client->adapter, client->addr,
 383                                 client->flags,
 384                                 I2C_SMBUS_WRITE, command,
 385                                 I2C_SMBUS_BYTE_DATA, &data);
 386                 if (!err)
 387                         break;
 388         }
 389         if (err < 0)
 390                 v4l_err(client, "error writing %02x, %02x, %02x\n",
 391                                 client->addr, command, value);
 392         return err;
 393 }
 394
 395 static s32 adv_smbus_write_i2c_block_data(struct adv76xx_state *state,
 396                                           enum adv76xx_page page, u8 command,
 397                                           unsigned length, const u8 *values)
 398 {
 399         struct i2c_client *client = state->i2c_clients[page];
 400         union i2c_smbus_data data;
 401
 402         if (length > I2C_SMBUS_BLOCK_MAX)
 403                 length = I2C_SMBUS_BLOCK_MAX;
 404         data.block[0] = length;
 405         memcpy(data.block + 1, values, length);
 406         return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 407                               I2C_SMBUS_WRITE, command,
 408                               I2C_SMBUS_I2C_BLOCK_DATA, &data);
 409 }
 410
 411 /* ----------------------------------------------------------------------- */
 412
 413 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 414 {
 415         struct adv76xx_state *state = to_state(sd);
 416
 417         return adv_smbus_read_byte_data(state, ADV76XX_PAGE_IO, reg);
 418 }
 419
 420 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 421 {
 422         struct adv76xx_state *state = to_state(sd);
 423
 424         return adv_smbus_write_byte_data(state, ADV76XX_PAGE_IO, reg, val);
 425 }
 426
 427 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 428 {
 429         return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
 430 }
 431
 432 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 433 {
 434         struct adv76xx_state *state = to_state(sd);
 435
 436         return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg);
 437 }
 438
 439 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 440 {
 441         struct adv76xx_state *state = to_state(sd);
 442
 443         return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val);
 444 }
 445
 446 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 447 {
 448         struct adv76xx_state *state = to_state(sd);
 449
 450         return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CEC, reg);
 451 }
 452
 453 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 454 {
 455         struct adv76xx_state *state = to_state(sd);
 456
 457         return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CEC, reg, val);
 458 }
 459
 460 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 461 {
 462         struct adv76xx_state *state = to_state(sd);
 463
 464         return adv_smbus_read_byte_data(state, ADV76XX_PAGE_INFOFRAME, reg);
 465 }
 466
 467 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 468 {
 469         struct adv76xx_state *state = to_state(sd);
 470
 471         return adv_smbus_write_byte_data(state, ADV76XX_PAGE_INFOFRAME,
 472                                          reg, val);
 473 }
 474
 475 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 476 {
 477         struct adv76xx_state *state = to_state(sd);
 478
 479         return adv_smbus_read_byte_data(state, ADV76XX_PAGE_AFE, reg);
 480 }
 481
 482 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 483 {
 484         struct adv76xx_state *state = to_state(sd);
 485
 486         return adv_smbus_write_byte_data(state, ADV76XX_PAGE_AFE, reg, val);
 487 }
 488
 489 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 490 {
 491         struct adv76xx_state *state = to_state(sd);
 492
 493         return adv_smbus_read_byte_data(state, ADV76XX_PAGE_REP, reg);
 494 }
 495
 496 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 497 {
 498         struct adv76xx_state *state = to_state(sd);
 499
 500         return adv_smbus_write_byte_data(state, ADV76XX_PAGE_REP, reg, val);
 501 }
 502
 503 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 504 {
 505         return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
 506 }
 507
 508 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 509 {
 510         struct adv76xx_state *state = to_state(sd);
 511
 512         return adv_smbus_read_byte_data(state, ADV76XX_PAGE_EDID, reg);
 513 }
 514
 515 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 516 {
 517         struct adv76xx_state *state = to_state(sd);
 518
 519         return adv_smbus_write_byte_data(state, ADV76XX_PAGE_EDID, reg, val);
 520 }
 521
 522 static inline int edid_write_block(struct v4l2_subdev *sd,
 523                                         unsigned len, const u8 *val)
 524 {
 525         struct adv76xx_state *state = to_state(sd);
 526         int err = 0;
 527         int i;
 528
 529         v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
 530
 531         for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
 532                 err = adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_EDID,
 533                                 i, I2C_SMBUS_BLOCK_MAX, val + i);
 534         return err;
 535 }
 536
 537 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
 538 {
 539         unsigned int i;
 540
 541         for (i = 0; i < state->info->num_dv_ports; ++i)
 542                 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
 543
 544         v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
 545 }
 546
 547 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
 548 {
 549         struct delayed_work *dwork = to_delayed_work(work);
 550         struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
 551                                                 delayed_work_enable_hotplug);
 552         struct v4l2_subdev *sd = &state->sd;
 553
 554         v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
 555
 556         adv76xx_set_hpd(state, state->edid.present);
 557 }
 558
 559 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 560 {
 561         struct adv76xx_state *state = to_state(sd);
 562
 563         return adv_smbus_read_byte_data(state, ADV76XX_PAGE_HDMI, reg);
 564 }
 565
 566 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
 567 {
 568         return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
 569 }
 570
 571 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 572 {
 573         struct adv76xx_state *state = to_state(sd);
 574
 575         return adv_smbus_write_byte_data(state, ADV76XX_PAGE_HDMI, reg, val);
 576 }
 577
 578 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 579 {
 580         return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
 581 }
 582
 583 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 584 {
 585         struct adv76xx_state *state = to_state(sd);
 586
 587         return adv_smbus_write_byte_data(state, ADV76XX_PAGE_TEST, reg, val);
 588 }
 589
 590 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 591 {
 592         struct adv76xx_state *state = to_state(sd);
 593
 594         return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CP, reg);
 595 }
 596
 597 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
 598 {
 599         return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
 600 }
 601
 602 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 603 {
 604         struct adv76xx_state *state = to_state(sd);
 605
 606         return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CP, reg, val);
 607 }
 608
 609 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 610 {
 611         return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
 612 }
 613
 614 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 615 {
 616         struct adv76xx_state *state = to_state(sd);
 617
 618         return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg);
 619 }
 620
 621 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 622 {
 623         struct adv76xx_state *state = to_state(sd);
 624
 625         return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val);
 626 }
 627
 628 #define ADV76XX_REG(page, offset)       (((page) << 8) | (offset))
 629 #define ADV76XX_REG_SEQ_TERM            0xffff
 630
 631 #ifdef CONFIG_VIDEO_ADV_DEBUG
 632 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
 633 {
 634         struct adv76xx_state *state = to_state(sd);
 635         unsigned int page = reg >> 8;
 636
 637         if (!(BIT(page) & state->info->page_mask))
 638                 return -EINVAL;
 639
 640         reg &= 0xff;
 641
 642         return adv_smbus_read_byte_data(state, page, reg);
 643 }
 644 #endif
 645
 646 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
 647 {
 648         struct adv76xx_state *state = to_state(sd);
 649         unsigned int page = reg >> 8;
 650
 651         if (!(BIT(page) & state->info->page_mask))
 652                 return -EINVAL;
 653
 654         reg &= 0xff;
 655
 656         return adv_smbus_write_byte_data(state, page, reg, val);
 657 }
 658
 659 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
 660                                   const struct adv76xx_reg_seq *reg_seq)
 661 {
 662         unsigned int i;
 663
 664         for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
 665                 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
 666 }
 667
 668 /* -----------------------------------------------------------------------------
 669  * Format helpers
 670  */
 671
 672 static const struct adv76xx_format_info adv7604_formats[] = {
 673         { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
 674           ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
 675         { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
 676           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 677         { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
 678           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 679         { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
 680           ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
 681         { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
 682           ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
 683         { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
 684           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 685         { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
 686           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 687         { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
 688           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 689         { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
 690           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 691         { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
 692           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 693         { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
 694           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 695         { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
 696           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 697         { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
 698           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 699         { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
 700           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 701         { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
 702           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 703         { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
 704           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 705         { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
 706           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 707         { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
 708           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 709         { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
 710           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 711 };
 712
 713 static const struct adv76xx_format_info adv7611_formats[] = {
 714         { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
 715           ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
 716         { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
 717           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 718         { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
 719           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 720         { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
 721           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 722         { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
 723           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 724         { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
 725           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 726         { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
 727           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 728         { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
 729           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 730         { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
 731           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 732         { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
 733           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 734         { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
 735           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 736         { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
 737           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 738         { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
 739           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 740 };
 741
 742 static const struct adv76xx_format_info *
 743 adv76xx_format_info(struct adv76xx_state *state, u32 code)
 744 {
 745         unsigned int i;
 746
 747         for (i = 0; i < state->info->nformats; ++i) {
 748                 if (state->info->formats[i].code == code)
 749                         return &state->info->formats[i];
 750         }
 751
 752         return NULL;
 753 }
 754
 755 /* ----------------------------------------------------------------------- */
 756
 757 static inline bool is_analog_input(struct v4l2_subdev *sd)
 758 {
 759         struct adv76xx_state *state = to_state(sd);
 760
 761         return state->selected_input == ADV7604_PAD_VGA_RGB ||
 762                state->selected_input == ADV7604_PAD_VGA_COMP;
 763 }
 764
 765 static inline bool is_digital_input(struct v4l2_subdev *sd)
 766 {
 767         struct adv76xx_state *state = to_state(sd);
 768
 769         return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
 770                state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
 771                state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
 772                state->selected_input == ADV7604_PAD_HDMI_PORT_D;
 773 }
 774
 775 /* ----------------------------------------------------------------------- */
 776
 777 #ifdef CONFIG_VIDEO_ADV_DEBUG
 778 static void adv76xx_inv_register(struct v4l2_subdev *sd)
 779 {
 780         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 781         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 782         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 783         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 784         v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
 785         v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
 786         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 787         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 788         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 789         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 790         v4l2_info(sd, "0xa00-0xaff: Test Map\n");
 791         v4l2_info(sd, "0xb00-0xbff: CP Map\n");
 792         v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
 793 }
 794
 795 static int adv76xx_g_register(struct v4l2_subdev *sd,
 796                                         struct v4l2_dbg_register *reg)
 797 {
 798         int ret;
 799
 800         ret = adv76xx_read_reg(sd, reg->reg);
 801         if (ret < 0) {
 802                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 803                 adv76xx_inv_register(sd);
 804                 return ret;
 805         }
 806
 807         reg->size = 1;
 808         reg->val = ret;
 809
 810         return 0;
 811 }
 812
 813 static int adv76xx_s_register(struct v4l2_subdev *sd,
 814                                         const struct v4l2_dbg_register *reg)
 815 {
 816         int ret;
 817
 818         ret = adv76xx_write_reg(sd, reg->reg, reg->val);
 819         if (ret < 0) {
 820                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 821                 adv76xx_inv_register(sd);
 822                 return ret;
 823         }
 824
 825         return 0;
 826 }
 827 #endif
 828
 829 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
 830 {
 831         u8 value = io_read(sd, 0x6f);
 832
 833         return ((value & 0x10) >> 4)
 834              | ((value & 0x08) >> 2)
 835              | ((value & 0x04) << 0)
 836              | ((value & 0x02) << 2);
 837 }
 838
 839 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
 840 {
 841         u8 value = io_read(sd, 0x6f);
 842
 843         return value & 1;
 844 }
 845
 846 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 847 {
 848         struct adv76xx_state *state = to_state(sd);
 849         const struct adv76xx_chip_info *info = state->info;
 850
 851         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
 852                                 info->read_cable_det(sd));
 853 }
 854
 855 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 856                 u8 prim_mode,
 857                 const struct adv76xx_video_standards *predef_vid_timings,
 858                 const struct v4l2_dv_timings *timings)
 859 {
 860         int i;
 861
 862         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 863                 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
 864                                         is_digital_input(sd) ? 250000 : 1000000))
 865                         continue;
 866                 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
 867                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
 868                                 prim_mode); /* v_freq and prim mode */
 869                 return 0;
 870         }
 871
 872         return -1;
 873 }
 874
 875 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 876                 struct v4l2_dv_timings *timings)
 877 {
 878         struct adv76xx_state *state = to_state(sd);
 879         int err;
 880
 881         v4l2_dbg(1, debug, sd, "%s", __func__);
 882
 883         if (adv76xx_has_afe(state)) {
 884                 /* reset to default values */
 885                 io_write(sd, 0x16, 0x43);
 886                 io_write(sd, 0x17, 0x5a);
 887         }
 888         /* disable embedded syncs for auto graphics mode */
 889         cp_write_clr_set(sd, 0x81, 0x10, 0x00);
 890         cp_write(sd, 0x8f, 0x00);
 891         cp_write(sd, 0x90, 0x00);
 892         cp_write(sd, 0xa2, 0x00);
 893         cp_write(sd, 0xa3, 0x00);
 894         cp_write(sd, 0xa4, 0x00);
 895         cp_write(sd, 0xa5, 0x00);
 896         cp_write(sd, 0xa6, 0x00);
 897         cp_write(sd, 0xa7, 0x00);
 898         cp_write(sd, 0xab, 0x00);
 899         cp_write(sd, 0xac, 0x00);
 900
 901         if (is_analog_input(sd)) {
 902                 err = find_and_set_predefined_video_timings(sd,
 903                                 0x01, adv7604_prim_mode_comp, timings);
 904                 if (err)
 905                         err = find_and_set_predefined_video_timings(sd,
 906                                         0x02, adv7604_prim_mode_gr, timings);
 907         } else if (is_digital_input(sd)) {
 908                 err = find_and_set_predefined_video_timings(sd,
 909                                 0x05, adv76xx_prim_mode_hdmi_comp, timings);
 910                 if (err)
 911                         err = find_and_set_predefined_video_timings(sd,
 912                                         0x06, adv76xx_prim_mode_hdmi_gr, timings);
 913         } else {
 914                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 915                                 __func__, state->selected_input);
 916                 err = -1;
 917         }
 918
 919
 920         return err;
 921 }
 922
 923 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 924                 const struct v4l2_bt_timings *bt)
 925 {
 926         struct adv76xx_state *state = to_state(sd);
 927         u32 width = htotal(bt);
 928         u32 height = vtotal(bt);
 929         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 930         u16 cp_start_eav = width - bt->hfrontporch;
 931         u16 cp_start_vbi = height - bt->vfrontporch;
 932         u16 cp_end_vbi = bt->vsync + bt->vbackporch;
 933         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 934                 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 935         const u8 pll[2] = {
 936                 0xc0 | ((width >> 8) & 0x1f),
 937                 width & 0xff
 938         };
 939
 940         v4l2_dbg(2, debug, sd, "%s\n", __func__);
 941
 942         if (is_analog_input(sd)) {
 943                 /* auto graphics */
 944                 io_write(sd, 0x00, 0x07); /* video std */
 945                 io_write(sd, 0x01, 0x02); /* prim mode */
 946                 /* enable embedded syncs for auto graphics mode */
 947                 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
 948
 949                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
 950                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
 951                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
 952                 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_IO,
 953                                                    0x16, 2, pll))
 954                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
 955
 956                 /* active video - horizontal timing */
 957                 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
 958                 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
 959                                    ((cp_start_eav >> 8) & 0x0f));
 960                 cp_write(sd, 0xa4, cp_start_eav & 0xff);
 961
 962                 /* active video - vertical timing */
 963                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
 964                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
 965                                    ((cp_end_vbi >> 8) & 0xf));
 966                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
 967         } else if (is_digital_input(sd)) {
 968                 /* set default prim_mode/vid_std for HDMI
 969                    according to [REF_03, c. 4.2] */
 970                 io_write(sd, 0x00, 0x02); /* video std */
 971                 io_write(sd, 0x01, 0x06); /* prim mode */
 972         } else {
 973                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 974                                 __func__, state->selected_input);
 975         }
 976
 977         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
 978         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
 979         cp_write(sd, 0xab, (height >> 4) & 0xff);
 980         cp_write(sd, 0xac, (height & 0x0f) << 4);
 981 }
 982
 983 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
 984 {
 985         struct adv76xx_state *state = to_state(sd);
 986         u8 offset_buf[4];
 987
 988         if (auto_offset) {
 989                 offset_a = 0x3ff;
 990                 offset_b = 0x3ff;
 991                 offset_c = 0x3ff;
 992         }
 993
 994         v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
 995                         __func__, auto_offset ? "Auto" : "Manual",
 996                         offset_a, offset_b, offset_c);
 997
 998         offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
 999         offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1000         offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1001         offset_buf[3] = offset_c & 0x0ff;
1002
1003         /* Registers must be written in this order with no i2c access in between */
1004         if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP,
1005                                            0x77, 4, offset_buf))
1006                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1007 }
1008
1009 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1010 {
1011         struct adv76xx_state *state = to_state(sd);
1012         u8 gain_buf[4];
1013         u8 gain_man = 1;
1014         u8 agc_mode_man = 1;
1015
1016         if (auto_gain) {
1017                 gain_man = 0;
1018                 agc_mode_man = 0;
1019                 gain_a = 0x100;
1020                 gain_b = 0x100;
1021                 gain_c = 0x100;
1022         }
1023
1024         v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1025                         __func__, auto_gain ? "Auto" : "Manual",
1026                         gain_a, gain_b, gain_c);
1027
1028         gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1029         gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1030         gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1031         gain_buf[3] = ((gain_c & 0x0ff));
1032
1033         /* Registers must be written in this order with no i2c access in between */
1034         if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP,
1035                                            0x73, 4, gain_buf))
1036                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1037 }
1038
1039 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1040 {
1041         struct adv76xx_state *state = to_state(sd);
1042         bool rgb_output = io_read(sd, 0x02) & 0x02;
1043         bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1044
1045         v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1046                         __func__, state->rgb_quantization_range,
1047                         rgb_output, hdmi_signal);
1048
1049         adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1050         adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1051
1052         switch (state->rgb_quantization_range) {
1053         case V4L2_DV_RGB_RANGE_AUTO:
1054                 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1055                         /* Receiving analog RGB signal
1056                          * Set RGB full range (0-255) */
1057                         io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1058                         break;
1059                 }
1060
1061                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1062                         /* Receiving analog YPbPr signal
1063                          * Set automode */
1064                         io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1065                         break;
1066                 }
1067
1068                 if (hdmi_signal) {
1069                         /* Receiving HDMI signal
1070                          * Set automode */
1071                         io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1072                         break;
1073                 }
1074
1075                 /* Receiving DVI-D signal
1076                  * ADV7604 selects RGB limited range regardless of
1077                  * input format (CE/IT) in automatic mode */
1078                 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1079                         /* RGB limited range (16-235) */
1080                         io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1081                 } else {
1082                         /* RGB full range (0-255) */
1083                         io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1084
1085                         if (is_digital_input(sd) && rgb_output) {
1086                                 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1087                         } else {
1088                                 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1089                                 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1090                         }
1091                 }
1092                 break;
1093         case V4L2_DV_RGB_RANGE_LIMITED:
1094                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1095                         /* YCrCb limited range (16-235) */
1096                         io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1097                         break;
1098                 }
1099
1100                 /* RGB limited range (16-235) */
1101                 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1102
1103                 break;
1104         case V4L2_DV_RGB_RANGE_FULL:
1105                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1106                         /* YCrCb full range (0-255) */
1107                         io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1108                         break;
1109                 }
1110
1111                 /* RGB full range (0-255) */
1112                 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1113
1114                 if (is_analog_input(sd) || hdmi_signal)
1115                         break;
1116
1117                 /* Adjust gain/offset for DVI-D signals only */
1118                 if (rgb_output) {
1119                         adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1120                 } else {
1121                         adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1122                         adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1123                 }
1124                 break;
1125         }
1126 }
1127
1128 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
1129 {
1130         struct v4l2_subdev *sd =
1131                 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1132
1133         struct adv76xx_state *state = to_state(sd);
1134
1135         switch (ctrl->id) {
1136         case V4L2_CID_BRIGHTNESS:
1137                 cp_write(sd, 0x3c, ctrl->val);
1138                 return 0;
1139         case V4L2_CID_CONTRAST:
1140                 cp_write(sd, 0x3a, ctrl->val);
1141                 return 0;
1142         case V4L2_CID_SATURATION:
1143                 cp_write(sd, 0x3b, ctrl->val);
1144                 return 0;
1145         case V4L2_CID_HUE:
1146                 cp_write(sd, 0x3d, ctrl->val);
1147                 return 0;
1148         case  V4L2_CID_DV_RX_RGB_RANGE:
1149                 state->rgb_quantization_range = ctrl->val;
1150                 set_rgb_quantization_range(sd);
1151                 return 0;
1152         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1153                 if (!adv76xx_has_afe(state))
1154                         return -EINVAL;
1155                 /* Set the analog sampling phase. This is needed to find the
1156                    best sampling phase for analog video: an application or
1157                    driver has to try a number of phases and analyze the picture
1158                    quality before settling on the best performing phase. */
1159                 afe_write(sd, 0xc8, ctrl->val);
1160                 return 0;
1161         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1162                 /* Use the default blue color for free running mode,
1163                    or supply your own. */
1164                 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1165                 return 0;
1166         case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1167                 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1168                 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1169                 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1170                 return 0;
1171         }
1172         return -EINVAL;
1173 }
1174
1175 /* ----------------------------------------------------------------------- */
1176
1177 static inline bool no_power(struct v4l2_subdev *sd)
1178 {
1179         /* Entire chip or CP powered off */
1180         return io_read(sd, 0x0c) & 0x24;
1181 }
1182
1183 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1184 {
1185         struct adv76xx_state *state = to_state(sd);
1186
1187         return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1188 }
1189
1190 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1191 {
1192         struct adv76xx_state *state = to_state(sd);
1193         const struct adv76xx_chip_info *info = state->info;
1194
1195         return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1196 }
1197
1198 static inline bool is_hdmi(struct v4l2_subdev *sd)
1199 {
1200         return hdmi_read(sd, 0x05) & 0x80;
1201 }
1202
1203 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1204 {
1205         struct adv76xx_state *state = to_state(sd);
1206
1207         /*
1208          * Chips without a AFE don't expose registers for the SSPD, so just assume
1209          * that we have a lock.
1210          */
1211         if (adv76xx_has_afe(state))
1212                 return false;
1213
1214         /* TODO channel 2 */
1215         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1216 }
1217
1218 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1219 {
1220         /* TODO channel 2 */
1221         return !(cp_read(sd, 0xb1) & 0x80);
1222 }
1223
1224 static inline bool no_signal(struct v4l2_subdev *sd)
1225 {
1226         bool ret;
1227
1228         ret = no_power(sd);
1229
1230         ret |= no_lock_stdi(sd);
1231         ret |= no_lock_sspd(sd);
1232
1233         if (is_digital_input(sd)) {
1234                 ret |= no_lock_tmds(sd);
1235                 ret |= no_signal_tmds(sd);
1236         }
1237
1238         return ret;
1239 }
1240
1241 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1242 {
1243         struct adv76xx_state *state = to_state(sd);
1244
1245         if (!adv76xx_has_afe(state))
1246                 return false;
1247
1248         /* CP has detected a non standard number of lines on the incoming
1249            video compared to what it is configured to receive by s_dv_timings */
1250         return io_read(sd, 0x12) & 0x01;
1251 }
1252
1253 static inline bool in_free_run(struct v4l2_subdev *sd)
1254 {
1255         return cp_read(sd, 0xff) & 0x10;
1256 }
1257
1258 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1259 {
1260         *status = 0;
1261         *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1262         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1263         if (!in_free_run(sd) && no_lock_cp(sd))
1264                 *status |= is_digital_input(sd) ?
1265                            V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1266
1267         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1268
1269         return 0;
1270 }
1271
1272 /* ----------------------------------------------------------------------- */
1273
1274 struct stdi_readback {
1275         u16 bl, lcf, lcvs;
1276         u8 hs_pol, vs_pol;
1277         bool interlaced;
1278 };
1279
1280 static int stdi2dv_timings(struct v4l2_subdev *sd,
1281                 struct stdi_readback *stdi,
1282                 struct v4l2_dv_timings *timings)
1283 {
1284         struct adv76xx_state *state = to_state(sd);
1285         u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
1286         u32 pix_clk;
1287         int i;
1288
1289         for (i = 0; adv76xx_timings[i].bt.height; i++) {
1290                 if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1)
1291                         continue;
1292                 if (adv76xx_timings[i].bt.vsync != stdi->lcvs)
1293                         continue;
1294
1295                 pix_clk = hfreq * htotal(&adv76xx_timings[i].bt);
1296
1297                 if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) &&
1298                     (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) {
1299                         *timings = adv76xx_timings[i];
1300                         return 0;
1301                 }
1302         }
1303
1304         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1305                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1306                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1307                         timings))
1308                 return 0;
1309         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1310                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1311                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1312                         state->aspect_ratio, timings))
1313                 return 0;
1314
1315         v4l2_dbg(2, debug, sd,
1316                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1317                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1318                 stdi->hs_pol, stdi->vs_pol);
1319         return -1;
1320 }
1321
1322
1323 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1324 {
1325         struct adv76xx_state *state = to_state(sd);
1326         const struct adv76xx_chip_info *info = state->info;
1327         u8 polarity;
1328
1329         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1330                 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1331                 return -1;
1332         }
1333
1334         /* read STDI */
1335         stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1336         stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1337         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1338         stdi->interlaced = io_read(sd, 0x12) & 0x10;
1339
1340         if (adv76xx_has_afe(state)) {
1341                 /* read SSPD */
1342                 polarity = cp_read(sd, 0xb5);
1343                 if ((polarity & 0x03) == 0x01) {
1344                         stdi->hs_pol = polarity & 0x10
1345                                      ? (polarity & 0x08 ? '+' : '-') : 'x';
1346                         stdi->vs_pol = polarity & 0x40
1347                                      ? (polarity & 0x20 ? '+' : '-') : 'x';
1348                 } else {
1349                         stdi->hs_pol = 'x';
1350                         stdi->vs_pol = 'x';
1351                 }
1352         } else {
1353                 polarity = hdmi_read(sd, 0x05);
1354                 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1355                 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1356         }
1357
1358         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1359                 v4l2_dbg(2, debug, sd,
1360                         "%s: signal lost during readout of STDI/SSPD\n", __func__);
1361                 return -1;
1362         }
1363
1364         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1365                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1366                 memset(stdi, 0, sizeof(struct stdi_readback));
1367                 return -1;
1368         }
1369
1370         v4l2_dbg(2, debug, sd,
1371                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1372                 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1373                 stdi->hs_pol, stdi->vs_pol,
1374                 stdi->interlaced ? "interlaced" : "progressive");
1375
1376         return 0;
1377 }
1378
1379 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1380                         struct v4l2_enum_dv_timings *timings)
1381 {
1382         struct adv76xx_state *state = to_state(sd);
1383
1384         if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1)
1385                 return -EINVAL;
1386
1387         if (timings->pad >= state->source_pad)
1388                 return -EINVAL;
1389
1390         memset(timings->reserved, 0, sizeof(timings->reserved));
1391         timings->timings = adv76xx_timings[timings->index];
1392         return 0;
1393 }
1394
1395 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1396                         struct v4l2_dv_timings_cap *cap)
1397 {
1398         struct adv76xx_state *state = to_state(sd);
1399
1400         if (cap->pad >= state->source_pad)
1401                 return -EINVAL;
1402
1403         cap->type = V4L2_DV_BT_656_1120;
1404         cap->bt.max_width = 1920;
1405         cap->bt.max_height = 1200;
1406         cap->bt.min_pixelclock = 25000000;
1407
1408         switch (cap->pad) {
1409         case ADV76XX_PAD_HDMI_PORT_A:
1410         case ADV7604_PAD_HDMI_PORT_B:
1411         case ADV7604_PAD_HDMI_PORT_C:
1412         case ADV7604_PAD_HDMI_PORT_D:
1413                 cap->bt.max_pixelclock = 225000000;
1414                 break;
1415         case ADV7604_PAD_VGA_RGB:
1416         case ADV7604_PAD_VGA_COMP:
1417         default:
1418                 cap->bt.max_pixelclock = 170000000;
1419                 break;
1420         }
1421
1422         cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1423                          V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1424         cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1425                 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1426         return 0;
1427 }
1428
1429 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1430    if the format is listed in adv76xx_timings[] */
1431 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1432                 struct v4l2_dv_timings *timings)
1433 {
1434         int i;
1435
1436         for (i = 0; adv76xx_timings[i].bt.width; i++) {
1437                 if (v4l2_match_dv_timings(timings, &adv76xx_timings[i],
1438                                         is_digital_input(sd) ? 250000 : 1000000)) {
1439                         *timings = adv76xx_timings[i];
1440                         break;
1441                 }
1442         }
1443 }
1444
1445 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1446 {
1447         unsigned int freq;
1448         int a, b;
1449
1450         a = hdmi_read(sd, 0x06);
1451         b = hdmi_read(sd, 0x3b);
1452         if (a < 0 || b < 0)
1453                 return 0;
1454         freq =  a * 1000000 + ((b & 0x30) >> 4) * 250000;
1455
1456         if (is_hdmi(sd)) {
1457                 /* adjust for deep color mode */
1458                 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1459
1460                 freq = freq * 8 / bits_per_channel;
1461         }
1462
1463         return freq;
1464 }
1465
1466 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1467 {
1468         int a, b;
1469
1470         a = hdmi_read(sd, 0x51);
1471         b = hdmi_read(sd, 0x52);
1472         if (a < 0 || b < 0)
1473                 return 0;
1474         return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1475 }
1476
1477 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
1478                         struct v4l2_dv_timings *timings)
1479 {
1480         struct adv76xx_state *state = to_state(sd);
1481         const struct adv76xx_chip_info *info = state->info;
1482         struct v4l2_bt_timings *bt = &timings->bt;
1483         struct stdi_readback stdi;
1484
1485         if (!timings)
1486                 return -EINVAL;
1487
1488         memset(timings, 0, sizeof(struct v4l2_dv_timings));
1489
1490         if (no_signal(sd)) {
1491                 state->restart_stdi_once = true;
1492                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1493                 return -ENOLINK;
1494         }
1495
1496         /* read STDI */
1497         if (read_stdi(sd, &stdi)) {
1498                 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1499                 return -ENOLINK;
1500         }
1501         bt->interlaced = stdi.interlaced ?
1502                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1503
1504         if (is_digital_input(sd)) {
1505                 timings->type = V4L2_DV_BT_656_1120;
1506
1507                 /* FIXME: All masks are incorrect for ADV7611 */
1508                 bt->width = hdmi_read16(sd, 0x07, 0xfff);
1509                 bt->height = hdmi_read16(sd, 0x09, 0xfff);
1510                 bt->pixelclock = info->read_hdmi_pixelclock(sd);
1511                 bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff);
1512                 bt->hsync = hdmi_read16(sd, 0x22, 0x3ff);
1513                 bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff);
1514                 bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2;
1515                 bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2;
1516                 bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2;
1517                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1518                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1519                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1520                         bt->height += hdmi_read16(sd, 0x0b, 0xfff);
1521                         bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2;
1522                         bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2;
1523                         bt->il_vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2;
1524                 }
1525                 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1526         } else {
1527                 /* find format
1528                  * Since LCVS values are inaccurate [REF_03, p. 275-276],
1529                  * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1530                  */
1531                 if (!stdi2dv_timings(sd, &stdi, timings))
1532                         goto found;
1533                 stdi.lcvs += 1;
1534                 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1535                 if (!stdi2dv_timings(sd, &stdi, timings))
1536                         goto found;
1537                 stdi.lcvs -= 2;
1538                 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1539                 if (stdi2dv_timings(sd, &stdi, timings)) {
1540                         /*
1541                          * The STDI block may measure wrong values, especially
1542                          * for lcvs and lcf. If the driver can not find any
1543                          * valid timing, the STDI block is restarted to measure
1544                          * the video timings again. The function will return an
1545                          * error, but the restart of STDI will generate a new
1546                          * STDI interrupt and the format detection process will
1547                          * restart.
1548                          */
1549                         if (state->restart_stdi_once) {
1550                                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1551                                 /* TODO restart STDI for Sync Channel 2 */
1552                                 /* enter one-shot mode */
1553                                 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1554                                 /* trigger STDI restart */
1555                                 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1556                                 /* reset to continuous mode */
1557                                 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1558                                 state->restart_stdi_once = false;
1559                                 return -ENOLINK;
1560                         }
1561                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1562                         return -ERANGE;
1563                 }
1564                 state->restart_stdi_once = true;
1565         }
1566 found:
1567
1568         if (no_signal(sd)) {
1569                 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1570                 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1571                 return -ENOLINK;
1572         }
1573
1574         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1575                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1576                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1577                                 __func__, (u32)bt->pixelclock);
1578                 return -ERANGE;
1579         }
1580
1581         if (debug > 1)
1582                 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1583                                       timings, true);
1584
1585         return 0;
1586 }
1587
1588 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
1589                 struct v4l2_dv_timings *timings)
1590 {
1591         struct adv76xx_state *state = to_state(sd);
1592         struct v4l2_bt_timings *bt;
1593         int err;
1594
1595         if (!timings)
1596                 return -EINVAL;
1597
1598         if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1599                 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1600                 return 0;
1601         }
1602
1603         bt = &timings->bt;
1604
1605         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1606                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1607                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1608                                 __func__, (u32)bt->pixelclock);
1609                 return -ERANGE;
1610         }
1611
1612         adv76xx_fill_optional_dv_timings_fields(sd, timings);
1613
1614         state->timings = *timings;
1615
1616         cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1617
1618         /* Use prim_mode and vid_std when available */
1619         err = configure_predefined_video_timings(sd, timings);
1620         if (err) {
1621                 /* custom settings when the video format
1622                  does not have prim_mode/vid_std */
1623                 configure_custom_video_timings(sd, bt);
1624         }
1625
1626         set_rgb_quantization_range(sd);
1627
1628         if (debug > 1)
1629                 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1630                                       timings, true);
1631         return 0;
1632 }
1633
1634 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
1635                 struct v4l2_dv_timings *timings)
1636 {
1637         struct adv76xx_state *state = to_state(sd);
1638
1639         *timings = state->timings;
1640         return 0;
1641 }
1642
1643 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1644 {
1645         hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1646 }
1647
1648 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1649 {
1650         hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1651 }
1652
1653 static void enable_input(struct v4l2_subdev *sd)
1654 {
1655         struct adv76xx_state *state = to_state(sd);
1656
1657         if (is_analog_input(sd)) {
1658                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1659         } else if (is_digital_input(sd)) {
1660                 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1661                 state->info->set_termination(sd, true);
1662                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1663                 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1664         } else {
1665                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1666                                 __func__, state->selected_input);
1667         }
1668 }
1669
1670 static void disable_input(struct v4l2_subdev *sd)
1671 {
1672         struct adv76xx_state *state = to_state(sd);
1673
1674         hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1675         msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1676         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1677         state->info->set_termination(sd, false);
1678 }
1679
1680 static void select_input(struct v4l2_subdev *sd)
1681 {
1682         struct adv76xx_state *state = to_state(sd);
1683         const struct adv76xx_chip_info *info = state->info;
1684
1685         if (is_analog_input(sd)) {
1686                 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1687
1688                 afe_write(sd, 0x00, 0x08); /* power up ADC */
1689                 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1690                 afe_write(sd, 0xc8, 0x00); /* phase control */
1691         } else if (is_digital_input(sd)) {
1692                 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1693
1694                 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1695
1696                 if (adv76xx_has_afe(state)) {
1697                         afe_write(sd, 0x00, 0xff); /* power down ADC */
1698                         afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1699                         afe_write(sd, 0xc8, 0x40); /* phase control */
1700                 }
1701
1702                 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1703                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1704                 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1705         } else {
1706                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1707                                 __func__, state->selected_input);
1708         }
1709 }
1710
1711 static int adv76xx_s_routing(struct v4l2_subdev *sd,
1712                 u32 input, u32 output, u32 config)
1713 {
1714         struct adv76xx_state *state = to_state(sd);
1715
1716         v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1717                         __func__, input, state->selected_input);
1718
1719         if (input == state->selected_input)
1720                 return 0;
1721
1722         if (input > state->info->max_port)
1723                 return -EINVAL;
1724
1725         state->selected_input = input;
1726
1727         disable_input(sd);
1728
1729         select_input(sd);
1730
1731         enable_input(sd);
1732
1733         return 0;
1734 }
1735
1736 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1737                                   struct v4l2_subdev_pad_config *cfg,
1738                                   struct v4l2_subdev_mbus_code_enum *code)
1739 {
1740         struct adv76xx_state *state = to_state(sd);
1741
1742         if (code->index >= state->info->nformats)
1743                 return -EINVAL;
1744
1745         code->code = state->info->formats[code->index].code;
1746
1747         return 0;
1748 }
1749
1750 static void adv76xx_fill_format(struct adv76xx_state *state,
1751                                 struct v4l2_mbus_framefmt *format)
1752 {
1753         memset(format, 0, sizeof(*format));
1754
1755         format->width = state->timings.bt.width;
1756         format->height = state->timings.bt.height;
1757         format->field = V4L2_FIELD_NONE;
1758         format->colorspace = V4L2_COLORSPACE_SRGB;
1759
1760         if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
1761                 format->colorspace = (state->timings.bt.height <= 576) ?
1762                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1763 }
1764
1765 /*
1766  * Compute the op_ch_sel value required to obtain on the bus the component order
1767  * corresponding to the selected format taking into account bus reordering
1768  * applied by the board at the output of the device.
1769  *
1770  * The following table gives the op_ch_value from the format component order
1771  * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1772  * adv76xx_bus_order value in row).
1773  *
1774  *           |  GBR(0)  GRB(1)  BGR(2)  RGB(3)  BRG(4)  RBG(5)
1775  * ----------+-------------------------------------------------
1776  * RGB (NOP) |  GBR     GRB     BGR     RGB     BRG     RBG
1777  * GRB (1-2) |  BGR     RGB     GBR     GRB     RBG     BRG
1778  * RBG (2-3) |  GRB     GBR     BRG     RBG     BGR     RGB
1779  * BGR (1-3) |  RBG     BRG     RGB     BGR     GRB     GBR
1780  * BRG (ROR) |  BRG     RBG     GRB     GBR     RGB     BGR
1781  * GBR (ROL) |  RGB     BGR     RBG     BRG     GBR     GRB
1782  */
1783 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1784 {
1785 #define _SEL(a,b,c,d,e,f)       { \
1786         ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1787         ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1788 #define _BUS(x)                 [ADV7604_BUS_ORDER_##x]
1789
1790         static const unsigned int op_ch_sel[6][6] = {
1791                 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1792                 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1793                 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1794                 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1795                 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1796                 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1797         };
1798
1799         return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1800 }
1801
1802 static void adv76xx_setup_format(struct adv76xx_state *state)
1803 {
1804         struct v4l2_subdev *sd = &state->sd;
1805
1806         io_write_clr_set(sd, 0x02, 0x02,
1807                         state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1808         io_write(sd, 0x03, state->format->op_format_sel |
1809                  state->pdata.op_format_mode_sel);
1810         io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1811         io_write_clr_set(sd, 0x05, 0x01,
1812                         state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1813 }
1814
1815 static int adv76xx_get_format(struct v4l2_subdev *sd,
1816                               struct v4l2_subdev_pad_config *cfg,
1817                               struct v4l2_subdev_format *format)
1818 {
1819         struct adv76xx_state *state = to_state(sd);
1820
1821         if (format->pad != state->source_pad)
1822                 return -EINVAL;
1823
1824         adv76xx_fill_format(state, &format->format);
1825
1826         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1827                 struct v4l2_mbus_framefmt *fmt;
1828
1829                 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1830                 format->format.code = fmt->code;
1831         } else {
1832                 format->format.code = state->format->code;
1833         }
1834
1835         return 0;
1836 }
1837
1838 static int adv76xx_set_format(struct v4l2_subdev *sd,
1839                               struct v4l2_subdev_pad_config *cfg,
1840                               struct v4l2_subdev_format *format)
1841 {
1842         struct adv76xx_state *state = to_state(sd);
1843         const struct adv76xx_format_info *info;
1844
1845         if (format->pad != state->source_pad)
1846                 return -EINVAL;
1847
1848         info = adv76xx_format_info(state, format->format.code);
1849         if (info == NULL)
1850                 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1851
1852         adv76xx_fill_format(state, &format->format);
1853         format->format.code = info->code;
1854
1855         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1856                 struct v4l2_mbus_framefmt *fmt;
1857
1858                 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1859                 fmt->code = format->format.code;
1860         } else {
1861                 state->format = info;
1862                 adv76xx_setup_format(state);
1863         }
1864
1865         return 0;
1866 }
1867
1868 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1869 {
1870         struct adv76xx_state *state = to_state(sd);
1871         const struct adv76xx_chip_info *info = state->info;
1872         const u8 irq_reg_0x43 = io_read(sd, 0x43);
1873         const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1874         const u8 irq_reg_0x70 = io_read(sd, 0x70);
1875         u8 fmt_change_digital;
1876         u8 fmt_change;
1877         u8 tx_5v;
1878
1879         if (irq_reg_0x43)
1880                 io_write(sd, 0x44, irq_reg_0x43);
1881         if (irq_reg_0x70)
1882                 io_write(sd, 0x71, irq_reg_0x70);
1883         if (irq_reg_0x6b)
1884                 io_write(sd, 0x6c, irq_reg_0x6b);
1885
1886         v4l2_dbg(2, debug, sd, "%s: ", __func__);
1887
1888         /* format change */
1889         fmt_change = irq_reg_0x43 & 0x98;
1890         fmt_change_digital = is_digital_input(sd)
1891                            ? irq_reg_0x6b & info->fmt_change_digital_mask
1892                            : 0;
1893
1894         if (fmt_change || fmt_change_digital) {
1895                 v4l2_dbg(1, debug, sd,
1896                         "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1897                         __func__, fmt_change, fmt_change_digital);
1898
1899                 v4l2_subdev_notify(sd, ADV76XX_FMT_CHANGE, NULL);
1900
1901                 if (handled)
1902                         *handled = true;
1903         }
1904         /* HDMI/DVI mode */
1905         if (irq_reg_0x6b & 0x01) {
1906                 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1907                         (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1908                 set_rgb_quantization_range(sd);
1909                 if (handled)
1910                         *handled = true;
1911         }
1912
1913         /* tx 5v detect */
1914         tx_5v = io_read(sd, 0x70) & info->cable_det_mask;
1915         if (tx_5v) {
1916                 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1917                 io_write(sd, 0x71, tx_5v);
1918                 adv76xx_s_detect_tx_5v_ctrl(sd);
1919                 if (handled)
1920                         *handled = true;
1921         }
1922         return 0;
1923 }
1924
1925 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1926 {
1927         struct adv76xx_state *state = to_state(sd);
1928         u8 *data = NULL;
1929
1930         memset(edid->reserved, 0, sizeof(edid->reserved));
1931
1932         switch (edid->pad) {
1933         case ADV76XX_PAD_HDMI_PORT_A:
1934         case ADV7604_PAD_HDMI_PORT_B:
1935         case ADV7604_PAD_HDMI_PORT_C:
1936         case ADV7604_PAD_HDMI_PORT_D:
1937                 if (state->edid.present & (1 << edid->pad))
1938                         data = state->edid.edid;
1939                 break;
1940         default:
1941                 return -EINVAL;
1942         }
1943
1944         if (edid->start_block == 0 && edid->blocks == 0) {
1945                 edid->blocks = data ? state->edid.blocks : 0;
1946                 return 0;
1947         }
1948
1949         if (data == NULL)
1950                 return -ENODATA;
1951
1952         if (edid->start_block >= state->edid.blocks)
1953                 return -EINVAL;
1954
1955         if (edid->start_block + edid->blocks > state->edid.blocks)
1956                 edid->blocks = state->edid.blocks - edid->start_block;
1957
1958         memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
1959
1960         return 0;
1961 }
1962
1963 static int get_edid_spa_location(const u8 *edid)
1964 {
1965         u8 d;
1966
1967         if ((edid[0x7e] != 1) ||
1968             (edid[0x80] != 0x02) ||
1969             (edid[0x81] != 0x03)) {
1970                 return -1;
1971         }
1972
1973         /* search Vendor Specific Data Block (tag 3) */
1974         d = edid[0x82] & 0x7f;
1975         if (d > 4) {
1976                 int i = 0x84;
1977                 int end = 0x80 + d;
1978
1979                 do {
1980                         u8 tag = edid[i] >> 5;
1981                         u8 len = edid[i] & 0x1f;
1982
1983                         if ((tag == 3) && (len >= 5))
1984                                 return i + 4;
1985                         i += len + 1;
1986                 } while (i < end);
1987         }
1988         return -1;
1989 }
1990
1991 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1992 {
1993         struct adv76xx_state *state = to_state(sd);
1994         const struct adv76xx_chip_info *info = state->info;
1995         int spa_loc;
1996         int err;
1997         int i;
1998
1999         memset(edid->reserved, 0, sizeof(edid->reserved));
2000
2001         if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
2002                 return -EINVAL;
2003         if (edid->start_block != 0)
2004                 return -EINVAL;
2005         if (edid->blocks == 0) {
2006                 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2007                 state->edid.present &= ~(1 << edid->pad);
2008                 adv76xx_set_hpd(state, state->edid.present);
2009                 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2010
2011                 /* Fall back to a 16:9 aspect ratio */
2012                 state->aspect_ratio.numerator = 16;
2013                 state->aspect_ratio.denominator = 9;
2014
2015                 if (!state->edid.present)
2016                         state->edid.blocks = 0;
2017
2018                 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2019                                 __func__, edid->pad, state->edid.present);
2020                 return 0;
2021         }
2022         if (edid->blocks > 2) {
2023                 edid->blocks = 2;
2024                 return -E2BIG;
2025         }
2026
2027         v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2028                         __func__, edid->pad, state->edid.present);
2029
2030         /* Disable hotplug and I2C access to EDID RAM from DDC port */
2031         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2032         adv76xx_set_hpd(state, 0);
2033         rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2034
2035         spa_loc = get_edid_spa_location(edid->edid);
2036         if (spa_loc < 0)
2037                 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2038
2039         switch (edid->pad) {
2040         case ADV76XX_PAD_HDMI_PORT_A:
2041                 state->spa_port_a[0] = edid->edid[spa_loc];
2042                 state->spa_port_a[1] = edid->edid[spa_loc + 1];
2043                 break;
2044         case ADV7604_PAD_HDMI_PORT_B:
2045                 rep_write(sd, 0x70, edid->edid[spa_loc]);
2046                 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
2047                 break;
2048         case ADV7604_PAD_HDMI_PORT_C:
2049                 rep_write(sd, 0x72, edid->edid[spa_loc]);
2050                 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
2051                 break;
2052         case ADV7604_PAD_HDMI_PORT_D:
2053                 rep_write(sd, 0x74, edid->edid[spa_loc]);
2054                 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
2055                 break;
2056         default:
2057                 return -EINVAL;
2058         }
2059
2060         if (info->type == ADV7604) {
2061                 rep_write(sd, 0x76, spa_loc & 0xff);
2062                 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
2063         } else {
2064                 /* FIXME: Where is the SPA location LSB register ? */
2065                 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
2066         }
2067
2068         edid->edid[spa_loc] = state->spa_port_a[0];
2069         edid->edid[spa_loc + 1] = state->spa_port_a[1];
2070
2071         memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2072         state->edid.blocks = edid->blocks;
2073         state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2074                         edid->edid[0x16]);
2075         state->edid.present |= 1 << edid->pad;
2076
2077         err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2078         if (err < 0) {
2079                 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2080                 return err;
2081         }
2082
2083         /* adv76xx calculates the checksums and enables I2C access to internal
2084            EDID RAM from DDC port. */
2085         rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2086
2087         for (i = 0; i < 1000; i++) {
2088                 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2089                         break;
2090                 mdelay(1);
2091         }
2092         if (i == 1000) {
2093                 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2094                 return -EIO;
2095         }
2096
2097         /* enable hotplug after 100 ms */
2098         queue_delayed_work(state->work_queues,
2099                         &state->delayed_work_enable_hotplug, HZ / 10);
2100         return 0;
2101 }
2102
2103 /*********** avi info frame CEA-861-E **************/
2104
2105 static void print_avi_infoframe(struct v4l2_subdev *sd)
2106 {
2107         int i;
2108         u8 buf[14];
2109         u8 avi_len;
2110         u8 avi_ver;
2111
2112         if (!is_hdmi(sd)) {
2113                 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2114                 return;
2115         }
2116         if (!(io_read(sd, 0x60) & 0x01)) {
2117                 v4l2_info(sd, "AVI infoframe not received\n");
2118                 return;
2119         }
2120
2121         if (io_read(sd, 0x83) & 0x01) {
2122                 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
2123                 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2124                 if (io_read(sd, 0x83) & 0x01) {
2125                         v4l2_info(sd, "AVI infoframe checksum error still present\n");
2126                         io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2127                 }
2128         }
2129
2130         avi_len = infoframe_read(sd, 0xe2);
2131         avi_ver = infoframe_read(sd, 0xe1);
2132         v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2133                         avi_ver, avi_len);
2134
2135         if (avi_ver != 0x02)
2136                 return;
2137
2138         for (i = 0; i < 14; i++)
2139                 buf[i] = infoframe_read(sd, i);
2140
2141         v4l2_info(sd,
2142                 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2143                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2144                 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2145 }
2146
2147 static int adv76xx_log_status(struct v4l2_subdev *sd)
2148 {
2149         struct adv76xx_state *state = to_state(sd);
2150         const struct adv76xx_chip_info *info = state->info;
2151         struct v4l2_dv_timings timings;
2152         struct stdi_readback stdi;
2153         u8 reg_io_0x02 = io_read(sd, 0x02);
2154         u8 edid_enabled;
2155         u8 cable_det;
2156
2157         static const char * const csc_coeff_sel_rb[16] = {
2158                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2159                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2160                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2161                 "reserved", "reserved", "reserved", "reserved", "manual"
2162         };
2163         static const char * const input_color_space_txt[16] = {
2164                 "RGB limited range (16-235)", "RGB full range (0-255)",
2165                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2166                 "xvYCC Bt.601", "xvYCC Bt.709",
2167                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2168                 "invalid", "invalid", "invalid", "invalid", "invalid",
2169                 "invalid", "invalid", "automatic"
2170         };
2171         static const char * const rgb_quantization_range_txt[] = {
2172                 "Automatic",
2173                 "RGB limited range (16-235)",
2174                 "RGB full range (0-255)",
2175         };
2176         static const char * const deep_color_mode_txt[4] = {
2177                 "8-bits per channel",
2178                 "10-bits per channel",
2179                 "12-bits per channel",
2180                 "16-bits per channel (not supported)"
2181         };
2182
2183         v4l2_info(sd, "-----Chip status-----\n");
2184         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2185         edid_enabled = rep_read(sd, info->edid_status_reg);
2186         v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2187                         ((edid_enabled & 0x01) ? "Yes" : "No"),
2188                         ((edid_enabled & 0x02) ? "Yes" : "No"),
2189                         ((edid_enabled & 0x04) ? "Yes" : "No"),
2190                         ((edid_enabled & 0x08) ? "Yes" : "No"));
2191         v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2192                         "enabled" : "disabled");
2193
2194         v4l2_info(sd, "-----Signal status-----\n");
2195         cable_det = info->read_cable_det(sd);
2196         v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2197                         ((cable_det & 0x01) ? "Yes" : "No"),
2198                         ((cable_det & 0x02) ? "Yes" : "No"),
2199                         ((cable_det & 0x04) ? "Yes" : "No"),
2200                         ((cable_det & 0x08) ? "Yes" : "No"));
2201         v4l2_info(sd, "TMDS signal detected: %s\n",
2202                         no_signal_tmds(sd) ? "false" : "true");
2203         v4l2_info(sd, "TMDS signal locked: %s\n",
2204                         no_lock_tmds(sd) ? "false" : "true");
2205         v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2206         v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2207         v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2208         v4l2_info(sd, "CP free run: %s\n",
2209                         (in_free_run(sd)) ? "on" : "off");
2210         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2211                         io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2212                         (io_read(sd, 0x01) & 0x70) >> 4);
2213
2214         v4l2_info(sd, "-----Video Timings-----\n");
2215         if (read_stdi(sd, &stdi))
2216                 v4l2_info(sd, "STDI: not locked\n");
2217         else
2218                 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2219                                 stdi.lcf, stdi.bl, stdi.lcvs,
2220                                 stdi.interlaced ? "interlaced" : "progressive",
2221                                 stdi.hs_pol, stdi.vs_pol);
2222         if (adv76xx_query_dv_timings(sd, &timings))
2223                 v4l2_info(sd, "No video detected\n");
2224         else
2225                 v4l2_print_dv_timings(sd->name, "Detected format: ",
2226                                       &timings, true);
2227         v4l2_print_dv_timings(sd->name, "Configured format: ",
2228                               &state->timings, true);
2229
2230         if (no_signal(sd))
2231                 return 0;
2232
2233         v4l2_info(sd, "-----Color space-----\n");
2234         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2235                         rgb_quantization_range_txt[state->rgb_quantization_range]);
2236         v4l2_info(sd, "Input color space: %s\n",
2237                         input_color_space_txt[reg_io_0x02 >> 4]);
2238         v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2239                         (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2240                         (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2241                         ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2242                                 "enabled" : "disabled");
2243         v4l2_info(sd, "Color space conversion: %s\n",
2244                         csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
2245
2246         if (!is_digital_input(sd))
2247                 return 0;
2248
2249         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2250         v4l2_info(sd, "Digital video port selected: %c\n",
2251                         (hdmi_read(sd, 0x00) & 0x03) + 'A');
2252         v4l2_info(sd, "HDCP encrypted content: %s\n",
2253                         (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2254         v4l2_info(sd, "HDCP keys read: %s%s\n",
2255                         (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2256                         (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2257         if (is_hdmi(sd)) {
2258                 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2259                 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2260                 bool audio_mute = io_read(sd, 0x65) & 0x40;
2261
2262                 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2263                                 audio_pll_locked ? "locked" : "not locked",
2264                                 audio_sample_packet_detect ? "detected" : "not detected",
2265                                 audio_mute ? "muted" : "enabled");
2266                 if (audio_pll_locked && audio_sample_packet_detect) {
2267                         v4l2_info(sd, "Audio format: %s\n",
2268                                         (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2269                 }
2270                 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2271                                 (hdmi_read(sd, 0x5c) << 8) +
2272                                 (hdmi_read(sd, 0x5d) & 0xf0));
2273                 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2274                                 (hdmi_read(sd, 0x5e) << 8) +
2275                                 hdmi_read(sd, 0x5f));
2276                 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2277
2278                 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2279
2280                 print_avi_infoframe(sd);
2281         }
2282
2283         return 0;
2284 }
2285
2286 /* ----------------------------------------------------------------------- */
2287
2288 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2289         .s_ctrl = adv76xx_s_ctrl,
2290 };
2291
2292 static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2293         .log_status = adv76xx_log_status,
2294         .interrupt_service_routine = adv76xx_isr,
2295 #ifdef CONFIG_VIDEO_ADV_DEBUG
2296         .g_register = adv76xx_g_register,
2297         .s_register = adv76xx_s_register,
2298 #endif
2299 };
2300
2301 static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2302         .s_routing = adv76xx_s_routing,
2303         .g_input_status = adv76xx_g_input_status,
2304         .s_dv_timings = adv76xx_s_dv_timings,
2305         .g_dv_timings = adv76xx_g_dv_timings,
2306         .query_dv_timings = adv76xx_query_dv_timings,
2307 };
2308
2309 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2310         .enum_mbus_code = adv76xx_enum_mbus_code,
2311         .get_fmt = adv76xx_get_format,
2312         .set_fmt = adv76xx_set_format,
2313         .get_edid = adv76xx_get_edid,
2314         .set_edid = adv76xx_set_edid,
2315         .dv_timings_cap = adv76xx_dv_timings_cap,
2316         .enum_dv_timings = adv76xx_enum_dv_timings,
2317 };
2318
2319 static const struct v4l2_subdev_ops adv76xx_ops = {
2320         .core = &adv76xx_core_ops,
2321         .video = &adv76xx_video_ops,
2322         .pad = &adv76xx_pad_ops,
2323 };
2324
2325 /* -------------------------- custom ctrls ---------------------------------- */
2326
2327 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2328         .ops = &adv76xx_ctrl_ops,
2329         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2330         .name = "Analog Sampling Phase",
2331         .type = V4L2_CTRL_TYPE_INTEGER,
2332         .min = 0,
2333         .max = 0x1f,
2334         .step = 1,
2335         .def = 0,
2336 };
2337
2338 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2339         .ops = &adv76xx_ctrl_ops,
2340         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2341         .name = "Free Running Color, Manual",
2342         .type = V4L2_CTRL_TYPE_BOOLEAN,
2343         .min = false,
2344         .max = true,
2345         .step = 1,
2346         .def = false,
2347 };
2348
2349 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2350         .ops = &adv76xx_ctrl_ops,
2351         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2352         .name = "Free Running Color",
2353         .type = V4L2_CTRL_TYPE_INTEGER,
2354         .min = 0x0,
2355         .max = 0xffffff,
2356         .step = 0x1,
2357         .def = 0x0,
2358 };
2359
2360 /* ----------------------------------------------------------------------- */
2361
2362 static int adv76xx_core_init(struct v4l2_subdev *sd)
2363 {
2364         struct adv76xx_state *state = to_state(sd);
2365         const struct adv76xx_chip_info *info = state->info;
2366         struct adv76xx_platform_data *pdata = &state->pdata;
2367
2368         hdmi_write(sd, 0x48,
2369                 (pdata->disable_pwrdnb ? 0x80 : 0) |
2370                 (pdata->disable_cable_det_rst ? 0x40 : 0));
2371
2372         disable_input(sd);
2373
2374         if (pdata->default_input >= 0 &&
2375             pdata->default_input < state->source_pad) {
2376                 state->selected_input = pdata->default_input;
2377                 select_input(sd);
2378                 enable_input(sd);
2379         }
2380
2381         /* power */
2382         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2383         io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
2384         cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */
2385
2386         /* video format */
2387         io_write_clr_set(sd, 0x02, 0x0f,
2388                         pdata->alt_gamma << 3 |
2389                         pdata->op_656_range << 2 |
2390                         pdata->alt_data_sat << 0);
2391         io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2392                         pdata->insert_av_codes << 2 |
2393                         pdata->replicate_av_codes << 1);
2394         adv76xx_setup_format(state);
2395
2396         cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
2397
2398         /* VS, HS polarities */
2399         io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2400                  pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2401
2402         /* Adjust drive strength */
2403         io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2404                                 pdata->dr_str_clk << 2 |
2405                                 pdata->dr_str_sync);
2406
2407         cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2408         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2409         cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
2410                                       ADI recommended setting [REF_01, c. 2.3.3] */
2411         cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
2412                                       ADI recommended setting [REF_01, c. 2.3.3] */
2413         cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2414                                      for digital formats */
2415
2416         /* HDMI audio */
2417         hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2418         hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2419         hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2420
2421         /* TODO from platform data */
2422         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
2423
2424         if (adv76xx_has_afe(state)) {
2425                 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2426                 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2427         }
2428
2429         /* interrupts */
2430         io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2431         io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2432         io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2433         io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2434         info->setup_irqs(sd);
2435
2436         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2437 }
2438
2439 static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2440 {
2441         io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2442 }
2443
2444 static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2445 {
2446         io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2447 }
2448
2449 static void adv76xx_unregister_clients(struct adv76xx_state *state)
2450 {
2451         unsigned int i;
2452
2453         for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2454                 if (state->i2c_clients[i])
2455                         i2c_unregister_device(state->i2c_clients[i]);
2456         }
2457 }
2458
2459 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2460                                                         u8 addr, u8 io_reg)
2461 {
2462         struct i2c_client *client = v4l2_get_subdevdata(sd);
2463
2464         if (addr)
2465                 io_write(sd, io_reg, addr << 1);
2466         return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2467 }
2468
2469 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
2470         /* reset ADI recommended settings for HDMI: */
2471         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2472         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2473         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2474         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2475         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2476         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2477         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2478         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2479         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2480         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2481         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2482         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2483         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2484
2485         /* set ADI recommended settings for digitizer */
2486         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2487         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2488         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2489         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2490         { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2491         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2492
2493         { ADV76XX_REG_SEQ_TERM, 0 },
2494 };
2495
2496 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
2497         /* set ADI recommended settings for HDMI: */
2498         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2499         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2500         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2501         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2502         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2503         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2504         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2505         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2506         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2507         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2508         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2509         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2510
2511         /* reset ADI recommended settings for digitizer */
2512         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2513         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2514         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2515
2516         { ADV76XX_REG_SEQ_TERM, 0 },
2517 };
2518
2519 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
2520         /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
2521         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2522         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2523         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2524         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2525         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2526         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2527         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2528         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2529         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2530         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2531         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2532
2533         { ADV76XX_REG_SEQ_TERM, 0 },
2534 };
2535
2536 static const struct adv76xx_chip_info adv76xx_chip_info[] = {
2537         [ADV7604] = {
2538                 .type = ADV7604,
2539                 .has_afe = true,
2540                 .max_port = ADV7604_PAD_VGA_COMP,
2541                 .num_dv_ports = 4,
2542                 .edid_enable_reg = 0x77,
2543                 .edid_status_reg = 0x7d,
2544                 .lcf_reg = 0xb3,
2545                 .tdms_lock_mask = 0xe0,
2546                 .cable_det_mask = 0x1e,
2547                 .fmt_change_digital_mask = 0xc1,
2548                 .cp_csc = 0xfc,
2549                 .formats = adv7604_formats,
2550                 .nformats = ARRAY_SIZE(adv7604_formats),
2551                 .set_termination = adv7604_set_termination,
2552                 .setup_irqs = adv7604_setup_irqs,
2553                 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2554                 .read_cable_det = adv7604_read_cable_det,
2555                 .recommended_settings = {
2556                     [0] = adv7604_recommended_settings_afe,
2557                     [1] = adv7604_recommended_settings_hdmi,
2558                 },
2559                 .num_recommended_settings = {
2560                     [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2561                     [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2562                 },
2563                 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2564                         BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
2565                         BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
2566                         BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2567                         BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2568                         BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
2569                         BIT(ADV7604_PAGE_VDP),
2570         },
2571         [ADV7611] = {
2572                 .type = ADV7611,
2573                 .has_afe = false,
2574                 .max_port = ADV76XX_PAD_HDMI_PORT_A,
2575                 .num_dv_ports = 1,
2576                 .edid_enable_reg = 0x74,
2577                 .edid_status_reg = 0x76,
2578                 .lcf_reg = 0xa3,
2579                 .tdms_lock_mask = 0x43,
2580                 .cable_det_mask = 0x01,
2581                 .fmt_change_digital_mask = 0x03,
2582                 .cp_csc = 0xf4,
2583                 .formats = adv7611_formats,
2584                 .nformats = ARRAY_SIZE(adv7611_formats),
2585                 .set_termination = adv7611_set_termination,
2586                 .setup_irqs = adv7611_setup_irqs,
2587                 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2588                 .read_cable_det = adv7611_read_cable_det,
2589                 .recommended_settings = {
2590                     [1] = adv7611_recommended_settings_hdmi,
2591                 },
2592                 .num_recommended_settings = {
2593                     [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2594                 },
2595                 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2596                         BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2597                         BIT(ADV76XX_PAGE_REP) |  BIT(ADV76XX_PAGE_EDID) |
2598                         BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
2599         },
2600 };
2601
2602 static struct i2c_device_id adv76xx_i2c_id[] = {
2603         { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
2604         { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
2605         { }
2606 };
2607 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
2608
2609 static struct of_device_id adv76xx_of_id[] __maybe_unused = {
2610         { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
2611         { }
2612 };
2613 MODULE_DEVICE_TABLE(of, adv76xx_of_id);
2614
2615 static int adv76xx_parse_dt(struct adv76xx_state *state)
2616 {
2617         struct v4l2_of_endpoint bus_cfg;
2618         struct device_node *endpoint;
2619         struct device_node *np;
2620         unsigned int flags;
2621
2622         np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
2623
2624         /* Parse the endpoint. */
2625         endpoint = of_graph_get_next_endpoint(np, NULL);
2626         if (!endpoint)
2627                 return -EINVAL;
2628
2629         v4l2_of_parse_endpoint(endpoint, &bus_cfg);
2630         of_node_put(endpoint);
2631
2632         flags = bus_cfg.bus.parallel.flags;
2633
2634         if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2635                 state->pdata.inv_hs_pol = 1;
2636
2637         if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2638                 state->pdata.inv_vs_pol = 1;
2639
2640         if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2641                 state->pdata.inv_llc_pol = 1;
2642
2643         if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2644                 state->pdata.insert_av_codes = 1;
2645                 state->pdata.op_656_range = 1;
2646         }
2647
2648         /* Disable the interrupt for now as no DT-based board uses it. */
2649         state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
2650
2651         /* Use the default I2C addresses. */
2652         state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
2653         state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
2654         state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
2655         state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2656         state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
2657         state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
2658         state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
2659         state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
2660         state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
2661         state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
2662         state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
2663         state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2664
2665         /* Hardcode the remaining platform data fields. */
2666         state->pdata.disable_pwrdnb = 0;
2667         state->pdata.disable_cable_det_rst = 0;
2668         state->pdata.default_input = -1;
2669         state->pdata.blank_data = 1;
2670         state->pdata.alt_data_sat = 1;
2671         state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2672         state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2673
2674         return 0;
2675 }
2676
2677 static int adv76xx_probe(struct i2c_client *client,
2678                          const struct i2c_device_id *id)
2679 {
2680         static const struct v4l2_dv_timings cea640x480 =
2681                 V4L2_DV_BT_CEA_640X480P59_94;
2682         struct adv76xx_state *state;
2683         struct v4l2_ctrl_handler *hdl;
2684         struct v4l2_subdev *sd;
2685         unsigned int i;
2686         u16 val;
2687         int err;
2688
2689         /* Check if the adapter supports the needed features */
2690         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2691                 return -EIO;
2692         v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
2693                         client->addr << 1);
2694
2695         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
2696         if (!state) {
2697                 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
2698                 return -ENOMEM;
2699         }
2700
2701         state->i2c_clients[ADV76XX_PAGE_IO] = client;
2702
2703         /* initialize variables */
2704         state->restart_stdi_once = true;
2705         state->selected_input = ~0;
2706
2707         if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2708                 const struct of_device_id *oid;
2709
2710                 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
2711                 state->info = oid->data;
2712
2713                 err = adv76xx_parse_dt(state);
2714                 if (err < 0) {
2715                         v4l_err(client, "DT parsing error\n");
2716                         return err;
2717                 }
2718         } else if (client->dev.platform_data) {
2719                 struct adv76xx_platform_data *pdata = client->dev.platform_data;
2720
2721                 state->info = (const struct adv76xx_chip_info *)id->driver_data;
2722                 state->pdata = *pdata;
2723         } else {
2724                 v4l_err(client, "No platform data!\n");
2725                 return -ENODEV;
2726         }
2727
2728         /* Request GPIOs. */
2729         for (i = 0; i < state->info->num_dv_ports; ++i) {
2730                 state->hpd_gpio[i] =
2731                         devm_gpiod_get_index_optional(&client->dev, "hpd", i,
2732                                                       GPIOD_OUT_LOW);
2733                 if (IS_ERR(state->hpd_gpio[i]))
2734                         return PTR_ERR(state->hpd_gpio[i]);
2735
2736                 if (state->hpd_gpio[i])
2737                         v4l_info(client, "Handling HPD %u GPIO\n", i);
2738         }
2739
2740         state->timings = cea640x480;
2741         state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
2742
2743         sd = &state->sd;
2744         v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
2745         snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2746                 id->name, i2c_adapter_id(client->adapter),
2747                 client->addr);
2748         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2749
2750         /*
2751          * Verify that the chip is present. On ADV7604 the RD_INFO register only
2752          * identifies the revision, while on ADV7611 it identifies the model as
2753          * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
2754          */
2755         if (state->info->type == ADV7604) {
2756                 val = adv_smbus_read_byte_data_check(client, 0xfb, false);
2757                 if (val != 0x68) {
2758                         v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2759                                         client->addr << 1);
2760                         return -ENODEV;
2761                 }
2762         } else {
2763                 val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8)
2764                     | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0);
2765                 if (val != 0x2051) {
2766                         v4l2_info(sd, "not an adv7611 on address 0x%x\n",
2767                                         client->addr << 1);
2768                         return -ENODEV;
2769                 }
2770         }
2771
2772         /* control handlers */
2773         hdl = &state->hdl;
2774         v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
2775
2776         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2777                         V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2778         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2779                         V4L2_CID_CONTRAST, 0, 255, 1, 128);
2780         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2781                         V4L2_CID_SATURATION, 0, 255, 1, 128);
2782         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2783                         V4L2_CID_HUE, 0, 128, 1, 0);
2784
2785         /* private controls */
2786         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2787                         V4L2_CID_DV_RX_POWER_PRESENT, 0,
2788                         (1 << state->info->num_dv_ports) - 1, 0, 0);
2789         state->rgb_quantization_range_ctrl =
2790                 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
2791                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2792                         0, V4L2_DV_RGB_RANGE_AUTO);
2793
2794         /* custom controls */
2795         if (adv76xx_has_afe(state))
2796                 state->analog_sampling_phase_ctrl =
2797                         v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2798         state->free_run_color_manual_ctrl =
2799                 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
2800         state->free_run_color_ctrl =
2801                 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
2802
2803         sd->ctrl_handler = hdl;
2804         if (hdl->error) {
2805                 err = hdl->error;
2806                 goto err_hdl;
2807         }
2808         state->detect_tx_5v_ctrl->is_private = true;
2809         state->rgb_quantization_range_ctrl->is_private = true;
2810         if (adv76xx_has_afe(state))
2811                 state->analog_sampling_phase_ctrl->is_private = true;
2812         state->free_run_color_manual_ctrl->is_private = true;
2813         state->free_run_color_ctrl->is_private = true;
2814
2815         if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
2816                 err = -ENODEV;
2817                 goto err_hdl;
2818         }
2819
2820         for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
2821                 if (!(BIT(i) & state->info->page_mask))
2822                         continue;
2823
2824                 state->i2c_clients[i] =
2825                         adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
2826                                              0xf2 + i);
2827                 if (state->i2c_clients[i] == NULL) {
2828                         err = -ENOMEM;
2829                         v4l2_err(sd, "failed to create i2c client %u\n", i);
2830                         goto err_i2c;
2831                 }
2832         }
2833
2834         /* work queues */
2835         state->work_queues = create_singlethread_workqueue(client->name);
2836         if (!state->work_queues) {
2837                 v4l2_err(sd, "Could not create work queue\n");
2838                 err = -ENOMEM;
2839                 goto err_i2c;
2840         }
2841
2842         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2843                         adv76xx_delayed_work_enable_hotplug);
2844
2845         state->source_pad = state->info->num_dv_ports
2846                           + (state->info->has_afe ? 2 : 0);
2847         for (i = 0; i < state->source_pad; ++i)
2848                 state->pads[i].flags = MEDIA_PAD_FL_SINK;
2849         state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
2850
2851         err = media_entity_init(&sd->entity, state->source_pad + 1,
2852                                 state->pads, 0);
2853         if (err)
2854                 goto err_work_queues;
2855
2856         err = adv76xx_core_init(sd);
2857         if (err)
2858                 goto err_entity;
2859         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2860                         client->addr << 1, client->adapter->name);
2861
2862         err = v4l2_async_register_subdev(sd);
2863         if (err)
2864                 goto err_entity;
2865
2866         return 0;
2867
2868 err_entity:
2869         media_entity_cleanup(&sd->entity);
2870 err_work_queues:
2871         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2872         destroy_workqueue(state->work_queues);
2873 err_i2c:
2874         adv76xx_unregister_clients(state);
2875 err_hdl:
2876         v4l2_ctrl_handler_free(hdl);
2877         return err;
2878 }
2879
2880 /* ----------------------------------------------------------------------- */
2881
2882 static int adv76xx_remove(struct i2c_client *client)
2883 {
2884         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2885         struct adv76xx_state *state = to_state(sd);
2886
2887         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2888         destroy_workqueue(state->work_queues);
2889         v4l2_async_unregister_subdev(sd);
2890         media_entity_cleanup(&sd->entity);
2891         adv76xx_unregister_clients(to_state(sd));
2892         v4l2_ctrl_handler_free(sd->ctrl_handler);
2893         return 0;
2894 }
2895
2896 /* ----------------------------------------------------------------------- */
2897
2898 static struct i2c_driver adv76xx_driver = {
2899         .driver = {
2900                 .owner = THIS_MODULE,
2901                 .name = "adv7604",
2902                 .of_match_table = of_match_ptr(adv76xx_of_id),
2903         },
2904         .probe = adv76xx_probe,
2905         .remove = adv76xx_remove,
2906         .id_table = adv76xx_i2c_id,
2907 };
2908
2909 module_i2c_driver(adv76xx_driver);