kernel/drivers/media/dvb-frontends/stv0367.c

   1 /*
   2  * stv0367.c
   3  *
   4  * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
   5  *
   6  * Copyright (C) ST Microelectronics.
   7  * Copyright (C) 2010,2011 NetUP Inc.
   8  * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/string.h>
  29 #include <linux/slab.h>
  30 #include <linux/i2c.h>
  31
  32 #include "stv0367.h"
  33 #include "stv0367_regs.h"
  34 #include "stv0367_priv.h"
  35
  36 /* Max transfer size done by I2C transfer functions */
  37 #define MAX_XFER_SIZE  64
  38
  39 static int stvdebug;
  40 module_param_named(debug, stvdebug, int, 0644);
  41
  42 static int i2cdebug;
  43 module_param_named(i2c_debug, i2cdebug, int, 0644);
  44
  45 #define dprintk(args...) \
  46         do { \
  47                 if (stvdebug) \
  48                         printk(KERN_DEBUG args); \
  49         } while (0)
  50         /* DVB-C */
  51
  52 struct stv0367cab_state {
  53         enum stv0367_cab_signal_type    state;
  54         u32     mclk;
  55         u32     adc_clk;
  56         s32     search_range;
  57         s32     derot_offset;
  58         /* results */
  59         int locked;                     /* channel found                */
  60         u32 freq_khz;                   /* found frequency (in kHz)     */
  61         u32 symbol_rate;                /* found symbol rate (in Bds)   */
  62         enum fe_spectral_inversion spect_inv; /* Spectrum Inversion     */
  63 };
  64
  65 struct stv0367ter_state {
  66         /* DVB-T */
  67         enum stv0367_ter_signal_type state;
  68         enum stv0367_ter_if_iq_mode if_iq_mode;
  69         enum stv0367_ter_mode mode;/* mode 2K or 8K */
  70         enum fe_guard_interval guard;
  71         enum stv0367_ter_hierarchy hierarchy;
  72         u32 frequency;
  73         enum fe_spectral_inversion sense; /*  current search spectrum */
  74         u8  force; /* force mode/guard */
  75         u8  bw; /* channel width 6, 7 or 8 in MHz */
  76         u8  pBW; /* channel width used during previous lock */
  77         u32 pBER;
  78         u32 pPER;
  79         u32 ucblocks;
  80         s8  echo_pos; /* echo position */
  81         u8  first_lock;
  82         u8  unlock_counter;
  83         u32 agc_val;
  84 };
  85
  86 struct stv0367_state {
  87         struct dvb_frontend fe;
  88         struct i2c_adapter *i2c;
  89         /* config settings */
  90         const struct stv0367_config *config;
  91         u8 chip_id;
  92         /* DVB-C */
  93         struct stv0367cab_state *cab_state;
  94         /* DVB-T */
  95         struct stv0367ter_state *ter_state;
  96 };
  97
  98 struct st_register {
  99         u16     addr;
 100         u8      value;
 101 };
 102
 103 /* values for STV4100 XTAL=30M int clk=53.125M*/
 104 static struct st_register def0367ter[STV0367TER_NBREGS] = {
 105         {R367TER_ID,            0x60},
 106         {R367TER_I2CRPT,        0xa0},
 107         /* {R367TER_I2CRPT,     0x22},*/
 108         {R367TER_TOPCTRL,       0x00},/* for xc5000; was 0x02 */
 109         {R367TER_IOCFG0,        0x40},
 110         {R367TER_DAC0R,         0x00},
 111         {R367TER_IOCFG1,        0x00},
 112         {R367TER_DAC1R,         0x00},
 113         {R367TER_IOCFG2,        0x62},
 114         {R367TER_SDFR,          0x00},
 115         {R367TER_STATUS,        0xf8},
 116         {R367TER_AUX_CLK,       0x0a},
 117         {R367TER_FREESYS1,      0x00},
 118         {R367TER_FREESYS2,      0x00},
 119         {R367TER_FREESYS3,      0x00},
 120         {R367TER_GPIO_CFG,      0x55},
 121         {R367TER_GPIO_CMD,      0x00},
 122         {R367TER_AGC2MAX,       0xff},
 123         {R367TER_AGC2MIN,       0x00},
 124         {R367TER_AGC1MAX,       0xff},
 125         {R367TER_AGC1MIN,       0x00},
 126         {R367TER_AGCR,          0xbc},
 127         {R367TER_AGC2TH,        0x00},
 128         {R367TER_AGC12C,        0x00},
 129         {R367TER_AGCCTRL1,      0x85},
 130         {R367TER_AGCCTRL2,      0x1f},
 131         {R367TER_AGC1VAL1,      0x00},
 132         {R367TER_AGC1VAL2,      0x00},
 133         {R367TER_AGC2VAL1,      0x6f},
 134         {R367TER_AGC2VAL2,      0x05},
 135         {R367TER_AGC2PGA,       0x00},
 136         {R367TER_OVF_RATE1,     0x00},
 137         {R367TER_OVF_RATE2,     0x00},
 138         {R367TER_GAIN_SRC1,     0xaa},/* for xc5000; was 0x2b */
 139         {R367TER_GAIN_SRC2,     0xd6},/* for xc5000; was 0x04 */
 140         {R367TER_INC_DEROT1,    0x55},
 141         {R367TER_INC_DEROT2,    0x55},
 142         {R367TER_PPM_CPAMP_DIR, 0x2c},
 143         {R367TER_PPM_CPAMP_INV, 0x00},
 144         {R367TER_FREESTFE_1,    0x00},
 145         {R367TER_FREESTFE_2,    0x1c},
 146         {R367TER_DCOFFSET,      0x00},
 147         {R367TER_EN_PROCESS,    0x05},
 148         {R367TER_SDI_SMOOTHER,  0x80},
 149         {R367TER_FE_LOOP_OPEN,  0x1c},
 150         {R367TER_FREQOFF1,      0x00},
 151         {R367TER_FREQOFF2,      0x00},
 152         {R367TER_FREQOFF3,      0x00},
 153         {R367TER_TIMOFF1,       0x00},
 154         {R367TER_TIMOFF2,       0x00},
 155         {R367TER_EPQ,           0x02},
 156         {R367TER_EPQAUTO,       0x01},
 157         {R367TER_SYR_UPDATE,    0xf5},
 158         {R367TER_CHPFREE,       0x00},
 159         {R367TER_PPM_STATE_MAC, 0x23},
 160         {R367TER_INR_THRESHOLD, 0xff},
 161         {R367TER_EPQ_TPS_ID_CELL, 0xf9},
 162         {R367TER_EPQ_CFG,       0x00},
 163         {R367TER_EPQ_STATUS,    0x01},
 164         {R367TER_AUTORELOCK,    0x81},
 165         {R367TER_BER_THR_VMSB,  0x00},
 166         {R367TER_BER_THR_MSB,   0x00},
 167         {R367TER_BER_THR_LSB,   0x00},
 168         {R367TER_CCD,           0x83},
 169         {R367TER_SPECTR_CFG,    0x00},
 170         {R367TER_CHC_DUMMY,     0x18},
 171         {R367TER_INC_CTL,       0x88},
 172         {R367TER_INCTHRES_COR1, 0xb4},
 173         {R367TER_INCTHRES_COR2, 0x96},
 174         {R367TER_INCTHRES_DET1, 0x0e},
 175         {R367TER_INCTHRES_DET2, 0x11},
 176         {R367TER_IIR_CELLNB,    0x8d},
 177         {R367TER_IIRCX_COEFF1_MSB, 0x00},
 178         {R367TER_IIRCX_COEFF1_LSB, 0x00},
 179         {R367TER_IIRCX_COEFF2_MSB, 0x09},
 180         {R367TER_IIRCX_COEFF2_LSB, 0x18},
 181         {R367TER_IIRCX_COEFF3_MSB, 0x14},
 182         {R367TER_IIRCX_COEFF3_LSB, 0x9c},
 183         {R367TER_IIRCX_COEFF4_MSB, 0x00},
 184         {R367TER_IIRCX_COEFF4_LSB, 0x00},
 185         {R367TER_IIRCX_COEFF5_MSB, 0x36},
 186         {R367TER_IIRCX_COEFF5_LSB, 0x42},
 187         {R367TER_FEPATH_CFG,    0x00},
 188         {R367TER_PMC1_FUNC,     0x65},
 189         {R367TER_PMC1_FOR,      0x00},
 190         {R367TER_PMC2_FUNC,     0x00},
 191         {R367TER_STATUS_ERR_DA, 0xe0},
 192         {R367TER_DIG_AGC_R,     0xfe},
 193         {R367TER_COMAGC_TARMSB, 0x0b},
 194         {R367TER_COM_AGC_TAR_ENMODE, 0x41},
 195         {R367TER_COM_AGC_CFG,   0x3e},
 196         {R367TER_COM_AGC_GAIN1, 0x39},
 197         {R367TER_AUT_AGC_TARGETMSB, 0x0b},
 198         {R367TER_LOCK_DET_MSB,  0x01},
 199         {R367TER_AGCTAR_LOCK_LSBS, 0x40},
 200         {R367TER_AUT_GAIN_EN,   0xf4},
 201         {R367TER_AUT_CFG,       0xf0},
 202         {R367TER_LOCKN,         0x23},
 203         {R367TER_INT_X_3,       0x00},
 204         {R367TER_INT_X_2,       0x03},
 205         {R367TER_INT_X_1,       0x8d},
 206         {R367TER_INT_X_0,       0xa0},
 207         {R367TER_MIN_ERRX_MSB,  0x00},
 208         {R367TER_COR_CTL,       0x23},
 209         {R367TER_COR_STAT,      0xf6},
 210         {R367TER_COR_INTEN,     0x00},
 211         {R367TER_COR_INTSTAT,   0x3f},
 212         {R367TER_COR_MODEGUARD, 0x03},
 213         {R367TER_AGC_CTL,       0x08},
 214         {R367TER_AGC_MANUAL1,   0x00},
 215         {R367TER_AGC_MANUAL2,   0x00},
 216         {R367TER_AGC_TARG,      0x16},
 217         {R367TER_AGC_GAIN1,     0x53},
 218         {R367TER_AGC_GAIN2,     0x1d},
 219         {R367TER_RESERVED_1,    0x00},
 220         {R367TER_RESERVED_2,    0x00},
 221         {R367TER_RESERVED_3,    0x00},
 222         {R367TER_CAS_CTL,       0x44},
 223         {R367TER_CAS_FREQ,      0xb3},
 224         {R367TER_CAS_DAGCGAIN,  0x12},
 225         {R367TER_SYR_CTL,       0x04},
 226         {R367TER_SYR_STAT,      0x10},
 227         {R367TER_SYR_NCO1,      0x00},
 228         {R367TER_SYR_NCO2,      0x00},
 229         {R367TER_SYR_OFFSET1,   0x00},
 230         {R367TER_SYR_OFFSET2,   0x00},
 231         {R367TER_FFT_CTL,       0x00},
 232         {R367TER_SCR_CTL,       0x70},
 233         {R367TER_PPM_CTL1,      0xf8},
 234         {R367TER_TRL_CTL,       0x14},/* for xc5000; was 0xac */
 235         {R367TER_TRL_NOMRATE1,  0xae},/* for xc5000; was 0x1e */
 236         {R367TER_TRL_NOMRATE2,  0x56},/* for xc5000; was 0x58 */
 237         {R367TER_TRL_TIME1,     0x1d},
 238         {R367TER_TRL_TIME2,     0xfc},
 239         {R367TER_CRL_CTL,       0x24},
 240         {R367TER_CRL_FREQ1,     0xad},
 241         {R367TER_CRL_FREQ2,     0x9d},
 242         {R367TER_CRL_FREQ3,     0xff},
 243         {R367TER_CHC_CTL,       0x01},
 244         {R367TER_CHC_SNR,       0xf0},
 245         {R367TER_BDI_CTL,       0x00},
 246         {R367TER_DMP_CTL,       0x00},
 247         {R367TER_TPS_RCVD1,     0x30},
 248         {R367TER_TPS_RCVD2,     0x02},
 249         {R367TER_TPS_RCVD3,     0x01},
 250         {R367TER_TPS_RCVD4,     0x00},
 251         {R367TER_TPS_ID_CELL1,  0x00},
 252         {R367TER_TPS_ID_CELL2,  0x00},
 253         {R367TER_TPS_RCVD5_SET1, 0x02},
 254         {R367TER_TPS_SET2,      0x02},
 255         {R367TER_TPS_SET3,      0x01},
 256         {R367TER_TPS_CTL,       0x00},
 257         {R367TER_CTL_FFTOSNUM,  0x34},
 258         {R367TER_TESTSELECT,    0x09},
 259         {R367TER_MSC_REV,       0x0a},
 260         {R367TER_PIR_CTL,       0x00},
 261         {R367TER_SNR_CARRIER1,  0xa1},
 262         {R367TER_SNR_CARRIER2,  0x9a},
 263         {R367TER_PPM_CPAMP,     0x2c},
 264         {R367TER_TSM_AP0,       0x00},
 265         {R367TER_TSM_AP1,       0x00},
 266         {R367TER_TSM_AP2 ,      0x00},
 267         {R367TER_TSM_AP3,       0x00},
 268         {R367TER_TSM_AP4,       0x00},
 269         {R367TER_TSM_AP5,       0x00},
 270         {R367TER_TSM_AP6,       0x00},
 271         {R367TER_TSM_AP7,       0x00},
 272         {R367TER_TSTRES,        0x00},
 273         {R367TER_ANACTRL,       0x0D},/* PLL stoped, restart at init!!! */
 274         {R367TER_TSTBUS,        0x00},
 275         {R367TER_TSTRATE,       0x00},
 276         {R367TER_CONSTMODE,     0x01},
 277         {R367TER_CONSTCARR1,    0x00},
 278         {R367TER_CONSTCARR2,    0x00},
 279         {R367TER_ICONSTEL,      0x0a},
 280         {R367TER_QCONSTEL,      0x15},
 281         {R367TER_TSTBISTRES0,   0x00},
 282         {R367TER_TSTBISTRES1,   0x00},
 283         {R367TER_TSTBISTRES2,   0x28},
 284         {R367TER_TSTBISTRES3,   0x00},
 285         {R367TER_RF_AGC1,       0xff},
 286         {R367TER_RF_AGC2,       0x83},
 287         {R367TER_ANADIGCTRL,    0x19},
 288         {R367TER_PLLMDIV,       0x01},/* for xc5000; was 0x0c */
 289         {R367TER_PLLNDIV,       0x06},/* for xc5000; was 0x55 */
 290         {R367TER_PLLSETUP,      0x18},
 291         {R367TER_DUAL_AD12,     0x0C},/* for xc5000 AGC voltage 1.6V */
 292         {R367TER_TSTBIST,       0x00},
 293         {R367TER_PAD_COMP_CTRL, 0x00},
 294         {R367TER_PAD_COMP_WR,   0x00},
 295         {R367TER_PAD_COMP_RD,   0xe0},
 296         {R367TER_SYR_TARGET_FFTADJT_MSB, 0x00},
 297         {R367TER_SYR_TARGET_FFTADJT_LSB, 0x00},
 298         {R367TER_SYR_TARGET_CHCADJT_MSB, 0x00},
 299         {R367TER_SYR_TARGET_CHCADJT_LSB, 0x00},
 300         {R367TER_SYR_FLAG,      0x00},
 301         {R367TER_CRL_TARGET1,   0x00},
 302         {R367TER_CRL_TARGET2,   0x00},
 303         {R367TER_CRL_TARGET3,   0x00},
 304         {R367TER_CRL_TARGET4,   0x00},
 305         {R367TER_CRL_FLAG,      0x00},
 306         {R367TER_TRL_TARGET1,   0x00},
 307         {R367TER_TRL_TARGET2,   0x00},
 308         {R367TER_TRL_CHC,       0x00},
 309         {R367TER_CHC_SNR_TARG,  0x00},
 310         {R367TER_TOP_TRACK,     0x00},
 311         {R367TER_TRACKER_FREE1, 0x00},
 312         {R367TER_ERROR_CRL1,    0x00},
 313         {R367TER_ERROR_CRL2,    0x00},
 314         {R367TER_ERROR_CRL3,    0x00},
 315         {R367TER_ERROR_CRL4,    0x00},
 316         {R367TER_DEC_NCO1,      0x2c},
 317         {R367TER_DEC_NCO2,      0x0f},
 318         {R367TER_DEC_NCO3,      0x20},
 319         {R367TER_SNR,           0xf1},
 320         {R367TER_SYR_FFTADJ1,   0x00},
 321         {R367TER_SYR_FFTADJ2,   0x00},
 322         {R367TER_SYR_CHCADJ1,   0x00},
 323         {R367TER_SYR_CHCADJ2,   0x00},
 324         {R367TER_SYR_OFF,       0x00},
 325         {R367TER_PPM_OFFSET1,   0x00},
 326         {R367TER_PPM_OFFSET2,   0x03},
 327         {R367TER_TRACKER_FREE2, 0x00},
 328         {R367TER_DEBG_LT10,     0x00},
 329         {R367TER_DEBG_LT11,     0x00},
 330         {R367TER_DEBG_LT12,     0x00},
 331         {R367TER_DEBG_LT13,     0x00},
 332         {R367TER_DEBG_LT14,     0x00},
 333         {R367TER_DEBG_LT15,     0x00},
 334         {R367TER_DEBG_LT16,     0x00},
 335         {R367TER_DEBG_LT17,     0x00},
 336         {R367TER_DEBG_LT18,     0x00},
 337         {R367TER_DEBG_LT19,     0x00},
 338         {R367TER_DEBG_LT1A,     0x00},
 339         {R367TER_DEBG_LT1B,     0x00},
 340         {R367TER_DEBG_LT1C,     0x00},
 341         {R367TER_DEBG_LT1D,     0x00},
 342         {R367TER_DEBG_LT1E,     0x00},
 343         {R367TER_DEBG_LT1F,     0x00},
 344         {R367TER_RCCFGH,        0x00},
 345         {R367TER_RCCFGM,        0x00},
 346         {R367TER_RCCFGL,        0x00},
 347         {R367TER_RCINSDELH,     0x00},
 348         {R367TER_RCINSDELM,     0x00},
 349         {R367TER_RCINSDELL,     0x00},
 350         {R367TER_RCSTATUS,      0x00},
 351         {R367TER_RCSPEED,       0x6f},
 352         {R367TER_RCDEBUGM,      0xe7},
 353         {R367TER_RCDEBUGL,      0x9b},
 354         {R367TER_RCOBSCFG,      0x00},
 355         {R367TER_RCOBSM,        0x00},
 356         {R367TER_RCOBSL,        0x00},
 357         {R367TER_RCFECSPY,      0x00},
 358         {R367TER_RCFSPYCFG,     0x00},
 359         {R367TER_RCFSPYDATA,    0x00},
 360         {R367TER_RCFSPYOUT,     0x00},
 361         {R367TER_RCFSTATUS,     0x00},
 362         {R367TER_RCFGOODPACK,   0x00},
 363         {R367TER_RCFPACKCNT,    0x00},
 364         {R367TER_RCFSPYMISC,    0x00},
 365         {R367TER_RCFBERCPT4,    0x00},
 366         {R367TER_RCFBERCPT3,    0x00},
 367         {R367TER_RCFBERCPT2,    0x00},
 368         {R367TER_RCFBERCPT1,    0x00},
 369         {R367TER_RCFBERCPT0,    0x00},
 370         {R367TER_RCFBERERR2,    0x00},
 371         {R367TER_RCFBERERR1,    0x00},
 372         {R367TER_RCFBERERR0,    0x00},
 373         {R367TER_RCFSTATESM,    0x00},
 374         {R367TER_RCFSTATESL,    0x00},
 375         {R367TER_RCFSPYBER,     0x00},
 376         {R367TER_RCFSPYDISTM,   0x00},
 377         {R367TER_RCFSPYDISTL,   0x00},
 378         {R367TER_RCFSPYOBS7,    0x00},
 379         {R367TER_RCFSPYOBS6,    0x00},
 380         {R367TER_RCFSPYOBS5,    0x00},
 381         {R367TER_RCFSPYOBS4,    0x00},
 382         {R367TER_RCFSPYOBS3,    0x00},
 383         {R367TER_RCFSPYOBS2,    0x00},
 384         {R367TER_RCFSPYOBS1,    0x00},
 385         {R367TER_RCFSPYOBS0,    0x00},
 386         {R367TER_TSGENERAL,     0x00},
 387         {R367TER_RC1SPEED,      0x6f},
 388         {R367TER_TSGSTATUS,     0x18},
 389         {R367TER_FECM,          0x01},
 390         {R367TER_VTH12,         0xff},
 391         {R367TER_VTH23,         0xa1},
 392         {R367TER_VTH34,         0x64},
 393         {R367TER_VTH56,         0x40},
 394         {R367TER_VTH67,         0x00},
 395         {R367TER_VTH78,         0x2c},
 396         {R367TER_VITCURPUN,     0x12},
 397         {R367TER_VERROR,        0x01},
 398         {R367TER_PRVIT,         0x3f},
 399         {R367TER_VAVSRVIT,      0x00},
 400         {R367TER_VSTATUSVIT,    0xbd},
 401         {R367TER_VTHINUSE,      0xa1},
 402         {R367TER_KDIV12,        0x20},
 403         {R367TER_KDIV23,        0x40},
 404         {R367TER_KDIV34,        0x20},
 405         {R367TER_KDIV56,        0x30},
 406         {R367TER_KDIV67,        0x00},
 407         {R367TER_KDIV78,        0x30},
 408         {R367TER_SIGPOWER,      0x54},
 409         {R367TER_DEMAPVIT,      0x40},
 410         {R367TER_VITSCALE,      0x00},
 411         {R367TER_FFEC1PRG,      0x00},
 412         {R367TER_FVITCURPUN,    0x12},
 413         {R367TER_FVERROR,       0x01},
 414         {R367TER_FVSTATUSVIT,   0xbd},
 415         {R367TER_DEBUG_LT1,     0x00},
 416         {R367TER_DEBUG_LT2,     0x00},
 417         {R367TER_DEBUG_LT3,     0x00},
 418         {R367TER_TSTSFMET,      0x00},
 419         {R367TER_SELOUT,        0x00},
 420         {R367TER_TSYNC,         0x00},
 421         {R367TER_TSTERR,        0x00},
 422         {R367TER_TSFSYNC,       0x00},
 423         {R367TER_TSTSFERR,      0x00},
 424         {R367TER_TSTTSSF1,      0x01},
 425         {R367TER_TSTTSSF2,      0x1f},
 426         {R367TER_TSTTSSF3,      0x00},
 427         {R367TER_TSTTS1,        0x00},
 428         {R367TER_TSTTS2,        0x1f},
 429         {R367TER_TSTTS3,        0x01},
 430         {R367TER_TSTTS4,        0x00},
 431         {R367TER_TSTTSRC,       0x00},
 432         {R367TER_TSTTSRS,       0x00},
 433         {R367TER_TSSTATEM,      0xb0},
 434         {R367TER_TSSTATEL,      0x40},
 435         {R367TER_TSCFGH,        0xC0},
 436         {R367TER_TSCFGM,        0xc0},/* for xc5000; was 0x00 */
 437         {R367TER_TSCFGL,        0x20},
 438         {R367TER_TSSYNC,        0x00},
 439         {R367TER_TSINSDELH,     0x00},
 440         {R367TER_TSINSDELM,     0x00},
 441         {R367TER_TSINSDELL,     0x00},
 442         {R367TER_TSDIVN,        0x03},
 443         {R367TER_TSDIVPM,       0x00},
 444         {R367TER_TSDIVPL,       0x00},
 445         {R367TER_TSDIVQM,       0x00},
 446         {R367TER_TSDIVQL,       0x00},
 447         {R367TER_TSDILSTKM,     0x00},
 448         {R367TER_TSDILSTKL,     0x00},
 449         {R367TER_TSSPEED,       0x40},/* for xc5000; was 0x6f */
 450         {R367TER_TSSTATUS,      0x81},
 451         {R367TER_TSSTATUS2,     0x6a},
 452         {R367TER_TSBITRATEM,    0x0f},
 453         {R367TER_TSBITRATEL,    0xc6},
 454         {R367TER_TSPACKLENM,    0x00},
 455         {R367TER_TSPACKLENL,    0xfc},
 456         {R367TER_TSBLOCLENM,    0x0a},
 457         {R367TER_TSBLOCLENL,    0x80},
 458         {R367TER_TSDLYH,        0x90},
 459         {R367TER_TSDLYM,        0x68},
 460         {R367TER_TSDLYL,        0x01},
 461         {R367TER_TSNPDAV,       0x00},
 462         {R367TER_TSBUFSTATH,    0x00},
 463         {R367TER_TSBUFSTATM,    0x00},
 464         {R367TER_TSBUFSTATL,    0x00},
 465         {R367TER_TSDEBUGM,      0xcf},
 466         {R367TER_TSDEBUGL,      0x1e},
 467         {R367TER_TSDLYSETH,     0x00},
 468         {R367TER_TSDLYSETM,     0x68},
 469         {R367TER_TSDLYSETL,     0x00},
 470         {R367TER_TSOBSCFG,      0x00},
 471         {R367TER_TSOBSM,        0x47},
 472         {R367TER_TSOBSL,        0x1f},
 473         {R367TER_ERRCTRL1,      0x95},
 474         {R367TER_ERRCNT1H,      0x80},
 475         {R367TER_ERRCNT1M,      0x00},
 476         {R367TER_ERRCNT1L,      0x00},
 477         {R367TER_ERRCTRL2,      0x95},
 478         {R367TER_ERRCNT2H,      0x00},
 479         {R367TER_ERRCNT2M,      0x00},
 480         {R367TER_ERRCNT2L,      0x00},
 481         {R367TER_FECSPY,        0x88},
 482         {R367TER_FSPYCFG,       0x2c},
 483         {R367TER_FSPYDATA,      0x3a},
 484         {R367TER_FSPYOUT,       0x06},
 485         {R367TER_FSTATUS,       0x61},
 486         {R367TER_FGOODPACK,     0xff},
 487         {R367TER_FPACKCNT,      0xff},
 488         {R367TER_FSPYMISC,      0x66},
 489         {R367TER_FBERCPT4,      0x00},
 490         {R367TER_FBERCPT3,      0x00},
 491         {R367TER_FBERCPT2,      0x36},
 492         {R367TER_FBERCPT1,      0x36},
 493         {R367TER_FBERCPT0,      0x14},
 494         {R367TER_FBERERR2,      0x00},
 495         {R367TER_FBERERR1,      0x03},
 496         {R367TER_FBERERR0,      0x28},
 497         {R367TER_FSTATESM,      0x00},
 498         {R367TER_FSTATESL,      0x02},
 499         {R367TER_FSPYBER,       0x00},
 500         {R367TER_FSPYDISTM,     0x01},
 501         {R367TER_FSPYDISTL,     0x9f},
 502         {R367TER_FSPYOBS7,      0xc9},
 503         {R367TER_FSPYOBS6,      0x99},
 504         {R367TER_FSPYOBS5,      0x08},
 505         {R367TER_FSPYOBS4,      0xec},
 506         {R367TER_FSPYOBS3,      0x01},
 507         {R367TER_FSPYOBS2,      0x0f},
 508         {R367TER_FSPYOBS1,      0xf5},
 509         {R367TER_FSPYOBS0,      0x08},
 510         {R367TER_SFDEMAP,       0x40},
 511         {R367TER_SFERROR,       0x00},
 512         {R367TER_SFAVSR,        0x30},
 513         {R367TER_SFECSTATUS,    0xcc},
 514         {R367TER_SFKDIV12,      0x20},
 515         {R367TER_SFKDIV23,      0x40},
 516         {R367TER_SFKDIV34,      0x20},
 517         {R367TER_SFKDIV56,      0x20},
 518         {R367TER_SFKDIV67,      0x00},
 519         {R367TER_SFKDIV78,      0x20},
 520         {R367TER_SFDILSTKM,     0x00},
 521         {R367TER_SFDILSTKL,     0x00},
 522         {R367TER_SFSTATUS,      0xb5},
 523         {R367TER_SFDLYH,        0x90},
 524         {R367TER_SFDLYM,        0x60},
 525         {R367TER_SFDLYL,        0x01},
 526         {R367TER_SFDLYSETH,     0xc0},
 527         {R367TER_SFDLYSETM,     0x60},
 528         {R367TER_SFDLYSETL,     0x00},
 529         {R367TER_SFOBSCFG,      0x00},
 530         {R367TER_SFOBSM,        0x47},
 531         {R367TER_SFOBSL,        0x05},
 532         {R367TER_SFECINFO,      0x40},
 533         {R367TER_SFERRCTRL,     0x74},
 534         {R367TER_SFERRCNTH,     0x80},
 535         {R367TER_SFERRCNTM ,    0x00},
 536         {R367TER_SFERRCNTL,     0x00},
 537         {R367TER_SYMBRATEM,     0x2f},
 538         {R367TER_SYMBRATEL,     0x50},
 539         {R367TER_SYMBSTATUS,    0x7f},
 540         {R367TER_SYMBCFG,       0x00},
 541         {R367TER_SYMBFIFOM,     0xf4},
 542         {R367TER_SYMBFIFOL,     0x0d},
 543         {R367TER_SYMBOFFSM,     0xf0},
 544         {R367TER_SYMBOFFSL,     0x2d},
 545         {R367TER_DEBUG_LT4,     0x00},
 546         {R367TER_DEBUG_LT5,     0x00},
 547         {R367TER_DEBUG_LT6,     0x00},
 548         {R367TER_DEBUG_LT7,     0x00},
 549         {R367TER_DEBUG_LT8,     0x00},
 550         {R367TER_DEBUG_LT9,     0x00},
 551 };
 552
 553 #define RF_LOOKUP_TABLE_SIZE  31
 554 #define RF_LOOKUP_TABLE2_SIZE 16
 555 /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
 556 static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
 557         {/*AGC1*/
 558                 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
 559                 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
 560                 76, 77, 78, 80, 83, 85, 88,
 561         }, {/*RF(dbm)*/
 562                 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
 563                 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
 564                 49, 50, 52, 53, 54, 55, 56,
 565         }
 566 };
 567 /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
 568 static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
 569         {/*AGC2*/
 570                 28, 29, 31, 32, 34, 35, 36, 37,
 571                 38, 39, 40, 41, 42, 43, 44, 45,
 572         }, {/*RF(dbm)*/
 573                 57, 58, 59, 60, 61, 62, 63, 64,
 574                 65, 66, 67, 68, 69, 70, 71, 72,
 575         }
 576 };
 577
 578 static struct st_register def0367cab[STV0367CAB_NBREGS] = {
 579         {R367CAB_ID,            0x60},
 580         {R367CAB_I2CRPT,        0xa0},
 581         /*{R367CAB_I2CRPT,      0x22},*/
 582         {R367CAB_TOPCTRL,       0x10},
 583         {R367CAB_IOCFG0,        0x80},
 584         {R367CAB_DAC0R,         0x00},
 585         {R367CAB_IOCFG1,        0x00},
 586         {R367CAB_DAC1R,         0x00},
 587         {R367CAB_IOCFG2,        0x00},
 588         {R367CAB_SDFR,          0x00},
 589         {R367CAB_AUX_CLK,       0x00},
 590         {R367CAB_FREESYS1,      0x00},
 591         {R367CAB_FREESYS2,      0x00},
 592         {R367CAB_FREESYS3,      0x00},
 593         {R367CAB_GPIO_CFG,      0x55},
 594         {R367CAB_GPIO_CMD,      0x01},
 595         {R367CAB_TSTRES,        0x00},
 596         {R367CAB_ANACTRL,       0x0d},/* was 0x00 need to check - I.M.L.*/
 597         {R367CAB_TSTBUS,        0x00},
 598         {R367CAB_RF_AGC1,       0xea},
 599         {R367CAB_RF_AGC2,       0x82},
 600         {R367CAB_ANADIGCTRL,    0x0b},
 601         {R367CAB_PLLMDIV,       0x01},
 602         {R367CAB_PLLNDIV,       0x08},
 603         {R367CAB_PLLSETUP,      0x18},
 604         {R367CAB_DUAL_AD12,     0x0C}, /* for xc5000 AGC voltage 1.6V */
 605         {R367CAB_TSTBIST,       0x00},
 606         {R367CAB_CTRL_1,        0x00},
 607         {R367CAB_CTRL_2,        0x03},
 608         {R367CAB_IT_STATUS1,    0x2b},
 609         {R367CAB_IT_STATUS2,    0x08},
 610         {R367CAB_IT_EN1,        0x00},
 611         {R367CAB_IT_EN2,        0x00},
 612         {R367CAB_CTRL_STATUS,   0x04},
 613         {R367CAB_TEST_CTL,      0x00},
 614         {R367CAB_AGC_CTL,       0x73},
 615         {R367CAB_AGC_IF_CFG,    0x50},
 616         {R367CAB_AGC_RF_CFG,    0x00},
 617         {R367CAB_AGC_PWM_CFG,   0x03},
 618         {R367CAB_AGC_PWR_REF_L, 0x5a},
 619         {R367CAB_AGC_PWR_REF_H, 0x00},
 620         {R367CAB_AGC_RF_TH_L,   0xff},
 621         {R367CAB_AGC_RF_TH_H,   0x07},
 622         {R367CAB_AGC_IF_LTH_L,  0x00},
 623         {R367CAB_AGC_IF_LTH_H,  0x08},
 624         {R367CAB_AGC_IF_HTH_L,  0xff},
 625         {R367CAB_AGC_IF_HTH_H,  0x07},
 626         {R367CAB_AGC_PWR_RD_L,  0xa0},
 627         {R367CAB_AGC_PWR_RD_M,  0xe9},
 628         {R367CAB_AGC_PWR_RD_H,  0x03},
 629         {R367CAB_AGC_PWM_IFCMD_L,       0xe4},
 630         {R367CAB_AGC_PWM_IFCMD_H,       0x00},
 631         {R367CAB_AGC_PWM_RFCMD_L,       0xff},
 632         {R367CAB_AGC_PWM_RFCMD_H,       0x07},
 633         {R367CAB_IQDEM_CFG,     0x01},
 634         {R367CAB_MIX_NCO_LL,    0x22},
 635         {R367CAB_MIX_NCO_HL,    0x96},
 636         {R367CAB_MIX_NCO_HH,    0x55},
 637         {R367CAB_SRC_NCO_LL,    0xff},
 638         {R367CAB_SRC_NCO_LH,    0x0c},
 639         {R367CAB_SRC_NCO_HL,    0xf5},
 640         {R367CAB_SRC_NCO_HH,    0x20},
 641         {R367CAB_IQDEM_GAIN_SRC_L,      0x06},
 642         {R367CAB_IQDEM_GAIN_SRC_H,      0x01},
 643         {R367CAB_IQDEM_DCRM_CFG_LL,     0xfe},
 644         {R367CAB_IQDEM_DCRM_CFG_LH,     0xff},
 645         {R367CAB_IQDEM_DCRM_CFG_HL,     0x0f},
 646         {R367CAB_IQDEM_DCRM_CFG_HH,     0x00},
 647         {R367CAB_IQDEM_ADJ_COEFF0,      0x34},
 648         {R367CAB_IQDEM_ADJ_COEFF1,      0xae},
 649         {R367CAB_IQDEM_ADJ_COEFF2,      0x46},
 650         {R367CAB_IQDEM_ADJ_COEFF3,      0x77},
 651         {R367CAB_IQDEM_ADJ_COEFF4,      0x96},
 652         {R367CAB_IQDEM_ADJ_COEFF5,      0x69},
 653         {R367CAB_IQDEM_ADJ_COEFF6,      0xc7},
 654         {R367CAB_IQDEM_ADJ_COEFF7,      0x01},
 655         {R367CAB_IQDEM_ADJ_EN,  0x04},
 656         {R367CAB_IQDEM_ADJ_AGC_REF,     0x94},
 657         {R367CAB_ALLPASSFILT1,  0xc9},
 658         {R367CAB_ALLPASSFILT2,  0x2d},
 659         {R367CAB_ALLPASSFILT3,  0xa3},
 660         {R367CAB_ALLPASSFILT4,  0xfb},
 661         {R367CAB_ALLPASSFILT5,  0xf6},
 662         {R367CAB_ALLPASSFILT6,  0x45},
 663         {R367CAB_ALLPASSFILT7,  0x6f},
 664         {R367CAB_ALLPASSFILT8,  0x7e},
 665         {R367CAB_ALLPASSFILT9,  0x05},
 666         {R367CAB_ALLPASSFILT10, 0x0a},
 667         {R367CAB_ALLPASSFILT11, 0x51},
 668         {R367CAB_TRL_AGC_CFG,   0x20},
 669         {R367CAB_TRL_LPF_CFG,   0x28},
 670         {R367CAB_TRL_LPF_ACQ_GAIN,      0x44},
 671         {R367CAB_TRL_LPF_TRK_GAIN,      0x22},
 672         {R367CAB_TRL_LPF_OUT_GAIN,      0x03},
 673         {R367CAB_TRL_LOCKDET_LTH,       0x04},
 674         {R367CAB_TRL_LOCKDET_HTH,       0x11},
 675         {R367CAB_TRL_LOCKDET_TRGVAL,    0x20},
 676         {R367CAB_IQ_QAM,        0x01},
 677         {R367CAB_FSM_STATE,     0xa0},
 678         {R367CAB_FSM_CTL,       0x08},
 679         {R367CAB_FSM_STS,       0x0c},
 680         {R367CAB_FSM_SNR0_HTH,  0x00},
 681         {R367CAB_FSM_SNR1_HTH,  0x00},
 682         {R367CAB_FSM_SNR2_HTH,  0x23},/* 0x00 */
 683         {R367CAB_FSM_SNR0_LTH,  0x00},
 684         {R367CAB_FSM_SNR1_LTH,  0x00},
 685         {R367CAB_FSM_EQA1_HTH,  0x00},
 686         {R367CAB_FSM_TEMPO,     0x32},
 687         {R367CAB_FSM_CONFIG,    0x03},
 688         {R367CAB_EQU_I_TESTTAP_L,       0x11},
 689         {R367CAB_EQU_I_TESTTAP_M,       0x00},
 690         {R367CAB_EQU_I_TESTTAP_H,       0x00},
 691         {R367CAB_EQU_TESTAP_CFG,        0x00},
 692         {R367CAB_EQU_Q_TESTTAP_L,       0xff},
 693         {R367CAB_EQU_Q_TESTTAP_M,       0x00},
 694         {R367CAB_EQU_Q_TESTTAP_H,       0x00},
 695         {R367CAB_EQU_TAP_CTRL,  0x00},
 696         {R367CAB_EQU_CTR_CRL_CONTROL_L, 0x11},
 697         {R367CAB_EQU_CTR_CRL_CONTROL_H, 0x05},
 698         {R367CAB_EQU_CTR_HIPOW_L,       0x00},
 699         {R367CAB_EQU_CTR_HIPOW_H,       0x00},
 700         {R367CAB_EQU_I_EQU_LO,  0xef},
 701         {R367CAB_EQU_I_EQU_HI,  0x00},
 702         {R367CAB_EQU_Q_EQU_LO,  0xee},
 703         {R367CAB_EQU_Q_EQU_HI,  0x00},
 704         {R367CAB_EQU_MAPPER,    0xc5},
 705         {R367CAB_EQU_SWEEP_RATE,        0x80},
 706         {R367CAB_EQU_SNR_LO,    0x64},
 707         {R367CAB_EQU_SNR_HI,    0x03},
 708         {R367CAB_EQU_GAMMA_LO,  0x00},
 709         {R367CAB_EQU_GAMMA_HI,  0x00},
 710         {R367CAB_EQU_ERR_GAIN,  0x36},
 711         {R367CAB_EQU_RADIUS,    0xaa},
 712         {R367CAB_EQU_FFE_MAINTAP,       0x00},
 713         {R367CAB_EQU_FFE_LEAKAGE,       0x63},
 714         {R367CAB_EQU_FFE_MAINTAP_POS,   0xdf},
 715         {R367CAB_EQU_GAIN_WIDE, 0x88},
 716         {R367CAB_EQU_GAIN_NARROW,       0x41},
 717         {R367CAB_EQU_CTR_LPF_GAIN,      0xd1},
 718         {R367CAB_EQU_CRL_LPF_GAIN,      0xa7},
 719         {R367CAB_EQU_GLOBAL_GAIN,       0x06},
 720         {R367CAB_EQU_CRL_LD_SEN,        0x85},
 721         {R367CAB_EQU_CRL_LD_VAL,        0xe2},
 722         {R367CAB_EQU_CRL_TFR,   0x20},
 723         {R367CAB_EQU_CRL_BISTH_LO,      0x00},
 724         {R367CAB_EQU_CRL_BISTH_HI,      0x00},
 725         {R367CAB_EQU_SWEEP_RANGE_LO,    0x00},
 726         {R367CAB_EQU_SWEEP_RANGE_HI,    0x00},
 727         {R367CAB_EQU_CRL_LIMITER,       0x40},
 728         {R367CAB_EQU_MODULUS_MAP,       0x90},
 729         {R367CAB_EQU_PNT_GAIN,  0xa7},
 730         {R367CAB_FEC_AC_CTR_0,  0x16},
 731         {R367CAB_FEC_AC_CTR_1,  0x0b},
 732         {R367CAB_FEC_AC_CTR_2,  0x88},
 733         {R367CAB_FEC_AC_CTR_3,  0x02},
 734         {R367CAB_FEC_STATUS,    0x12},
 735         {R367CAB_RS_COUNTER_0,  0x7d},
 736         {R367CAB_RS_COUNTER_1,  0xd0},
 737         {R367CAB_RS_COUNTER_2,  0x19},
 738         {R367CAB_RS_COUNTER_3,  0x0b},
 739         {R367CAB_RS_COUNTER_4,  0xa3},
 740         {R367CAB_RS_COUNTER_5,  0x00},
 741         {R367CAB_BERT_0,        0x01},
 742         {R367CAB_BERT_1,        0x25},
 743         {R367CAB_BERT_2,        0x41},
 744         {R367CAB_BERT_3,        0x39},
 745         {R367CAB_OUTFORMAT_0,   0xc2},
 746         {R367CAB_OUTFORMAT_1,   0x22},
 747         {R367CAB_SMOOTHER_2,    0x28},
 748         {R367CAB_TSMF_CTRL_0,   0x01},
 749         {R367CAB_TSMF_CTRL_1,   0xc6},
 750         {R367CAB_TSMF_CTRL_3,   0x43},
 751         {R367CAB_TS_ON_ID_0,    0x00},
 752         {R367CAB_TS_ON_ID_1,    0x00},
 753         {R367CAB_TS_ON_ID_2,    0x00},
 754         {R367CAB_TS_ON_ID_3,    0x00},
 755         {R367CAB_RE_STATUS_0,   0x00},
 756         {R367CAB_RE_STATUS_1,   0x00},
 757         {R367CAB_RE_STATUS_2,   0x00},
 758         {R367CAB_RE_STATUS_3,   0x00},
 759         {R367CAB_TS_STATUS_0,   0x00},
 760         {R367CAB_TS_STATUS_1,   0x00},
 761         {R367CAB_TS_STATUS_2,   0xa0},
 762         {R367CAB_TS_STATUS_3,   0x00},
 763         {R367CAB_T_O_ID_0,      0x00},
 764         {R367CAB_T_O_ID_1,      0x00},
 765         {R367CAB_T_O_ID_2,      0x00},
 766         {R367CAB_T_O_ID_3,      0x00},
 767 };
 768
 769 static
 770 int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
 771 {
 772         u8 buf[MAX_XFER_SIZE];
 773         struct i2c_msg msg = {
 774                 .addr = state->config->demod_address,
 775                 .flags = 0,
 776                 .buf = buf,
 777                 .len = len + 2
 778         };
 779         int ret;
 780
 781         if (2 + len > sizeof(buf)) {
 782                 printk(KERN_WARNING
 783                        "%s: i2c wr reg=%04x: len=%d is too big!\n",
 784                        KBUILD_MODNAME, reg, len);
 785                 return -EINVAL;
 786         }
 787
 788
 789         buf[0] = MSB(reg);
 790         buf[1] = LSB(reg);
 791         memcpy(buf + 2, data, len);
 792
 793         if (i2cdebug)
 794                 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
 795                         state->config->demod_address, reg, buf[2]);
 796
 797         ret = i2c_transfer(state->i2c, &msg, 1);
 798         if (ret != 1)
 799                 printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n",
 800                         __func__, state->config->demod_address, reg, buf[2]);
 801
 802         return (ret != 1) ? -EREMOTEIO : 0;
 803 }
 804
 805 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
 806 {
 807         return stv0367_writeregs(state, reg, &data, 1);
 808 }
 809
 810 static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
 811 {
 812         u8 b0[] = { 0, 0 };
 813         u8 b1[] = { 0 };
 814         struct i2c_msg msg[] = {
 815                 {
 816                         .addr = state->config->demod_address,
 817                         .flags = 0,
 818                         .buf = b0,
 819                         .len = 2
 820                 }, {
 821                         .addr = state->config->demod_address,
 822                         .flags = I2C_M_RD,
 823                         .buf = b1,
 824                         .len = 1
 825                 }
 826         };
 827         int ret;
 828
 829         b0[0] = MSB(reg);
 830         b0[1] = LSB(reg);
 831
 832         ret = i2c_transfer(state->i2c, msg, 2);
 833         if (ret != 2)
 834                 printk(KERN_ERR "%s: i2c read error ([%02x] %02x: %02x)\n",
 835                         __func__, state->config->demod_address, reg, b1[0]);
 836
 837         if (i2cdebug)
 838                 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
 839                         state->config->demod_address, reg, b1[0]);
 840
 841         return b1[0];
 842 }
 843
 844 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
 845 {
 846         u8 position = 0, i = 0;
 847
 848         (*mask) = label & 0xff;
 849
 850         while ((position == 0) && (i < 8)) {
 851                 position = ((*mask) >> i) & 0x01;
 852                 i++;
 853         }
 854
 855         (*pos) = (i - 1);
 856 }
 857
 858 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
 859 {
 860         u8 reg, mask, pos;
 861
 862         reg = stv0367_readreg(state, (label >> 16) & 0xffff);
 863         extract_mask_pos(label, &mask, &pos);
 864
 865         val = mask & (val << pos);
 866
 867         reg = (reg & (~mask)) | val;
 868         stv0367_writereg(state, (label >> 16) & 0xffff, reg);
 869
 870 }
 871
 872 static void stv0367_setbits(u8 *reg, u32 label, u8 val)
 873 {
 874         u8 mask, pos;
 875
 876         extract_mask_pos(label, &mask, &pos);
 877
 878         val = mask & (val << pos);
 879
 880         (*reg) = ((*reg) & (~mask)) | val;
 881 }
 882
 883 static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
 884 {
 885         u8 val = 0xff;
 886         u8 mask, pos;
 887
 888         extract_mask_pos(label, &mask, &pos);
 889
 890         val = stv0367_readreg(state, label >> 16);
 891         val = (val & mask) >> pos;
 892
 893         return val;
 894 }
 895
 896 #if 0 /* Currently, unused */
 897 static u8 stv0367_getbits(u8 reg, u32 label)
 898 {
 899         u8 mask, pos;
 900
 901         extract_mask_pos(label, &mask, &pos);
 902
 903         return (reg & mask) >> pos;
 904 }
 905 #endif
 906 static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
 907 {
 908         struct stv0367_state *state = fe->demodulator_priv;
 909         u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
 910
 911         dprintk("%s:\n", __func__);
 912
 913         if (enable) {
 914                 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
 915                 stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
 916         } else {
 917                 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
 918                 stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
 919         }
 920
 921         stv0367_writereg(state, R367TER_I2CRPT, tmp);
 922
 923         return 0;
 924 }
 925
 926 static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
 927 {
 928         struct dvb_frontend_ops *frontend_ops = &fe->ops;
 929         struct dvb_tuner_ops    *tuner_ops = &frontend_ops->tuner_ops;
 930         u32 freq = 0;
 931         int err = 0;
 932
 933         dprintk("%s:\n", __func__);
 934
 935         if (tuner_ops->get_frequency) {
 936                 err = tuner_ops->get_frequency(fe, &freq);
 937                 if (err < 0) {
 938                         printk(KERN_ERR "%s: Invalid parameter\n", __func__);
 939                         return err;
 940                 }
 941
 942                 dprintk("%s: frequency=%d\n", __func__, freq);
 943
 944         } else
 945                 return -1;
 946
 947         return freq;
 948 }
 949
 950 static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
 951         {
 952                 {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
 953                 {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
 954                 {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
 955                 {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
 956                 {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
 957                 {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
 958         }, {
 959                 {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
 960                 {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
 961                 {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
 962                 {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
 963                 {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
 964                 {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
 965         }, {
 966                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
 967                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 968                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 969                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 970                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 971                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
 972         }
 973 };
 974
 975 static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
 976         {
 977                 {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
 978                 {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
 979                 {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
 980                 {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
 981                 {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
 982                 {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
 983         }, {
 984                 {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
 985                 {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
 986                 {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
 987                 {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
 988                 {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
 989                 {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
 990         }, {
 991                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
 992                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 993                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 994                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 995                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
 996                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
 997         }
 998 };
 999
1000 static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
1001         {
1002                 {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
1003                 {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
1004                 {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
1005                 {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
1006                 {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
1007                 {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
1008         }, {
1009                 {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
1010                 {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
1011                 {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
1012                 {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
1013                 {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
1014                 {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
1015
1016         }, {
1017                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
1018                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1019                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1020                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1021                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1022                 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
1023         }
1024 };
1025
1026 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
1027 {
1028         u32 mclk_Hz = 0; /* master clock frequency (Hz) */
1029         u32 m, n, p;
1030
1031         dprintk("%s:\n", __func__);
1032
1033         if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
1034                 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
1035                 if (n == 0)
1036                         n = n + 1;
1037
1038                 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
1039                 if (m == 0)
1040                         m = m + 1;
1041
1042                 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
1043                 if (p > 5)
1044                         p = 5;
1045
1046                 mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
1047
1048                 dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
1049                                 n, m, p, mclk_Hz, ExtClk_Hz);
1050         } else
1051                 mclk_Hz = ExtClk_Hz;
1052
1053         dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
1054
1055         return mclk_Hz;
1056 }
1057
1058 static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
1059                                 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
1060 {
1061         int i, j, k, freq;
1062
1063         dprintk("%s:\n", __func__);
1064
1065         freq = stv0367ter_get_mclk(state, DemodXtal);
1066
1067         if (freq == 53125000)
1068                 k = 1; /* equivalent to Xtal 25M on 362*/
1069         else if (freq == 54000000)
1070                 k = 0; /* equivalent to Xtal 27M on 362*/
1071         else if (freq == 52500000)
1072                 k = 2; /* equivalent to Xtal 30M on 362*/
1073         else
1074                 return 0;
1075
1076         for (i = 1; i <= 6; i++) {
1077                 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
1078
1079                 for (j = 1; j <= 5; j++) {
1080                         stv0367_writereg(state,
1081                                 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
1082                                 MSB(CellsCoeffs[k][i-1][j-1]));
1083                         stv0367_writereg(state,
1084                                 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
1085                                 LSB(CellsCoeffs[k][i-1][j-1]));
1086                 }
1087         }
1088
1089         return 1;
1090
1091 }
1092
1093 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
1094 {
1095         dprintk("%s:\n", __func__);
1096
1097         stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
1098
1099         /* Lock detect 1 */
1100         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
1101         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1102         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1103
1104         /* Lock detect 2 */
1105         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
1106         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1107         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1108
1109         /* Lock detect 3 */
1110         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
1111         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1112         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1113
1114         /* Lock detect 4 */
1115         stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
1116         stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1117         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1118
1119 }
1120
1121 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
1122                                                         u32 DemodXtalValue)
1123 {
1124         dprintk("%s:\n", __func__);
1125
1126         stv0367_writebits(state, F367TER_NRST_IIR, 0);
1127
1128         switch (Bandwidth) {
1129         case 6:
1130                 if (!stv0367ter_filt_coeff_init(state,
1131                                 CellsCoeffs_6MHz_367cofdm,
1132                                 DemodXtalValue))
1133                         return 0;
1134                 break;
1135         case 7:
1136                 if (!stv0367ter_filt_coeff_init(state,
1137                                 CellsCoeffs_7MHz_367cofdm,
1138                                 DemodXtalValue))
1139                         return 0;
1140                 break;
1141         case 8:
1142                 if (!stv0367ter_filt_coeff_init(state,
1143                                 CellsCoeffs_8MHz_367cofdm,
1144                                 DemodXtalValue))
1145                         return 0;
1146                 break;
1147         default:
1148                 return 0;
1149         }
1150
1151         stv0367_writebits(state, F367TER_NRST_IIR, 1);
1152
1153         return 1;
1154 }
1155
1156 static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
1157 {
1158
1159         u8 com_n;
1160
1161         dprintk("%s:\n", __func__);
1162
1163         com_n = stv0367_readbits(state, F367TER_COM_N);
1164
1165         stv0367_writebits(state, F367TER_COM_N, 0x07);
1166
1167         stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
1168         stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
1169
1170         stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
1171         stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
1172
1173         stv0367_writebits(state, F367TER_COM_N, com_n);
1174
1175 }
1176
1177 static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
1178 {
1179         int local_tempo = 0;
1180         switch (mode) {
1181         case 0:
1182                 local_tempo = tempo1;
1183                 break;
1184         case 1:
1185                 local_tempo = tempo2;
1186                 break ;
1187
1188         case 2:
1189                 local_tempo = tempo3;
1190                 break;
1191
1192         default:
1193                 break;
1194         }
1195         /*      msleep(local_tempo);  */
1196         return local_tempo;
1197 }
1198
1199 static enum
1200 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
1201 {
1202         int wd = 100;
1203         unsigned short int SYR_var;
1204         s32 SYRStatus;
1205
1206         dprintk("%s:\n", __func__);
1207
1208         SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1209
1210         while ((!SYR_var) && (wd > 0)) {
1211                 usleep_range(2000, 3000);
1212                 wd -= 2;
1213                 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1214         }
1215
1216         if (!SYR_var)
1217                 SYRStatus = FE_TER_NOSYMBOL;
1218         else
1219                 SYRStatus =  FE_TER_SYMBOLOK;
1220
1221         dprintk("stv0367ter_check_syr SYRStatus %s\n",
1222                                 SYR_var == 0 ? "No Symbol" : "OK");
1223
1224         return SYRStatus;
1225 }
1226
1227 static enum
1228 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
1229                                                                 s32 FFTmode)
1230 {
1231
1232         s32  CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
1233         int wd = 0;
1234
1235         dprintk("%s:\n", __func__);
1236
1237         switch (FFTmode) {
1238         case 0: /*2k mode*/
1239                 CPAMPMin = 20;
1240                 wd = 10;
1241                 break;
1242         case 1: /*8k mode*/
1243                 CPAMPMin = 80;
1244                 wd = 55;
1245                 break;
1246         case 2: /*4k mode*/
1247                 CPAMPMin = 40;
1248                 wd = 30;
1249                 break;
1250         default:
1251                 CPAMPMin = 0xffff;  /*drives to NOCPAMP */
1252                 break;
1253         }
1254
1255         dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
1256
1257         CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1258         while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
1259                 usleep_range(1000, 2000);
1260                 wd -= 1;
1261                 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1262                 /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
1263         }
1264         dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
1265         if (CPAMPvalue < CPAMPMin) {
1266                 CPAMPStatus = FE_TER_NOCPAMP;
1267                 printk(KERN_ERR "CPAMP failed\n");
1268         } else {
1269                 printk(KERN_ERR "CPAMP OK !\n");
1270                 CPAMPStatus = FE_TER_CPAMPOK;
1271         }
1272
1273         return CPAMPStatus;
1274 }
1275
1276 static enum stv0367_ter_signal_type
1277 stv0367ter_lock_algo(struct stv0367_state *state)
1278 {
1279         enum stv0367_ter_signal_type ret_flag;
1280         short int wd, tempo;
1281         u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
1282         u8 tmp, tmp2;
1283
1284         dprintk("%s:\n", __func__);
1285
1286         if (state == NULL)
1287                 return FE_TER_SWNOK;
1288
1289         try = 0;
1290         do {
1291                 ret_flag = FE_TER_LOCKOK;
1292
1293                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1294
1295                 if (state->config->if_iq_mode != 0)
1296                         stv0367_writebits(state, F367TER_COM_N, 0x07);
1297
1298                 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
1299                 stv0367_writebits(state, F367TER_MODE, 0);
1300                 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
1301                 usleep_range(5000, 10000);
1302
1303                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1304
1305
1306                 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
1307                         return FE_TER_NOSYMBOL;
1308                 else { /*
1309                         if chip locked on wrong mode first try,
1310                         it must lock correctly second try */
1311                         mode = stv0367_readbits(state, F367TER_SYR_MODE);
1312                         if (stv0367ter_check_cpamp(state, mode) ==
1313                                                         FE_TER_NOCPAMP) {
1314                                 if (try == 0)
1315                                         ret_flag = FE_TER_NOCPAMP;
1316
1317                         }
1318                 }
1319
1320                 try++;
1321         } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
1322
1323         tmp  = stv0367_readreg(state, R367TER_SYR_STAT);
1324         tmp2 = stv0367_readreg(state, R367TER_STATUS);
1325         dprintk("state=%p\n", state);
1326         dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
1327                                                         mode, tmp, tmp2);
1328
1329         tmp  = stv0367_readreg(state, R367TER_PRVIT);
1330         tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
1331         dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
1332
1333         tmp  = stv0367_readreg(state, R367TER_GAIN_SRC1);
1334         dprintk("GAIN_SRC1=0x%x\n", tmp);
1335
1336         if ((mode != 0) && (mode != 1) && (mode != 2))
1337                 return FE_TER_SWNOK;
1338
1339         /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
1340
1341         /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
1342         and set channel predictor in automatic */
1343 #if 0
1344         switch (guard) {
1345
1346         case 0:
1347         case 1:
1348                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1349                 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
1350                 break;
1351         case 2:
1352         case 3:
1353                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1354                 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1355                 break;
1356
1357         default:
1358                 return FE_TER_SWNOK;
1359         }
1360 #endif
1361
1362         /*reset fec an reedsolo FOR 367 only*/
1363         stv0367_writebits(state, F367TER_RST_SFEC, 1);
1364         stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
1365         usleep_range(1000, 2000);
1366         stv0367_writebits(state, F367TER_RST_SFEC, 0);
1367         stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
1368
1369         u_var1 = stv0367_readbits(state, F367TER_LK);
1370         u_var2 = stv0367_readbits(state, F367TER_PRF);
1371         u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1372         /*      u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
1373
1374         wd = stv0367ter_duration(mode, 125, 500, 250);
1375         tempo = stv0367ter_duration(mode, 4, 16, 8);
1376
1377         /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4))  && (wd>=0)) */
1378         while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
1379                 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1380                 wd -= tempo;
1381                 u_var1 = stv0367_readbits(state, F367TER_LK);
1382                 u_var2 = stv0367_readbits(state, F367TER_PRF);
1383                 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1384                 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
1385         }
1386
1387         if (!u_var1)
1388                 return FE_TER_NOLOCK;
1389
1390
1391         if (!u_var2)
1392                 return FE_TER_NOPRFOUND;
1393
1394         if (!u_var3)
1395                 return FE_TER_NOTPS;
1396
1397         guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1398         stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1399         switch (guard) {
1400         case 0:
1401         case 1:
1402                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1403                 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
1404                 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
1405                 break;
1406         case 2:
1407         case 3:
1408                 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1409                 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
1410                 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
1411                 break;
1412
1413         default:
1414                 return FE_TER_SWNOK;
1415         }
1416
1417         /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
1418         if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
1419                         (mode == 1) &&
1420                         (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
1421                 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
1422                 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
1423                 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
1424         } else
1425                 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
1426
1427         wd = stv0367ter_duration(mode, 125, 500, 250);
1428         u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1429
1430         while ((!u_var4) && (wd >= 0)) {
1431                 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1432                 wd -= tempo;
1433                 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1434         }
1435
1436         if (!u_var4)
1437                 return FE_TER_NOLOCK;
1438
1439         /* for 367 leave COM_N at 0x7 for IQ_mode*/
1440         /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
1441                 tempo=0;
1442                 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
1443                 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
1444                         ChipWaitOrAbort(state,1);
1445                         tempo+=1;
1446                 }
1447
1448                 stv0367_writebits(state,F367TER_COM_N,0x17);
1449         } */
1450
1451         stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
1452
1453         dprintk("FE_TER_LOCKOK !!!\n");
1454
1455         return  FE_TER_LOCKOK;
1456
1457 }
1458
1459 static void stv0367ter_set_ts_mode(struct stv0367_state *state,
1460                                         enum stv0367_ts_mode PathTS)
1461 {
1462
1463         dprintk("%s:\n", __func__);
1464
1465         if (state == NULL)
1466                 return;
1467
1468         stv0367_writebits(state, F367TER_TS_DIS, 0);
1469         switch (PathTS) {
1470         default:
1471                 /*for removing warning :default we can assume in parallel mode*/
1472         case STV0367_PARALLEL_PUNCT_CLOCK:
1473                 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
1474                 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
1475                 break;
1476         case STV0367_SERIAL_PUNCT_CLOCK:
1477                 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
1478                 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
1479                 break;
1480         }
1481 }
1482
1483 static void stv0367ter_set_clk_pol(struct stv0367_state *state,
1484                                         enum stv0367_clk_pol clock)
1485 {
1486
1487         dprintk("%s:\n", __func__);
1488
1489         if (state == NULL)
1490                 return;
1491
1492         switch (clock) {
1493         case STV0367_RISINGEDGE_CLOCK:
1494                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
1495                 break;
1496         case STV0367_FALLINGEDGE_CLOCK:
1497                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1498                 break;
1499                 /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
1500         default:
1501                 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1502                 break;
1503         }
1504 }
1505
1506 #if 0
1507 static void stv0367ter_core_sw(struct stv0367_state *state)
1508 {
1509
1510         dprintk("%s:\n", __func__);
1511
1512         stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1513         stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1514         msleep(350);
1515 }
1516 #endif
1517 static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
1518 {
1519         struct stv0367_state *state = fe->demodulator_priv;
1520
1521         dprintk("%s:\n", __func__);
1522
1523         if (standby_on) {
1524                 stv0367_writebits(state, F367TER_STDBY, 1);
1525                 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
1526                 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
1527         } else {
1528                 stv0367_writebits(state, F367TER_STDBY, 0);
1529                 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
1530                 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
1531         }
1532
1533         return 0;
1534 }
1535
1536 static int stv0367ter_sleep(struct dvb_frontend *fe)
1537 {
1538         return stv0367ter_standby(fe, 1);
1539 }
1540
1541 static int stv0367ter_init(struct dvb_frontend *fe)
1542 {
1543         struct stv0367_state *state = fe->demodulator_priv;
1544         struct stv0367ter_state *ter_state = state->ter_state;
1545         int i;
1546
1547         dprintk("%s:\n", __func__);
1548
1549         ter_state->pBER = 0;
1550
1551         for (i = 0; i < STV0367TER_NBREGS; i++)
1552                 stv0367_writereg(state, def0367ter[i].addr,
1553                                         def0367ter[i].value);
1554
1555         switch (state->config->xtal) {
1556                 /*set internal freq to 53.125MHz */
1557         case 16000000:
1558                 stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
1559                 stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
1560                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1561                 break;
1562         case 25000000:
1563                 stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
1564                 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1565                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1566                 break;
1567         default:
1568         case 27000000:
1569                 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
1570                 stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
1571                 stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
1572                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1573                 break;
1574         case 30000000:
1575                 stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
1576                 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1577                 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1578                 break;
1579         }
1580
1581         stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
1582         stv0367_writereg(state, R367TER_ANACTRL, 0x00);
1583
1584         /*Set TS1 and TS2 to serial or parallel mode */
1585         stv0367ter_set_ts_mode(state, state->config->ts_mode);
1586         stv0367ter_set_clk_pol(state, state->config->clk_pol);
1587
1588         state->chip_id = stv0367_readreg(state, R367TER_ID);
1589         ter_state->first_lock = 0;
1590         ter_state->unlock_counter = 2;
1591
1592         return 0;
1593 }
1594
1595 static int stv0367ter_algo(struct dvb_frontend *fe)
1596 {
1597         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1598         struct stv0367_state *state = fe->demodulator_priv;
1599         struct stv0367ter_state *ter_state = state->ter_state;
1600         int offset = 0, tempo = 0;
1601         u8 u_var;
1602         u8 /*constell,*/ counter;
1603         s8 step;
1604         s32 timing_offset = 0;
1605         u32 trl_nomrate = 0, InternalFreq = 0, temp = 0;
1606
1607         dprintk("%s:\n", __func__);
1608
1609         ter_state->frequency = p->frequency;
1610         ter_state->force = FE_TER_FORCENONE
1611                         + stv0367_readbits(state, F367TER_FORCE) * 2;
1612         ter_state->if_iq_mode = state->config->if_iq_mode;
1613         switch (state->config->if_iq_mode) {
1614         case FE_TER_NORMAL_IF_TUNER:  /* Normal IF mode */
1615                 dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1616                 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1617                 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1618                 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1619                 break;
1620         case FE_TER_LONGPATH_IF_TUNER:  /* Long IF mode */
1621                 dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1622                 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1623                 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1624                 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1625                 break;
1626         case FE_TER_IQ_TUNER:  /* IQ mode */
1627                 dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1628                 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1629                 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1630                 break;
1631         default:
1632                 printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1633                 return -EINVAL;
1634         }
1635
1636         usleep_range(5000, 7000);
1637
1638         switch (p->inversion) {
1639         case INVERSION_AUTO:
1640         default:
1641                 dprintk("%s: inversion AUTO\n", __func__);
1642                 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1643                         stv0367_writebits(state, F367TER_IQ_INVERT,
1644                                                 ter_state->sense);
1645                 else
1646                         stv0367_writebits(state, F367TER_INV_SPECTR,
1647                                                 ter_state->sense);
1648
1649                 break;
1650         case INVERSION_ON:
1651         case INVERSION_OFF:
1652                 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1653                         stv0367_writebits(state, F367TER_IQ_INVERT,
1654                                                 p->inversion);
1655                 else
1656                         stv0367_writebits(state, F367TER_INV_SPECTR,
1657                                                 p->inversion);
1658
1659                 break;
1660         }
1661
1662         if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1663                                 (ter_state->pBW != ter_state->bw)) {
1664                 stv0367ter_agc_iir_lock_detect_set(state);
1665
1666                 /*set fine agc target to 180 for LPIF or IQ mode*/
1667                 /* set Q_AGCTarget */
1668                 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1669                 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1670                 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1671
1672                 /* set Q_AGCTarget */
1673                 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1674                 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1675                 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1676
1677                 if (!stv0367_iir_filt_init(state, ter_state->bw,
1678                                                 state->config->xtal))
1679                         return -EINVAL;
1680                 /*set IIR filter once for 6,7 or 8MHz BW*/
1681                 ter_state->pBW = ter_state->bw;
1682
1683                 stv0367ter_agc_iir_rst(state);
1684         }
1685
1686         if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1687                 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1688         else
1689                 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1690
1691         InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1692         temp = (int)
1693                 ((((ter_state->bw * 64 * (1 << 15) * 100)
1694                                                 / (InternalFreq)) * 10) / 7);
1695
1696         stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1697         temp = temp / 2;
1698         stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1699         stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1700
1701         temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1702                         stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1703                         stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1704         temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1705         stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1706         stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1707         temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1708                         stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1709
1710         temp = (int)
1711                 ((InternalFreq - state->config->if_khz) * (1 << 16)
1712                                                         / (InternalFreq));
1713
1714         dprintk("DEROT temp=0x%x\n", temp);
1715         stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1716         stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1717
1718         ter_state->echo_pos = 0;
1719         ter_state->ucblocks = 0; /* liplianin */
1720         ter_state->pBER = 0; /* liplianin */
1721         stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1722
1723         if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1724                 return 0;
1725
1726         ter_state->state = FE_TER_LOCKOK;
1727
1728         ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1729         ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1730
1731         ter_state->first_lock = 1; /* we know sense now :) */
1732
1733         ter_state->agc_val =
1734                         (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1735                         (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1736                         stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1737                         (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1738
1739         /* Carrier offset calculation */
1740         stv0367_writebits(state, F367TER_FREEZE, 1);
1741         offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1742         offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1743         offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1744         stv0367_writebits(state, F367TER_FREEZE, 0);
1745         if (offset > 8388607)
1746                 offset -= 16777216;
1747
1748         offset = offset * 2 / 16384;
1749
1750         if (ter_state->mode == FE_TER_MODE_2K)
1751                 offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1752         else if (ter_state->mode == FE_TER_MODE_4K)
1753                 offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1754         else  if (ter_state->mode == FE_TER_MODE_8K)
1755                 offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1756
1757         if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1758                 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1759                                 (stv0367_readbits(state,
1760                                         F367TER_STATUS_INV_SPECRUM) == 1)))
1761                         offset = offset * -1;
1762         }
1763
1764         if (ter_state->bw == 6)
1765                 offset = (offset * 6) / 8;
1766         else if (ter_state->bw == 7)
1767                 offset = (offset * 7) / 8;
1768
1769         ter_state->frequency += offset;
1770
1771         tempo = 10;  /* exit even if timing_offset stays null */
1772         while ((timing_offset == 0) && (tempo > 0)) {
1773                 usleep_range(10000, 20000);     /*was 20ms  */
1774                 /* fine tuning of timing offset if required */
1775                 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1776                                 + 256 * stv0367_readbits(state,
1777                                                         F367TER_TRL_TOFFSET_HI);
1778                 if (timing_offset >= 32768)
1779                         timing_offset -= 65536;
1780                 trl_nomrate = (512 * stv0367_readbits(state,
1781                                                         F367TER_TRL_NOMRATE_HI)
1782                         + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1783                         + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1784
1785                 timing_offset = ((signed)(1000000 / trl_nomrate) *
1786                                                         timing_offset) / 2048;
1787                 tempo--;
1788         }
1789
1790         if (timing_offset <= 0) {
1791                 timing_offset = (timing_offset - 11) / 22;
1792                 step = -1;
1793         } else {
1794                 timing_offset = (timing_offset + 11) / 22;
1795                 step = 1;
1796         }
1797
1798         for (counter = 0; counter < abs(timing_offset); counter++) {
1799                 trl_nomrate += step;
1800                 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1801                                                 trl_nomrate % 2);
1802                 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1803                                                 trl_nomrate / 2);
1804                 usleep_range(1000, 2000);
1805         }
1806
1807         usleep_range(5000, 6000);
1808         /* unlocks could happen in case of trl centring big step,
1809         then a core off/on restarts demod */
1810         u_var = stv0367_readbits(state, F367TER_LK);
1811
1812         if (!u_var) {
1813                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1814                 msleep(20);
1815                 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1816         }
1817
1818         return 0;
1819 }
1820
1821 static int stv0367ter_set_frontend(struct dvb_frontend *fe)
1822 {
1823         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1824         struct stv0367_state *state = fe->demodulator_priv;
1825         struct stv0367ter_state *ter_state = state->ter_state;
1826
1827         /*u8 trials[2]; */
1828         s8 num_trials, index;
1829         u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1830
1831         stv0367ter_init(fe);
1832
1833         if (fe->ops.tuner_ops.set_params) {
1834                 if (fe->ops.i2c_gate_ctrl)
1835                         fe->ops.i2c_gate_ctrl(fe, 1);
1836                 fe->ops.tuner_ops.set_params(fe);
1837                 if (fe->ops.i2c_gate_ctrl)
1838                         fe->ops.i2c_gate_ctrl(fe, 0);
1839         }
1840
1841         switch (p->transmission_mode) {
1842         default:
1843         case TRANSMISSION_MODE_AUTO:
1844         case TRANSMISSION_MODE_2K:
1845                 ter_state->mode = FE_TER_MODE_2K;
1846                 break;
1847 /*      case TRANSMISSION_MODE_4K:
1848                 pLook.mode = FE_TER_MODE_4K;
1849                 break;*/
1850         case TRANSMISSION_MODE_8K:
1851                 ter_state->mode = FE_TER_MODE_8K;
1852                 break;
1853         }
1854
1855         switch (p->guard_interval) {
1856         default:
1857         case GUARD_INTERVAL_1_32:
1858         case GUARD_INTERVAL_1_16:
1859         case GUARD_INTERVAL_1_8:
1860         case GUARD_INTERVAL_1_4:
1861                 ter_state->guard = p->guard_interval;
1862                 break;
1863         case GUARD_INTERVAL_AUTO:
1864                 ter_state->guard = GUARD_INTERVAL_1_32;
1865                 break;
1866         }
1867
1868         switch (p->bandwidth_hz) {
1869         case 6000000:
1870                 ter_state->bw = FE_TER_CHAN_BW_6M;
1871                 break;
1872         case 7000000:
1873                 ter_state->bw = FE_TER_CHAN_BW_7M;
1874                 break;
1875         case 8000000:
1876         default:
1877                 ter_state->bw = FE_TER_CHAN_BW_8M;
1878         }
1879
1880         ter_state->hierarchy = FE_TER_HIER_NONE;
1881
1882         switch (p->inversion) {
1883         case INVERSION_OFF:
1884         case INVERSION_ON:
1885                 num_trials = 1;
1886                 break;
1887         default:
1888                 num_trials = 2;
1889                 if (ter_state->first_lock)
1890                         num_trials = 1;
1891                 break;
1892         }
1893
1894         ter_state->state = FE_TER_NOLOCK;
1895         index = 0;
1896
1897         while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1898                 if (!ter_state->first_lock) {
1899                         if (p->inversion == INVERSION_AUTO)
1900                                 ter_state->sense = SenseTrials[index];
1901
1902                 }
1903                 stv0367ter_algo(fe);
1904
1905                 if ((ter_state->state == FE_TER_LOCKOK) &&
1906                                 (p->inversion == INVERSION_AUTO) &&
1907                                                                 (index == 1)) {
1908                         /* invert spectrum sense */
1909                         SenseTrials[index] = SenseTrials[0];
1910                         SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1911                 }
1912
1913                 index++;
1914         }
1915
1916         return 0;
1917 }
1918
1919 static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1920 {
1921         struct stv0367_state *state = fe->demodulator_priv;
1922         struct stv0367ter_state *ter_state = state->ter_state;
1923         u32 errs = 0;
1924
1925         /*wait for counting completion*/
1926         if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1927                 errs =
1928                         ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1929                         * (1 << 16))
1930                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1931                         * (1 << 8))
1932                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1933                 ter_state->ucblocks = errs;
1934         }
1935
1936         (*ucblocks) = ter_state->ucblocks;
1937
1938         return 0;
1939 }
1940
1941 static int stv0367ter_get_frontend(struct dvb_frontend *fe)
1942 {
1943         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1944         struct stv0367_state *state = fe->demodulator_priv;
1945         struct stv0367ter_state *ter_state = state->ter_state;
1946         enum stv0367_ter_mode mode;
1947         int constell = 0,/* snr = 0,*/ Data = 0;
1948
1949         p->frequency = stv0367_get_tuner_freq(fe);
1950         if ((int)p->frequency < 0)
1951                 p->frequency = -p->frequency;
1952
1953         constell = stv0367_readbits(state, F367TER_TPS_CONST);
1954         if (constell == 0)
1955                 p->modulation = QPSK;
1956         else if (constell == 1)
1957                 p->modulation = QAM_16;
1958         else
1959                 p->modulation = QAM_64;
1960
1961         p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1962
1963         /* Get the Hierarchical mode */
1964         Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1965
1966         switch (Data) {
1967         case 0:
1968                 p->hierarchy = HIERARCHY_NONE;
1969                 break;
1970         case 1:
1971                 p->hierarchy = HIERARCHY_1;
1972                 break;
1973         case 2:
1974                 p->hierarchy = HIERARCHY_2;
1975                 break;
1976         case 3:
1977                 p->hierarchy = HIERARCHY_4;
1978                 break;
1979         default:
1980                 p->hierarchy = HIERARCHY_AUTO;
1981                 break; /* error */
1982         }
1983
1984         /* Get the FEC Rate */
1985         if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1986                 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1987         else
1988                 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1989
1990         switch (Data) {
1991         case 0:
1992                 p->code_rate_HP = FEC_1_2;
1993                 break;
1994         case 1:
1995                 p->code_rate_HP = FEC_2_3;
1996                 break;
1997         case 2:
1998                 p->code_rate_HP = FEC_3_4;
1999                 break;
2000         case 3:
2001                 p->code_rate_HP = FEC_5_6;
2002                 break;
2003         case 4:
2004                 p->code_rate_HP = FEC_7_8;
2005                 break;
2006         default:
2007                 p->code_rate_HP = FEC_AUTO;
2008                 break; /* error */
2009         }
2010
2011         mode = stv0367_readbits(state, F367TER_SYR_MODE);
2012
2013         switch (mode) {
2014         case FE_TER_MODE_2K:
2015                 p->transmission_mode = TRANSMISSION_MODE_2K;
2016                 break;
2017 /*      case FE_TER_MODE_4K:
2018                 p->transmission_mode = TRANSMISSION_MODE_4K;
2019                 break;*/
2020         case FE_TER_MODE_8K:
2021                 p->transmission_mode = TRANSMISSION_MODE_8K;
2022                 break;
2023         default:
2024                 p->transmission_mode = TRANSMISSION_MODE_AUTO;
2025         }
2026
2027         p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
2028
2029         return 0;
2030 }
2031
2032 static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
2033 {
2034         struct stv0367_state *state = fe->demodulator_priv;
2035         u32 snru32 = 0;
2036         int cpt = 0;
2037         u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
2038
2039         while (cpt < 10) {
2040                 usleep_range(2000, 3000);
2041                 if (cut == 0x50) /*cut 1.0 cut 1.1*/
2042                         snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
2043                 else /*cu2.0*/
2044                         snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
2045
2046                 cpt++;
2047         }
2048
2049         snru32 /= 10;/*average on 10 values*/
2050
2051         *snr = snru32 / 1000;
2052
2053         return 0;
2054 }
2055
2056 #if 0
2057 static int stv0367ter_status(struct dvb_frontend *fe)
2058 {
2059
2060         struct stv0367_state *state = fe->demodulator_priv;
2061         struct stv0367ter_state *ter_state = state->ter_state;
2062         int locked = FALSE;
2063
2064         locked = (stv0367_readbits(state, F367TER_LK));
2065         if (!locked)
2066                 ter_state->unlock_counter += 1;
2067         else
2068                 ter_state->unlock_counter = 0;
2069
2070         if (ter_state->unlock_counter > 2) {
2071                 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
2072                                 (!stv0367_readbits(state, F367TER_LK))) {
2073                         stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
2074                         usleep_range(2000, 3000);
2075                         stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
2076                         msleep(350);
2077                         locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
2078                                         (stv0367_readbits(state, F367TER_LK));
2079                 }
2080
2081         }
2082
2083         return locked;
2084 }
2085 #endif
2086 static int stv0367ter_read_status(struct dvb_frontend *fe,
2087                                   enum fe_status *status)
2088 {
2089         struct stv0367_state *state = fe->demodulator_priv;
2090
2091         dprintk("%s:\n", __func__);
2092
2093         *status = 0;
2094
2095         if (stv0367_readbits(state, F367TER_LK)) {
2096                 *status |= FE_HAS_LOCK;
2097                 dprintk("%s: stv0367 has locked\n", __func__);
2098         }
2099
2100         return 0;
2101 }
2102
2103 static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
2104 {
2105         struct stv0367_state *state = fe->demodulator_priv;
2106         struct stv0367ter_state *ter_state = state->ter_state;
2107         u32 Errors = 0, tber = 0, temporary = 0;
2108         int abc = 0, def = 0;
2109
2110
2111         /*wait for counting completion*/
2112         if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
2113                 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
2114                         * (1 << 16))
2115                         + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
2116                         * (1 << 8))
2117                         + ((u32)stv0367_readbits(state,
2118                                                 F367TER_SFEC_ERR_CNT_LO));
2119         /*measurement not completed, load previous value*/
2120         else {
2121                 tber = ter_state->pBER;
2122                 return 0;
2123         }
2124
2125         abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
2126         def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
2127
2128         if (Errors == 0) {
2129                 tber = 0;
2130         } else if (abc == 0x7) {
2131                 if (Errors <= 4) {
2132                         temporary = (Errors * 1000000000) / (8 * (1 << 14));
2133                         temporary =  temporary;
2134                 } else if (Errors <= 42) {
2135                         temporary = (Errors * 100000000) / (8 * (1 << 14));
2136                         temporary = temporary * 10;
2137                 } else if (Errors <= 429) {
2138                         temporary = (Errors * 10000000) / (8 * (1 << 14));
2139                         temporary = temporary * 100;
2140                 } else if (Errors <= 4294) {
2141                         temporary = (Errors * 1000000) / (8 * (1 << 14));
2142                         temporary = temporary * 1000;
2143                 } else if (Errors <= 42949) {
2144                         temporary = (Errors * 100000) / (8 * (1 << 14));
2145                         temporary = temporary * 10000;
2146                 } else if (Errors <= 429496) {
2147                         temporary = (Errors * 10000) / (8 * (1 << 14));
2148                         temporary = temporary * 100000;
2149                 } else { /*if (Errors<4294967) 2^22 max error*/
2150                         temporary = (Errors * 1000) / (8 * (1 << 14));
2151                         temporary = temporary * 100000; /* still to *10 */
2152                 }
2153
2154                 /* Byte error*/
2155                 if (def == 2)
2156                         /*tber=Errors/(8*(1 <<14));*/
2157                         tber = temporary;
2158                 else if (def == 3)
2159                         /*tber=Errors/(8*(1 <<16));*/
2160                         tber = temporary / 4;
2161                 else if (def == 4)
2162                         /*tber=Errors/(8*(1 <<18));*/
2163                         tber = temporary / 16;
2164                 else if (def == 5)
2165                         /*tber=Errors/(8*(1 <<20));*/
2166                         tber = temporary / 64;
2167                 else if (def == 6)
2168                         /*tber=Errors/(8*(1 <<22));*/
2169                         tber = temporary / 256;
2170                 else
2171                         /* should not pass here*/
2172                         tber = 0;
2173
2174                 if ((Errors < 4294967) && (Errors > 429496))
2175                         tber *= 10;
2176
2177         }
2178
2179         /* save actual value */
2180         ter_state->pBER = tber;
2181
2182         (*ber) = tber;
2183
2184         return 0;
2185 }
2186 #if 0
2187 static u32 stv0367ter_get_per(struct stv0367_state *state)
2188 {
2189         struct stv0367ter_state *ter_state = state->ter_state;
2190         u32 Errors = 0, Per = 0, temporary = 0;
2191         int abc = 0, def = 0, cpt = 0;
2192
2193         while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
2194                         (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
2195                 usleep_range(1000, 2000);
2196                 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
2197                         * (1 << 16))
2198                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
2199                         * (1 << 8))
2200                         + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
2201                 cpt++;
2202         }
2203         abc = stv0367_readbits(state, F367TER_ERR_SRC1);
2204         def = stv0367_readbits(state, F367TER_NUM_EVT1);
2205
2206         if (Errors == 0)
2207                 Per = 0;
2208         else if (abc == 0x9) {
2209                 if (Errors <= 4) {
2210                         temporary = (Errors * 1000000000) / (8 * (1 << 8));
2211                         temporary =  temporary;
2212                 } else if (Errors <= 42) {
2213                         temporary = (Errors * 100000000) / (8 * (1 << 8));
2214                         temporary = temporary * 10;
2215                 } else if (Errors <= 429) {
2216                         temporary = (Errors * 10000000) / (8 * (1 << 8));
2217                         temporary = temporary * 100;
2218                 } else if (Errors <= 4294) {
2219                         temporary = (Errors * 1000000) / (8 * (1 << 8));
2220                         temporary = temporary * 1000;
2221                 } else if (Errors <= 42949) {
2222                         temporary = (Errors * 100000) / (8 * (1 << 8));
2223                         temporary = temporary * 10000;
2224                 } else { /*if(Errors<=429496)  2^16 errors max*/
2225                         temporary = (Errors * 10000) / (8 * (1 << 8));
2226                         temporary = temporary * 100000;
2227                 }
2228
2229                 /* pkt error*/
2230                 if (def == 2)
2231                         /*Per=Errors/(1 << 8);*/
2232                         Per = temporary;
2233                 else if (def == 3)
2234                         /*Per=Errors/(1 << 10);*/
2235                         Per = temporary / 4;
2236                 else if (def == 4)
2237                         /*Per=Errors/(1 << 12);*/
2238                         Per = temporary / 16;
2239                 else if (def == 5)
2240                         /*Per=Errors/(1 << 14);*/
2241                         Per = temporary / 64;
2242                 else if (def == 6)
2243                         /*Per=Errors/(1 << 16);*/
2244                         Per = temporary / 256;
2245                 else
2246                         Per = 0;
2247
2248         }
2249         /* save actual value */
2250         ter_state->pPER = Per;
2251
2252         return Per;
2253 }
2254 #endif
2255 static int stv0367_get_tune_settings(struct dvb_frontend *fe,
2256                                         struct dvb_frontend_tune_settings
2257                                         *fe_tune_settings)
2258 {
2259         fe_tune_settings->min_delay_ms = 1000;
2260         fe_tune_settings->step_size = 0;
2261         fe_tune_settings->max_drift = 0;
2262
2263         return 0;
2264 }
2265
2266 static void stv0367_release(struct dvb_frontend *fe)
2267 {
2268         struct stv0367_state *state = fe->demodulator_priv;
2269
2270         kfree(state->ter_state);
2271         kfree(state->cab_state);
2272         kfree(state);
2273 }
2274
2275 static struct dvb_frontend_ops stv0367ter_ops = {
2276         .delsys = { SYS_DVBT },
2277         .info = {
2278                 .name                   = "ST STV0367 DVB-T",
2279                 .frequency_min          = 47000000,
2280                 .frequency_max          = 862000000,
2281                 .frequency_stepsize     = 15625,
2282                 .frequency_tolerance    = 0,
2283                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2284                         FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2285                         FE_CAN_FEC_AUTO |
2286                         FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2287                         FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
2288                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
2289                         FE_CAN_INVERSION_AUTO |
2290                         FE_CAN_MUTE_TS
2291         },
2292         .release = stv0367_release,
2293         .init = stv0367ter_init,
2294         .sleep = stv0367ter_sleep,
2295         .i2c_gate_ctrl = stv0367ter_gate_ctrl,
2296         .set_frontend = stv0367ter_set_frontend,
2297         .get_frontend = stv0367ter_get_frontend,
2298         .get_tune_settings = stv0367_get_tune_settings,
2299         .read_status = stv0367ter_read_status,
2300         .read_ber = stv0367ter_read_ber,/* too slow */
2301 /*      .read_signal_strength = stv0367_read_signal_strength,*/
2302         .read_snr = stv0367ter_read_snr,
2303         .read_ucblocks = stv0367ter_read_ucblocks,
2304 };
2305
2306 struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
2307                                    struct i2c_adapter *i2c)
2308 {
2309         struct stv0367_state *state = NULL;
2310         struct stv0367ter_state *ter_state = NULL;
2311
2312         /* allocate memory for the internal state */
2313         state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2314         if (state == NULL)
2315                 goto error;
2316         ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
2317         if (ter_state == NULL)
2318                 goto error;
2319
2320         /* setup the state */
2321         state->i2c = i2c;
2322         state->config = config;
2323         state->ter_state = ter_state;
2324         state->fe.ops = stv0367ter_ops;
2325         state->fe.demodulator_priv = state;
2326         state->chip_id = stv0367_readreg(state, 0xf000);
2327
2328         dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2329
2330         /* check if the demod is there */
2331         if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2332                 goto error;
2333
2334         return &state->fe;
2335
2336 error:
2337         kfree(ter_state);
2338         kfree(state);
2339         return NULL;
2340 }
2341 EXPORT_SYMBOL(stv0367ter_attach);
2342
2343 static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
2344 {
2345         struct stv0367_state *state = fe->demodulator_priv;
2346
2347         dprintk("%s:\n", __func__);
2348
2349         stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
2350
2351         return 0;
2352 }
2353
2354 static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
2355 {
2356         struct stv0367_state *state = fe->demodulator_priv;
2357         u32 mclk_Hz = 0;/* master clock frequency (Hz) */
2358         u32 M, N, P;
2359
2360
2361         if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
2362                 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
2363                 if (N == 0)
2364                         N = N + 1;
2365
2366                 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
2367                 if (M == 0)
2368                         M = M + 1;
2369
2370                 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
2371
2372                 if (P > 5)
2373                         P = 5;
2374
2375                 mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
2376                 dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
2377                                                                 mclk_Hz);
2378         } else
2379                 mclk_Hz = ExtClk_Hz;
2380
2381         dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
2382
2383         return mclk_Hz;
2384 }
2385
2386 static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
2387 {
2388         u32 ADCClk_Hz = ExtClk_Hz;
2389
2390         ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
2391
2392         return ADCClk_Hz;
2393 }
2394
2395 static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
2396                                                  u32 SymbolRate,
2397                                                  enum stv0367cab_mod QAMSize)
2398 {
2399         /* Set QAM size */
2400         stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
2401
2402         /* Set Registers settings specific to the QAM size */
2403         switch (QAMSize) {
2404         case FE_CAB_MOD_QAM4:
2405                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2406                 break;
2407         case FE_CAB_MOD_QAM16:
2408                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
2409                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2410                 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2411                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2412                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2413                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2414                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2415                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
2416                 break;
2417         case FE_CAB_MOD_QAM32:
2418                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2419                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
2420                 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2421                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2422                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
2423                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
2424                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2425                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2426                 break;
2427         case FE_CAB_MOD_QAM64:
2428                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
2429                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2430                 if (SymbolRate > 45000000) {
2431                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2432                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2433                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
2434                 } else if (SymbolRate > 25000000) {
2435                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2436                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2437                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2438                 } else {
2439                         stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2440                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2441                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2442                 }
2443                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2444                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2445                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
2446                 break;
2447         case FE_CAB_MOD_QAM128:
2448                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2449                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
2450                 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2451                 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
2452                 if (SymbolRate > 45000000)
2453                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2454                 else if (SymbolRate > 25000000)
2455                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2456                 else
2457                         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
2458
2459                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
2460                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2461                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2462                 break;
2463         case FE_CAB_MOD_QAM256:
2464                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
2465                 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2466                 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2467                 if (SymbolRate > 45000000)
2468                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2469                 else if (SymbolRate > 25000000)
2470                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2471                 else
2472                         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2473
2474                 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2475                 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
2476                 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2477                 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2478                 break;
2479         case FE_CAB_MOD_QAM512:
2480                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2481                 break;
2482         case FE_CAB_MOD_QAM1024:
2483                 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2484                 break;
2485         default:
2486                 break;
2487         }
2488
2489         return QAMSize;
2490 }
2491
2492 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
2493                                         u32 adc_hz, s32 derot_hz)
2494 {
2495         u32 sampled_if = 0;
2496         u32 adc_khz;
2497
2498         adc_khz = adc_hz / 1000;
2499
2500         dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
2501
2502         if (adc_khz != 0) {
2503                 if (derot_hz < 1000000)
2504                         derot_hz = adc_hz / 4; /* ZIF operation */
2505                 if (derot_hz > adc_hz)
2506                         derot_hz = derot_hz - adc_hz;
2507                 sampled_if = (u32)derot_hz / 1000;
2508                 sampled_if *= 32768;
2509                 sampled_if /= adc_khz;
2510                 sampled_if *= 256;
2511         }
2512
2513         if (sampled_if > 8388607)
2514                 sampled_if = 8388607;
2515
2516         dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
2517
2518         stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
2519         stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
2520         stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
2521
2522         return derot_hz;
2523 }
2524
2525 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
2526 {
2527         u32 sampled_if;
2528
2529         sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
2530                         (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
2531                         (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
2532
2533         sampled_if /= 256;
2534         sampled_if *= (adc_hz / 1000);
2535         sampled_if += 1;
2536         sampled_if /= 32768;
2537
2538         return sampled_if;
2539 }
2540
2541 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
2542                         u32 mclk_hz, u32 SymbolRate,
2543                         enum stv0367cab_mod QAMSize)
2544 {
2545         u32 QamSizeCorr = 0;
2546         u32 u32_tmp = 0, u32_tmp1 = 0;
2547         u32 adp_khz;
2548
2549         dprintk("%s:\n", __func__);
2550
2551         /* Set Correction factor of SRC gain */
2552         switch (QAMSize) {
2553         case FE_CAB_MOD_QAM4:
2554                 QamSizeCorr = 1110;
2555                 break;
2556         case FE_CAB_MOD_QAM16:
2557                 QamSizeCorr = 1032;
2558                 break;
2559         case FE_CAB_MOD_QAM32:
2560                 QamSizeCorr =  954;
2561                 break;
2562         case FE_CAB_MOD_QAM64:
2563                 QamSizeCorr =  983;
2564                 break;
2565         case FE_CAB_MOD_QAM128:
2566                 QamSizeCorr =  957;
2567                 break;
2568         case FE_CAB_MOD_QAM256:
2569                 QamSizeCorr =  948;
2570                 break;
2571         case FE_CAB_MOD_QAM512:
2572                 QamSizeCorr =    0;
2573                 break;
2574         case FE_CAB_MOD_QAM1024:
2575                 QamSizeCorr =  944;
2576                 break;
2577         default:
2578                 break;
2579         }
2580
2581         /* Transfer ratio calculation */
2582         if (adc_hz != 0) {
2583                 u32_tmp = 256 * SymbolRate;
2584                 u32_tmp = u32_tmp / adc_hz;
2585         }
2586         stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2587
2588         /* Symbol rate and SRC gain calculation */
2589         adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2590         if (adp_khz != 0) {
2591                 u32_tmp = SymbolRate;
2592                 u32_tmp1 = SymbolRate;
2593
2594                 if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2595                         /* Symbol rate calculation */
2596                         u32_tmp *= 2048; /* 2048 = 2^11 */
2597                         u32_tmp = u32_tmp / adp_khz;
2598                         u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2599                         u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2600                         u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2601
2602                         /* SRC Gain Calculation */
2603                         u32_tmp1 *= 2048; /* *2*2^10 */
2604                         u32_tmp1 /= 439; /* *2/878 */
2605                         u32_tmp1 *= 256; /* *2^8 */
2606                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2607                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2608                         u32_tmp1 = u32_tmp1 / 10000000;
2609
2610                 } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2611                         /* Symbol rate calculation */
2612                         u32_tmp *= 1024 ; /* 1024 = 2**10 */
2613                         u32_tmp = u32_tmp / adp_khz;
2614                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2615                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2616                         u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2617
2618                         /* SRC Gain Calculation */
2619                         u32_tmp1 *= 1024; /* *2*2^9 */
2620                         u32_tmp1 /= 439; /* *2/878 */
2621                         u32_tmp1 *= 256; /* *2^8 */
2622                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2623                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2624                         u32_tmp1 = u32_tmp1 / 5000000;
2625                 } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2626                         /* Symbol rate calculation */
2627                         u32_tmp *= 512 ; /* 512 = 2**9 */
2628                         u32_tmp = u32_tmp / adp_khz;
2629                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2630                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2631                         u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2632
2633                         /* SRC Gain Calculation */
2634                         u32_tmp1 *= 512; /* *2*2^8 */
2635                         u32_tmp1 /= 439; /* *2/878 */
2636                         u32_tmp1 *= 256; /* *2^8 */
2637                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2638                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2639                         u32_tmp1 = u32_tmp1 / 2500000;
2640                 } else {
2641                         /* Symbol rate calculation */
2642                         u32_tmp *= 256 ; /* 256 = 2**8 */
2643                         u32_tmp = u32_tmp / adp_khz;
2644                         u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2645                         u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2646                         u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2647
2648                         /* SRC Gain Calculation */
2649                         u32_tmp1 *= 256; /* 2*2^7 */
2650                         u32_tmp1 /= 439; /* *2/878 */
2651                         u32_tmp1 *= 256; /* *2^8 */
2652                         u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2653                         u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2654                         u32_tmp1 = u32_tmp1 / 1250000;
2655                 }
2656         }
2657 #if 0
2658         /* Filters' coefficients are calculated and written
2659         into registers only if the filters are enabled */
2660         if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2661                 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2662                                                                 SymbolRate);
2663                 /* AllPass filter must be enabled
2664                 when the adjacents filter is used */
2665                 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2666                 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2667         } else
2668                 /* AllPass filter must be disabled
2669                 when the adjacents filter is not used */
2670 #endif
2671         stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2672
2673         stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2674         stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2675         stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2676         stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2677
2678         stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2679         stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2680
2681         return SymbolRate ;
2682 }
2683
2684 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2685 {
2686         u32 regsym;
2687         u32 adp_khz;
2688
2689         regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2690                 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2691                 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2692                 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2693
2694         adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2695
2696         if (regsym < 134217728) {               /* 134217728L = 2**27*/
2697                 regsym = regsym * 32;           /* 32 = 2**5 */
2698                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2699                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2700                 regsym = regsym / 128;          /* 128 = 2**7 */
2701                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2702                 regsym /= 2048 ;                /* 2048 = 2**11 */
2703         } else if (regsym < 268435456) {        /* 268435456L = 2**28 */
2704                 regsym = regsym * 16;           /* 16 = 2**4 */
2705                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2706                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2707                 regsym = regsym / 128;          /* 128 = 2**7 */
2708                 regsym *= 125 ;                 /* 125 = 1000/2**3*/
2709                 regsym /= 1024 ;                /* 256 = 2**10*/
2710         } else if (regsym < 536870912) {        /* 536870912L = 2**29*/
2711                 regsym = regsym * 8;            /* 8 = 2**3 */
2712                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2713                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2714                 regsym = regsym / 128;          /* 128 = 2**7 */
2715                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2716                 regsym /= 512 ;                 /* 128 = 2**9 */
2717         } else {
2718                 regsym = regsym * 4;            /* 4 = 2**2 */
2719                 regsym = regsym / 32768;        /* 32768L = 2**15 */
2720                 regsym = adp_khz * regsym;      /* AdpClk in kHz */
2721                 regsym = regsym / 128;          /* 128 = 2**7 */
2722                 regsym *= 125 ;                 /* 125 = 1000/2**3 */
2723                 regsym /= 256 ;                 /* 64 = 2**8 */
2724         }
2725
2726         return regsym;
2727 }
2728
2729 static int stv0367cab_read_status(struct dvb_frontend *fe,
2730                                   enum fe_status *status)
2731 {
2732         struct stv0367_state *state = fe->demodulator_priv;
2733
2734         dprintk("%s:\n", __func__);
2735
2736         *status = 0;
2737
2738         if (stv0367_readbits(state, F367CAB_QAMFEC_LOCK)) {
2739                 *status |= FE_HAS_LOCK;
2740                 dprintk("%s: stv0367 has locked\n", __func__);
2741         }
2742
2743         return 0;
2744 }
2745
2746 static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2747 {
2748         struct stv0367_state *state = fe->demodulator_priv;
2749
2750         dprintk("%s:\n", __func__);
2751
2752         if (standby_on) {
2753                 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2754                 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2755                 stv0367_writebits(state, F367CAB_STDBY, 1);
2756                 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2757                 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2758                 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2759                 stv0367_writebits(state, F367CAB_POFFQ, 1);
2760                 stv0367_writebits(state, F367CAB_POFFI, 1);
2761         } else {
2762                 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2763                 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2764                 stv0367_writebits(state, F367CAB_STDBY, 0);
2765                 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2766                 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2767                 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2768                 stv0367_writebits(state, F367CAB_POFFQ, 0);
2769                 stv0367_writebits(state, F367CAB_POFFI, 0);
2770         }
2771
2772         return 0;
2773 }
2774
2775 static int stv0367cab_sleep(struct dvb_frontend *fe)
2776 {
2777         return stv0367cab_standby(fe, 1);
2778 }
2779
2780 static int stv0367cab_init(struct dvb_frontend *fe)
2781 {
2782         struct stv0367_state *state = fe->demodulator_priv;
2783         struct stv0367cab_state *cab_state = state->cab_state;
2784         int i;
2785
2786         dprintk("%s:\n", __func__);
2787
2788         for (i = 0; i < STV0367CAB_NBREGS; i++)
2789                 stv0367_writereg(state, def0367cab[i].addr,
2790                                                 def0367cab[i].value);
2791
2792         switch (state->config->ts_mode) {
2793         case STV0367_DVBCI_CLOCK:
2794                 dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2795                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2796                 break;
2797         case STV0367_SERIAL_PUNCT_CLOCK:
2798         case STV0367_SERIAL_CONT_CLOCK:
2799                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2800                 break;
2801         case STV0367_PARALLEL_PUNCT_CLOCK:
2802         case STV0367_OUTPUTMODE_DEFAULT:
2803                 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2804                 break;
2805         }
2806
2807         switch (state->config->clk_pol) {
2808         case STV0367_RISINGEDGE_CLOCK:
2809                 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2810                 break;
2811         case STV0367_FALLINGEDGE_CLOCK:
2812         case STV0367_CLOCKPOLARITY_DEFAULT:
2813                 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2814                 break;
2815         }
2816
2817         stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2818
2819         stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2820
2821         stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2822
2823         stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2824
2825         stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2826
2827         cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2828         cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2829
2830         return 0;
2831 }
2832 static
2833 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2834                                              struct dtv_frontend_properties *p)
2835 {
2836         struct stv0367cab_state *cab_state = state->cab_state;
2837         enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2838         u32     QAMFEC_Lock, QAM_Lock, u32_tmp,
2839                 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2840                 CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2841         u8      TrackAGCAccum;
2842         s32     tmp;
2843
2844         dprintk("%s:\n", __func__);
2845
2846         /* Timeouts calculation */
2847         /* A max lock time of 25 ms is allowed for delayed AGC */
2848         AGCTimeOut = 25;
2849         /* 100000 symbols needed by the TRL as a maximum value */
2850         TRLTimeOut = 100000000 / p->symbol_rate;
2851         /* CRLSymbols is the needed number of symbols to achieve a lock
2852            within [-4%, +4%] of the symbol rate.
2853            CRL timeout is calculated
2854            for a lock within [-search_range, +search_range].
2855            EQL timeout can be changed depending on
2856            the micro-reflections we want to handle.
2857            A characterization must be performed
2858            with these echoes to get new timeout values.
2859         */
2860         switch (p->modulation) {
2861         case QAM_16:
2862                 CRLSymbols = 150000;
2863                 EQLTimeOut = 100;
2864                 break;
2865         case QAM_32:
2866                 CRLSymbols = 250000;
2867                 EQLTimeOut = 100;
2868                 break;
2869         case QAM_64:
2870                 CRLSymbols = 200000;
2871                 EQLTimeOut = 100;
2872                 break;
2873         case QAM_128:
2874                 CRLSymbols = 250000;
2875                 EQLTimeOut = 100;
2876                 break;
2877         case QAM_256:
2878                 CRLSymbols = 250000;
2879                 EQLTimeOut = 100;
2880                 break;
2881         default:
2882                 CRLSymbols = 200000;
2883                 EQLTimeOut = 100;
2884                 break;
2885         }
2886 #if 0
2887         if (pIntParams->search_range < 0) {
2888                 CRLTimeOut = (25 * CRLSymbols *
2889                                 (-pIntParams->search_range / 1000)) /
2890                                         (pIntParams->symbol_rate / 1000);
2891         } else
2892 #endif
2893         CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2894                                         (p->symbol_rate / 1000);
2895
2896         CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
2897         /* Timeouts below 50ms are coerced */
2898         if (CRLTimeOut < 50)
2899                 CRLTimeOut = 50;
2900         /* A maximum of 100 TS packets is needed to get FEC lock even in case
2901         the spectrum inversion needs to be changed.
2902            This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2903         */
2904         FECTimeOut = 20;
2905         DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2906
2907         dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2908
2909         /* Reset the TRL to ensure nothing starts until the
2910            AGC is stable which ensures a better lock time
2911         */
2912         stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2913         /* Set AGC accumulation time to minimum and lock threshold to maximum
2914         in order to speed up the AGC lock */
2915         TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2916         stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2917         /* Modulus Mapper is disabled */
2918         stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2919         /* Disable the sweep function */
2920         stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2921         /* The sweep function is never used, Sweep rate must be set to 0 */
2922         /* Set the derotator frequency in Hz */
2923         stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2924                 (1000 * (s32)state->config->if_khz + cab_state->derot_offset));
2925         /* Disable the Allpass Filter when the symbol rate is out of range */
2926         if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
2927                 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2928                 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2929         }
2930 #if 0
2931         /* Check if the tuner is locked */
2932         tuner_lock = stv0367cab_tuner_get_status(fe);
2933         if (tuner_lock == 0)
2934                 return FE_367CAB_NOTUNER;
2935 #endif
2936         /* Release the TRL to start demodulator acquisition */
2937         /* Wait for QAM lock */
2938         LockTime = 0;
2939         stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2940         do {
2941                 QAM_Lock = stv0367_readbits(state, F367CAB_FSM_STATUS);
2942                 if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2943                                                         (QAM_Lock == 0x04))
2944                         /*
2945                          * We don't wait longer, the frequency/phase offset
2946                          * must be too big
2947                          */
2948                         LockTime = DemodTimeOut;
2949                 else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2950                                                         (QAM_Lock == 0x02))
2951                         /*
2952                          * We don't wait longer, either there is no signal or
2953                          * it is not the right symbol rate or it is an analog
2954                          * carrier
2955                          */
2956                 {
2957                         LockTime = DemodTimeOut;
2958                         u32_tmp = stv0367_readbits(state,
2959                                                 F367CAB_AGC_PWR_WORD_LO) +
2960                                         (stv0367_readbits(state,
2961                                                 F367CAB_AGC_PWR_WORD_ME) << 8) +
2962                                         (stv0367_readbits(state,
2963                                                 F367CAB_AGC_PWR_WORD_HI) << 16);
2964                         if (u32_tmp >= 131072)
2965                                 u32_tmp = 262144 - u32_tmp;
2966                         u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2967                                                         F367CAB_AGC_IF_BWSEL)));
2968
2969                         if (u32_tmp < stv0367_readbits(state,
2970                                                 F367CAB_AGC_PWRREF_LO) +
2971                                         256 * stv0367_readbits(state,
2972                                                 F367CAB_AGC_PWRREF_HI) - 10)
2973                                 QAM_Lock = 0x0f;
2974                 } else {
2975                         usleep_range(10000, 20000);
2976                         LockTime += 10;
2977                 }
2978                 dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2979                 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2980
2981                 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2982
2983         } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2984                                                 (LockTime < DemodTimeOut));
2985
2986         dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2987
2988         tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2989         dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2990         tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2991         dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2992
2993         tmp  = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2994         dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2995
2996         if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2997                 /* Wait for FEC lock */
2998                 LockTime = 0;
2999                 do {
3000                         usleep_range(5000, 7000);
3001                         LockTime += 5;
3002                         QAMFEC_Lock = stv0367_readbits(state,
3003                                                         F367CAB_QAMFEC_LOCK);
3004                 } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
3005         } else
3006                 QAMFEC_Lock = 0;
3007
3008         if (QAMFEC_Lock) {
3009                 signalType = FE_CAB_DATAOK;
3010                 cab_state->spect_inv = stv0367_readbits(state,
3011                                                         F367CAB_QUAD_INV);
3012 #if 0
3013 /* not clear for me */
3014                 if (state->config->if_khz != 0) {
3015                         if (state->config->if_khz > cab_state->adc_clk / 1000) {
3016                                 cab_state->freq_khz =
3017                                         FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3018                                 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3019                                 - cab_state->adc_clk / 1000 + state->config->if_khz;
3020                         } else {
3021                                 cab_state->freq_khz =
3022                                                 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3023                                                 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3024                                                                                 + state->config->if_khz;
3025                         }
3026                 } else {
3027                         cab_state->freq_khz =
3028                                 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
3029                                 stv0367cab_get_derot_freq(state,
3030                                                         cab_state->adc_clk) -
3031                                 cab_state->adc_clk / 4000;
3032                 }
3033 #endif
3034                 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
3035                                                         cab_state->mclk);
3036                 cab_state->locked = 1;
3037
3038                 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
3039         } else {
3040                 switch (QAM_Lock) {
3041                 case 1:
3042                         signalType = FE_CAB_NOAGC;
3043                         break;
3044                 case 2:
3045                         signalType = FE_CAB_NOTIMING;
3046                         break;
3047                 case 3:
3048                         signalType = FE_CAB_TIMINGOK;
3049                         break;
3050                 case 4:
3051                         signalType = FE_CAB_NOCARRIER;
3052                         break;
3053                 case 5:
3054                         signalType = FE_CAB_CARRIEROK;
3055                         break;
3056                 case 7:
3057                         signalType = FE_CAB_NOBLIND;
3058                         break;
3059                 case 8:
3060                         signalType = FE_CAB_BLINDOK;
3061                         break;
3062                 case 10:
3063                         signalType = FE_CAB_NODEMOD;
3064                         break;
3065                 case 11:
3066                         signalType = FE_CAB_DEMODOK;
3067                         break;
3068                 case 12:
3069                         signalType = FE_CAB_DEMODOK;
3070                         break;
3071                 case 13:
3072                         signalType = FE_CAB_NODEMOD;
3073                         break;
3074                 case 14:
3075                         signalType = FE_CAB_NOBLIND;
3076                         break;
3077                 case 15:
3078                         signalType = FE_CAB_NOSIGNAL;
3079                         break;
3080                 default:
3081                         break;
3082                 }
3083
3084         }
3085
3086         /* Set the AGC control values to tracking values */
3087         stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
3088         return signalType;
3089 }
3090
3091 static int stv0367cab_set_frontend(struct dvb_frontend *fe)
3092 {
3093         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3094         struct stv0367_state *state = fe->demodulator_priv;
3095         struct stv0367cab_state *cab_state = state->cab_state;
3096         enum stv0367cab_mod QAMSize = 0;
3097
3098         dprintk("%s: freq = %d, srate = %d\n", __func__,
3099                                         p->frequency, p->symbol_rate);
3100
3101         cab_state->derot_offset = 0;
3102
3103         switch (p->modulation) {
3104         case QAM_16:
3105                 QAMSize = FE_CAB_MOD_QAM16;
3106                 break;
3107         case QAM_32:
3108                 QAMSize = FE_CAB_MOD_QAM32;
3109                 break;
3110         case QAM_64:
3111                 QAMSize = FE_CAB_MOD_QAM64;
3112                 break;
3113         case QAM_128:
3114                 QAMSize = FE_CAB_MOD_QAM128;
3115                 break;
3116         case QAM_256:
3117                 QAMSize = FE_CAB_MOD_QAM256;
3118                 break;
3119         default:
3120                 break;
3121         }
3122
3123         stv0367cab_init(fe);
3124
3125         /* Tuner Frequency Setting */
3126         if (fe->ops.tuner_ops.set_params) {
3127                 if (fe->ops.i2c_gate_ctrl)
3128                         fe->ops.i2c_gate_ctrl(fe, 1);
3129                 fe->ops.tuner_ops.set_params(fe);
3130                 if (fe->ops.i2c_gate_ctrl)
3131                         fe->ops.i2c_gate_ctrl(fe, 0);
3132         }
3133
3134         stv0367cab_SetQamSize(
3135                         state,
3136                         p->symbol_rate,
3137                         QAMSize);
3138
3139         stv0367cab_set_srate(state,
3140                         cab_state->adc_clk,
3141                         cab_state->mclk,
3142                         p->symbol_rate,
3143                         QAMSize);
3144         /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
3145         cab_state->state = stv0367cab_algo(state, p);
3146         return 0;
3147 }
3148
3149 static int stv0367cab_get_frontend(struct dvb_frontend *fe)
3150 {
3151         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3152         struct stv0367_state *state = fe->demodulator_priv;
3153         struct stv0367cab_state *cab_state = state->cab_state;
3154
3155         enum stv0367cab_mod QAMSize;
3156
3157         dprintk("%s:\n", __func__);
3158
3159         p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
3160
3161         QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3162         switch (QAMSize) {
3163         case FE_CAB_MOD_QAM16:
3164                 p->modulation = QAM_16;
3165                 break;
3166         case FE_CAB_MOD_QAM32:
3167                 p->modulation = QAM_32;
3168                 break;
3169         case FE_CAB_MOD_QAM64:
3170                 p->modulation = QAM_64;
3171                 break;
3172         case FE_CAB_MOD_QAM128:
3173                 p->modulation = QAM_128;
3174                 break;
3175         case FE_CAB_MOD_QAM256:
3176                 p->modulation = QAM_256;
3177                 break;
3178         default:
3179                 break;
3180         }
3181
3182         p->frequency = stv0367_get_tuner_freq(fe);
3183
3184         dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
3185
3186         if (state->config->if_khz == 0) {
3187                 p->frequency +=
3188                         (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
3189                         cab_state->adc_clk / 4000);
3190                 return 0;
3191         }
3192
3193         if (state->config->if_khz > cab_state->adc_clk / 1000)
3194                 p->frequency += (state->config->if_khz
3195                         - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3196                         - cab_state->adc_clk / 1000);
3197         else
3198                 p->frequency += (state->config->if_khz
3199                         - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
3200
3201         return 0;
3202 }
3203
3204 #if 0
3205 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
3206                         u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
3207 {
3208         stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
3209         stv0367cab_GetPacketsCount(state, Monitor_results);
3210
3211         return;
3212 }
3213
3214 static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
3215 {
3216         struct stv0367_state *state = fe->demodulator_priv;
3217
3218         return 0;
3219 }
3220 #endif
3221 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
3222 {
3223         s32 rfLevel = 0;
3224         s32 RfAgcPwm = 0, IfAgcPwm = 0;
3225         u8 i;
3226
3227         stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
3228
3229         RfAgcPwm =
3230                 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
3231                 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
3232         RfAgcPwm = 100 * RfAgcPwm / 1023;
3233
3234         IfAgcPwm =
3235                 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
3236                 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
3237         if (IfAgcPwm >= 2048)
3238                 IfAgcPwm -= 2048;
3239         else
3240                 IfAgcPwm += 2048;
3241
3242         IfAgcPwm = 100 * IfAgcPwm / 4095;
3243
3244         /* For DTT75467 on NIM */
3245         if (RfAgcPwm < 90  && IfAgcPwm < 28) {
3246                 for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
3247                         if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
3248                                 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
3249                                 break;
3250                         }
3251                 }
3252                 if (i == RF_LOOKUP_TABLE_SIZE)
3253                         rfLevel = -56;
3254         } else { /*if IF AGC>10*/
3255                 for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
3256                         if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
3257                                 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
3258                                 break;
3259                         }
3260                 }
3261                 if (i == RF_LOOKUP_TABLE2_SIZE)
3262                         rfLevel = -72;
3263         }
3264         return rfLevel;
3265 }
3266
3267 static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
3268 {
3269         struct stv0367_state *state = fe->demodulator_priv;
3270
3271         s32 signal =  stv0367cab_get_rf_lvl(state);
3272
3273         dprintk("%s: signal=%d dBm\n", __func__, signal);
3274
3275         if (signal <= -72)
3276                 *strength = 65535;
3277         else
3278                 *strength = (22 + signal) * (-1311);
3279
3280         dprintk("%s: strength=%d\n", __func__, (*strength));
3281
3282         return 0;
3283 }
3284
3285 static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
3286 {
3287         struct stv0367_state *state = fe->demodulator_priv;
3288         u32 noisepercentage;
3289         enum stv0367cab_mod QAMSize;
3290         u32 regval = 0, temp = 0;
3291         int power, i;
3292
3293         QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3294         switch (QAMSize) {
3295         case FE_CAB_MOD_QAM4:
3296                 power = 21904;
3297                 break;
3298         case FE_CAB_MOD_QAM16:
3299                 power = 20480;
3300                 break;
3301         case FE_CAB_MOD_QAM32:
3302                 power = 23040;
3303                 break;
3304         case FE_CAB_MOD_QAM64:
3305                 power = 21504;
3306                 break;
3307         case FE_CAB_MOD_QAM128:
3308                 power = 23616;
3309                 break;
3310         case FE_CAB_MOD_QAM256:
3311                 power = 21760;
3312                 break;
3313         case FE_CAB_MOD_QAM512:
3314                 power = 1;
3315                 break;
3316         case FE_CAB_MOD_QAM1024:
3317                 power = 21280;
3318                 break;
3319         default:
3320                 power = 1;
3321                 break;
3322         }
3323
3324         for (i = 0; i < 10; i++) {
3325                 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
3326                         + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
3327         }
3328
3329         regval /= 10; /*for average over 10 times in for loop above*/
3330         if (regval != 0) {
3331                 temp = power
3332                         * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
3333                 temp /= regval;
3334         }
3335
3336         /* table values, not needed to calculate logarithms */
3337         if (temp >= 5012)
3338                 noisepercentage = 100;
3339         else if (temp >= 3981)
3340                 noisepercentage = 93;
3341         else if (temp >= 3162)
3342                 noisepercentage = 86;
3343         else if (temp >= 2512)
3344                 noisepercentage = 79;
3345         else if (temp >= 1995)
3346                 noisepercentage = 72;
3347         else if (temp >= 1585)
3348                 noisepercentage = 65;
3349         else if (temp >= 1259)
3350                 noisepercentage = 58;
3351         else if (temp >= 1000)
3352                 noisepercentage = 50;
3353         else if (temp >= 794)
3354                 noisepercentage = 43;
3355         else if (temp >= 501)
3356                 noisepercentage = 36;
3357         else if (temp >= 316)
3358                 noisepercentage = 29;
3359         else if (temp >= 200)
3360                 noisepercentage = 22;
3361         else if (temp >= 158)
3362                 noisepercentage = 14;
3363         else if (temp >= 126)
3364                 noisepercentage = 7;
3365         else
3366                 noisepercentage = 0;
3367
3368         dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
3369
3370         *snr = (noisepercentage * 65535) / 100;
3371
3372         return 0;
3373 }
3374
3375 static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
3376 {
3377         struct stv0367_state *state = fe->demodulator_priv;
3378         int corrected, tscount;
3379
3380         *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
3381                         | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
3382         corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
3383                         | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
3384         tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
3385                         | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
3386
3387         dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
3388                                 __func__, *ucblocks, corrected, tscount);
3389
3390         return 0;
3391 };
3392
3393 static struct dvb_frontend_ops stv0367cab_ops = {
3394         .delsys = { SYS_DVBC_ANNEX_A },
3395         .info = {
3396                 .name = "ST STV0367 DVB-C",
3397                 .frequency_min = 47000000,
3398                 .frequency_max = 862000000,
3399                 .frequency_stepsize = 62500,
3400                 .symbol_rate_min = 870000,
3401                 .symbol_rate_max = 11700000,
3402                 .caps = 0x400 |/* FE_CAN_QAM_4 */
3403                         FE_CAN_QAM_16 | FE_CAN_QAM_32  |
3404                         FE_CAN_QAM_64 | FE_CAN_QAM_128 |
3405                         FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
3406         },
3407         .release                                = stv0367_release,
3408         .init                                   = stv0367cab_init,
3409         .sleep                                  = stv0367cab_sleep,
3410         .i2c_gate_ctrl                          = stv0367cab_gate_ctrl,
3411         .set_frontend                           = stv0367cab_set_frontend,
3412         .get_frontend                           = stv0367cab_get_frontend,
3413         .read_status                            = stv0367cab_read_status,
3414 /*      .read_ber                               = stv0367cab_read_ber, */
3415         .read_signal_strength                   = stv0367cab_read_strength,
3416         .read_snr                               = stv0367cab_read_snr,
3417         .read_ucblocks                          = stv0367cab_read_ucblcks,
3418         .get_tune_settings                      = stv0367_get_tune_settings,
3419 };
3420
3421 struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
3422                                    struct i2c_adapter *i2c)
3423 {
3424         struct stv0367_state *state = NULL;
3425         struct stv0367cab_state *cab_state = NULL;
3426
3427         /* allocate memory for the internal state */
3428         state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3429         if (state == NULL)
3430                 goto error;
3431         cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3432         if (cab_state == NULL)
3433                 goto error;
3434
3435         /* setup the state */
3436         state->i2c = i2c;
3437         state->config = config;
3438         cab_state->search_range = 280000;
3439         state->cab_state = cab_state;
3440         state->fe.ops = stv0367cab_ops;
3441         state->fe.demodulator_priv = state;
3442         state->chip_id = stv0367_readreg(state, 0xf000);
3443
3444         dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3445
3446         /* check if the demod is there */
3447         if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3448                 goto error;
3449
3450         return &state->fe;
3451
3452 error:
3453         kfree(cab_state);
3454         kfree(state);
3455         return NULL;
3456 }
3457 EXPORT_SYMBOL(stv0367cab_attach);
3458
3459 MODULE_PARM_DESC(debug, "Set debug");
3460 MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3461
3462 MODULE_AUTHOR("Igor M. Liplianin");
3463 MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3464 MODULE_LICENSE("GPL");