kernel/drivers/media/dvb-frontends/mb86a20s.c

   1 /*
   2  *   Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
   3  *
   4  *   Copyright (C) 2010-2013 Mauro Carvalho Chehab
   5  *   Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
   6  *
   7  *   This program is free software; you can redistribute it and/or
   8  *   modify it under the terms of the GNU General Public License as
   9  *   published by the Free Software Foundation version 2.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  *   General Public License for more details.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <asm/div64.h>
  19
  20 #include "dvb_frontend.h"
  21 #include "mb86a20s.h"
  22
  23 #define NUM_LAYERS 3
  24
  25 enum mb86a20s_bandwidth {
  26         MB86A20S_13SEG = 0,
  27         MB86A20S_13SEG_PARTIAL = 1,
  28         MB86A20S_1SEG = 2,
  29         MB86A20S_3SEG = 3,
  30 };
  31
  32 static u8 mb86a20s_subchannel[] = {
  33         0xb0, 0xc0, 0xd0, 0xe0,
  34         0xf0, 0x00, 0x10, 0x20,
  35 };
  36
  37 struct mb86a20s_state {
  38         struct i2c_adapter *i2c;
  39         const struct mb86a20s_config *config;
  40         u32 last_frequency;
  41
  42         struct dvb_frontend frontend;
  43
  44         u32 if_freq;
  45         enum mb86a20s_bandwidth bw;
  46         bool inversion;
  47         u32 subchannel;
  48
  49         u32 estimated_rate[NUM_LAYERS];
  50         unsigned long get_strength_time;
  51
  52         bool need_init;
  53 };
  54
  55 struct regdata {
  56         u8 reg;
  57         u8 data;
  58 };
  59
  60 #define BER_SAMPLING_RATE       1       /* Seconds */
  61
  62 /*
  63  * Initialization sequence: Use whatevere default values that PV SBTVD
  64  * does on its initialisation, obtained via USB snoop
  65  */
  66 static struct regdata mb86a20s_init1[] = {
  67         { 0x70, 0x0f },
  68         { 0x70, 0xff },
  69         { 0x08, 0x01 },
  70         { 0x50, 0xd1 }, { 0x51, 0x20 },
  71 };
  72
  73 static struct regdata mb86a20s_init2[] = {
  74         { 0x50, 0xd1 }, { 0x51, 0x22 },
  75         { 0x39, 0x01 },
  76         { 0x71, 0x00 },
  77         { 0x3b, 0x21 },
  78         { 0x3c, 0x3a },
  79         { 0x01, 0x0d },
  80         { 0x04, 0x08 }, { 0x05, 0x05 },
  81         { 0x04, 0x0e }, { 0x05, 0x00 },
  82         { 0x04, 0x0f }, { 0x05, 0x14 },
  83         { 0x04, 0x0b }, { 0x05, 0x8c },
  84         { 0x04, 0x00 }, { 0x05, 0x00 },
  85         { 0x04, 0x01 }, { 0x05, 0x07 },
  86         { 0x04, 0x02 }, { 0x05, 0x0f },
  87         { 0x04, 0x03 }, { 0x05, 0xa0 },
  88         { 0x04, 0x09 }, { 0x05, 0x00 },
  89         { 0x04, 0x0a }, { 0x05, 0xff },
  90         { 0x04, 0x27 }, { 0x05, 0x64 },
  91         { 0x04, 0x28 }, { 0x05, 0x00 },
  92         { 0x04, 0x1e }, { 0x05, 0xff },
  93         { 0x04, 0x29 }, { 0x05, 0x0a },
  94         { 0x04, 0x32 }, { 0x05, 0x0a },
  95         { 0x04, 0x14 }, { 0x05, 0x02 },
  96         { 0x04, 0x04 }, { 0x05, 0x00 },
  97         { 0x04, 0x05 }, { 0x05, 0x22 },
  98         { 0x04, 0x06 }, { 0x05, 0x0e },
  99         { 0x04, 0x07 }, { 0x05, 0xd8 },
 100         { 0x04, 0x12 }, { 0x05, 0x00 },
 101         { 0x04, 0x13 }, { 0x05, 0xff },
 102
 103         /*
 104          * On this demod, when the bit count reaches the count below,
 105          * it collects the bit error count. The bit counters are initialized
 106          * to 65535 here. This warrants that all of them will be quickly
 107          * calculated when device gets locked. As TMCC is parsed, the values
 108          * will be adjusted later in the driver's code.
 109          */
 110         { 0x52, 0x01 },                         /* Turn on BER before Viterbi */
 111         { 0x50, 0xa7 }, { 0x51, 0x00 },
 112         { 0x50, 0xa8 }, { 0x51, 0xff },
 113         { 0x50, 0xa9 }, { 0x51, 0xff },
 114         { 0x50, 0xaa }, { 0x51, 0x00 },
 115         { 0x50, 0xab }, { 0x51, 0xff },
 116         { 0x50, 0xac }, { 0x51, 0xff },
 117         { 0x50, 0xad }, { 0x51, 0x00 },
 118         { 0x50, 0xae }, { 0x51, 0xff },
 119         { 0x50, 0xaf }, { 0x51, 0xff },
 120
 121         /*
 122          * On this demod, post BER counts blocks. When the count reaches the
 123          * value below, it collects the block error count. The block counters
 124          * are initialized to 127 here. This warrants that all of them will be
 125          * quickly calculated when device gets locked. As TMCC is parsed, the
 126          * values will be adjusted later in the driver's code.
 127          */
 128         { 0x5e, 0x07 },                         /* Turn on BER after Viterbi */
 129         { 0x50, 0xdc }, { 0x51, 0x00 },
 130         { 0x50, 0xdd }, { 0x51, 0x7f },
 131         { 0x50, 0xde }, { 0x51, 0x00 },
 132         { 0x50, 0xdf }, { 0x51, 0x7f },
 133         { 0x50, 0xe0 }, { 0x51, 0x00 },
 134         { 0x50, 0xe1 }, { 0x51, 0x7f },
 135
 136         /*
 137          * On this demod, when the block count reaches the count below,
 138          * it collects the block error count. The block counters are initialized
 139          * to 127 here. This warrants that all of them will be quickly
 140          * calculated when device gets locked. As TMCC is parsed, the values
 141          * will be adjusted later in the driver's code.
 142          */
 143         { 0x50, 0xb0 }, { 0x51, 0x07 },         /* Enable PER */
 144         { 0x50, 0xb2 }, { 0x51, 0x00 },
 145         { 0x50, 0xb3 }, { 0x51, 0x7f },
 146         { 0x50, 0xb4 }, { 0x51, 0x00 },
 147         { 0x50, 0xb5 }, { 0x51, 0x7f },
 148         { 0x50, 0xb6 }, { 0x51, 0x00 },
 149         { 0x50, 0xb7 }, { 0x51, 0x7f },
 150
 151         { 0x50, 0x50 }, { 0x51, 0x02 },         /* MER manual mode */
 152         { 0x50, 0x51 }, { 0x51, 0x04 },         /* MER symbol 4 */
 153         { 0x45, 0x04 },                         /* CN symbol 4 */
 154         { 0x48, 0x04 },                         /* CN manual mode */
 155         { 0x50, 0xd5 }, { 0x51, 0x01 },
 156         { 0x50, 0xd6 }, { 0x51, 0x1f },
 157         { 0x50, 0xd2 }, { 0x51, 0x03 },
 158         { 0x50, 0xd7 }, { 0x51, 0x3f },
 159         { 0x1c, 0x01 },
 160         { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
 161         { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
 162         { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
 163         { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
 164         { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
 165         { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
 166         { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
 167         { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
 168         { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
 169         { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
 170         { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
 171         { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
 172         { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
 173         { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
 174         { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
 175         { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
 176         { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
 177         { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
 178         { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
 179         { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
 180         { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
 181         { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
 182         { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
 183         { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
 184         { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
 185         { 0x50, 0x1e }, { 0x51, 0x5d },
 186         { 0x50, 0x22 }, { 0x51, 0x00 },
 187         { 0x50, 0x23 }, { 0x51, 0xc8 },
 188         { 0x50, 0x24 }, { 0x51, 0x00 },
 189         { 0x50, 0x25 }, { 0x51, 0xf0 },
 190         { 0x50, 0x26 }, { 0x51, 0x00 },
 191         { 0x50, 0x27 }, { 0x51, 0xc3 },
 192         { 0x50, 0x39 }, { 0x51, 0x02 },
 193         { 0x50, 0xd5 }, { 0x51, 0x01 },
 194         { 0xd0, 0x00 },
 195 };
 196
 197 static struct regdata mb86a20s_reset_reception[] = {
 198         { 0x70, 0xf0 },
 199         { 0x70, 0xff },
 200         { 0x08, 0x01 },
 201         { 0x08, 0x00 },
 202 };
 203
 204 static struct regdata mb86a20s_per_ber_reset[] = {
 205         { 0x53, 0x00 }, /* pre BER Counter reset */
 206         { 0x53, 0x07 },
 207
 208         { 0x5f, 0x00 }, /* post BER Counter reset */
 209         { 0x5f, 0x07 },
 210
 211         { 0x50, 0xb1 }, /* PER Counter reset */
 212         { 0x51, 0x07 },
 213         { 0x51, 0x00 },
 214 };
 215
 216 /*
 217  * I2C read/write functions and macros
 218  */
 219
 220 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
 221                              u8 i2c_addr, u8 reg, u8 data)
 222 {
 223         u8 buf[] = { reg, data };
 224         struct i2c_msg msg = {
 225                 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
 226         };
 227         int rc;
 228
 229         rc = i2c_transfer(state->i2c, &msg, 1);
 230         if (rc != 1) {
 231                 dev_err(&state->i2c->dev,
 232                         "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
 233                         __func__, rc, reg, data);
 234                 return rc;
 235         }
 236
 237         return 0;
 238 }
 239
 240 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
 241                                      u8 i2c_addr, struct regdata *rd, int size)
 242 {
 243         int i, rc;
 244
 245         for (i = 0; i < size; i++) {
 246                 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
 247                                            rd[i].data);
 248                 if (rc < 0)
 249                         return rc;
 250         }
 251         return 0;
 252 }
 253
 254 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
 255                                 u8 i2c_addr, u8 reg)
 256 {
 257         u8 val;
 258         int rc;
 259         struct i2c_msg msg[] = {
 260                 { .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
 261                 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
 262         };
 263
 264         rc = i2c_transfer(state->i2c, msg, 2);
 265
 266         if (rc != 2) {
 267                 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
 268                         __func__, reg, rc);
 269                 return (rc < 0) ? rc : -EIO;
 270         }
 271
 272         return val;
 273 }
 274
 275 #define mb86a20s_readreg(state, reg) \
 276         mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
 277 #define mb86a20s_writereg(state, reg, val) \
 278         mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
 279 #define mb86a20s_writeregdata(state, regdata) \
 280         mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
 281         regdata, ARRAY_SIZE(regdata))
 282
 283 /*
 284  * Ancillary internal routines (likely compiled inlined)
 285  *
 286  * The functions below assume that gateway lock has already obtained
 287  */
 288
 289 static int mb86a20s_read_status(struct dvb_frontend *fe, enum fe_status *status)
 290 {
 291         struct mb86a20s_state *state = fe->demodulator_priv;
 292         int val;
 293
 294         *status = 0;
 295
 296         val = mb86a20s_readreg(state, 0x0a) & 0xf;
 297         if (val < 0)
 298                 return val;
 299
 300         if (val >= 2)
 301                 *status |= FE_HAS_SIGNAL;
 302
 303         if (val >= 4)
 304                 *status |= FE_HAS_CARRIER;
 305
 306         if (val >= 5)
 307                 *status |= FE_HAS_VITERBI;
 308
 309         if (val >= 7)
 310                 *status |= FE_HAS_SYNC;
 311
 312         /*
 313          * Actually, on state S8, it starts receiving TS, but the TS
 314          * output is only on normal state after the transition to S9.
 315          */
 316         if (val >= 9)
 317                 *status |= FE_HAS_LOCK;
 318
 319         dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
 320                  __func__, *status, val);
 321
 322         return val;
 323 }
 324
 325 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
 326 {
 327         struct mb86a20s_state *state = fe->demodulator_priv;
 328         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 329         int rc;
 330         unsigned rf_max, rf_min, rf;
 331
 332         if (state->get_strength_time &&
 333            (!time_after(jiffies, state->get_strength_time)))
 334                 return c->strength.stat[0].uvalue;
 335
 336         /* Reset its value if an error happen */
 337         c->strength.stat[0].uvalue = 0;
 338
 339         /* Does a binary search to get RF strength */
 340         rf_max = 0xfff;
 341         rf_min = 0;
 342         do {
 343                 rf = (rf_max + rf_min) / 2;
 344                 rc = mb86a20s_writereg(state, 0x04, 0x1f);
 345                 if (rc < 0)
 346                         return rc;
 347                 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
 348                 if (rc < 0)
 349                         return rc;
 350                 rc = mb86a20s_writereg(state, 0x04, 0x20);
 351                 if (rc < 0)
 352                         return rc;
 353                 rc = mb86a20s_writereg(state, 0x05, rf);
 354                 if (rc < 0)
 355                         return rc;
 356
 357                 rc = mb86a20s_readreg(state, 0x02);
 358                 if (rc < 0)
 359                         return rc;
 360                 if (rc & 0x08)
 361                         rf_min = (rf_max + rf_min) / 2;
 362                 else
 363                         rf_max = (rf_max + rf_min) / 2;
 364                 if (rf_max - rf_min < 4) {
 365                         rf = (rf_max + rf_min) / 2;
 366
 367                         /* Rescale it from 2^12 (4096) to 2^16 */
 368                         rf = rf << (16 - 12);
 369                         if (rf)
 370                                 rf |= (1 << 12) - 1;
 371
 372                         dev_dbg(&state->i2c->dev,
 373                                 "%s: signal strength = %d (%d < RF=%d < %d)\n",
 374                                 __func__, rf, rf_min, rf >> 4, rf_max);
 375                         c->strength.stat[0].uvalue = rf;
 376                         state->get_strength_time = jiffies +
 377                                                    msecs_to_jiffies(1000);
 378                         return 0;
 379                 }
 380         } while (1);
 381 }
 382
 383 static int mb86a20s_get_modulation(struct mb86a20s_state *state,
 384                                    unsigned layer)
 385 {
 386         int rc;
 387         static unsigned char reg[] = {
 388                 [0] = 0x86,     /* Layer A */
 389                 [1] = 0x8a,     /* Layer B */
 390                 [2] = 0x8e,     /* Layer C */
 391         };
 392
 393         if (layer >= ARRAY_SIZE(reg))
 394                 return -EINVAL;
 395         rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
 396         if (rc < 0)
 397                 return rc;
 398         rc = mb86a20s_readreg(state, 0x6e);
 399         if (rc < 0)
 400                 return rc;
 401         switch ((rc >> 4) & 0x07) {
 402         case 0:
 403                 return DQPSK;
 404         case 1:
 405                 return QPSK;
 406         case 2:
 407                 return QAM_16;
 408         case 3:
 409                 return QAM_64;
 410         default:
 411                 return QAM_AUTO;
 412         }
 413 }
 414
 415 static int mb86a20s_get_fec(struct mb86a20s_state *state,
 416                             unsigned layer)
 417 {
 418         int rc;
 419
 420         static unsigned char reg[] = {
 421                 [0] = 0x87,     /* Layer A */
 422                 [1] = 0x8b,     /* Layer B */
 423                 [2] = 0x8f,     /* Layer C */
 424         };
 425
 426         if (layer >= ARRAY_SIZE(reg))
 427                 return -EINVAL;
 428         rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
 429         if (rc < 0)
 430                 return rc;
 431         rc = mb86a20s_readreg(state, 0x6e);
 432         if (rc < 0)
 433                 return rc;
 434         switch ((rc >> 4) & 0x07) {
 435         case 0:
 436                 return FEC_1_2;
 437         case 1:
 438                 return FEC_2_3;
 439         case 2:
 440                 return FEC_3_4;
 441         case 3:
 442                 return FEC_5_6;
 443         case 4:
 444                 return FEC_7_8;
 445         default:
 446                 return FEC_AUTO;
 447         }
 448 }
 449
 450 static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
 451                                      unsigned layer)
 452 {
 453         int rc;
 454         int interleaving[] = {
 455                 0, 1, 2, 4, 8
 456         };
 457
 458         static unsigned char reg[] = {
 459                 [0] = 0x88,     /* Layer A */
 460                 [1] = 0x8c,     /* Layer B */
 461                 [2] = 0x90,     /* Layer C */
 462         };
 463
 464         if (layer >= ARRAY_SIZE(reg))
 465                 return -EINVAL;
 466         rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
 467         if (rc < 0)
 468                 return rc;
 469         rc = mb86a20s_readreg(state, 0x6e);
 470         if (rc < 0)
 471                 return rc;
 472
 473         return interleaving[(rc >> 4) & 0x07];
 474 }
 475
 476 static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
 477                                       unsigned layer)
 478 {
 479         int rc, count;
 480         static unsigned char reg[] = {
 481                 [0] = 0x89,     /* Layer A */
 482                 [1] = 0x8d,     /* Layer B */
 483                 [2] = 0x91,     /* Layer C */
 484         };
 485
 486         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
 487
 488         if (layer >= ARRAY_SIZE(reg))
 489                 return -EINVAL;
 490
 491         rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
 492         if (rc < 0)
 493                 return rc;
 494         rc = mb86a20s_readreg(state, 0x6e);
 495         if (rc < 0)
 496                 return rc;
 497         count = (rc >> 4) & 0x0f;
 498
 499         dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
 500
 501         return count;
 502 }
 503
 504 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
 505 {
 506         struct mb86a20s_state *state = fe->demodulator_priv;
 507         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 508
 509         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
 510
 511         /* Fixed parameters */
 512         c->delivery_system = SYS_ISDBT;
 513         c->bandwidth_hz = 6000000;
 514
 515         /* Initialize values that will be later autodetected */
 516         c->isdbt_layer_enabled = 0;
 517         c->transmission_mode = TRANSMISSION_MODE_AUTO;
 518         c->guard_interval = GUARD_INTERVAL_AUTO;
 519         c->isdbt_sb_mode = 0;
 520         c->isdbt_sb_segment_count = 0;
 521 }
 522
 523 /*
 524  * Estimates the bit rate using the per-segment bit rate given by
 525  * ABNT/NBR 15601 spec (table 4).
 526  */
 527 static u32 isdbt_rate[3][5][4] = {
 528         {       /* DQPSK/QPSK */
 529                 {  280850,  312060,  330420,  340430 }, /* 1/2 */
 530                 {  374470,  416080,  440560,  453910 }, /* 2/3 */
 531                 {  421280,  468090,  495630,  510650 }, /* 3/4 */
 532                 {  468090,  520100,  550700,  567390 }, /* 5/6 */
 533                 {  491500,  546110,  578230,  595760 }, /* 7/8 */
 534         }, {    /* QAM16 */
 535                 {  561710,  624130,  660840,  680870 }, /* 1/2 */
 536                 {  748950,  832170,  881120,  907820 }, /* 2/3 */
 537                 {  842570,  936190,  991260, 1021300 }, /* 3/4 */
 538                 {  936190, 1040210, 1101400, 1134780 }, /* 5/6 */
 539                 {  983000, 1092220, 1156470, 1191520 }, /* 7/8 */
 540         }, {    /* QAM64 */
 541                 {  842570,  936190,  991260, 1021300 }, /* 1/2 */
 542                 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
 543                 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
 544                 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
 545                 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
 546         }
 547 };
 548
 549 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
 550                                    u32 modulation, u32 forward_error_correction,
 551                                    u32 guard_interval,
 552                                    u32 segment)
 553 {
 554         struct mb86a20s_state *state = fe->demodulator_priv;
 555         u32 rate;
 556         int mod, fec, guard;
 557
 558         /*
 559          * If modulation/fec/guard is not detected, the default is
 560          * to consider the lowest bit rate, to avoid taking too long time
 561          * to get BER.
 562          */
 563         switch (modulation) {
 564         case DQPSK:
 565         case QPSK:
 566         default:
 567                 mod = 0;
 568                 break;
 569         case QAM_16:
 570                 mod = 1;
 571                 break;
 572         case QAM_64:
 573                 mod = 2;
 574                 break;
 575         }
 576
 577         switch (forward_error_correction) {
 578         default:
 579         case FEC_1_2:
 580         case FEC_AUTO:
 581                 fec = 0;
 582                 break;
 583         case FEC_2_3:
 584                 fec = 1;
 585                 break;
 586         case FEC_3_4:
 587                 fec = 2;
 588                 break;
 589         case FEC_5_6:
 590                 fec = 3;
 591                 break;
 592         case FEC_7_8:
 593                 fec = 4;
 594                 break;
 595         }
 596
 597         switch (guard_interval) {
 598         default:
 599         case GUARD_INTERVAL_1_4:
 600                 guard = 0;
 601                 break;
 602         case GUARD_INTERVAL_1_8:
 603                 guard = 1;
 604                 break;
 605         case GUARD_INTERVAL_1_16:
 606                 guard = 2;
 607                 break;
 608         case GUARD_INTERVAL_1_32:
 609                 guard = 3;
 610                 break;
 611         }
 612
 613         /* Samples BER at BER_SAMPLING_RATE seconds */
 614         rate = isdbt_rate[mod][fec][guard] * segment * BER_SAMPLING_RATE;
 615
 616         /* Avoids sampling too quickly or to overflow the register */
 617         if (rate < 256)
 618                 rate = 256;
 619         else if (rate > (1 << 24) - 1)
 620                 rate = (1 << 24) - 1;
 621
 622         dev_dbg(&state->i2c->dev,
 623                 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
 624                 __func__, 'A' + layer,
 625                 segment * isdbt_rate[mod][fec][guard]/1000,
 626                 rate, rate);
 627
 628         state->estimated_rate[layer] = rate;
 629 }
 630
 631 static int mb86a20s_get_frontend(struct dvb_frontend *fe)
 632 {
 633         struct mb86a20s_state *state = fe->demodulator_priv;
 634         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 635         int layer, rc;
 636
 637         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
 638
 639         /* Reset frontend cache to default values */
 640         mb86a20s_reset_frontend_cache(fe);
 641
 642         /* Check for partial reception */
 643         rc = mb86a20s_writereg(state, 0x6d, 0x85);
 644         if (rc < 0)
 645                 return rc;
 646         rc = mb86a20s_readreg(state, 0x6e);
 647         if (rc < 0)
 648                 return rc;
 649         c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
 650
 651         /* Get per-layer data */
 652
 653         for (layer = 0; layer < NUM_LAYERS; layer++) {
 654                 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
 655                         __func__, 'A' + layer);
 656
 657                 rc = mb86a20s_get_segment_count(state, layer);
 658                 if (rc < 0)
 659                         goto noperlayer_error;
 660                 if (rc >= 0 && rc < 14) {
 661                         c->layer[layer].segment_count = rc;
 662                 } else {
 663                         c->layer[layer].segment_count = 0;
 664                         state->estimated_rate[layer] = 0;
 665                         continue;
 666                 }
 667                 c->isdbt_layer_enabled |= 1 << layer;
 668                 rc = mb86a20s_get_modulation(state, layer);
 669                 if (rc < 0)
 670                         goto noperlayer_error;
 671                 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
 672                         __func__, rc);
 673                 c->layer[layer].modulation = rc;
 674                 rc = mb86a20s_get_fec(state, layer);
 675                 if (rc < 0)
 676                         goto noperlayer_error;
 677                 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
 678                         __func__, rc);
 679                 c->layer[layer].fec = rc;
 680                 rc = mb86a20s_get_interleaving(state, layer);
 681                 if (rc < 0)
 682                         goto noperlayer_error;
 683                 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
 684                         __func__, rc);
 685                 c->layer[layer].interleaving = rc;
 686                 mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation,
 687                                        c->layer[layer].fec,
 688                                        c->guard_interval,
 689                                        c->layer[layer].segment_count);
 690         }
 691
 692         rc = mb86a20s_writereg(state, 0x6d, 0x84);
 693         if (rc < 0)
 694                 return rc;
 695         if ((rc & 0x60) == 0x20) {
 696                 c->isdbt_sb_mode = 1;
 697                 /* At least, one segment should exist */
 698                 if (!c->isdbt_sb_segment_count)
 699                         c->isdbt_sb_segment_count = 1;
 700         }
 701
 702         /* Get transmission mode and guard interval */
 703         rc = mb86a20s_readreg(state, 0x07);
 704         if (rc < 0)
 705                 return rc;
 706         c->transmission_mode = TRANSMISSION_MODE_AUTO;
 707         if ((rc & 0x60) == 0x20) {
 708                 /* Only modes 2 and 3 are supported */
 709                 switch ((rc >> 2) & 0x03) {
 710                 case 1:
 711                         c->transmission_mode = TRANSMISSION_MODE_4K;
 712                         break;
 713                 case 2:
 714                         c->transmission_mode = TRANSMISSION_MODE_8K;
 715                         break;
 716                 }
 717         }
 718         c->guard_interval = GUARD_INTERVAL_AUTO;
 719         if (!(rc & 0x10)) {
 720                 /* Guard interval 1/32 is not supported */
 721                 switch (rc & 0x3) {
 722                 case 0:
 723                         c->guard_interval = GUARD_INTERVAL_1_4;
 724                         break;
 725                 case 1:
 726                         c->guard_interval = GUARD_INTERVAL_1_8;
 727                         break;
 728                 case 2:
 729                         c->guard_interval = GUARD_INTERVAL_1_16;
 730                         break;
 731                 }
 732         }
 733         return 0;
 734
 735 noperlayer_error:
 736
 737         /* per-layer info is incomplete; discard all per-layer */
 738         c->isdbt_layer_enabled = 0;
 739
 740         return rc;
 741 }
 742
 743 static int mb86a20s_reset_counters(struct dvb_frontend *fe)
 744 {
 745         struct mb86a20s_state *state = fe->demodulator_priv;
 746         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 747         int rc, val;
 748
 749         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
 750
 751         /* Reset the counters, if the channel changed */
 752         if (state->last_frequency != c->frequency) {
 753                 memset(&c->cnr, 0, sizeof(c->cnr));
 754                 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
 755                 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
 756                 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
 757                 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
 758                 memset(&c->block_error, 0, sizeof(c->block_error));
 759                 memset(&c->block_count, 0, sizeof(c->block_count));
 760
 761                 state->last_frequency = c->frequency;
 762         }
 763
 764         /* Clear status for most stats */
 765
 766         /* BER/PER counter reset */
 767         rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
 768         if (rc < 0)
 769                 goto err;
 770
 771         /* CNR counter reset */
 772         rc = mb86a20s_readreg(state, 0x45);
 773         if (rc < 0)
 774                 goto err;
 775         val = rc;
 776         rc = mb86a20s_writereg(state, 0x45, val | 0x10);
 777         if (rc < 0)
 778                 goto err;
 779         rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
 780         if (rc < 0)
 781                 goto err;
 782
 783         /* MER counter reset */
 784         rc = mb86a20s_writereg(state, 0x50, 0x50);
 785         if (rc < 0)
 786                 goto err;
 787         rc = mb86a20s_readreg(state, 0x51);
 788         if (rc < 0)
 789                 goto err;
 790         val = rc;
 791         rc = mb86a20s_writereg(state, 0x51, val | 0x01);
 792         if (rc < 0)
 793                 goto err;
 794         rc = mb86a20s_writereg(state, 0x51, val & 0x06);
 795         if (rc < 0)
 796                 goto err;
 797
 798         goto ok;
 799 err:
 800         dev_err(&state->i2c->dev,
 801                 "%s: Can't reset FE statistics (error %d).\n",
 802                 __func__, rc);
 803 ok:
 804         return rc;
 805 }
 806
 807 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
 808                                 unsigned layer,
 809                                 u32 *error, u32 *count)
 810 {
 811         struct mb86a20s_state *state = fe->demodulator_priv;
 812         int rc, val;
 813
 814         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
 815
 816         if (layer >= NUM_LAYERS)
 817                 return -EINVAL;
 818
 819         /* Check if the BER measures are already available */
 820         rc = mb86a20s_readreg(state, 0x54);
 821         if (rc < 0)
 822                 return rc;
 823
 824         /* Check if data is available for that layer */
 825         if (!(rc & (1 << layer))) {
 826                 dev_dbg(&state->i2c->dev,
 827                         "%s: preBER for layer %c is not available yet.\n",
 828                         __func__, 'A' + layer);
 829                 return -EBUSY;
 830         }
 831
 832         /* Read Bit Error Count */
 833         rc = mb86a20s_readreg(state, 0x55 + layer * 3);
 834         if (rc < 0)
 835                 return rc;
 836         *error = rc << 16;
 837         rc = mb86a20s_readreg(state, 0x56 + layer * 3);
 838         if (rc < 0)
 839                 return rc;
 840         *error |= rc << 8;
 841         rc = mb86a20s_readreg(state, 0x57 + layer * 3);
 842         if (rc < 0)
 843                 return rc;
 844         *error |= rc;
 845
 846         dev_dbg(&state->i2c->dev,
 847                 "%s: bit error before Viterbi for layer %c: %d.\n",
 848                 __func__, 'A' + layer, *error);
 849
 850         /* Read Bit Count */
 851         rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
 852         if (rc < 0)
 853                 return rc;
 854         rc = mb86a20s_readreg(state, 0x51);
 855         if (rc < 0)
 856                 return rc;
 857         *count = rc << 16;
 858         rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
 859         if (rc < 0)
 860                 return rc;
 861         rc = mb86a20s_readreg(state, 0x51);
 862         if (rc < 0)
 863                 return rc;
 864         *count |= rc << 8;
 865         rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
 866         if (rc < 0)
 867                 return rc;
 868         rc = mb86a20s_readreg(state, 0x51);
 869         if (rc < 0)
 870                 return rc;
 871         *count |= rc;
 872
 873         dev_dbg(&state->i2c->dev,
 874                 "%s: bit count before Viterbi for layer %c: %d.\n",
 875                 __func__, 'A' + layer, *count);
 876
 877
 878         /*
 879          * As we get TMCC data from the frontend, we can better estimate the
 880          * BER bit counters, in order to do the BER measure during a longer
 881          * time. Use those data, if available, to update the bit count
 882          * measure.
 883          */
 884
 885         if (state->estimated_rate[layer]
 886             && state->estimated_rate[layer] != *count) {
 887                 dev_dbg(&state->i2c->dev,
 888                         "%s: updating layer %c preBER counter to %d.\n",
 889                         __func__, 'A' + layer, state->estimated_rate[layer]);
 890
 891                 /* Turn off BER before Viterbi */
 892                 rc = mb86a20s_writereg(state, 0x52, 0x00);
 893
 894                 /* Update counter for this layer */
 895                 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
 896                 if (rc < 0)
 897                         return rc;
 898                 rc = mb86a20s_writereg(state, 0x51,
 899                                        state->estimated_rate[layer] >> 16);
 900                 if (rc < 0)
 901                         return rc;
 902                 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
 903                 if (rc < 0)
 904                         return rc;
 905                 rc = mb86a20s_writereg(state, 0x51,
 906                                        state->estimated_rate[layer] >> 8);
 907                 if (rc < 0)
 908                         return rc;
 909                 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
 910                 if (rc < 0)
 911                         return rc;
 912                 rc = mb86a20s_writereg(state, 0x51,
 913                                        state->estimated_rate[layer]);
 914                 if (rc < 0)
 915                         return rc;
 916
 917                 /* Turn on BER before Viterbi */
 918                 rc = mb86a20s_writereg(state, 0x52, 0x01);
 919
 920                 /* Reset all preBER counters */
 921                 rc = mb86a20s_writereg(state, 0x53, 0x00);
 922                 if (rc < 0)
 923                         return rc;
 924                 rc = mb86a20s_writereg(state, 0x53, 0x07);
 925         } else {
 926                 /* Reset counter to collect new data */
 927                 rc = mb86a20s_readreg(state, 0x53);
 928                 if (rc < 0)
 929                         return rc;
 930                 val = rc;
 931                 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
 932                 if (rc < 0)
 933                         return rc;
 934                 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
 935         }
 936
 937         return rc;
 938 }
 939
 940 static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
 941                                  unsigned layer,
 942                                   u32 *error, u32 *count)
 943 {
 944         struct mb86a20s_state *state = fe->demodulator_priv;
 945         u32 counter, collect_rate;
 946         int rc, val;
 947
 948         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
 949
 950         if (layer >= NUM_LAYERS)
 951                 return -EINVAL;
 952
 953         /* Check if the BER measures are already available */
 954         rc = mb86a20s_readreg(state, 0x60);
 955         if (rc < 0)
 956                 return rc;
 957
 958         /* Check if data is available for that layer */
 959         if (!(rc & (1 << layer))) {
 960                 dev_dbg(&state->i2c->dev,
 961                         "%s: post BER for layer %c is not available yet.\n",
 962                         __func__, 'A' + layer);
 963                 return -EBUSY;
 964         }
 965
 966         /* Read Bit Error Count */
 967         rc = mb86a20s_readreg(state, 0x64 + layer * 3);
 968         if (rc < 0)
 969                 return rc;
 970         *error = rc << 16;
 971         rc = mb86a20s_readreg(state, 0x65 + layer * 3);
 972         if (rc < 0)
 973                 return rc;
 974         *error |= rc << 8;
 975         rc = mb86a20s_readreg(state, 0x66 + layer * 3);
 976         if (rc < 0)
 977                 return rc;
 978         *error |= rc;
 979
 980         dev_dbg(&state->i2c->dev,
 981                 "%s: post bit error for layer %c: %d.\n",
 982                 __func__, 'A' + layer, *error);
 983
 984         /* Read Bit Count */
 985         rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
 986         if (rc < 0)
 987                 return rc;
 988         rc = mb86a20s_readreg(state, 0x51);
 989         if (rc < 0)
 990                 return rc;
 991         counter = rc << 8;
 992         rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
 993         if (rc < 0)
 994                 return rc;
 995         rc = mb86a20s_readreg(state, 0x51);
 996         if (rc < 0)
 997                 return rc;
 998         counter |= rc;
 999         *count = counter * 204 * 8;
1000
1001         dev_dbg(&state->i2c->dev,
1002                 "%s: post bit count for layer %c: %d.\n",
1003                 __func__, 'A' + layer, *count);
1004
1005         /*
1006          * As we get TMCC data from the frontend, we can better estimate the
1007          * BER bit counters, in order to do the BER measure during a longer
1008          * time. Use those data, if available, to update the bit count
1009          * measure.
1010          */
1011
1012         if (!state->estimated_rate[layer])
1013                 goto reset_measurement;
1014
1015         collect_rate = state->estimated_rate[layer] / 204 / 8;
1016         if (collect_rate < 32)
1017                 collect_rate = 32;
1018         if (collect_rate > 65535)
1019                 collect_rate = 65535;
1020         if (collect_rate != counter) {
1021                 dev_dbg(&state->i2c->dev,
1022                         "%s: updating postBER counter on layer %c to %d.\n",
1023                         __func__, 'A' + layer, collect_rate);
1024
1025                 /* Turn off BER after Viterbi */
1026                 rc = mb86a20s_writereg(state, 0x5e, 0x00);
1027
1028                 /* Update counter for this layer */
1029                 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1030                 if (rc < 0)
1031                         return rc;
1032                 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1033                 if (rc < 0)
1034                         return rc;
1035                 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1036                 if (rc < 0)
1037                         return rc;
1038                 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1039                 if (rc < 0)
1040                         return rc;
1041
1042                 /* Turn on BER after Viterbi */
1043                 rc = mb86a20s_writereg(state, 0x5e, 0x07);
1044
1045                 /* Reset all preBER counters */
1046                 rc = mb86a20s_writereg(state, 0x5f, 0x00);
1047                 if (rc < 0)
1048                         return rc;
1049                 rc = mb86a20s_writereg(state, 0x5f, 0x07);
1050
1051                 return rc;
1052         }
1053
1054 reset_measurement:
1055         /* Reset counter to collect new data */
1056         rc = mb86a20s_readreg(state, 0x5f);
1057         if (rc < 0)
1058                 return rc;
1059         val = rc;
1060         rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
1061         if (rc < 0)
1062                 return rc;
1063         rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
1064
1065         return rc;
1066 }
1067
1068 static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1069                             unsigned layer,
1070                             u32 *error, u32 *count)
1071 {
1072         struct mb86a20s_state *state = fe->demodulator_priv;
1073         int rc, val;
1074         u32 collect_rate;
1075         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1076
1077         if (layer >= NUM_LAYERS)
1078                 return -EINVAL;
1079
1080         /* Check if the PER measures are already available */
1081         rc = mb86a20s_writereg(state, 0x50, 0xb8);
1082         if (rc < 0)
1083                 return rc;
1084         rc = mb86a20s_readreg(state, 0x51);
1085         if (rc < 0)
1086                 return rc;
1087
1088         /* Check if data is available for that layer */
1089
1090         if (!(rc & (1 << layer))) {
1091                 dev_dbg(&state->i2c->dev,
1092                         "%s: block counts for layer %c aren't available yet.\n",
1093                         __func__, 'A' + layer);
1094                 return -EBUSY;
1095         }
1096
1097         /* Read Packet error Count */
1098         rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1099         if (rc < 0)
1100                 return rc;
1101         rc = mb86a20s_readreg(state, 0x51);
1102         if (rc < 0)
1103                 return rc;
1104         *error = rc << 8;
1105         rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1106         if (rc < 0)
1107                 return rc;
1108         rc = mb86a20s_readreg(state, 0x51);
1109         if (rc < 0)
1110                 return rc;
1111         *error |= rc;
1112         dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
1113                 __func__, 'A' + layer, *error);
1114
1115         /* Read Bit Count */
1116         rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1117         if (rc < 0)
1118                 return rc;
1119         rc = mb86a20s_readreg(state, 0x51);
1120         if (rc < 0)
1121                 return rc;
1122         *count = rc << 8;
1123         rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1124         if (rc < 0)
1125                 return rc;
1126         rc = mb86a20s_readreg(state, 0x51);
1127         if (rc < 0)
1128                 return rc;
1129         *count |= rc;
1130
1131         dev_dbg(&state->i2c->dev,
1132                 "%s: block count for layer %c: %d.\n",
1133                 __func__, 'A' + layer, *count);
1134
1135         /*
1136          * As we get TMCC data from the frontend, we can better estimate the
1137          * BER bit counters, in order to do the BER measure during a longer
1138          * time. Use those data, if available, to update the bit count
1139          * measure.
1140          */
1141
1142         if (!state->estimated_rate[layer])
1143                 goto reset_measurement;
1144
1145         collect_rate = state->estimated_rate[layer] / 204 / 8;
1146         if (collect_rate < 32)
1147                 collect_rate = 32;
1148         if (collect_rate > 65535)
1149                 collect_rate = 65535;
1150
1151         if (collect_rate != *count) {
1152                 dev_dbg(&state->i2c->dev,
1153                         "%s: updating PER counter on layer %c to %d.\n",
1154                         __func__, 'A' + layer, collect_rate);
1155
1156                 /* Stop PER measurement */
1157                 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1158                 if (rc < 0)
1159                         return rc;
1160                 rc = mb86a20s_writereg(state, 0x51, 0x00);
1161                 if (rc < 0)
1162                         return rc;
1163
1164                 /* Update this layer's counter */
1165                 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1166                 if (rc < 0)
1167                         return rc;
1168                 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1169                 if (rc < 0)
1170                         return rc;
1171                 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1172                 if (rc < 0)
1173                         return rc;
1174                 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1175                 if (rc < 0)
1176                         return rc;
1177
1178                 /* start PER measurement */
1179                 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1180                 if (rc < 0)
1181                         return rc;
1182                 rc = mb86a20s_writereg(state, 0x51, 0x07);
1183                 if (rc < 0)
1184                         return rc;
1185
1186                 /* Reset all counters to collect new data */
1187                 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1188                 if (rc < 0)
1189                         return rc;
1190                 rc = mb86a20s_writereg(state, 0x51, 0x07);
1191                 if (rc < 0)
1192                         return rc;
1193                 rc = mb86a20s_writereg(state, 0x51, 0x00);
1194
1195                 return rc;
1196         }
1197
1198 reset_measurement:
1199         /* Reset counter to collect new data */
1200         rc = mb86a20s_writereg(state, 0x50, 0xb1);
1201         if (rc < 0)
1202                 return rc;
1203         rc = mb86a20s_readreg(state, 0x51);
1204         if (rc < 0)
1205                 return rc;
1206         val = rc;
1207         rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
1208         if (rc < 0)
1209                 return rc;
1210         rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
1211
1212         return rc;
1213 }
1214
1215 struct linear_segments {
1216         unsigned x, y;
1217 };
1218
1219 /*
1220  * All tables below return a dB/1000 measurement
1221  */
1222
1223 static const struct linear_segments cnr_to_db_table[] = {
1224         { 19648,     0},
1225         { 18187,  1000},
1226         { 16534,  2000},
1227         { 14823,  3000},
1228         { 13161,  4000},
1229         { 11622,  5000},
1230         { 10279,  6000},
1231         {  9089,  7000},
1232         {  8042,  8000},
1233         {  7137,  9000},
1234         {  6342, 10000},
1235         {  5641, 11000},
1236         {  5030, 12000},
1237         {  4474, 13000},
1238         {  3988, 14000},
1239         {  3556, 15000},
1240         {  3180, 16000},
1241         {  2841, 17000},
1242         {  2541, 18000},
1243         {  2276, 19000},
1244         {  2038, 20000},
1245         {  1800, 21000},
1246         {  1625, 22000},
1247         {  1462, 23000},
1248         {  1324, 24000},
1249         {  1175, 25000},
1250         {  1063, 26000},
1251         {   980, 27000},
1252         {   907, 28000},
1253         {   840, 29000},
1254         {   788, 30000},
1255 };
1256
1257 static const struct linear_segments cnr_64qam_table[] = {
1258         { 3922688,     0},
1259         { 3920384,  1000},
1260         { 3902720,  2000},
1261         { 3894784,  3000},
1262         { 3882496,  4000},
1263         { 3872768,  5000},
1264         { 3858944,  6000},
1265         { 3851520,  7000},
1266         { 3838976,  8000},
1267         { 3829248,  9000},
1268         { 3818240, 10000},
1269         { 3806976, 11000},
1270         { 3791872, 12000},
1271         { 3767040, 13000},
1272         { 3720960, 14000},
1273         { 3637504, 15000},
1274         { 3498496, 16000},
1275         { 3296000, 17000},
1276         { 3031040, 18000},
1277         { 2715392, 19000},
1278         { 2362624, 20000},
1279         { 1963264, 21000},
1280         { 1649664, 22000},
1281         { 1366784, 23000},
1282         { 1120768, 24000},
1283         {  890880, 25000},
1284         {  723456, 26000},
1285         {  612096, 27000},
1286         {  518912, 28000},
1287         {  448256, 29000},
1288         {  388864, 30000},
1289 };
1290
1291 static const struct linear_segments cnr_16qam_table[] = {
1292         { 5314816,     0},
1293         { 5219072,  1000},
1294         { 5118720,  2000},
1295         { 4998912,  3000},
1296         { 4875520,  4000},
1297         { 4736000,  5000},
1298         { 4604160,  6000},
1299         { 4458752,  7000},
1300         { 4300288,  8000},
1301         { 4092928,  9000},
1302         { 3836160, 10000},
1303         { 3521024, 11000},
1304         { 3155968, 12000},
1305         { 2756864, 13000},
1306         { 2347008, 14000},
1307         { 1955072, 15000},
1308         { 1593600, 16000},
1309         { 1297920, 17000},
1310         { 1043968, 18000},
1311         {  839680, 19000},
1312         {  672256, 20000},
1313         {  523008, 21000},
1314         {  424704, 22000},
1315         {  345088, 23000},
1316         {  280064, 24000},
1317         {  221440, 25000},
1318         {  179712, 26000},
1319         {  151040, 27000},
1320         {  128512, 28000},
1321         {  110080, 29000},
1322         {   95744, 30000},
1323 };
1324
1325 static const struct linear_segments cnr_qpsk_table[] = {
1326         { 2834176,     0},
1327         { 2683648,  1000},
1328         { 2536960,  2000},
1329         { 2391808,  3000},
1330         { 2133248,  4000},
1331         { 1906176,  5000},
1332         { 1666560,  6000},
1333         { 1422080,  7000},
1334         { 1189632,  8000},
1335         {  976384,  9000},
1336         {  790272, 10000},
1337         {  633344, 11000},
1338         {  505600, 12000},
1339         {  402944, 13000},
1340         {  320768, 14000},
1341         {  255488, 15000},
1342         {  204032, 16000},
1343         {  163072, 17000},
1344         {  130304, 18000},
1345         {  105216, 19000},
1346         {   83456, 20000},
1347         {   65024, 21000},
1348         {   52480, 22000},
1349         {   42752, 23000},
1350         {   34560, 24000},
1351         {   27136, 25000},
1352         {   22016, 26000},
1353         {   18432, 27000},
1354         {   15616, 28000},
1355         {   13312, 29000},
1356         {   11520, 30000},
1357 };
1358
1359 static u32 interpolate_value(u32 value, const struct linear_segments *segments,
1360                              unsigned len)
1361 {
1362         u64 tmp64;
1363         u32 dx, dy;
1364         int i, ret;
1365
1366         if (value >= segments[0].x)
1367                 return segments[0].y;
1368         if (value < segments[len-1].x)
1369                 return segments[len-1].y;
1370
1371         for (i = 1; i < len - 1; i++) {
1372                 /* If value is identical, no need to interpolate */
1373                 if (value == segments[i].x)
1374                         return segments[i].y;
1375                 if (value > segments[i].x)
1376                         break;
1377         }
1378
1379         /* Linear interpolation between the two (x,y) points */
1380         dy = segments[i].y - segments[i - 1].y;
1381         dx = segments[i - 1].x - segments[i].x;
1382         tmp64 = value - segments[i].x;
1383         tmp64 *= dy;
1384         do_div(tmp64, dx);
1385         ret = segments[i].y - tmp64;
1386
1387         return ret;
1388 }
1389
1390 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1391 {
1392         struct mb86a20s_state *state = fe->demodulator_priv;
1393         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1394         u32 cnr_linear, cnr;
1395         int rc, val;
1396
1397         /* Check if CNR is available */
1398         rc = mb86a20s_readreg(state, 0x45);
1399         if (rc < 0)
1400                 return rc;
1401
1402         if (!(rc & 0x40)) {
1403                 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
1404                          __func__);
1405                 return -EBUSY;
1406         }
1407         val = rc;
1408
1409         rc = mb86a20s_readreg(state, 0x46);
1410         if (rc < 0)
1411                 return rc;
1412         cnr_linear = rc << 8;
1413
1414         rc = mb86a20s_readreg(state, 0x46);
1415         if (rc < 0)
1416                 return rc;
1417         cnr_linear |= rc;
1418
1419         cnr = interpolate_value(cnr_linear,
1420                                 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1421
1422         c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1423         c->cnr.stat[0].svalue = cnr;
1424
1425         dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1426                 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1427
1428         /* CNR counter reset */
1429         rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1430         if (rc < 0)
1431                 return rc;
1432         rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1433
1434         return rc;
1435 }
1436
1437 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
1438 {
1439         struct mb86a20s_state *state = fe->demodulator_priv;
1440         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1441         u32 mer, cnr;
1442         int rc, val, layer;
1443         const struct linear_segments *segs;
1444         unsigned segs_len;
1445
1446         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1447
1448         /* Check if the measures are already available */
1449         rc = mb86a20s_writereg(state, 0x50, 0x5b);
1450         if (rc < 0)
1451                 return rc;
1452         rc = mb86a20s_readreg(state, 0x51);
1453         if (rc < 0)
1454                 return rc;
1455
1456         /* Check if data is available */
1457         if (!(rc & 0x01)) {
1458                 dev_dbg(&state->i2c->dev,
1459                         "%s: MER measures aren't available yet.\n", __func__);
1460                 return -EBUSY;
1461         }
1462
1463         /* Read all layers */
1464         for (layer = 0; layer < NUM_LAYERS; layer++) {
1465                 if (!(c->isdbt_layer_enabled & (1 << layer))) {
1466                         c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1467                         continue;
1468                 }
1469
1470                 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
1471                 if (rc < 0)
1472                         return rc;
1473                 rc = mb86a20s_readreg(state, 0x51);
1474                 if (rc < 0)
1475                         return rc;
1476                 mer = rc << 16;
1477                 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
1478                 if (rc < 0)
1479                         return rc;
1480                 rc = mb86a20s_readreg(state, 0x51);
1481                 if (rc < 0)
1482                         return rc;
1483                 mer |= rc << 8;
1484                 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
1485                 if (rc < 0)
1486                         return rc;
1487                 rc = mb86a20s_readreg(state, 0x51);
1488                 if (rc < 0)
1489                         return rc;
1490                 mer |= rc;
1491
1492                 switch (c->layer[layer].modulation) {
1493                 case DQPSK:
1494                 case QPSK:
1495                         segs = cnr_qpsk_table;
1496                         segs_len = ARRAY_SIZE(cnr_qpsk_table);
1497                         break;
1498                 case QAM_16:
1499                         segs = cnr_16qam_table;
1500                         segs_len = ARRAY_SIZE(cnr_16qam_table);
1501                         break;
1502                 default:
1503                 case QAM_64:
1504                         segs = cnr_64qam_table;
1505                         segs_len = ARRAY_SIZE(cnr_64qam_table);
1506                         break;
1507                 }
1508                 cnr = interpolate_value(mer, segs, segs_len);
1509
1510                 c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
1511                 c->cnr.stat[1 + layer].svalue = cnr;
1512
1513                 dev_dbg(&state->i2c->dev,
1514                         "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1515                         __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
1516
1517         }
1518
1519         /* Start a new MER measurement */
1520         /* MER counter reset */
1521         rc = mb86a20s_writereg(state, 0x50, 0x50);
1522         if (rc < 0)
1523                 return rc;
1524         rc = mb86a20s_readreg(state, 0x51);
1525         if (rc < 0)
1526                 return rc;
1527         val = rc;
1528
1529         rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1530         if (rc < 0)
1531                 return rc;
1532         rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1533         if (rc < 0)
1534                 return rc;
1535
1536         return 0;
1537 }
1538
1539 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1540 {
1541         struct mb86a20s_state *state = fe->demodulator_priv;
1542         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1543         int layer;
1544
1545         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1546
1547         /* Fill the length of each status counter */
1548
1549         /* Only global stats */
1550         c->strength.len = 1;
1551
1552         /* Per-layer stats - 3 layers + global */
1553         c->cnr.len = NUM_LAYERS + 1;
1554         c->pre_bit_error.len = NUM_LAYERS + 1;
1555         c->pre_bit_count.len = NUM_LAYERS + 1;
1556         c->post_bit_error.len = NUM_LAYERS + 1;
1557         c->post_bit_count.len = NUM_LAYERS + 1;
1558         c->block_error.len = NUM_LAYERS + 1;
1559         c->block_count.len = NUM_LAYERS + 1;
1560
1561         /* Signal is always available */
1562         c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1563         c->strength.stat[0].uvalue = 0;
1564
1565         /* Put all of them at FE_SCALE_NOT_AVAILABLE */
1566         for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
1567                 c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1568                 c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1569                 c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1570                 c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1571                 c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1572                 c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1573                 c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1574         }
1575 }
1576
1577 static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
1578 {
1579         struct mb86a20s_state *state = fe->demodulator_priv;
1580         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1581         int rc = 0, layer;
1582         u32 bit_error = 0, bit_count = 0;
1583         u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
1584         u32 t_post_bit_error = 0, t_post_bit_count = 0;
1585         u32 block_error = 0, block_count = 0;
1586         u32 t_block_error = 0, t_block_count = 0;
1587         int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1588         int per_layers = 0;
1589
1590         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1591
1592         mb86a20s_get_main_CNR(fe);
1593
1594         /* Get per-layer stats */
1595         mb86a20s_get_blk_error_layer_CNR(fe);
1596
1597         /*
1598          * At state 7, only CNR is available
1599          * For BER measures, state=9 is required
1600          * FIXME: we may get MER measures with state=8
1601          */
1602         if (status_nr < 9)
1603                 return 0;
1604
1605         for (layer = 0; layer < NUM_LAYERS; layer++) {
1606                 if (c->isdbt_layer_enabled & (1 << layer)) {
1607                         /* Layer is active and has rc segments */
1608                         active_layers++;
1609
1610                         /* Handle BER before vterbi */
1611                         rc = mb86a20s_get_pre_ber(fe, layer,
1612                                                   &bit_error, &bit_count);
1613                         if (rc >= 0) {
1614                                 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1615                                 c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
1616                                 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1617                                 c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
1618                         } else if (rc != -EBUSY) {
1619                                 /*
1620                                         * If an I/O error happened,
1621                                         * measures are now unavailable
1622                                         */
1623                                 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1624                                 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1625                                 dev_err(&state->i2c->dev,
1626                                         "%s: Can't get BER for layer %c (error %d).\n",
1627                                         __func__, 'A' + layer, rc);
1628                         }
1629                         if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1630                                 pre_ber_layers++;
1631
1632                         /* Handle BER post vterbi */
1633                         rc = mb86a20s_get_post_ber(fe, layer,
1634                                                    &bit_error, &bit_count);
1635                         if (rc >= 0) {
1636                                 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1637                                 c->post_bit_error.stat[1 + layer].uvalue += bit_error;
1638                                 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1639                                 c->post_bit_count.stat[1 + layer].uvalue += bit_count;
1640                         } else if (rc != -EBUSY) {
1641                                 /*
1642                                         * If an I/O error happened,
1643                                         * measures are now unavailable
1644                                         */
1645                                 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1646                                 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1647                                 dev_err(&state->i2c->dev,
1648                                         "%s: Can't get BER for layer %c (error %d).\n",
1649                                         __func__, 'A' + layer, rc);
1650                         }
1651                         if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1652                                 post_ber_layers++;
1653
1654                         /* Handle Block errors for PER/UCB reports */
1655                         rc = mb86a20s_get_blk_error(fe, layer,
1656                                                 &block_error,
1657                                                 &block_count);
1658                         if (rc >= 0) {
1659                                 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1660                                 c->block_error.stat[1 + layer].uvalue += block_error;
1661                                 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1662                                 c->block_count.stat[1 + layer].uvalue += block_count;
1663                         } else if (rc != -EBUSY) {
1664                                 /*
1665                                         * If an I/O error happened,
1666                                         * measures are now unavailable
1667                                         */
1668                                 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1669                                 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1670                                 dev_err(&state->i2c->dev,
1671                                         "%s: Can't get PER for layer %c (error %d).\n",
1672                                         __func__, 'A' + layer, rc);
1673
1674                         }
1675                         if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1676                                 per_layers++;
1677
1678                         /* Update total preBER */
1679                         t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
1680                         t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
1681
1682                         /* Update total postBER */
1683                         t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
1684                         t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
1685
1686                         /* Update total PER */
1687                         t_block_error += c->block_error.stat[1 + layer].uvalue;
1688                         t_block_count += c->block_count.stat[1 + layer].uvalue;
1689                 }
1690         }
1691
1692         /*
1693          * Start showing global count if at least one error count is
1694          * available.
1695          */
1696         if (pre_ber_layers) {
1697                 /*
1698                  * At least one per-layer BER measure was read. We can now
1699                  * calculate the total BER
1700                  *
1701                  * Total Bit Error/Count is calculated as the sum of the
1702                  * bit errors on all active layers.
1703                  */
1704                 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1705                 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1706                 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1707                 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
1708         } else {
1709                 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1710                 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1711         }
1712
1713         /*
1714          * Start showing global count if at least one error count is
1715          * available.
1716          */
1717         if (post_ber_layers) {
1718                 /*
1719                  * At least one per-layer BER measure was read. We can now
1720                  * calculate the total BER
1721                  *
1722                  * Total Bit Error/Count is calculated as the sum of the
1723                  * bit errors on all active layers.
1724                  */
1725                 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1726                 c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1727                 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1728                 c->post_bit_count.stat[0].uvalue = t_post_bit_count;
1729         } else {
1730                 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1731                 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1732         }
1733
1734         if (per_layers) {
1735                 /*
1736                  * At least one per-layer UCB measure was read. We can now
1737                  * calculate the total UCB
1738                  *
1739                  * Total block Error/Count is calculated as the sum of the
1740                  * block errors on all active layers.
1741                  */
1742                 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1743                 c->block_error.stat[0].uvalue = t_block_error;
1744                 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1745                 c->block_count.stat[0].uvalue = t_block_count;
1746         } else {
1747                 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1748                 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1749         }
1750
1751         return rc;
1752 }
1753
1754 /*
1755  * The functions below are called via DVB callbacks, so they need to
1756  * properly use the I2C gate control
1757  */
1758
1759 static int mb86a20s_initfe(struct dvb_frontend *fe)
1760 {
1761         struct mb86a20s_state *state = fe->demodulator_priv;
1762         u64 pll;
1763         u32 fclk;
1764         int rc;
1765         u8  regD5 = 1, reg71, reg09 = 0x3a;
1766
1767         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1768
1769         if (fe->ops.i2c_gate_ctrl)
1770                 fe->ops.i2c_gate_ctrl(fe, 0);
1771
1772         /* Initialize the frontend */
1773         rc = mb86a20s_writeregdata(state, mb86a20s_init1);
1774         if (rc < 0)
1775                 goto err;
1776
1777         if (!state->inversion)
1778                 reg09 |= 0x04;
1779         rc = mb86a20s_writereg(state, 0x09, reg09);
1780         if (rc < 0)
1781                 goto err;
1782         if (!state->bw)
1783                 reg71 = 1;
1784         else
1785                 reg71 = 0;
1786         rc = mb86a20s_writereg(state, 0x39, reg71);
1787         if (rc < 0)
1788                 goto err;
1789         rc = mb86a20s_writereg(state, 0x71, state->bw);
1790         if (rc < 0)
1791                 goto err;
1792         if (state->subchannel) {
1793                 rc = mb86a20s_writereg(state, 0x44, state->subchannel);
1794                 if (rc < 0)
1795                         goto err;
1796         }
1797
1798         fclk = state->config->fclk;
1799         if (!fclk)
1800                 fclk = 32571428;
1801
1802         /* Adjust IF frequency to match tuner */
1803         if (fe->ops.tuner_ops.get_if_frequency)
1804                 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1805
1806         if (!state->if_freq)
1807                 state->if_freq = 3300000;
1808
1809         pll = (((u64)1) << 34) * state->if_freq;
1810         do_div(pll, 63 * fclk);
1811         pll = (1 << 25) - pll;
1812         rc = mb86a20s_writereg(state, 0x28, 0x2a);
1813         if (rc < 0)
1814                 goto err;
1815         rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1816         if (rc < 0)
1817                 goto err;
1818         rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1819         if (rc < 0)
1820                 goto err;
1821         rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1822         if (rc < 0)
1823                 goto err;
1824         dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
1825                 __func__, fclk, state->if_freq, (long long)pll);
1826
1827         /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1828         pll = state->if_freq * 1677721600L;
1829         do_div(pll, 1628571429L);
1830         rc = mb86a20s_writereg(state, 0x28, 0x20);
1831         if (rc < 0)
1832                 goto err;
1833         rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1834         if (rc < 0)
1835                 goto err;
1836         rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1837         if (rc < 0)
1838                 goto err;
1839         rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1840         if (rc < 0)
1841                 goto err;
1842         dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
1843                 __func__, state->if_freq, (long long)pll);
1844
1845         if (!state->config->is_serial)
1846                 regD5 &= ~1;
1847
1848         rc = mb86a20s_writereg(state, 0x50, 0xd5);
1849         if (rc < 0)
1850                 goto err;
1851         rc = mb86a20s_writereg(state, 0x51, regD5);
1852         if (rc < 0)
1853                 goto err;
1854
1855         rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1856         if (rc < 0)
1857                 goto err;
1858
1859
1860 err:
1861         if (fe->ops.i2c_gate_ctrl)
1862                 fe->ops.i2c_gate_ctrl(fe, 1);
1863
1864         if (rc < 0) {
1865                 state->need_init = true;
1866                 dev_info(&state->i2c->dev,
1867                          "mb86a20s: Init failed. Will try again later\n");
1868         } else {
1869                 state->need_init = false;
1870                 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
1871         }
1872         return rc;
1873 }
1874
1875 static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1876 {
1877         struct mb86a20s_state *state = fe->demodulator_priv;
1878         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1879         int rc, if_freq;
1880         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1881
1882         if (!c->isdbt_layer_enabled)
1883                 c->isdbt_layer_enabled = 7;
1884
1885         if (c->isdbt_layer_enabled == 1)
1886                 state->bw = MB86A20S_1SEG;
1887         else if (c->isdbt_partial_reception)
1888                 state->bw = MB86A20S_13SEG_PARTIAL;
1889         else
1890                 state->bw = MB86A20S_13SEG;
1891
1892         if (c->inversion == INVERSION_ON)
1893                 state->inversion = true;
1894         else
1895                 state->inversion = false;
1896
1897         if (!c->isdbt_sb_mode) {
1898                 state->subchannel = 0;
1899         } else {
1900                 if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
1901                         c->isdbt_sb_subchannel = 0;
1902
1903                 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
1904         }
1905
1906         /*
1907          * Gate should already be opened, but it doesn't hurt to
1908          * double-check
1909          */
1910         if (fe->ops.i2c_gate_ctrl)
1911                 fe->ops.i2c_gate_ctrl(fe, 1);
1912         fe->ops.tuner_ops.set_params(fe);
1913
1914         if (fe->ops.tuner_ops.get_if_frequency)
1915                 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1916
1917         /*
1918          * Make it more reliable: if, for some reason, the initial
1919          * device initialization doesn't happen, initialize it when
1920          * a SBTVD parameters are adjusted.
1921          *
1922          * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1923          * the agc callback logic is not called during DVB attach time,
1924          * causing mb86a20s to not be initialized with Kworld SBTVD.
1925          * So, this hack is needed, in order to make Kworld SBTVD to work.
1926          *
1927          * It is also needed to change the IF after the initial init.
1928          *
1929          * HACK: Always init the frontend when set_frontend is called:
1930          * it was noticed that, on some devices, it fails to lock on a
1931          * different channel. So, it is better to reset everything, even
1932          * wasting some time, than to loose channel lock.
1933          */
1934         mb86a20s_initfe(fe);
1935
1936         if (fe->ops.i2c_gate_ctrl)
1937                 fe->ops.i2c_gate_ctrl(fe, 0);
1938
1939         rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
1940         mb86a20s_reset_counters(fe);
1941         mb86a20s_stats_not_ready(fe);
1942
1943         if (fe->ops.i2c_gate_ctrl)
1944                 fe->ops.i2c_gate_ctrl(fe, 1);
1945
1946         return rc;
1947 }
1948
1949 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1950                                           enum fe_status *status)
1951 {
1952         struct mb86a20s_state *state = fe->demodulator_priv;
1953         int rc, status_nr;
1954
1955         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1956
1957         if (fe->ops.i2c_gate_ctrl)
1958                 fe->ops.i2c_gate_ctrl(fe, 0);
1959
1960         /* Get lock */
1961         status_nr = mb86a20s_read_status(fe, status);
1962         if (status_nr < 7) {
1963                 mb86a20s_stats_not_ready(fe);
1964                 mb86a20s_reset_frontend_cache(fe);
1965         }
1966         if (status_nr < 0) {
1967                 dev_err(&state->i2c->dev,
1968                         "%s: Can't read frontend lock status\n", __func__);
1969                 goto error;
1970         }
1971
1972         /* Get signal strength */
1973         rc = mb86a20s_read_signal_strength(fe);
1974         if (rc < 0) {
1975                 dev_err(&state->i2c->dev,
1976                         "%s: Can't reset VBER registers.\n", __func__);
1977                 mb86a20s_stats_not_ready(fe);
1978                 mb86a20s_reset_frontend_cache(fe);
1979
1980                 rc = 0;         /* Status is OK */
1981                 goto error;
1982         }
1983
1984         if (status_nr >= 7) {
1985                 /* Get TMCC info*/
1986                 rc = mb86a20s_get_frontend(fe);
1987                 if (rc < 0) {
1988                         dev_err(&state->i2c->dev,
1989                                 "%s: Can't get FE TMCC data.\n", __func__);
1990                         rc = 0;         /* Status is OK */
1991                         goto error;
1992                 }
1993
1994                 /* Get statistics */
1995                 rc = mb86a20s_get_stats(fe, status_nr);
1996                 if (rc < 0 && rc != -EBUSY) {
1997                         dev_err(&state->i2c->dev,
1998                                 "%s: Can't get FE statistics.\n", __func__);
1999                         rc = 0;
2000                         goto error;
2001                 }
2002                 rc = 0; /* Don't return EBUSY to userspace */
2003         }
2004         goto ok;
2005
2006 error:
2007         mb86a20s_stats_not_ready(fe);
2008
2009 ok:
2010         if (fe->ops.i2c_gate_ctrl)
2011                 fe->ops.i2c_gate_ctrl(fe, 1);
2012
2013         return rc;
2014 }
2015
2016 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
2017                                                     u16 *strength)
2018 {
2019         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2020
2021
2022         *strength = c->strength.stat[0].uvalue;
2023
2024         return 0;
2025 }
2026
2027 static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe)
2028 {
2029         /*
2030          * get_frontend is now handled together with other stats
2031          * retrival, when read_status() is called, as some statistics
2032          * will depend on the layers detection.
2033          */
2034         return 0;
2035 };
2036
2037 static int mb86a20s_tune(struct dvb_frontend *fe,
2038                         bool re_tune,
2039                         unsigned int mode_flags,
2040                         unsigned int *delay,
2041                         enum fe_status *status)
2042 {
2043         struct mb86a20s_state *state = fe->demodulator_priv;
2044         int rc = 0;
2045
2046         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2047
2048         if (re_tune)
2049                 rc = mb86a20s_set_frontend(fe);
2050
2051         if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
2052                 mb86a20s_read_status_and_stats(fe, status);
2053
2054         return rc;
2055 }
2056
2057 static void mb86a20s_release(struct dvb_frontend *fe)
2058 {
2059         struct mb86a20s_state *state = fe->demodulator_priv;
2060
2061         dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2062
2063         kfree(state);
2064 }
2065
2066 static int mb86a20s_get_frontend_algo(struct dvb_frontend *fe)
2067 {
2068         return DVBFE_ALGO_HW;
2069 }
2070
2071 static struct dvb_frontend_ops mb86a20s_ops;
2072
2073 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
2074                                     struct i2c_adapter *i2c)
2075 {
2076         struct mb86a20s_state *state;
2077         u8      rev;
2078
2079         dev_dbg(&i2c->dev, "%s called.\n", __func__);
2080
2081         /* allocate memory for the internal state */
2082         state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
2083         if (state == NULL) {
2084                 dev_err(&i2c->dev,
2085                         "%s: unable to allocate memory for state\n", __func__);
2086                 goto error;
2087         }
2088
2089         /* setup the state */
2090         state->config = config;
2091         state->i2c = i2c;
2092
2093         /* create dvb_frontend */
2094         memcpy(&state->frontend.ops, &mb86a20s_ops,
2095                 sizeof(struct dvb_frontend_ops));
2096         state->frontend.demodulator_priv = state;
2097
2098         /* Check if it is a mb86a20s frontend */
2099         rev = mb86a20s_readreg(state, 0);
2100
2101         if (rev == 0x13) {
2102                 dev_info(&i2c->dev,
2103                          "Detected a Fujitsu mb86a20s frontend\n");
2104         } else {
2105                 dev_dbg(&i2c->dev,
2106                         "Frontend revision %d is unknown - aborting.\n",
2107                        rev);
2108                 goto error;
2109         }
2110
2111         return &state->frontend;
2112
2113 error:
2114         kfree(state);
2115         return NULL;
2116 }
2117 EXPORT_SYMBOL(mb86a20s_attach);
2118
2119 static struct dvb_frontend_ops mb86a20s_ops = {
2120         .delsys = { SYS_ISDBT },
2121         /* Use dib8000 values per default */
2122         .info = {
2123                 .name = "Fujitsu mb86A20s",
2124                 .caps = FE_CAN_RECOVER  |
2125                         FE_CAN_FEC_1_2  | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2126                         FE_CAN_FEC_5_6  | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2127                         FE_CAN_QPSK     | FE_CAN_QAM_16  | FE_CAN_QAM_64 |
2128                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2129                         FE_CAN_GUARD_INTERVAL_AUTO    | FE_CAN_HIERARCHY_AUTO,
2130                 /* Actually, those values depend on the used tuner */
2131                 .frequency_min = 45000000,
2132                 .frequency_max = 864000000,
2133                 .frequency_stepsize = 62500,
2134         },
2135
2136         .release = mb86a20s_release,
2137
2138         .init = mb86a20s_initfe,
2139         .set_frontend = mb86a20s_set_frontend,
2140         .get_frontend = mb86a20s_get_frontend_dummy,
2141         .read_status = mb86a20s_read_status_and_stats,
2142         .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
2143         .tune = mb86a20s_tune,
2144         .get_frontend_algo = mb86a20s_get_frontend_algo,
2145 };
2146
2147 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2148 MODULE_AUTHOR("Mauro Carvalho Chehab");
2149 MODULE_LICENSE("GPL");