kernel/drivers/media/dvb-frontends/lgdt3305.c

   1 /*
   2  *    Support for LG Electronics LGDT3304 and LGDT3305 - VSB/QAM
   3  *
   4  *    Copyright (C) 2008, 2009, 2010 Michael Krufky <mkrufky@linuxtv.org>
   5  *
   6  *    LGDT3304 support by Jarod Wilson <jarod@redhat.com>
   7  *
   8  *    This program is free software; you can redistribute it and/or modify
   9  *    it under the terms of the GNU General Public License as published by
  10  *    the Free Software Foundation; either version 2 of the License, or
  11  *    (at your option) any later version.
  12  *
  13  *    This program is distributed in the hope that it will be useful,
  14  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *    GNU General Public License for more details.
  17  *
  18  *    You should have received a copy of the GNU General Public License
  19  *    along with this program; if not, write to the Free Software
  20  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  */
  23
  24 #include <asm/div64.h>
  25 #include <linux/dvb/frontend.h>
  26 #include <linux/slab.h>
  27 #include "dvb_math.h"
  28 #include "lgdt3305.h"
  29
  30 static int debug;
  31 module_param(debug, int, 0644);
  32 MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
  33
  34 #define DBG_INFO 1
  35 #define DBG_REG  2
  36
  37 #define lg_printk(kern, fmt, arg...)                                    \
  38         printk(kern "%s: " fmt, __func__, ##arg)
  39
  40 #define lg_info(fmt, arg...)    printk(KERN_INFO "lgdt3305: " fmt, ##arg)
  41 #define lg_warn(fmt, arg...)    lg_printk(KERN_WARNING,       fmt, ##arg)
  42 #define lg_err(fmt, arg...)     lg_printk(KERN_ERR,           fmt, ##arg)
  43 #define lg_dbg(fmt, arg...) if (debug & DBG_INFO)                       \
  44                                 lg_printk(KERN_DEBUG,         fmt, ##arg)
  45 #define lg_reg(fmt, arg...) if (debug & DBG_REG)                        \
  46                                 lg_printk(KERN_DEBUG,         fmt, ##arg)
  47
  48 #define lg_fail(ret)                                                    \
  49 ({                                                                      \
  50         int __ret;                                                      \
  51         __ret = (ret < 0);                                              \
  52         if (__ret)                                                      \
  53                 lg_err("error %d on line %d\n", ret, __LINE__);         \
  54         __ret;                                                          \
  55 })
  56
  57 struct lgdt3305_state {
  58         struct i2c_adapter *i2c_adap;
  59         const struct lgdt3305_config *cfg;
  60
  61         struct dvb_frontend frontend;
  62
  63         fe_modulation_t current_modulation;
  64         u32 current_frequency;
  65         u32 snr;
  66 };
  67
  68 /* ------------------------------------------------------------------------ */
  69
  70 /* FIXME: verify & document the LGDT3304 registers */
  71
  72 #define LGDT3305_GEN_CTRL_1                   0x0000
  73 #define LGDT3305_GEN_CTRL_2                   0x0001
  74 #define LGDT3305_GEN_CTRL_3                   0x0002
  75 #define LGDT3305_GEN_STATUS                   0x0003
  76 #define LGDT3305_GEN_CONTROL                  0x0007
  77 #define LGDT3305_GEN_CTRL_4                   0x000a
  78 #define LGDT3305_DGTL_AGC_REF_1               0x0012
  79 #define LGDT3305_DGTL_AGC_REF_2               0x0013
  80 #define LGDT3305_CR_CTR_FREQ_1                0x0106
  81 #define LGDT3305_CR_CTR_FREQ_2                0x0107
  82 #define LGDT3305_CR_CTR_FREQ_3                0x0108
  83 #define LGDT3305_CR_CTR_FREQ_4                0x0109
  84 #define LGDT3305_CR_MSE_1                     0x011b
  85 #define LGDT3305_CR_MSE_2                     0x011c
  86 #define LGDT3305_CR_LOCK_STATUS               0x011d
  87 #define LGDT3305_CR_CTRL_7                    0x0126
  88 #define LGDT3305_AGC_POWER_REF_1              0x0300
  89 #define LGDT3305_AGC_POWER_REF_2              0x0301
  90 #define LGDT3305_AGC_DELAY_PT_1               0x0302
  91 #define LGDT3305_AGC_DELAY_PT_2               0x0303
  92 #define LGDT3305_RFAGC_LOOP_FLTR_BW_1         0x0306
  93 #define LGDT3305_RFAGC_LOOP_FLTR_BW_2         0x0307
  94 #define LGDT3305_IFBW_1                       0x0308
  95 #define LGDT3305_IFBW_2                       0x0309
  96 #define LGDT3305_AGC_CTRL_1                   0x030c
  97 #define LGDT3305_AGC_CTRL_4                   0x0314
  98 #define LGDT3305_EQ_MSE_1                     0x0413
  99 #define LGDT3305_EQ_MSE_2                     0x0414
 100 #define LGDT3305_EQ_MSE_3                     0x0415
 101 #define LGDT3305_PT_MSE_1                     0x0417
 102 #define LGDT3305_PT_MSE_2                     0x0418
 103 #define LGDT3305_PT_MSE_3                     0x0419
 104 #define LGDT3305_FEC_BLOCK_CTRL               0x0504
 105 #define LGDT3305_FEC_LOCK_STATUS              0x050a
 106 #define LGDT3305_FEC_PKT_ERR_1                0x050c
 107 #define LGDT3305_FEC_PKT_ERR_2                0x050d
 108 #define LGDT3305_TP_CTRL_1                    0x050e
 109 #define LGDT3305_BERT_PERIOD                  0x0801
 110 #define LGDT3305_BERT_ERROR_COUNT_1           0x080a
 111 #define LGDT3305_BERT_ERROR_COUNT_2           0x080b
 112 #define LGDT3305_BERT_ERROR_COUNT_3           0x080c
 113 #define LGDT3305_BERT_ERROR_COUNT_4           0x080d
 114
 115 static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val)
 116 {
 117         int ret;
 118         u8 buf[] = { reg >> 8, reg & 0xff, val };
 119         struct i2c_msg msg = {
 120                 .addr = state->cfg->i2c_addr, .flags = 0,
 121                 .buf = buf, .len = 3,
 122         };
 123
 124         lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
 125
 126         ret = i2c_transfer(state->i2c_adap, &msg, 1);
 127
 128         if (ret != 1) {
 129                 lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
 130                        msg.buf[0], msg.buf[1], msg.buf[2], ret);
 131                 if (ret < 0)
 132                         return ret;
 133                 else
 134                         return -EREMOTEIO;
 135         }
 136         return 0;
 137 }
 138
 139 static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val)
 140 {
 141         int ret;
 142         u8 reg_buf[] = { reg >> 8, reg & 0xff };
 143         struct i2c_msg msg[] = {
 144                 { .addr = state->cfg->i2c_addr,
 145                   .flags = 0, .buf = reg_buf, .len = 2 },
 146                 { .addr = state->cfg->i2c_addr,
 147                   .flags = I2C_M_RD, .buf = val, .len = 1 },
 148         };
 149
 150         lg_reg("reg: 0x%04x\n", reg);
 151
 152         ret = i2c_transfer(state->i2c_adap, msg, 2);
 153
 154         if (ret != 2) {
 155                 lg_err("error (addr %02x reg %04x error (ret == %i)\n",
 156                        state->cfg->i2c_addr, reg, ret);
 157                 if (ret < 0)
 158                         return ret;
 159                 else
 160                         return -EREMOTEIO;
 161         }
 162         return 0;
 163 }
 164
 165 #define read_reg(state, reg)                                            \
 166 ({                                                                      \
 167         u8 __val;                                                       \
 168         int ret = lgdt3305_read_reg(state, reg, &__val);                \
 169         if (lg_fail(ret))                                               \
 170                 __val = 0;                                              \
 171         __val;                                                          \
 172 })
 173
 174 static int lgdt3305_set_reg_bit(struct lgdt3305_state *state,
 175                                 u16 reg, int bit, int onoff)
 176 {
 177         u8 val;
 178         int ret;
 179
 180         lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
 181
 182         ret = lgdt3305_read_reg(state, reg, &val);
 183         if (lg_fail(ret))
 184                 goto fail;
 185
 186         val &= ~(1 << bit);
 187         val |= (onoff & 1) << bit;
 188
 189         ret = lgdt3305_write_reg(state, reg, val);
 190 fail:
 191         return ret;
 192 }
 193
 194 struct lgdt3305_reg {
 195         u16 reg;
 196         u8 val;
 197 };
 198
 199 static int lgdt3305_write_regs(struct lgdt3305_state *state,
 200                                struct lgdt3305_reg *regs, int len)
 201 {
 202         int i, ret;
 203
 204         lg_reg("writing %d registers...\n", len);
 205
 206         for (i = 0; i < len - 1; i++) {
 207                 ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val);
 208                 if (lg_fail(ret))
 209                         return ret;
 210         }
 211         return 0;
 212 }
 213
 214 /* ------------------------------------------------------------------------ */
 215
 216 static int lgdt3305_soft_reset(struct lgdt3305_state *state)
 217 {
 218         int ret;
 219
 220         lg_dbg("\n");
 221
 222         ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 0);
 223         if (lg_fail(ret))
 224                 goto fail;
 225
 226         msleep(20);
 227         ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 1);
 228 fail:
 229         return ret;
 230 }
 231
 232 static inline int lgdt3305_mpeg_mode(struct lgdt3305_state *state,
 233                                      enum lgdt3305_mpeg_mode mode)
 234 {
 235         lg_dbg("(%d)\n", mode);
 236         return lgdt3305_set_reg_bit(state, LGDT3305_TP_CTRL_1, 5, mode);
 237 }
 238
 239 static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state)
 240 {
 241         u8 val;
 242         int ret;
 243         enum lgdt3305_tp_clock_edge edge = state->cfg->tpclk_edge;
 244         enum lgdt3305_tp_clock_mode mode = state->cfg->tpclk_mode;
 245         enum lgdt3305_tp_valid_polarity valid = state->cfg->tpvalid_polarity;
 246
 247         lg_dbg("edge = %d, valid = %d\n", edge, valid);
 248
 249         ret = lgdt3305_read_reg(state, LGDT3305_TP_CTRL_1, &val);
 250         if (lg_fail(ret))
 251                 goto fail;
 252
 253         val &= ~0x09;
 254
 255         if (edge)
 256                 val |= 0x08;
 257         if (mode)
 258                 val |= 0x40;
 259         if (valid)
 260                 val |= 0x01;
 261
 262         ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val);
 263         if (lg_fail(ret))
 264                 goto fail;
 265
 266         ret = lgdt3305_soft_reset(state);
 267 fail:
 268         return ret;
 269 }
 270
 271 static int lgdt3305_set_modulation(struct lgdt3305_state *state,
 272                                    struct dtv_frontend_properties *p)
 273 {
 274         u8 opermode;
 275         int ret;
 276
 277         lg_dbg("\n");
 278
 279         ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_1, &opermode);
 280         if (lg_fail(ret))
 281                 goto fail;
 282
 283         opermode &= ~0x03;
 284
 285         switch (p->modulation) {
 286         case VSB_8:
 287                 opermode |= 0x03;
 288                 break;
 289         case QAM_64:
 290                 opermode |= 0x00;
 291                 break;
 292         case QAM_256:
 293                 opermode |= 0x01;
 294                 break;
 295         default:
 296                 return -EINVAL;
 297         }
 298         ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode);
 299 fail:
 300         return ret;
 301 }
 302
 303 static int lgdt3305_set_filter_extension(struct lgdt3305_state *state,
 304                                          struct dtv_frontend_properties *p)
 305 {
 306         int val;
 307
 308         switch (p->modulation) {
 309         case VSB_8:
 310                 val = 0;
 311                 break;
 312         case QAM_64:
 313         case QAM_256:
 314                 val = 1;
 315                 break;
 316         default:
 317                 return -EINVAL;
 318         }
 319         lg_dbg("val = %d\n", val);
 320
 321         return lgdt3305_set_reg_bit(state, 0x043f, 2, val);
 322 }
 323
 324 /* ------------------------------------------------------------------------ */
 325
 326 static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state,
 327                                          struct dtv_frontend_properties *p)
 328 {
 329         u16 agc_ref;
 330
 331         switch (p->modulation) {
 332         case VSB_8:
 333                 agc_ref = 0x32c4;
 334                 break;
 335         case QAM_64:
 336                 agc_ref = 0x2a00;
 337                 break;
 338         case QAM_256:
 339                 agc_ref = 0x2a80;
 340                 break;
 341         default:
 342                 return -EINVAL;
 343         }
 344
 345         lg_dbg("agc ref: 0x%04x\n", agc_ref);
 346
 347         lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8);
 348         lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff);
 349
 350         return 0;
 351 }
 352
 353 static int lgdt3305_rfagc_loop(struct lgdt3305_state *state,
 354                                struct dtv_frontend_properties *p)
 355 {
 356         u16 ifbw, rfbw, agcdelay;
 357
 358         switch (p->modulation) {
 359         case VSB_8:
 360                 agcdelay = 0x04c0;
 361                 rfbw     = 0x8000;
 362                 ifbw     = 0x8000;
 363                 break;
 364         case QAM_64:
 365         case QAM_256:
 366                 agcdelay = 0x046b;
 367                 rfbw     = 0x8889;
 368                 /* FIXME: investigate optimal ifbw & rfbw values for the
 369                  *        DT3304 and re-write this switch..case block */
 370                 if (state->cfg->demod_chip == LGDT3304)
 371                         ifbw = 0x6666;
 372                 else /* (state->cfg->demod_chip == LGDT3305) */
 373                         ifbw = 0x8888;
 374                 break;
 375         default:
 376                 return -EINVAL;
 377         }
 378
 379         if (state->cfg->rf_agc_loop) {
 380                 lg_dbg("agcdelay: 0x%04x, rfbw: 0x%04x\n", agcdelay, rfbw);
 381
 382                 /* rf agc loop filter bandwidth */
 383                 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1,
 384                                    agcdelay >> 8);
 385                 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2,
 386                                    agcdelay & 0xff);
 387
 388                 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1,
 389                                    rfbw >> 8);
 390                 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2,
 391                                    rfbw & 0xff);
 392         } else {
 393                 lg_dbg("ifbw: 0x%04x\n", ifbw);
 394
 395                 /* if agc loop filter bandwidth */
 396                 lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8);
 397                 lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff);
 398         }
 399
 400         return 0;
 401 }
 402
 403 static int lgdt3305_agc_setup(struct lgdt3305_state *state,
 404                               struct dtv_frontend_properties *p)
 405 {
 406         int lockdten, acqen;
 407
 408         switch (p->modulation) {
 409         case VSB_8:
 410                 lockdten = 0;
 411                 acqen = 0;
 412                 break;
 413         case QAM_64:
 414         case QAM_256:
 415                 lockdten = 1;
 416                 acqen = 1;
 417                 break;
 418         default:
 419                 return -EINVAL;
 420         }
 421
 422         lg_dbg("lockdten = %d, acqen = %d\n", lockdten, acqen);
 423
 424         /* control agc function */
 425         switch (state->cfg->demod_chip) {
 426         case LGDT3304:
 427                 lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1);
 428                 lgdt3305_set_reg_bit(state, 0x030e, 2, acqen);
 429                 break;
 430         case LGDT3305:
 431                 lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1);
 432                 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 2, acqen);
 433                 break;
 434         default:
 435                 return -EINVAL;
 436         }
 437
 438         return lgdt3305_rfagc_loop(state, p);
 439 }
 440
 441 static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state,
 442                                       struct dtv_frontend_properties *p)
 443 {
 444         u16 usref = 0;
 445
 446         switch (p->modulation) {
 447         case VSB_8:
 448                 if (state->cfg->usref_8vsb)
 449                         usref = state->cfg->usref_8vsb;
 450                 break;
 451         case QAM_64:
 452                 if (state->cfg->usref_qam64)
 453                         usref = state->cfg->usref_qam64;
 454                 break;
 455         case QAM_256:
 456                 if (state->cfg->usref_qam256)
 457                         usref = state->cfg->usref_qam256;
 458                 break;
 459         default:
 460                 return -EINVAL;
 461         }
 462
 463         if (usref) {
 464                 lg_dbg("set manual mode: 0x%04x\n", usref);
 465
 466                 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 3, 1);
 467
 468                 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1,
 469                                    0xff & (usref >> 8));
 470                 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2,
 471                                    0xff & (usref >> 0));
 472         }
 473         return 0;
 474 }
 475
 476 /* ------------------------------------------------------------------------ */
 477
 478 static int lgdt3305_spectral_inversion(struct lgdt3305_state *state,
 479                                        struct dtv_frontend_properties *p,
 480                                        int inversion)
 481 {
 482         int ret;
 483
 484         lg_dbg("(%d)\n", inversion);
 485
 486         switch (p->modulation) {
 487         case VSB_8:
 488                 ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7,
 489                                          inversion ? 0xf9 : 0x79);
 490                 break;
 491         case QAM_64:
 492         case QAM_256:
 493                 ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL,
 494                                          inversion ? 0xfd : 0xff);
 495                 break;
 496         default:
 497                 ret = -EINVAL;
 498         }
 499         return ret;
 500 }
 501
 502 static int lgdt3305_set_if(struct lgdt3305_state *state,
 503                            struct dtv_frontend_properties *p)
 504 {
 505         u16 if_freq_khz;
 506         u8 nco1, nco2, nco3, nco4;
 507         u64 nco;
 508
 509         switch (p->modulation) {
 510         case VSB_8:
 511                 if_freq_khz = state->cfg->vsb_if_khz;
 512                 break;
 513         case QAM_64:
 514         case QAM_256:
 515                 if_freq_khz = state->cfg->qam_if_khz;
 516                 break;
 517         default:
 518                 return -EINVAL;
 519         }
 520
 521         nco = if_freq_khz / 10;
 522
 523         switch (p->modulation) {
 524         case VSB_8:
 525                 nco <<= 24;
 526                 do_div(nco, 625);
 527                 break;
 528         case QAM_64:
 529         case QAM_256:
 530                 nco <<= 28;
 531                 do_div(nco, 625);
 532                 break;
 533         default:
 534                 return -EINVAL;
 535         }
 536
 537         nco1 = (nco >> 24) & 0x3f;
 538         nco1 |= 0x40;
 539         nco2 = (nco >> 16) & 0xff;
 540         nco3 = (nco >> 8) & 0xff;
 541         nco4 = nco & 0xff;
 542
 543         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1);
 544         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2);
 545         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3);
 546         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4);
 547
 548         lg_dbg("%d KHz -> [%02x%02x%02x%02x]\n",
 549                if_freq_khz, nco1, nco2, nco3, nco4);
 550
 551         return 0;
 552 }
 553
 554 /* ------------------------------------------------------------------------ */
 555
 556 static int lgdt3305_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 557 {
 558         struct lgdt3305_state *state = fe->demodulator_priv;
 559
 560         if (state->cfg->deny_i2c_rptr)
 561                 return 0;
 562
 563         lg_dbg("(%d)\n", enable);
 564
 565         return lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_2, 5,
 566                                     enable ? 0 : 1);
 567 }
 568
 569 static int lgdt3305_sleep(struct dvb_frontend *fe)
 570 {
 571         struct lgdt3305_state *state = fe->demodulator_priv;
 572         u8 gen_ctrl_3, gen_ctrl_4;
 573
 574         lg_dbg("\n");
 575
 576         gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3);
 577         gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4);
 578
 579         /* hold in software reset while sleeping */
 580         gen_ctrl_3 &= ~0x01;
 581         /* tristate the IF-AGC pin */
 582         gen_ctrl_3 |=  0x02;
 583         /* tristate the RF-AGC pin */
 584         gen_ctrl_3 |=  0x04;
 585
 586         /* disable vsb/qam module */
 587         gen_ctrl_4 &= ~0x01;
 588         /* disable adc module */
 589         gen_ctrl_4 &= ~0x02;
 590
 591         lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3);
 592         lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4);
 593
 594         return 0;
 595 }
 596
 597 static int lgdt3305_init(struct dvb_frontend *fe)
 598 {
 599         struct lgdt3305_state *state = fe->demodulator_priv;
 600         int ret;
 601
 602         static struct lgdt3305_reg lgdt3304_init_data[] = {
 603                 { .reg = LGDT3305_GEN_CTRL_1,           .val = 0x03, },
 604                 { .reg = 0x000d,                        .val = 0x02, },
 605                 { .reg = 0x000e,                        .val = 0x02, },
 606                 { .reg = LGDT3305_DGTL_AGC_REF_1,       .val = 0x32, },
 607                 { .reg = LGDT3305_DGTL_AGC_REF_2,       .val = 0xc4, },
 608                 { .reg = LGDT3305_CR_CTR_FREQ_1,        .val = 0x00, },
 609                 { .reg = LGDT3305_CR_CTR_FREQ_2,        .val = 0x00, },
 610                 { .reg = LGDT3305_CR_CTR_FREQ_3,        .val = 0x00, },
 611                 { .reg = LGDT3305_CR_CTR_FREQ_4,        .val = 0x00, },
 612                 { .reg = LGDT3305_CR_CTRL_7,            .val = 0xf9, },
 613                 { .reg = 0x0112,                        .val = 0x17, },
 614                 { .reg = 0x0113,                        .val = 0x15, },
 615                 { .reg = 0x0114,                        .val = 0x18, },
 616                 { .reg = 0x0115,                        .val = 0xff, },
 617                 { .reg = 0x0116,                        .val = 0x3c, },
 618                 { .reg = 0x0214,                        .val = 0x67, },
 619                 { .reg = 0x0424,                        .val = 0x8d, },
 620                 { .reg = 0x0427,                        .val = 0x12, },
 621                 { .reg = 0x0428,                        .val = 0x4f, },
 622                 { .reg = LGDT3305_IFBW_1,               .val = 0x80, },
 623                 { .reg = LGDT3305_IFBW_2,               .val = 0x00, },
 624                 { .reg = 0x030a,                        .val = 0x08, },
 625                 { .reg = 0x030b,                        .val = 0x9b, },
 626                 { .reg = 0x030d,                        .val = 0x00, },
 627                 { .reg = 0x030e,                        .val = 0x1c, },
 628                 { .reg = 0x0314,                        .val = 0xe1, },
 629                 { .reg = 0x000d,                        .val = 0x82, },
 630                 { .reg = LGDT3305_TP_CTRL_1,            .val = 0x5b, },
 631                 { .reg = LGDT3305_TP_CTRL_1,            .val = 0x5b, },
 632         };
 633
 634         static struct lgdt3305_reg lgdt3305_init_data[] = {
 635                 { .reg = LGDT3305_GEN_CTRL_1,           .val = 0x03, },
 636                 { .reg = LGDT3305_GEN_CTRL_2,           .val = 0xb0, },
 637                 { .reg = LGDT3305_GEN_CTRL_3,           .val = 0x01, },
 638                 { .reg = LGDT3305_GEN_CONTROL,          .val = 0x6f, },
 639                 { .reg = LGDT3305_GEN_CTRL_4,           .val = 0x03, },
 640                 { .reg = LGDT3305_DGTL_AGC_REF_1,       .val = 0x32, },
 641                 { .reg = LGDT3305_DGTL_AGC_REF_2,       .val = 0xc4, },
 642                 { .reg = LGDT3305_CR_CTR_FREQ_1,        .val = 0x00, },
 643                 { .reg = LGDT3305_CR_CTR_FREQ_2,        .val = 0x00, },
 644                 { .reg = LGDT3305_CR_CTR_FREQ_3,        .val = 0x00, },
 645                 { .reg = LGDT3305_CR_CTR_FREQ_4,        .val = 0x00, },
 646                 { .reg = LGDT3305_CR_CTRL_7,            .val = 0x79, },
 647                 { .reg = LGDT3305_AGC_POWER_REF_1,      .val = 0x32, },
 648                 { .reg = LGDT3305_AGC_POWER_REF_2,      .val = 0xc4, },
 649                 { .reg = LGDT3305_AGC_DELAY_PT_1,       .val = 0x0d, },
 650                 { .reg = LGDT3305_AGC_DELAY_PT_2,       .val = 0x30, },
 651                 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1, .val = 0x80, },
 652                 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2, .val = 0x00, },
 653                 { .reg = LGDT3305_IFBW_1,               .val = 0x80, },
 654                 { .reg = LGDT3305_IFBW_2,               .val = 0x00, },
 655                 { .reg = LGDT3305_AGC_CTRL_1,           .val = 0x30, },
 656                 { .reg = LGDT3305_AGC_CTRL_4,           .val = 0x61, },
 657                 { .reg = LGDT3305_FEC_BLOCK_CTRL,       .val = 0xff, },
 658                 { .reg = LGDT3305_TP_CTRL_1,            .val = 0x1b, },
 659         };
 660
 661         lg_dbg("\n");
 662
 663         switch (state->cfg->demod_chip) {
 664         case LGDT3304:
 665                 ret = lgdt3305_write_regs(state, lgdt3304_init_data,
 666                                           ARRAY_SIZE(lgdt3304_init_data));
 667                 break;
 668         case LGDT3305:
 669                 ret = lgdt3305_write_regs(state, lgdt3305_init_data,
 670                                           ARRAY_SIZE(lgdt3305_init_data));
 671                 break;
 672         default:
 673                 ret = -EINVAL;
 674         }
 675         if (lg_fail(ret))
 676                 goto fail;
 677
 678         ret = lgdt3305_soft_reset(state);
 679 fail:
 680         return ret;
 681 }
 682
 683 static int lgdt3304_set_parameters(struct dvb_frontend *fe)
 684 {
 685         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 686         struct lgdt3305_state *state = fe->demodulator_priv;
 687         int ret;
 688
 689         lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
 690
 691         if (fe->ops.tuner_ops.set_params) {
 692                 ret = fe->ops.tuner_ops.set_params(fe);
 693                 if (fe->ops.i2c_gate_ctrl)
 694                         fe->ops.i2c_gate_ctrl(fe, 0);
 695                 if (lg_fail(ret))
 696                         goto fail;
 697                 state->current_frequency = p->frequency;
 698         }
 699
 700         ret = lgdt3305_set_modulation(state, p);
 701         if (lg_fail(ret))
 702                 goto fail;
 703
 704         ret = lgdt3305_passband_digital_agc(state, p);
 705         if (lg_fail(ret))
 706                 goto fail;
 707
 708         ret = lgdt3305_agc_setup(state, p);
 709         if (lg_fail(ret))
 710                 goto fail;
 711
 712         /* reg 0x030d is 3304-only... seen in vsb and qam usbsnoops... */
 713         switch (p->modulation) {
 714         case VSB_8:
 715                 lgdt3305_write_reg(state, 0x030d, 0x00);
 716                 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f);
 717                 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c);
 718                 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac);
 719                 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba);
 720                 break;
 721         case QAM_64:
 722         case QAM_256:
 723                 lgdt3305_write_reg(state, 0x030d, 0x14);
 724                 ret = lgdt3305_set_if(state, p);
 725                 if (lg_fail(ret))
 726                         goto fail;
 727                 break;
 728         default:
 729                 return -EINVAL;
 730         }
 731
 732
 733         ret = lgdt3305_spectral_inversion(state, p,
 734                                           state->cfg->spectral_inversion
 735                                           ? 1 : 0);
 736         if (lg_fail(ret))
 737                 goto fail;
 738
 739         state->current_modulation = p->modulation;
 740
 741         ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
 742         if (lg_fail(ret))
 743                 goto fail;
 744
 745         /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
 746         ret = lgdt3305_mpeg_mode_polarity(state);
 747 fail:
 748         return ret;
 749 }
 750
 751 static int lgdt3305_set_parameters(struct dvb_frontend *fe)
 752 {
 753         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 754         struct lgdt3305_state *state = fe->demodulator_priv;
 755         int ret;
 756
 757         lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
 758
 759         if (fe->ops.tuner_ops.set_params) {
 760                 ret = fe->ops.tuner_ops.set_params(fe);
 761                 if (fe->ops.i2c_gate_ctrl)
 762                         fe->ops.i2c_gate_ctrl(fe, 0);
 763                 if (lg_fail(ret))
 764                         goto fail;
 765                 state->current_frequency = p->frequency;
 766         }
 767
 768         ret = lgdt3305_set_modulation(state, p);
 769         if (lg_fail(ret))
 770                 goto fail;
 771
 772         ret = lgdt3305_passband_digital_agc(state, p);
 773         if (lg_fail(ret))
 774                 goto fail;
 775         ret = lgdt3305_set_agc_power_ref(state, p);
 776         if (lg_fail(ret))
 777                 goto fail;
 778         ret = lgdt3305_agc_setup(state, p);
 779         if (lg_fail(ret))
 780                 goto fail;
 781
 782         /* low if */
 783         ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f);
 784         if (lg_fail(ret))
 785                 goto fail;
 786         ret = lgdt3305_set_reg_bit(state, LGDT3305_CR_CTR_FREQ_1, 6, 1);
 787         if (lg_fail(ret))
 788                 goto fail;
 789
 790         ret = lgdt3305_set_if(state, p);
 791         if (lg_fail(ret))
 792                 goto fail;
 793         ret = lgdt3305_spectral_inversion(state, p,
 794                                           state->cfg->spectral_inversion
 795                                           ? 1 : 0);
 796         if (lg_fail(ret))
 797                 goto fail;
 798
 799         ret = lgdt3305_set_filter_extension(state, p);
 800         if (lg_fail(ret))
 801                 goto fail;
 802
 803         state->current_modulation = p->modulation;
 804
 805         ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
 806         if (lg_fail(ret))
 807                 goto fail;
 808
 809         /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
 810         ret = lgdt3305_mpeg_mode_polarity(state);
 811 fail:
 812         return ret;
 813 }
 814
 815 static int lgdt3305_get_frontend(struct dvb_frontend *fe)
 816 {
 817         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 818         struct lgdt3305_state *state = fe->demodulator_priv;
 819
 820         lg_dbg("\n");
 821
 822         p->modulation = state->current_modulation;
 823         p->frequency = state->current_frequency;
 824         return 0;
 825 }
 826
 827 /* ------------------------------------------------------------------------ */
 828
 829 static int lgdt3305_read_cr_lock_status(struct lgdt3305_state *state,
 830                                         int *locked)
 831 {
 832         u8 val;
 833         int ret;
 834         char *cr_lock_state = "";
 835
 836         *locked = 0;
 837
 838         ret = lgdt3305_read_reg(state, LGDT3305_CR_LOCK_STATUS, &val);
 839         if (lg_fail(ret))
 840                 goto fail;
 841
 842         switch (state->current_modulation) {
 843         case QAM_256:
 844         case QAM_64:
 845                 if (val & (1 << 1))
 846                         *locked = 1;
 847
 848                 switch (val & 0x07) {
 849                 case 0:
 850                         cr_lock_state = "QAM UNLOCK";
 851                         break;
 852                 case 4:
 853                         cr_lock_state = "QAM 1stLock";
 854                         break;
 855                 case 6:
 856                         cr_lock_state = "QAM 2ndLock";
 857                         break;
 858                 case 7:
 859                         cr_lock_state = "QAM FinalLock";
 860                         break;
 861                 default:
 862                         cr_lock_state = "CLOCKQAM-INVALID!";
 863                         break;
 864                 }
 865                 break;
 866         case VSB_8:
 867                 if (val & (1 << 7)) {
 868                         *locked = 1;
 869                         cr_lock_state = "CLOCKVSB";
 870                 }
 871                 break;
 872         default:
 873                 ret = -EINVAL;
 874         }
 875         lg_dbg("(%d) %s\n", *locked, cr_lock_state);
 876 fail:
 877         return ret;
 878 }
 879
 880 static int lgdt3305_read_fec_lock_status(struct lgdt3305_state *state,
 881                                          int *locked)
 882 {
 883         u8 val;
 884         int ret, mpeg_lock, fec_lock, viterbi_lock;
 885
 886         *locked = 0;
 887
 888         switch (state->current_modulation) {
 889         case QAM_256:
 890         case QAM_64:
 891                 ret = lgdt3305_read_reg(state,
 892                                         LGDT3305_FEC_LOCK_STATUS, &val);
 893                 if (lg_fail(ret))
 894                         goto fail;
 895
 896                 mpeg_lock    = (val & (1 << 0)) ? 1 : 0;
 897                 fec_lock     = (val & (1 << 2)) ? 1 : 0;
 898                 viterbi_lock = (val & (1 << 3)) ? 1 : 0;
 899
 900                 *locked = mpeg_lock && fec_lock && viterbi_lock;
 901
 902                 lg_dbg("(%d) %s%s%s\n", *locked,
 903                        mpeg_lock    ? "mpeg lock  "  : "",
 904                        fec_lock     ? "fec lock  "   : "",
 905                        viterbi_lock ? "viterbi lock" : "");
 906                 break;
 907         case VSB_8:
 908         default:
 909                 ret = -EINVAL;
 910         }
 911 fail:
 912         return ret;
 913 }
 914
 915 static int lgdt3305_read_status(struct dvb_frontend *fe, fe_status_t *status)
 916 {
 917         struct lgdt3305_state *state = fe->demodulator_priv;
 918         u8 val;
 919         int ret, signal, inlock, nofecerr, snrgood,
 920                 cr_lock, fec_lock, sync_lock;
 921
 922         *status = 0;
 923
 924         ret = lgdt3305_read_reg(state, LGDT3305_GEN_STATUS, &val);
 925         if (lg_fail(ret))
 926                 goto fail;
 927
 928         signal    = (val & (1 << 4)) ? 1 : 0;
 929         inlock    = (val & (1 << 3)) ? 0 : 1;
 930         sync_lock = (val & (1 << 2)) ? 1 : 0;
 931         nofecerr  = (val & (1 << 1)) ? 1 : 0;
 932         snrgood   = (val & (1 << 0)) ? 1 : 0;
 933
 934         lg_dbg("%s%s%s%s%s\n",
 935                signal    ? "SIGNALEXIST " : "",
 936                inlock    ? "INLOCK "      : "",
 937                sync_lock ? "SYNCLOCK "    : "",
 938                nofecerr  ? "NOFECERR "    : "",
 939                snrgood   ? "SNRGOOD "     : "");
 940
 941         ret = lgdt3305_read_cr_lock_status(state, &cr_lock);
 942         if (lg_fail(ret))
 943                 goto fail;
 944
 945         if (signal)
 946                 *status |= FE_HAS_SIGNAL;
 947         if (cr_lock)
 948                 *status |= FE_HAS_CARRIER;
 949         if (nofecerr)
 950                 *status |= FE_HAS_VITERBI;
 951         if (sync_lock)
 952                 *status |= FE_HAS_SYNC;
 953
 954         switch (state->current_modulation) {
 955         case QAM_256:
 956         case QAM_64:
 957                 /* signal bit is unreliable on the DT3304 in QAM mode */
 958                 if (((LGDT3304 == state->cfg->demod_chip)) && (cr_lock))
 959                         *status |= FE_HAS_SIGNAL;
 960
 961                 ret = lgdt3305_read_fec_lock_status(state, &fec_lock);
 962                 if (lg_fail(ret))
 963                         goto fail;
 964
 965                 if (fec_lock)
 966                         *status |= FE_HAS_LOCK;
 967                 break;
 968         case VSB_8:
 969                 if (inlock)
 970                         *status |= FE_HAS_LOCK;
 971                 break;
 972         default:
 973                 ret = -EINVAL;
 974         }
 975 fail:
 976         return ret;
 977 }
 978
 979 /* ------------------------------------------------------------------------ */
 980
 981 /* borrowed from lgdt330x.c */
 982 static u32 calculate_snr(u32 mse, u32 c)
 983 {
 984         if (mse == 0) /* no signal */
 985                 return 0;
 986
 987         mse = intlog10(mse);
 988         if (mse > c) {
 989                 /* Negative SNR, which is possible, but realisticly the
 990                 demod will lose lock before the signal gets this bad.  The
 991                 API only allows for unsigned values, so just return 0 */
 992                 return 0;
 993         }
 994         return 10*(c - mse);
 995 }
 996
 997 static int lgdt3305_read_snr(struct dvb_frontend *fe, u16 *snr)
 998 {
 999         struct lgdt3305_state *state = fe->demodulator_priv;
1000         u32 noise;      /* noise value */
1001         u32 c;          /* per-modulation SNR calculation constant */
1002
1003         switch (state->current_modulation) {
1004         case VSB_8:
1005 #ifdef USE_PTMSE
1006                 /* Use Phase Tracker Mean-Square Error Register */
1007                 /* SNR for ranges from -13.11 to +44.08 */
1008                 noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) |
1009                         (read_reg(state, LGDT3305_PT_MSE_2) << 8) |
1010                         (read_reg(state, LGDT3305_PT_MSE_3) & 0xff);
1011                 c = 73957994; /* log10(25*32^2)*2^24 */
1012 #else
1013                 /* Use Equalizer Mean-Square Error Register */
1014                 /* SNR for ranges from -16.12 to +44.08 */
1015                 noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) |
1016                         (read_reg(state, LGDT3305_EQ_MSE_2) << 8) |
1017                         (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff);
1018                 c = 73957994; /* log10(25*32^2)*2^24 */
1019 #endif
1020                 break;
1021         case QAM_64:
1022         case QAM_256:
1023                 noise = (read_reg(state, LGDT3305_CR_MSE_1) << 8) |
1024                         (read_reg(state, LGDT3305_CR_MSE_2) & 0xff);
1025
1026                 c = (state->current_modulation == QAM_64) ?
1027                         97939837 : 98026066;
1028                 /* log10(688128)*2^24 and log10(696320)*2^24 */
1029                 break;
1030         default:
1031                 return -EINVAL;
1032         }
1033         state->snr = calculate_snr(noise, c);
1034         /* report SNR in dB * 10 */
1035         *snr = (state->snr / ((1 << 24) / 10));
1036         lg_dbg("noise = 0x%08x, snr = %d.%02d dB\n", noise,
1037                state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
1038
1039         return 0;
1040 }
1041
1042 static int lgdt3305_read_signal_strength(struct dvb_frontend *fe,
1043                                          u16 *strength)
1044 {
1045         /* borrowed from lgdt330x.c
1046          *
1047          * Calculate strength from SNR up to 35dB
1048          * Even though the SNR can go higher than 35dB,
1049          * there is some comfort factor in having a range of
1050          * strong signals that can show at 100%
1051          */
1052         struct lgdt3305_state *state = fe->demodulator_priv;
1053         u16 snr;
1054         int ret;
1055
1056         *strength = 0;
1057
1058         ret = fe->ops.read_snr(fe, &snr);
1059         if (lg_fail(ret))
1060                 goto fail;
1061         /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
1062         /* scale the range 0 - 35*2^24 into 0 - 65535 */
1063         if (state->snr >= 8960 * 0x10000)
1064                 *strength = 0xffff;
1065         else
1066                 *strength = state->snr / 8960;
1067 fail:
1068         return ret;
1069 }
1070
1071 /* ------------------------------------------------------------------------ */
1072
1073 static int lgdt3305_read_ber(struct dvb_frontend *fe, u32 *ber)
1074 {
1075         *ber = 0;
1076         return 0;
1077 }
1078
1079 static int lgdt3305_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1080 {
1081         struct lgdt3305_state *state = fe->demodulator_priv;
1082
1083         *ucblocks =
1084                 (read_reg(state, LGDT3305_FEC_PKT_ERR_1) << 8) |
1085                 (read_reg(state, LGDT3305_FEC_PKT_ERR_2) & 0xff);
1086
1087         return 0;
1088 }
1089
1090 static int lgdt3305_get_tune_settings(struct dvb_frontend *fe,
1091                                       struct dvb_frontend_tune_settings
1092                                         *fe_tune_settings)
1093 {
1094         fe_tune_settings->min_delay_ms = 500;
1095         lg_dbg("\n");
1096         return 0;
1097 }
1098
1099 static void lgdt3305_release(struct dvb_frontend *fe)
1100 {
1101         struct lgdt3305_state *state = fe->demodulator_priv;
1102         lg_dbg("\n");
1103         kfree(state);
1104 }
1105
1106 static struct dvb_frontend_ops lgdt3304_ops;
1107 static struct dvb_frontend_ops lgdt3305_ops;
1108
1109 struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config,
1110                                      struct i2c_adapter *i2c_adap)
1111 {
1112         struct lgdt3305_state *state = NULL;
1113         int ret;
1114         u8 val;
1115
1116         lg_dbg("(%d-%04x)\n",
1117                i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1118                config ? config->i2c_addr : 0);
1119
1120         state = kzalloc(sizeof(struct lgdt3305_state), GFP_KERNEL);
1121         if (state == NULL)
1122                 goto fail;
1123
1124         state->cfg = config;
1125         state->i2c_adap = i2c_adap;
1126
1127         switch (config->demod_chip) {
1128         case LGDT3304:
1129                 memcpy(&state->frontend.ops, &lgdt3304_ops,
1130                        sizeof(struct dvb_frontend_ops));
1131                 break;
1132         case LGDT3305:
1133                 memcpy(&state->frontend.ops, &lgdt3305_ops,
1134                        sizeof(struct dvb_frontend_ops));
1135                 break;
1136         default:
1137                 goto fail;
1138         }
1139         state->frontend.demodulator_priv = state;
1140
1141         /* verify that we're talking to a lg dt3304/5 */
1142         ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_2, &val);
1143         if ((lg_fail(ret)) | (val == 0))
1144                 goto fail;
1145         ret = lgdt3305_write_reg(state, 0x0808, 0x80);
1146         if (lg_fail(ret))
1147                 goto fail;
1148         ret = lgdt3305_read_reg(state, 0x0808, &val);
1149         if ((lg_fail(ret)) | (val != 0x80))
1150                 goto fail;
1151         ret = lgdt3305_write_reg(state, 0x0808, 0x00);
1152         if (lg_fail(ret))
1153                 goto fail;
1154
1155         state->current_frequency = -1;
1156         state->current_modulation = -1;
1157
1158         return &state->frontend;
1159 fail:
1160         lg_warn("unable to detect %s hardware\n",
1161                 config->demod_chip ? "LGDT3304" : "LGDT3305");
1162         kfree(state);
1163         return NULL;
1164 }
1165 EXPORT_SYMBOL(lgdt3305_attach);
1166
1167 static struct dvb_frontend_ops lgdt3304_ops = {
1168         .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1169         .info = {
1170                 .name = "LG Electronics LGDT3304 VSB/QAM Frontend",
1171                 .frequency_min      = 54000000,
1172                 .frequency_max      = 858000000,
1173                 .frequency_stepsize = 62500,
1174                 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
1175         },
1176         .i2c_gate_ctrl        = lgdt3305_i2c_gate_ctrl,
1177         .init                 = lgdt3305_init,
1178         .sleep                = lgdt3305_sleep,
1179         .set_frontend         = lgdt3304_set_parameters,
1180         .get_frontend         = lgdt3305_get_frontend,
1181         .get_tune_settings    = lgdt3305_get_tune_settings,
1182         .read_status          = lgdt3305_read_status,
1183         .read_ber             = lgdt3305_read_ber,
1184         .read_signal_strength = lgdt3305_read_signal_strength,
1185         .read_snr             = lgdt3305_read_snr,
1186         .read_ucblocks        = lgdt3305_read_ucblocks,
1187         .release              = lgdt3305_release,
1188 };
1189
1190 static struct dvb_frontend_ops lgdt3305_ops = {
1191         .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1192         .info = {
1193                 .name = "LG Electronics LGDT3305 VSB/QAM Frontend",
1194                 .frequency_min      = 54000000,
1195                 .frequency_max      = 858000000,
1196                 .frequency_stepsize = 62500,
1197                 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
1198         },
1199         .i2c_gate_ctrl        = lgdt3305_i2c_gate_ctrl,
1200         .init                 = lgdt3305_init,
1201         .sleep                = lgdt3305_sleep,
1202         .set_frontend         = lgdt3305_set_parameters,
1203         .get_frontend         = lgdt3305_get_frontend,
1204         .get_tune_settings    = lgdt3305_get_tune_settings,
1205         .read_status          = lgdt3305_read_status,
1206         .read_ber             = lgdt3305_read_ber,
1207         .read_signal_strength = lgdt3305_read_signal_strength,
1208         .read_snr             = lgdt3305_read_snr,
1209         .read_ucblocks        = lgdt3305_read_ucblocks,
1210         .release              = lgdt3305_release,
1211 };
1212
1213 MODULE_DESCRIPTION("LG Electronics LGDT3304/5 ATSC/QAM-B Demodulator Driver");
1214 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
1215 MODULE_LICENSE("GPL");
1216 MODULE_VERSION("0.2");