kernel/drivers/media/dvb-frontends/drx39xyj/drxj.c

   1 /*
   2   Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
   3   All rights reserved.
   4
   5   Redistribution and use in source and binary forms, with or without
   6   modification, are permitted provided that the following conditions are met:
   7
   8   * Redistributions of source code must retain the above copyright notice,
   9     this list of conditions and the following disclaimer.
  10   * Redistributions in binary form must reproduce the above copyright notice,
  11     this list of conditions and the following disclaimer in the documentation
  12         and/or other materials provided with the distribution.
  13   * Neither the name of Trident Microsystems nor Hauppauge Computer Works
  14     nor the names of its contributors may be used to endorse or promote
  15         products derived from this software without specific prior written
  16         permission.
  17
  18   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  19   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  22   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  28   POSSIBILITY OF SUCH DAMAGE.
  29
  30   DRXJ specific implementation of DRX driver
  31   authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen
  32
  33   The Linux DVB Driver for Micronas DRX39xx family (drx3933j) was
  34   written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
  35
  36   This program is free software; you can redistribute it and/or modify
  37   it under the terms of the GNU General Public License as published by
  38   the Free Software Foundation; either version 2 of the License, or
  39   (at your option) any later version.
  40
  41   This program is distributed in the hope that it will be useful,
  42   but WITHOUT ANY WARRANTY; without even the implied warranty of
  43   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  44
  45   GNU General Public License for more details.
  46
  47   You should have received a copy of the GNU General Public License
  48   along with this program; if not, write to the Free Software
  49   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  50 */
  51
  52 /*-----------------------------------------------------------------------------
  53 INCLUDE FILES
  54 ----------------------------------------------------------------------------*/
  55
  56 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
  57
  58 #include <linux/module.h>
  59 #include <linux/init.h>
  60 #include <linux/string.h>
  61 #include <linux/slab.h>
  62 #include <asm/div64.h>
  63
  64 #include "dvb_frontend.h"
  65 #include "drx39xxj.h"
  66
  67 #include "drxj.h"
  68 #include "drxj_map.h"
  69
  70 /*============================================================================*/
  71 /*=== DEFINES ================================================================*/
  72 /*============================================================================*/
  73
  74 #define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw"
  75
  76 /**
  77 * \brief Maximum u32 value.
  78 */
  79 #ifndef MAX_U32
  80 #define MAX_U32  ((u32) (0xFFFFFFFFL))
  81 #endif
  82
  83 /* Customer configurable hardware settings, etc */
  84 #ifndef MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
  85 #define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
  86 #endif
  87
  88 #ifndef MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
  89 #define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
  90 #endif
  91
  92 #ifndef MPEG_OUTPUT_CLK_DRIVE_STRENGTH
  93 #define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x06
  94 #endif
  95
  96 #ifndef OOB_CRX_DRIVE_STRENGTH
  97 #define OOB_CRX_DRIVE_STRENGTH 0x02
  98 #endif
  99
 100 #ifndef OOB_DRX_DRIVE_STRENGTH
 101 #define OOB_DRX_DRIVE_STRENGTH 0x02
 102 #endif
 103 /**** START DJCOMBO patches to DRXJ registermap constants *********************/
 104 /**** registermap 200706071303 from drxj **************************************/
 105 #define   ATV_TOP_CR_AMP_TH_FM                                              0x0
 106 #define   ATV_TOP_CR_AMP_TH_L                                               0xA
 107 #define   ATV_TOP_CR_AMP_TH_LP                                              0xA
 108 #define   ATV_TOP_CR_AMP_TH_BG                                              0x8
 109 #define   ATV_TOP_CR_AMP_TH_DK                                              0x8
 110 #define   ATV_TOP_CR_AMP_TH_I                                               0x8
 111 #define     ATV_TOP_CR_CONT_CR_D_MN                                         0x18
 112 #define     ATV_TOP_CR_CONT_CR_D_FM                                         0x0
 113 #define     ATV_TOP_CR_CONT_CR_D_L                                          0x20
 114 #define     ATV_TOP_CR_CONT_CR_D_LP                                         0x20
 115 #define     ATV_TOP_CR_CONT_CR_D_BG                                         0x18
 116 #define     ATV_TOP_CR_CONT_CR_D_DK                                         0x18
 117 #define     ATV_TOP_CR_CONT_CR_D_I                                          0x18
 118 #define     ATV_TOP_CR_CONT_CR_I_MN                                         0x80
 119 #define     ATV_TOP_CR_CONT_CR_I_FM                                         0x0
 120 #define     ATV_TOP_CR_CONT_CR_I_L                                          0x80
 121 #define     ATV_TOP_CR_CONT_CR_I_LP                                         0x80
 122 #define     ATV_TOP_CR_CONT_CR_I_BG                                         0x80
 123 #define     ATV_TOP_CR_CONT_CR_I_DK                                         0x80
 124 #define     ATV_TOP_CR_CONT_CR_I_I                                          0x80
 125 #define     ATV_TOP_CR_CONT_CR_P_MN                                         0x4
 126 #define     ATV_TOP_CR_CONT_CR_P_FM                                         0x0
 127 #define     ATV_TOP_CR_CONT_CR_P_L                                          0x4
 128 #define     ATV_TOP_CR_CONT_CR_P_LP                                         0x4
 129 #define     ATV_TOP_CR_CONT_CR_P_BG                                         0x4
 130 #define     ATV_TOP_CR_CONT_CR_P_DK                                         0x4
 131 #define     ATV_TOP_CR_CONT_CR_P_I                                          0x4
 132 #define   ATV_TOP_CR_OVM_TH_MN                                              0xA0
 133 #define   ATV_TOP_CR_OVM_TH_FM                                              0x0
 134 #define   ATV_TOP_CR_OVM_TH_L                                               0xA0
 135 #define   ATV_TOP_CR_OVM_TH_LP                                              0xA0
 136 #define   ATV_TOP_CR_OVM_TH_BG                                              0xA0
 137 #define   ATV_TOP_CR_OVM_TH_DK                                              0xA0
 138 #define   ATV_TOP_CR_OVM_TH_I                                               0xA0
 139 #define     ATV_TOP_EQU0_EQU_C0_FM                                          0x0
 140 #define     ATV_TOP_EQU0_EQU_C0_L                                           0x3
 141 #define     ATV_TOP_EQU0_EQU_C0_LP                                          0x3
 142 #define     ATV_TOP_EQU0_EQU_C0_BG                                          0x7
 143 #define     ATV_TOP_EQU0_EQU_C0_DK                                          0x0
 144 #define     ATV_TOP_EQU0_EQU_C0_I                                           0x3
 145 #define     ATV_TOP_EQU1_EQU_C1_FM                                          0x0
 146 #define     ATV_TOP_EQU1_EQU_C1_L                                           0x1F6
 147 #define     ATV_TOP_EQU1_EQU_C1_LP                                          0x1F6
 148 #define     ATV_TOP_EQU1_EQU_C1_BG                                          0x197
 149 #define     ATV_TOP_EQU1_EQU_C1_DK                                          0x198
 150 #define     ATV_TOP_EQU1_EQU_C1_I                                           0x1F6
 151 #define     ATV_TOP_EQU2_EQU_C2_FM                                          0x0
 152 #define     ATV_TOP_EQU2_EQU_C2_L                                           0x28
 153 #define     ATV_TOP_EQU2_EQU_C2_LP                                          0x28
 154 #define     ATV_TOP_EQU2_EQU_C2_BG                                          0xC5
 155 #define     ATV_TOP_EQU2_EQU_C2_DK                                          0xB0
 156 #define     ATV_TOP_EQU2_EQU_C2_I                                           0x28
 157 #define     ATV_TOP_EQU3_EQU_C3_FM                                          0x0
 158 #define     ATV_TOP_EQU3_EQU_C3_L                                           0x192
 159 #define     ATV_TOP_EQU3_EQU_C3_LP                                          0x192
 160 #define     ATV_TOP_EQU3_EQU_C3_BG                                          0x12E
 161 #define     ATV_TOP_EQU3_EQU_C3_DK                                          0x18E
 162 #define     ATV_TOP_EQU3_EQU_C3_I                                           0x192
 163 #define     ATV_TOP_STD_MODE_MN                                             0x0
 164 #define     ATV_TOP_STD_MODE_FM                                             0x1
 165 #define     ATV_TOP_STD_MODE_L                                              0x0
 166 #define     ATV_TOP_STD_MODE_LP                                             0x0
 167 #define     ATV_TOP_STD_MODE_BG                                             0x0
 168 #define     ATV_TOP_STD_MODE_DK                                             0x0
 169 #define     ATV_TOP_STD_MODE_I                                              0x0
 170 #define     ATV_TOP_STD_VID_POL_MN                                          0x0
 171 #define     ATV_TOP_STD_VID_POL_FM                                          0x0
 172 #define     ATV_TOP_STD_VID_POL_L                                           0x2
 173 #define     ATV_TOP_STD_VID_POL_LP                                          0x2
 174 #define     ATV_TOP_STD_VID_POL_BG                                          0x0
 175 #define     ATV_TOP_STD_VID_POL_DK                                          0x0
 176 #define     ATV_TOP_STD_VID_POL_I                                           0x0
 177 #define   ATV_TOP_VID_AMP_MN                                                0x380
 178 #define   ATV_TOP_VID_AMP_FM                                                0x0
 179 #define   ATV_TOP_VID_AMP_L                                                 0xF50
 180 #define   ATV_TOP_VID_AMP_LP                                                0xF50
 181 #define   ATV_TOP_VID_AMP_BG                                                0x380
 182 #define   ATV_TOP_VID_AMP_DK                                                0x394
 183 #define   ATV_TOP_VID_AMP_I                                                 0x3D8
 184 #define   IQM_CF_OUT_ENA_OFDM__M                                            0x4
 185 #define     IQM_FS_ADJ_SEL_B_QAM                                            0x1
 186 #define     IQM_FS_ADJ_SEL_B_OFF                                            0x0
 187 #define     IQM_FS_ADJ_SEL_B_VSB                                            0x2
 188 #define     IQM_RC_ADJ_SEL_B_OFF                                            0x0
 189 #define     IQM_RC_ADJ_SEL_B_QAM                                            0x1
 190 #define     IQM_RC_ADJ_SEL_B_VSB                                            0x2
 191 /**** END DJCOMBO patches to DRXJ registermap *********************************/
 192
 193 #include "drx_driver_version.h"
 194
 195 /* #define DRX_DEBUG */
 196 #ifdef DRX_DEBUG
 197 #include <stdio.h>
 198 #endif
 199
 200 /*-----------------------------------------------------------------------------
 201 ENUMS
 202 ----------------------------------------------------------------------------*/
 203
 204 /*-----------------------------------------------------------------------------
 205 DEFINES
 206 ----------------------------------------------------------------------------*/
 207 #ifndef DRXJ_WAKE_UP_KEY
 208 #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr)
 209 #endif
 210
 211 /**
 212 * \def DRXJ_DEF_I2C_ADDR
 213 * \brief Default I2C addres of a demodulator instance.
 214 */
 215 #define DRXJ_DEF_I2C_ADDR (0x52)
 216
 217 /**
 218 * \def DRXJ_DEF_DEMOD_DEV_ID
 219 * \brief Default device identifier of a demodultor instance.
 220 */
 221 #define DRXJ_DEF_DEMOD_DEV_ID      (1)
 222
 223 /**
 224 * \def DRXJ_SCAN_TIMEOUT
 225 * \brief Timeout value for waiting on demod lock during channel scan (millisec).
 226 */
 227 #define DRXJ_SCAN_TIMEOUT    1000
 228
 229 /**
 230 * \def HI_I2C_DELAY
 231 * \brief HI timing delay for I2C timing (in nano seconds)
 232 *
 233 *  Used to compute HI_CFG_DIV
 234 */
 235 #define HI_I2C_DELAY    42
 236
 237 /**
 238 * \def HI_I2C_BRIDGE_DELAY
 239 * \brief HI timing delay for I2C timing (in nano seconds)
 240 *
 241 *  Used to compute HI_CFG_BDL
 242 */
 243 #define HI_I2C_BRIDGE_DELAY   750
 244
 245 /**
 246 * \brief Time Window for MER and SER Measurement in Units of Segment duration.
 247 */
 248 #define VSB_TOP_MEASUREMENT_PERIOD  64
 249 #define SYMBOLS_PER_SEGMENT         832
 250
 251 /**
 252 * \brief bit rate and segment rate constants used for SER and BER.
 253 */
 254 /* values taken from the QAM microcode */
 255 #define DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN 0
 256 #define DRXJ_QAM_SL_SIG_POWER_QPSK        32768
 257 #define DRXJ_QAM_SL_SIG_POWER_QAM8        24576
 258 #define DRXJ_QAM_SL_SIG_POWER_QAM16       40960
 259 #define DRXJ_QAM_SL_SIG_POWER_QAM32       20480
 260 #define DRXJ_QAM_SL_SIG_POWER_QAM64       43008
 261 #define DRXJ_QAM_SL_SIG_POWER_QAM128      20992
 262 #define DRXJ_QAM_SL_SIG_POWER_QAM256      43520
 263 /**
 264 * \brief Min supported symbolrates.
 265 */
 266 #ifndef DRXJ_QAM_SYMBOLRATE_MIN
 267 #define DRXJ_QAM_SYMBOLRATE_MIN          (520000)
 268 #endif
 269
 270 /**
 271 * \brief Max supported symbolrates.
 272 */
 273 #ifndef DRXJ_QAM_SYMBOLRATE_MAX
 274 #define DRXJ_QAM_SYMBOLRATE_MAX         (7233000)
 275 #endif
 276
 277 /**
 278 * \def DRXJ_QAM_MAX_WAITTIME
 279 * \brief Maximal wait time for QAM auto constellation in ms
 280 */
 281 #ifndef DRXJ_QAM_MAX_WAITTIME
 282 #define DRXJ_QAM_MAX_WAITTIME 900
 283 #endif
 284
 285 #ifndef DRXJ_QAM_FEC_LOCK_WAITTIME
 286 #define DRXJ_QAM_FEC_LOCK_WAITTIME 150
 287 #endif
 288
 289 #ifndef DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME
 290 #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200
 291 #endif
 292
 293 /**
 294 * \def SCU status and results
 295 * \brief SCU
 296 */
 297 #define DRX_SCU_READY               0
 298 #define DRXJ_MAX_WAITTIME           100 /* ms */
 299 #define FEC_RS_MEASUREMENT_PERIOD   12894       /* 1 sec */
 300 #define FEC_RS_MEASUREMENT_PRESCALE 1   /* n sec */
 301
 302 /**
 303 * \def DRX_AUD_MAX_DEVIATION
 304 * \brief Needed for calculation of prescale feature in AUD
 305 */
 306 #ifndef DRXJ_AUD_MAX_FM_DEVIATION
 307 #define DRXJ_AUD_MAX_FM_DEVIATION  100  /* kHz */
 308 #endif
 309
 310 /**
 311 * \brief Needed for calculation of NICAM prescale feature in AUD
 312 */
 313 #ifndef DRXJ_AUD_MAX_NICAM_PRESCALE
 314 #define DRXJ_AUD_MAX_NICAM_PRESCALE  (9)        /* dB */
 315 #endif
 316
 317 /**
 318 * \brief Needed for calculation of NICAM prescale feature in AUD
 319 */
 320 #ifndef DRXJ_AUD_MAX_WAITTIME
 321 #define DRXJ_AUD_MAX_WAITTIME  250      /* ms */
 322 #endif
 323
 324 /* ATV config changed flags */
 325 #define DRXJ_ATV_CHANGED_COEF          (0x00000001UL)
 326 #define DRXJ_ATV_CHANGED_PEAK_FLT      (0x00000008UL)
 327 #define DRXJ_ATV_CHANGED_NOISE_FLT     (0x00000010UL)
 328 #define DRXJ_ATV_CHANGED_OUTPUT        (0x00000020UL)
 329 #define DRXJ_ATV_CHANGED_SIF_ATT       (0x00000040UL)
 330
 331 /* UIO define */
 332 #define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0
 333 #define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1
 334
 335 /*
 336  * MICROCODE RELATED DEFINES
 337  */
 338
 339 /* Magic word for checking correct Endianess of microcode data */
 340 #define DRX_UCODE_MAGIC_WORD         ((((u16)'H')<<8)+((u16)'L'))
 341
 342 /* CRC flag in ucode header, flags field. */
 343 #define DRX_UCODE_CRC_FLAG           (0x0001)
 344
 345 /*
 346  * Maximum size of buffer used to verify the microcode.
 347  * Must be an even number
 348  */
 349 #define DRX_UCODE_MAX_BUF_SIZE       (DRXDAP_MAX_RCHUNKSIZE)
 350
 351 #if DRX_UCODE_MAX_BUF_SIZE & 1
 352 #error DRX_UCODE_MAX_BUF_SIZE must be an even number
 353 #endif
 354
 355 /*
 356  * Power mode macros
 357  */
 358
 359 #define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \
 360                                        (mode == DRX_POWER_MODE_10) || \
 361                                        (mode == DRX_POWER_MODE_11) || \
 362                                        (mode == DRX_POWER_MODE_12) || \
 363                                        (mode == DRX_POWER_MODE_13) || \
 364                                        (mode == DRX_POWER_MODE_14) || \
 365                                        (mode == DRX_POWER_MODE_15) || \
 366                                        (mode == DRX_POWER_MODE_16) || \
 367                                        (mode == DRX_POWER_DOWN))
 368
 369 /* Pin safe mode macro */
 370 #define DRXJ_PIN_SAFE_MODE 0x0000
 371 /*============================================================================*/
 372 /*=== GLOBAL VARIABLEs =======================================================*/
 373 /*============================================================================*/
 374 /**
 375 */
 376
 377 /**
 378 * \brief Temporary register definitions.
 379 *        (register definitions that are not yet available in register master)
 380 */
 381
 382 /******************************************************************************/
 383 /* Audio block 0x103 is write only. To avoid shadowing in driver accessing    */
 384 /* RAM adresses directly. This must be READ ONLY to avoid problems.           */
 385 /* Writing to the interface adresses is more than only writing the RAM        */
 386 /* locations                                                                  */
 387 /******************************************************************************/
 388 /**
 389 * \brief RAM location of MODUS registers
 390 */
 391 #define AUD_DEM_RAM_MODUS_HI__A              0x10204A3
 392 #define AUD_DEM_RAM_MODUS_HI__M              0xF000
 393
 394 #define AUD_DEM_RAM_MODUS_LO__A              0x10204A4
 395 #define AUD_DEM_RAM_MODUS_LO__M              0x0FFF
 396
 397 /**
 398 * \brief RAM location of I2S config registers
 399 */
 400 #define AUD_DEM_RAM_I2S_CONFIG1__A           0x10204B1
 401 #define AUD_DEM_RAM_I2S_CONFIG2__A           0x10204B2
 402
 403 /**
 404 * \brief RAM location of DCO config registers
 405 */
 406 #define AUD_DEM_RAM_DCO_B_HI__A              0x1020461
 407 #define AUD_DEM_RAM_DCO_B_LO__A              0x1020462
 408 #define AUD_DEM_RAM_DCO_A_HI__A              0x1020463
 409 #define AUD_DEM_RAM_DCO_A_LO__A              0x1020464
 410
 411 /**
 412 * \brief RAM location of Threshold registers
 413 */
 414 #define AUD_DEM_RAM_NICAM_THRSHLD__A         0x102045A
 415 #define AUD_DEM_RAM_A2_THRSHLD__A            0x10204BB
 416 #define AUD_DEM_RAM_BTSC_THRSHLD__A          0x10204A6
 417
 418 /**
 419 * \brief RAM location of Carrier Threshold registers
 420 */
 421 #define AUD_DEM_RAM_CM_A_THRSHLD__A          0x10204AF
 422 #define AUD_DEM_RAM_CM_B_THRSHLD__A          0x10204B0
 423
 424 /**
 425 * \brief FM Matrix register fix
 426 */
 427 #ifdef AUD_DEM_WR_FM_MATRIX__A
 428 #undef  AUD_DEM_WR_FM_MATRIX__A
 429 #endif
 430 #define AUD_DEM_WR_FM_MATRIX__A              0x105006F
 431
 432 /*============================================================================*/
 433 /**
 434 * \brief Defines required for audio
 435 */
 436 #define AUD_VOLUME_ZERO_DB                      115
 437 #define AUD_VOLUME_DB_MIN                       -60
 438 #define AUD_VOLUME_DB_MAX                       12
 439 #define AUD_CARRIER_STRENGTH_QP_0DB             0x4000
 440 #define AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100   421
 441 #define AUD_MAX_AVC_REF_LEVEL                   15
 442 #define AUD_I2S_FREQUENCY_MAX                   48000UL
 443 #define AUD_I2S_FREQUENCY_MIN                   12000UL
 444 #define AUD_RDS_ARRAY_SIZE                      18
 445
 446 /**
 447 * \brief Needed for calculation of prescale feature in AUD
 448 */
 449 #ifndef DRX_AUD_MAX_FM_DEVIATION
 450 #define DRX_AUD_MAX_FM_DEVIATION  (100) /* kHz */
 451 #endif
 452
 453 /**
 454 * \brief Needed for calculation of NICAM prescale feature in AUD
 455 */
 456 #ifndef DRX_AUD_MAX_NICAM_PRESCALE
 457 #define DRX_AUD_MAX_NICAM_PRESCALE  (9) /* dB */
 458 #endif
 459
 460 /*============================================================================*/
 461 /* Values for I2S Master/Slave pin configurations */
 462 #define SIO_PDR_I2S_CL_CFG_MODE__MASTER      0x0004
 463 #define SIO_PDR_I2S_CL_CFG_DRIVE__MASTER     0x0008
 464 #define SIO_PDR_I2S_CL_CFG_MODE__SLAVE       0x0004
 465 #define SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE      0x0000
 466
 467 #define SIO_PDR_I2S_DA_CFG_MODE__MASTER      0x0003
 468 #define SIO_PDR_I2S_DA_CFG_DRIVE__MASTER     0x0008
 469 #define SIO_PDR_I2S_DA_CFG_MODE__SLAVE       0x0003
 470 #define SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE      0x0008
 471
 472 #define SIO_PDR_I2S_WS_CFG_MODE__MASTER      0x0004
 473 #define SIO_PDR_I2S_WS_CFG_DRIVE__MASTER     0x0008
 474 #define SIO_PDR_I2S_WS_CFG_MODE__SLAVE       0x0004
 475 #define SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE      0x0000
 476
 477 /*============================================================================*/
 478 /*=== REGISTER ACCESS MACROS =================================================*/
 479 /*============================================================================*/
 480
 481 /**
 482 * This macro is used to create byte arrays for block writes.
 483 * Block writes speed up I2C traffic between host and demod.
 484 * The macro takes care of the required byte order in a 16 bits word.
 485 * x -> lowbyte(x), highbyte(x)
 486 */
 487 #define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \
 488                        ((u8)((((u16)x)>>8)&0xFF))
 489 /**
 490 * This macro is used to convert byte array to 16 bit register value for block read.
 491 * Block read speed up I2C traffic between host and demod.
 492 * The macro takes care of the required byte order in a 16 bits word.
 493 */
 494 #define DRXJ_8TO16(x) ((u16) (x[0] | (x[1] << 8)))
 495
 496 /*============================================================================*/
 497 /*=== MISC DEFINES ===========================================================*/
 498 /*============================================================================*/
 499
 500 /*============================================================================*/
 501 /*=== HI COMMAND RELATED DEFINES =============================================*/
 502 /*============================================================================*/
 503
 504 /**
 505 * \brief General maximum number of retries for ucode command interfaces
 506 */
 507 #define DRXJ_MAX_RETRIES (100)
 508
 509 /*============================================================================*/
 510 /*=== STANDARD RELATED MACROS ================================================*/
 511 /*============================================================================*/
 512
 513 #define DRXJ_ISATVSTD(std) ((std == DRX_STANDARD_PAL_SECAM_BG) || \
 514                                (std == DRX_STANDARD_PAL_SECAM_DK) || \
 515                                (std == DRX_STANDARD_PAL_SECAM_I) || \
 516                                (std == DRX_STANDARD_PAL_SECAM_L) || \
 517                                (std == DRX_STANDARD_PAL_SECAM_LP) || \
 518                                (std == DRX_STANDARD_NTSC) || \
 519                                (std == DRX_STANDARD_FM))
 520
 521 #define DRXJ_ISQAMSTD(std) ((std == DRX_STANDARD_ITU_A) || \
 522                                (std == DRX_STANDARD_ITU_B) || \
 523                                (std == DRX_STANDARD_ITU_C) || \
 524                                (std == DRX_STANDARD_ITU_D))
 525
 526 /*-----------------------------------------------------------------------------
 527 GLOBAL VARIABLES
 528 ----------------------------------------------------------------------------*/
 529 /*
 530  * DRXJ DAP structures
 531  */
 532
 533 static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
 534                                       u32 addr,
 535                                       u16 datasize,
 536                                       u8 *data, u32 flags);
 537
 538
 539 static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
 540                                                  u32 waddr,
 541                                                  u32 raddr,
 542                                                  u16 wdata, u16 *rdata);
 543
 544 static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
 545                                       u32 addr,
 546                                       u16 *data, u32 flags);
 547
 548 static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
 549                                       u32 addr,
 550                                       u32 *data, u32 flags);
 551
 552 static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
 553                                        u32 addr,
 554                                        u16 datasize,
 555                                        u8 *data, u32 flags);
 556
 557 static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
 558                                        u32 addr,
 559                                        u16 data, u32 flags);
 560
 561 static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
 562                                        u32 addr,
 563                                        u32 data, u32 flags);
 564
 565 static struct drxj_data drxj_data_g = {
 566         false,                  /* has_lna : true if LNA (aka PGA) present      */
 567         false,                  /* has_oob : true if OOB supported              */
 568         false,                  /* has_ntsc: true if NTSC supported             */
 569         false,                  /* has_btsc: true if BTSC supported             */
 570         false,                  /* has_smatx: true if SMA_TX pin is available   */
 571         false,                  /* has_smarx: true if SMA_RX pin is available   */
 572         false,                  /* has_gpio : true if GPIO pin is available     */
 573         false,                  /* has_irqn : true if IRQN pin is available     */
 574         0,                      /* mfx A1/A2/A... */
 575
 576         /* tuner settings */
 577         false,                  /* tuner mirrors RF signal    */
 578         /* standard/channel settings */
 579         DRX_STANDARD_UNKNOWN,   /* current standard           */
 580         DRX_CONSTELLATION_AUTO, /* constellation              */
 581         0,                      /* frequency in KHz           */
 582         DRX_BANDWIDTH_UNKNOWN,  /* curr_bandwidth              */
 583         DRX_MIRROR_NO,          /* mirror                     */
 584
 585         /* signal quality information: */
 586         /* default values taken from the QAM Programming guide */
 587         /*   fec_bits_desired should not be less than 4000000    */
 588         4000000,                /* fec_bits_desired    */
 589         5,                      /* fec_vd_plen         */
 590         4,                      /* qam_vd_prescale     */
 591         0xFFFF,                 /* qamVDPeriod       */
 592         204 * 8,                /* fec_rs_plen annex A */
 593         1,                      /* fec_rs_prescale     */
 594         FEC_RS_MEASUREMENT_PERIOD,      /* fec_rs_period     */
 595         true,                   /* reset_pkt_err_acc    */
 596         0,                      /* pkt_err_acc_start    */
 597
 598         /* HI configuration */
 599         0,                      /* hi_cfg_timing_div    */
 600         0,                      /* hi_cfg_bridge_delay  */
 601         0,                      /* hi_cfg_wake_up_key    */
 602         0,                      /* hi_cfg_ctrl         */
 603         0,                      /* HICfgTimeout      */
 604         /* UIO configuartion */
 605         DRX_UIO_MODE_DISABLE,   /* uio_sma_rx_mode      */
 606         DRX_UIO_MODE_DISABLE,   /* uio_sma_tx_mode      */
 607         DRX_UIO_MODE_DISABLE,   /* uioASELMode       */
 608         DRX_UIO_MODE_DISABLE,   /* uio_irqn_mode       */
 609         /* FS setting */
 610         0UL,                    /* iqm_fs_rate_ofs      */
 611         false,                  /* pos_image          */
 612         /* RC setting */
 613         0UL,                    /* iqm_rc_rate_ofs      */
 614         /* AUD information */
 615 /*   false,                  * flagSetAUDdone    */
 616 /*   false,                  * detectedRDS       */
 617 /*   true,                   * flagASDRequest    */
 618 /*   false,                  * flagHDevClear     */
 619 /*   false,                  * flagHDevSet       */
 620 /*   (u16) 0xFFF,          * rdsLastCount      */
 621
 622         /* ATV configuartion */
 623         0UL,                    /* flags cfg changes */
 624         /* shadow of ATV_TOP_EQU0__A */
 625         {-5,
 626          ATV_TOP_EQU0_EQU_C0_FM,
 627          ATV_TOP_EQU0_EQU_C0_L,
 628          ATV_TOP_EQU0_EQU_C0_LP,
 629          ATV_TOP_EQU0_EQU_C0_BG,
 630          ATV_TOP_EQU0_EQU_C0_DK,
 631          ATV_TOP_EQU0_EQU_C0_I},
 632         /* shadow of ATV_TOP_EQU1__A */
 633         {-50,
 634          ATV_TOP_EQU1_EQU_C1_FM,
 635          ATV_TOP_EQU1_EQU_C1_L,
 636          ATV_TOP_EQU1_EQU_C1_LP,
 637          ATV_TOP_EQU1_EQU_C1_BG,
 638          ATV_TOP_EQU1_EQU_C1_DK,
 639          ATV_TOP_EQU1_EQU_C1_I},
 640         /* shadow of ATV_TOP_EQU2__A */
 641         {210,
 642          ATV_TOP_EQU2_EQU_C2_FM,
 643          ATV_TOP_EQU2_EQU_C2_L,
 644          ATV_TOP_EQU2_EQU_C2_LP,
 645          ATV_TOP_EQU2_EQU_C2_BG,
 646          ATV_TOP_EQU2_EQU_C2_DK,
 647          ATV_TOP_EQU2_EQU_C2_I},
 648         /* shadow of ATV_TOP_EQU3__A */
 649         {-160,
 650          ATV_TOP_EQU3_EQU_C3_FM,
 651          ATV_TOP_EQU3_EQU_C3_L,
 652          ATV_TOP_EQU3_EQU_C3_LP,
 653          ATV_TOP_EQU3_EQU_C3_BG,
 654          ATV_TOP_EQU3_EQU_C3_DK,
 655          ATV_TOP_EQU3_EQU_C3_I},
 656         false,                  /* flag: true=bypass             */
 657         ATV_TOP_VID_PEAK__PRE,  /* shadow of ATV_TOP_VID_PEAK__A */
 658         ATV_TOP_NOISE_TH__PRE,  /* shadow of ATV_TOP_NOISE_TH__A */
 659         true,                   /* flag CVBS ouput enable        */
 660         false,                  /* flag SIF ouput enable         */
 661         DRXJ_SIF_ATTENUATION_0DB,       /* current SIF att setting       */
 662         {                       /* qam_rf_agc_cfg */
 663          DRX_STANDARD_ITU_B,    /* standard            */
 664          DRX_AGC_CTRL_AUTO,     /* ctrl_mode            */
 665          0,                     /* output_level         */
 666          0,                     /* min_output_level      */
 667          0xFFFF,                /* max_output_level      */
 668          0x0000,                /* speed               */
 669          0x0000,                /* top                 */
 670          0x0000                 /* c.o.c.              */
 671          },
 672         {                       /* qam_if_agc_cfg */
 673          DRX_STANDARD_ITU_B,    /* standard            */
 674          DRX_AGC_CTRL_AUTO,     /* ctrl_mode            */
 675          0,                     /* output_level         */
 676          0,                     /* min_output_level      */
 677          0xFFFF,                /* max_output_level      */
 678          0x0000,                /* speed               */
 679          0x0000,                /* top    (don't care) */
 680          0x0000                 /* c.o.c. (don't care) */
 681          },
 682         {                       /* vsb_rf_agc_cfg */
 683          DRX_STANDARD_8VSB,     /* standard       */
 684          DRX_AGC_CTRL_AUTO,     /* ctrl_mode       */
 685          0,                     /* output_level    */
 686          0,                     /* min_output_level */
 687          0xFFFF,                /* max_output_level */
 688          0x0000,                /* speed          */
 689          0x0000,                /* top    (don't care) */
 690          0x0000                 /* c.o.c. (don't care) */
 691          },
 692         {                       /* vsb_if_agc_cfg */
 693          DRX_STANDARD_8VSB,     /* standard       */
 694          DRX_AGC_CTRL_AUTO,     /* ctrl_mode       */
 695          0,                     /* output_level    */
 696          0,                     /* min_output_level */
 697          0xFFFF,                /* max_output_level */
 698          0x0000,                /* speed          */
 699          0x0000,                /* top    (don't care) */
 700          0x0000                 /* c.o.c. (don't care) */
 701          },
 702         0,                      /* qam_pga_cfg */
 703         0,                      /* vsb_pga_cfg */
 704         {                       /* qam_pre_saw_cfg */
 705          DRX_STANDARD_ITU_B,    /* standard  */
 706          0,                     /* reference */
 707          false                  /* use_pre_saw */
 708          },
 709         {                       /* vsb_pre_saw_cfg */
 710          DRX_STANDARD_8VSB,     /* standard  */
 711          0,                     /* reference */
 712          false                  /* use_pre_saw */
 713          },
 714
 715         /* Version information */
 716 #ifndef _CH_
 717         {
 718          "01234567890",         /* human readable version microcode             */
 719          "01234567890"          /* human readable version device specific code  */
 720          },
 721         {
 722          {                      /* struct drx_version for microcode                   */
 723           DRX_MODULE_UNKNOWN,
 724           (char *)(NULL),
 725           0,
 726           0,
 727           0,
 728           (char *)(NULL)
 729           },
 730          {                      /* struct drx_version for device specific code */
 731           DRX_MODULE_UNKNOWN,
 732           (char *)(NULL),
 733           0,
 734           0,
 735           0,
 736           (char *)(NULL)
 737           }
 738          },
 739         {
 740          {                      /* struct drx_version_list for microcode */
 741           (struct drx_version *) (NULL),
 742           (struct drx_version_list *) (NULL)
 743           },
 744          {                      /* struct drx_version_list for device specific code */
 745           (struct drx_version *) (NULL),
 746           (struct drx_version_list *) (NULL)
 747           }
 748          },
 749 #endif
 750         false,                  /* smart_ant_inverted */
 751         /* Tracking filter setting for OOB  */
 752         {
 753          12000,
 754          9300,
 755          6600,
 756          5280,
 757          3700,
 758          3000,
 759          2000,
 760          0},
 761         false,                  /* oob_power_on           */
 762         0,                      /* mpeg_ts_static_bitrate  */
 763         false,                  /* disable_te_ihandling   */
 764         false,                  /* bit_reverse_mpeg_outout */
 765         DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO,        /* mpeg_output_clock_rate */
 766         DRXJ_MPEG_START_WIDTH_1CLKCYC,  /* mpeg_start_width */
 767
 768         /* Pre SAW & Agc configuration for ATV */
 769         {
 770          DRX_STANDARD_NTSC,     /* standard     */
 771          7,                     /* reference    */
 772          true                   /* use_pre_saw    */
 773          },
 774         {                       /* ATV RF-AGC */
 775          DRX_STANDARD_NTSC,     /* standard              */
 776          DRX_AGC_CTRL_AUTO,     /* ctrl_mode              */
 777          0,                     /* output_level           */
 778          0,                     /* min_output_level (d.c.) */
 779          0,                     /* max_output_level (d.c.) */
 780          3,                     /* speed                 */
 781          9500,                  /* top                   */
 782          4000                   /* cut-off current       */
 783          },
 784         {                       /* ATV IF-AGC */
 785          DRX_STANDARD_NTSC,     /* standard              */
 786          DRX_AGC_CTRL_AUTO,     /* ctrl_mode              */
 787          0,                     /* output_level           */
 788          0,                     /* min_output_level (d.c.) */
 789          0,                     /* max_output_level (d.c.) */
 790          3,                     /* speed                 */
 791          2400,                  /* top                   */
 792          0                      /* c.o.c.         (d.c.) */
 793          },
 794         140,                    /* ATV PGA config */
 795         0,                      /* curr_symbol_rate */
 796
 797         false,                  /* pdr_safe_mode     */
 798         SIO_PDR_GPIO_CFG__PRE,  /* pdr_safe_restore_val_gpio  */
 799         SIO_PDR_VSYNC_CFG__PRE, /* pdr_safe_restore_val_v_sync */
 800         SIO_PDR_SMA_RX_CFG__PRE,        /* pdr_safe_restore_val_sma_rx */
 801         SIO_PDR_SMA_TX_CFG__PRE,        /* pdr_safe_restore_val_sma_tx */
 802
 803         4,                      /* oob_pre_saw            */
 804         DRXJ_OOB_LO_POW_MINUS10DB,      /* oob_lo_pow             */
 805         {
 806          false                  /* aud_data, only first member */
 807          },
 808 };
 809
 810 /**
 811 * \var drxj_default_addr_g
 812 * \brief Default I2C address and device identifier.
 813 */
 814 static struct i2c_device_addr drxj_default_addr_g = {
 815         DRXJ_DEF_I2C_ADDR,      /* i2c address */
 816         DRXJ_DEF_DEMOD_DEV_ID   /* device id */
 817 };
 818
 819 /**
 820 * \var drxj_default_comm_attr_g
 821 * \brief Default common attributes of a drxj demodulator instance.
 822 */
 823 static struct drx_common_attr drxj_default_comm_attr_g = {
 824         NULL,                   /* ucode file           */
 825         true,                   /* ucode verify switch  */
 826         {0},                    /* version record       */
 827
 828         44000,                  /* IF in kHz in case no tuner instance is used  */
 829         (151875 - 0),           /* system clock frequency in kHz                */
 830         0,                      /* oscillator frequency kHz                     */
 831         0,                      /* oscillator deviation in ppm, signed          */
 832         false,                  /* If true mirror frequency spectrum            */
 833         {
 834          /* MPEG output configuration */
 835          true,                  /* If true, enable MPEG ouput    */
 836          false,                 /* If true, insert RS byte       */
 837          false,                 /* If true, parallel out otherwise serial */
 838          false,                 /* If true, invert DATA signals  */
 839          false,                 /* If true, invert ERR signal    */
 840          false,                 /* If true, invert STR signals   */
 841          false,                 /* If true, invert VAL signals   */
 842          false,                 /* If true, invert CLK signals   */
 843          true,                  /* If true, static MPEG clockrate will
 844                                    be used, otherwise clockrate will
 845                                    adapt to the bitrate of the TS */
 846          19392658UL,            /* Maximum bitrate in b/s in case
 847                                    static clockrate is selected */
 848          DRX_MPEG_STR_WIDTH_1   /* MPEG Start width in clock cycles */
 849          },
 850         /* Initilisations below can be ommited, they require no user input and
 851            are initialy 0, NULL or false. The compiler will initialize them to these
 852            values when ommited.  */
 853         false,                  /* is_opened */
 854
 855         /* SCAN */
 856         NULL,                   /* no scan params yet               */
 857         0,                      /* current scan index               */
 858         0,                      /* next scan frequency              */
 859         false,                  /* scan ready flag                  */
 860         0,                      /* max channels to scan             */
 861         0,                      /* nr of channels scanned           */
 862         NULL,                   /* default scan function            */
 863         NULL,                   /* default context pointer          */
 864         0,                      /* millisec to wait for demod lock  */
 865         DRXJ_DEMOD_LOCK,        /* desired lock               */
 866         false,
 867
 868         /* Power management */
 869         DRX_POWER_UP,
 870
 871         /* Tuner */
 872         1,                      /* nr of I2C port to wich tuner is     */
 873         0L,                     /* minimum RF input frequency, in kHz  */
 874         0L,                     /* maximum RF input frequency, in kHz  */
 875         false,                  /* Rf Agc Polarity                     */
 876         false,                  /* If Agc Polarity                     */
 877         false,                  /* tuner slow mode                     */
 878
 879         {                       /* current channel (all 0)             */
 880          0UL                    /* channel.frequency */
 881          },
 882         DRX_STANDARD_UNKNOWN,   /* current standard */
 883         DRX_STANDARD_UNKNOWN,   /* previous standard */
 884         DRX_STANDARD_UNKNOWN,   /* di_cache_standard   */
 885         false,                  /* use_bootloader */
 886         0UL,                    /* capabilities */
 887         0                       /* mfx */
 888 };
 889
 890 /**
 891 * \var drxj_default_demod_g
 892 * \brief Default drxj demodulator instance.
 893 */
 894 static struct drx_demod_instance drxj_default_demod_g = {
 895         &drxj_default_addr_g,   /* i2c address & device id */
 896         &drxj_default_comm_attr_g,      /* demod common attributes */
 897         &drxj_data_g            /* demod device specific attributes */
 898 };
 899
 900 /**
 901 * \brief Default audio data structure for DRK demodulator instance.
 902 *
 903 * This structure is DRXK specific.
 904 *
 905 */
 906 static struct drx_aud_data drxj_default_aud_data_g = {
 907         false,                  /* audio_is_active */
 908         DRX_AUD_STANDARD_AUTO,  /* audio_standard  */
 909
 910         /* i2sdata */
 911         {
 912          false,                 /* output_enable   */
 913          48000,                 /* frequency      */
 914          DRX_I2S_MODE_MASTER,   /* mode           */
 915          DRX_I2S_WORDLENGTH_32, /* word_length     */
 916          DRX_I2S_POLARITY_RIGHT,        /* polarity       */
 917          DRX_I2S_FORMAT_WS_WITH_DATA    /* format         */
 918          },
 919         /* volume            */
 920         {
 921          true,                  /* mute;          */
 922          0,                     /* volume         */
 923          DRX_AUD_AVC_OFF,       /* avc_mode        */
 924          0,                     /* avc_ref_level    */
 925          DRX_AUD_AVC_MAX_GAIN_12DB,     /* avc_max_gain     */
 926          DRX_AUD_AVC_MAX_ATTEN_24DB,    /* avc_max_atten    */
 927          0,                     /* strength_left   */
 928          0                      /* strength_right  */
 929          },
 930         DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, /* auto_sound */
 931         /*  ass_thresholds */
 932         {
 933          440,                   /* A2    */
 934          12,                    /* BTSC  */
 935          700,                   /* NICAM */
 936          },
 937         /* carrier */
 938         {
 939          /* a */
 940          {
 941           42,                   /* thres */
 942           DRX_NO_CARRIER_NOISE, /* opt   */
 943           0,                    /* shift */
 944           0                     /* dco   */
 945           },
 946          /* b */
 947          {
 948           42,                   /* thres */
 949           DRX_NO_CARRIER_MUTE,  /* opt   */
 950           0,                    /* shift */
 951           0                     /* dco   */
 952           },
 953
 954          },
 955         /* mixer */
 956         {
 957          DRX_AUD_SRC_STEREO_OR_A,       /* source_i2s */
 958          DRX_AUD_I2S_MATRIX_STEREO,     /* matrix_i2s */
 959          DRX_AUD_FM_MATRIX_SOUND_A      /* matrix_fm  */
 960          },
 961         DRX_AUD_DEVIATION_NORMAL,       /* deviation */
 962         DRX_AUD_AVSYNC_OFF,     /* av_sync */
 963
 964         /* prescale */
 965         {
 966          DRX_AUD_MAX_FM_DEVIATION,      /* fm_deviation */
 967          DRX_AUD_MAX_NICAM_PRESCALE     /* nicam_gain */
 968          },
 969         DRX_AUD_FM_DEEMPH_75US, /* deemph */
 970         DRX_BTSC_STEREO,        /* btsc_detect */
 971         0,                      /* rds_data_counter */
 972         false                   /* rds_data_present */
 973 };
 974
 975 /*-----------------------------------------------------------------------------
 976 STRUCTURES
 977 ----------------------------------------------------------------------------*/
 978 struct drxjeq_stat {
 979         u16 eq_mse;
 980         u8 eq_mode;
 981         u8 eq_ctrl;
 982         u8 eq_stat;
 983 };
 984
 985 /* HI command */
 986 struct drxj_hi_cmd {
 987         u16 cmd;
 988         u16 param1;
 989         u16 param2;
 990         u16 param3;
 991         u16 param4;
 992         u16 param5;
 993         u16 param6;
 994 };
 995
 996 /*============================================================================*/
 997 /*=== MICROCODE RELATED STRUCTURES ===========================================*/
 998 /*============================================================================*/
 999
1000 /**
1001  * struct drxu_code_block_hdr - Structure of the microcode block headers
1002  *
1003  * @addr:       Destination address of the data in this block
1004  * @size:       Size of the block data following this header counted in
1005  *              16 bits words
1006  * @CRC:        CRC value of the data block, only valid if CRC flag is
1007  *              set.
1008  */
1009 struct drxu_code_block_hdr {
1010         u32 addr;
1011         u16 size;
1012         u16 flags;
1013         u16 CRC;
1014 };
1015
1016 /*-----------------------------------------------------------------------------
1017 FUNCTIONS
1018 ----------------------------------------------------------------------------*/
1019 /* Some prototypes */
1020 static int
1021 hi_command(struct i2c_device_addr *dev_addr,
1022            const struct drxj_hi_cmd *cmd, u16 *result);
1023
1024 static int
1025 ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat);
1026
1027 static int
1028 ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode);
1029
1030 static int power_down_aud(struct drx_demod_instance *demod);
1031
1032 static int
1033 ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw);
1034
1035 static int
1036 ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain);
1037
1038 /*============================================================================*/
1039 /*============================================================================*/
1040 /*==                          HELPER FUNCTIONS                              ==*/
1041 /*============================================================================*/
1042 /*============================================================================*/
1043
1044
1045 /*============================================================================*/
1046
1047 /*
1048 * \fn u32 frac28(u32 N, u32 D)
1049 * \brief Compute: (1<<28)*N/D
1050 * \param N 32 bits
1051 * \param D 32 bits
1052 * \return (1<<28)*N/D
1053 * This function is used to avoid floating-point calculations as they may
1054 * not be present on the target platform.
1055
1056 * frac28 performs an unsigned 28/28 bits division to 32-bit fixed point
1057 * fraction used for setting the Frequency Shifter registers.
1058 * N and D can hold numbers up to width: 28-bits.
1059 * The 4 bits integer part and the 28 bits fractional part are calculated.
1060
1061 * Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999
1062
1063 * N: 0...(1<<28)-1 = 268435454
1064 * D: 0...(1<<28)-1
1065 * Q: 0...(1<<32)-1
1066 */
1067 static u32 frac28(u32 N, u32 D)
1068 {
1069         int i = 0;
1070         u32 Q1 = 0;
1071         u32 R0 = 0;
1072
1073         R0 = (N % D) << 4;      /* 32-28 == 4 shifts possible at max */
1074         Q1 = N / D;             /* integer part, only the 4 least significant bits
1075                                    will be visible in the result */
1076
1077         /* division using radix 16, 7 nibbles in the result */
1078         for (i = 0; i < 7; i++) {
1079                 Q1 = (Q1 << 4) | R0 / D;
1080                 R0 = (R0 % D) << 4;
1081         }
1082         /* rounding */
1083         if ((R0 >> 3) >= D)
1084                 Q1++;
1085
1086         return Q1;
1087 }
1088
1089 /**
1090 * \fn u32 log1_times100( u32 x)
1091 * \brief Compute: 100*log10(x)
1092 * \param x 32 bits
1093 * \return 100*log10(x)
1094 *
1095 * 100*log10(x)
1096 * = 100*(log2(x)/log2(10)))
1097 * = (100*(2^15)*log2(x))/((2^15)*log2(10))
1098 * = ((200*(2^15)*log2(x))/((2^15)*log2(10)))/2
1099 * = ((200*(2^15)*(log2(x/y)+log2(y)))/((2^15)*log2(10)))/2
1100 * = ((200*(2^15)*log2(x/y))+(200*(2^15)*log2(y)))/((2^15)*log2(10)))/2
1101 *
1102 * where y = 2^k and 1<= (x/y) < 2
1103 */
1104
1105 static u32 log1_times100(u32 x)
1106 {
1107         static const u8 scale = 15;
1108         static const u8 index_width = 5;
1109         /*
1110            log2lut[n] = (1<<scale) * 200 * log2( 1.0 + ( (1.0/(1<<INDEXWIDTH)) * n ))
1111            0 <= n < ((1<<INDEXWIDTH)+1)
1112          */
1113
1114         static const u32 log2lut[] = {
1115                 0,              /* 0.000000 */
1116                 290941,         /* 290941.300628 */
1117                 573196,         /* 573196.476418 */
1118                 847269,         /* 847269.179851 */
1119                 1113620,        /* 1113620.489452 */
1120                 1372674,        /* 1372673.576986 */
1121                 1624818,        /* 1624817.752104 */
1122                 1870412,        /* 1870411.981536 */
1123                 2109788,        /* 2109787.962654 */
1124                 2343253,        /* 2343252.817465 */
1125                 2571091,        /* 2571091.461923 */
1126                 2793569,        /* 2793568.696416 */
1127                 3010931,        /* 3010931.055901 */
1128                 3223408,        /* 3223408.452106 */
1129                 3431216,        /* 3431215.635215 */
1130                 3634553,        /* 3634553.498355 */
1131                 3833610,        /* 3833610.244726 */
1132                 4028562,        /* 4028562.434393 */
1133                 4219576,        /* 4219575.925308 */
1134                 4406807,        /* 4406806.721144 */
1135                 4590402,        /* 4590401.736809 */
1136                 4770499,        /* 4770499.491025 */
1137                 4947231,        /* 4947230.734179 */
1138                 5120719,        /* 5120719.018555 */
1139                 5291081,        /* 5291081.217197 */
1140                 5458428,        /* 5458427.996830 */
1141                 5622864,        /* 5622864.249668 */
1142                 5784489,        /* 5784489.488298 */
1143                 5943398,        /* 5943398.207380 */
1144                 6099680,        /* 6099680.215452 */
1145                 6253421,        /* 6253420.939751 */
1146                 6404702,        /* 6404701.706649 */
1147                 6553600,        /* 6553600.000000 */
1148         };
1149
1150         u8 i = 0;
1151         u32 y = 0;
1152         u32 d = 0;
1153         u32 k = 0;
1154         u32 r = 0;
1155
1156         if (x == 0)
1157                 return 0;
1158
1159         /* Scale x (normalize) */
1160         /* computing y in log(x/y) = log(x) - log(y) */
1161         if ((x & (((u32) (-1)) << (scale + 1))) == 0) {
1162                 for (k = scale; k > 0; k--) {
1163                         if (x & (((u32) 1) << scale))
1164                                 break;
1165                         x <<= 1;
1166                 }
1167         } else {
1168                 for (k = scale; k < 31; k++) {
1169                         if ((x & (((u32) (-1)) << (scale + 1))) == 0)
1170                                 break;
1171                         x >>= 1;
1172                 }
1173         }
1174         /*
1175            Now x has binary point between bit[scale] and bit[scale-1]
1176            and 1.0 <= x < 2.0 */
1177
1178         /* correction for divison: log(x) = log(x/y)+log(y) */
1179         y = k * ((((u32) 1) << scale) * 200);
1180
1181         /* remove integer part */
1182         x &= ((((u32) 1) << scale) - 1);
1183         /* get index */
1184         i = (u8) (x >> (scale - index_width));
1185         /* compute delta (x-a) */
1186         d = x & ((((u32) 1) << (scale - index_width)) - 1);
1187         /* compute log, multiplication ( d* (.. )) must be within range ! */
1188         y += log2lut[i] +
1189             ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width));
1190         /* Conver to log10() */
1191         y /= 108853;            /* (log2(10) << scale) */
1192         r = (y >> 1);
1193         /* rounding */
1194         if (y & ((u32)1))
1195                 r++;
1196
1197         return r;
1198
1199 }
1200
1201 /**
1202 * \fn u32 frac_times1e6( u16 N, u32 D)
1203 * \brief Compute: (N/D) * 1000000.
1204 * \param N nominator 16-bits.
1205 * \param D denominator 32-bits.
1206 * \return u32
1207 * \retval ((N/D) * 1000000), 32 bits
1208 *
1209 * No check on D=0!
1210 */
1211 static u32 frac_times1e6(u32 N, u32 D)
1212 {
1213         u32 remainder = 0;
1214         u32 frac = 0;
1215
1216         /*
1217            frac = (N * 1000000) / D
1218            To let it fit in a 32 bits computation:
1219            frac = (N * (1000000 >> 4)) / (D >> 4)
1220            This would result in a problem in case D < 16 (div by 0).
1221            So we do it more elaborate as shown below.
1222          */
1223         frac = (((u32) N) * (1000000 >> 4)) / D;
1224         frac <<= 4;
1225         remainder = (((u32) N) * (1000000 >> 4)) % D;
1226         remainder <<= 4;
1227         frac += remainder / D;
1228         remainder = remainder % D;
1229         if ((remainder * 2) > D)
1230                 frac++;
1231
1232         return frac;
1233 }
1234
1235 /*============================================================================*/
1236
1237
1238 /**
1239 * \brief Values for NICAM prescaler gain. Computed from dB to integer
1240 *        and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20).
1241 *
1242 */
1243 static const u16 nicam_presc_table_val[43] = {
1244         1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4,
1245         5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16,
1246         18, 20, 23, 25, 28, 32, 36, 40, 45,
1247         51, 57, 64, 71, 80, 90, 101, 113, 127
1248 };
1249
1250 /*============================================================================*/
1251 /*==                        END HELPER FUNCTIONS                            ==*/
1252 /*============================================================================*/
1253
1254 /*============================================================================*/
1255 /*============================================================================*/
1256 /*==                      DRXJ DAP FUNCTIONS                                ==*/
1257 /*============================================================================*/
1258 /*============================================================================*/
1259
1260 /*
1261    This layer takes care of some device specific register access protocols:
1262    -conversion to short address format
1263    -access to audio block
1264    This layer is placed between the drx_dap_fasi and the rest of the drxj
1265    specific implementation. This layer can use address map knowledge whereas
1266    dap_fasi may not use memory map knowledge.
1267
1268    * For audio currently only 16 bits read and write register access is
1269      supported. More is not needed. RMW and 32 or 8 bit access on audio
1270      registers will have undefined behaviour. Flags (RMW, CRC reset, broadcast
1271      single/multi master) will be ignored.
1272
1273    TODO: check ignoring single/multimaster is ok for AUD access ?
1274 */
1275
1276 #define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1) ? true : false)
1277 #define DRXJ_DAP_AUDTRIF_TIMEOUT 80     /* millisec */
1278 /*============================================================================*/
1279
1280 /**
1281 * \fn bool is_handled_by_aud_tr_if( u32 addr )
1282 * \brief Check if this address is handled by the audio token ring interface.
1283 * \param addr
1284 * \return bool
1285 * \retval true  Yes, handled by audio token ring interface
1286 * \retval false No, not handled by audio token ring interface
1287 *
1288 */
1289 static
1290 bool is_handled_by_aud_tr_if(u32 addr)
1291 {
1292         bool retval = false;
1293
1294         if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) &&
1295             (DRXDAP_FASI_ADDR2BANK(addr) > 1) &&
1296             (DRXDAP_FASI_ADDR2BANK(addr) < 6)) {
1297                 retval = true;
1298         }
1299
1300         return retval;
1301 }
1302
1303 /*============================================================================*/
1304
1305 int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
1306                                  u16 w_count,
1307                                  u8 *wData,
1308                                  struct i2c_device_addr *r_dev_addr,
1309                                  u16 r_count, u8 *r_data)
1310 {
1311         struct drx39xxj_state *state;
1312         struct i2c_msg msg[2];
1313         unsigned int num_msgs;
1314
1315         if (w_dev_addr == NULL) {
1316                 /* Read only */
1317                 state = r_dev_addr->user_data;
1318                 msg[0].addr = r_dev_addr->i2c_addr >> 1;
1319                 msg[0].flags = I2C_M_RD;
1320                 msg[0].buf = r_data;
1321                 msg[0].len = r_count;
1322                 num_msgs = 1;
1323         } else if (r_dev_addr == NULL) {
1324                 /* Write only */
1325                 state = w_dev_addr->user_data;
1326                 msg[0].addr = w_dev_addr->i2c_addr >> 1;
1327                 msg[0].flags = 0;
1328                 msg[0].buf = wData;
1329                 msg[0].len = w_count;
1330                 num_msgs = 1;
1331         } else {
1332                 /* Both write and read */
1333                 state = w_dev_addr->user_data;
1334                 msg[0].addr = w_dev_addr->i2c_addr >> 1;
1335                 msg[0].flags = 0;
1336                 msg[0].buf = wData;
1337                 msg[0].len = w_count;
1338                 msg[1].addr = r_dev_addr->i2c_addr >> 1;
1339                 msg[1].flags = I2C_M_RD;
1340                 msg[1].buf = r_data;
1341                 msg[1].len = r_count;
1342                 num_msgs = 2;
1343         }
1344
1345         if (state->i2c == NULL) {
1346                 pr_err("i2c was zero, aborting\n");
1347                 return 0;
1348         }
1349         if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) {
1350                 pr_warn("drx3933: I2C write/read failed\n");
1351                 return -EREMOTEIO;
1352         }
1353
1354 #ifdef DJH_DEBUG
1355         if (w_dev_addr == NULL || r_dev_addr == NULL)
1356                 return 0;
1357
1358         state = w_dev_addr->user_data;
1359
1360         if (state->i2c == NULL)
1361                 return 0;
1362
1363         msg[0].addr = w_dev_addr->i2c_addr;
1364         msg[0].flags = 0;
1365         msg[0].buf = wData;
1366         msg[0].len = w_count;
1367         msg[1].addr = r_dev_addr->i2c_addr;
1368         msg[1].flags = I2C_M_RD;
1369         msg[1].buf = r_data;
1370         msg[1].len = r_count;
1371         num_msgs = 2;
1372
1373         pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
1374                w_dev_addr->i2c_addr, state->i2c, w_count, r_count);
1375
1376         if (i2c_transfer(state->i2c, msg, 2) != 2) {
1377                 pr_warn("drx3933: I2C write/read failed\n");
1378                 return -EREMOTEIO;
1379         }
1380 #endif
1381         return 0;
1382 }
1383
1384 /*============================================================================*/
1385
1386 /******************************
1387 *
1388 * int drxdap_fasi_read_block (
1389 *      struct i2c_device_addr *dev_addr,      -- address of I2C device
1390 *      u32 addr,         -- address of chip register/memory
1391 *      u16            datasize,     -- number of bytes to read
1392 *      u8 *data,         -- data to receive
1393 *      u32 flags)        -- special device flags
1394 *
1395 * Read block data from chip address. Because the chip is word oriented,
1396 * the number of bytes to read must be even.
1397 *
1398 * Make sure that the buffer to receive the data is large enough.
1399 *
1400 * Although this function expects an even number of bytes, it is still byte
1401 * oriented, and the data read back is NOT translated to the endianness of
1402 * the target platform.
1403 *
1404 * Output:
1405 * - 0     if reading was successful
1406 *                  in that case: data read is in *data.
1407 * - -EIO  if anything went wrong
1408 *
1409 ******************************/
1410
1411 static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
1412                                          u32 addr,
1413                                          u16 datasize,
1414                                          u8 *data, u32 flags)
1415 {
1416         u8 buf[4];
1417         u16 bufx;
1418         int rc;
1419         u16 overhead_size = 0;
1420
1421         /* Check parameters ******************************************************* */
1422         if (dev_addr == NULL)
1423                 return -EINVAL;
1424
1425         overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
1426             (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
1427
1428         if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
1429             ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
1430              DRXDAP_FASI_LONG_FORMAT(addr)) ||
1431             (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
1432             ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
1433                 return -EINVAL;
1434         }
1435
1436         /* ReadModifyWrite & mode flag bits are not allowed */
1437         flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
1438 #if DRXDAP_SINGLE_MASTER
1439         flags |= DRXDAP_FASI_SINGLE_MASTER;
1440 #endif
1441
1442         /* Read block from I2C **************************************************** */
1443         do {
1444                 u16 todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ?
1445                               datasize : DRXDAP_MAX_RCHUNKSIZE);
1446
1447                 bufx = 0;
1448
1449                 addr &= ~DRXDAP_FASI_FLAGS;
1450                 addr |= flags;
1451
1452 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1453                 /* short format address preferred but long format otherwise */
1454                 if (DRXDAP_FASI_LONG_FORMAT(addr)) {
1455 #endif
1456 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1457                         buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
1458                         buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
1459                         buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
1460                         buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
1461 #endif
1462 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1463                 } else {
1464 #endif
1465 #if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)
1466                         buf[bufx++] = (u8) ((addr << 1) & 0xFF);
1467                         buf[bufx++] =
1468                             (u8) (((addr >> 16) & 0x0F) |
1469                                     ((addr >> 18) & 0xF0));
1470 #endif
1471 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1472                 }
1473 #endif
1474
1475 #if DRXDAP_SINGLE_MASTER
1476                 /*
1477                  * In single master mode, split the read and write actions.
1478                  * No special action is needed for write chunks here.
1479                  */
1480                 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf,
1481                                            NULL, 0, NULL);
1482                 if (rc == 0)
1483                         rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data);
1484 #else
1485                 /* In multi master mode, do everything in one RW action */
1486                 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,
1487                                           data);
1488 #endif
1489                 data += todo;
1490                 addr += (todo >> 1);
1491                 datasize -= todo;
1492         } while (datasize && rc == 0);
1493
1494         return rc;
1495 }
1496
1497
1498 /******************************
1499 *
1500 * int drxdap_fasi_read_reg16 (
1501 *     struct i2c_device_addr *dev_addr, -- address of I2C device
1502 *     u32 addr,    -- address of chip register/memory
1503 *     u16 *data,    -- data to receive
1504 *     u32 flags)   -- special device flags
1505 *
1506 * Read one 16-bit register or memory location. The data received back is
1507 * converted back to the target platform's endianness.
1508 *
1509 * Output:
1510 * - 0     if reading was successful
1511 *                  in that case: read data is at *data
1512 * - -EIO  if anything went wrong
1513 *
1514 ******************************/
1515
1516 static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr,
1517                                          u32 addr,
1518                                          u16 *data, u32 flags)
1519 {
1520         u8 buf[sizeof(*data)];
1521         int rc;
1522
1523         if (!data)
1524                 return -EINVAL;
1525
1526         rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1527         *data = buf[0] + (((u16) buf[1]) << 8);
1528         return rc;
1529 }
1530
1531 /******************************
1532 *
1533 * int drxdap_fasi_read_reg32 (
1534 *     struct i2c_device_addr *dev_addr, -- address of I2C device
1535 *     u32 addr,    -- address of chip register/memory
1536 *     u32 *data,    -- data to receive
1537 *     u32 flags)   -- special device flags
1538 *
1539 * Read one 32-bit register or memory location. The data received back is
1540 * converted back to the target platform's endianness.
1541 *
1542 * Output:
1543 * - 0     if reading was successful
1544 *                  in that case: read data is at *data
1545 * - -EIO  if anything went wrong
1546 *
1547 ******************************/
1548
1549 static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
1550                                          u32 addr,
1551                                          u32 *data, u32 flags)
1552 {
1553         u8 buf[sizeof(*data)];
1554         int rc;
1555
1556         if (!data)
1557                 return -EINVAL;
1558
1559         rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1560         *data = (((u32) buf[0]) << 0) +
1561             (((u32) buf[1]) << 8) +
1562             (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1563         return rc;
1564 }
1565
1566 /******************************
1567 *
1568 * int drxdap_fasi_write_block (
1569 *      struct i2c_device_addr *dev_addr,    -- address of I2C device
1570 *      u32 addr,       -- address of chip register/memory
1571 *      u16            datasize,   -- number of bytes to read
1572 *      u8 *data,       -- data to receive
1573 *      u32 flags)      -- special device flags
1574 *
1575 * Write block data to chip address. Because the chip is word oriented,
1576 * the number of bytes to write must be even.
1577 *
1578 * Although this function expects an even number of bytes, it is still byte
1579 * oriented, and the data being written is NOT translated from the endianness of
1580 * the target platform.
1581 *
1582 * Output:
1583 * - 0     if writing was successful
1584 * - -EIO  if anything went wrong
1585 *
1586 ******************************/
1587
1588 static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
1589                                           u32 addr,
1590                                           u16 datasize,
1591                                           u8 *data, u32 flags)
1592 {
1593         u8 buf[DRXDAP_MAX_WCHUNKSIZE];
1594         int st = -EIO;
1595         int first_err = 0;
1596         u16 overhead_size = 0;
1597         u16 block_size = 0;
1598
1599         /* Check parameters ******************************************************* */
1600         if (dev_addr == NULL)
1601                 return -EINVAL;
1602
1603         overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
1604             (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
1605
1606         if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
1607             ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
1608              DRXDAP_FASI_LONG_FORMAT(addr)) ||
1609             (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
1610             ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1))
1611                 return -EINVAL;
1612
1613         flags &= DRXDAP_FASI_FLAGS;
1614         flags &= ~DRXDAP_FASI_MODEFLAGS;
1615 #if DRXDAP_SINGLE_MASTER
1616         flags |= DRXDAP_FASI_SINGLE_MASTER;
1617 #endif
1618
1619         /* Write block to I2C ***************************************************** */
1620         block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1;
1621         do {
1622                 u16 todo = 0;
1623                 u16 bufx = 0;
1624
1625                 /* Buffer device address */
1626                 addr &= ~DRXDAP_FASI_FLAGS;
1627                 addr |= flags;
1628 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1629                 /* short format address preferred but long format otherwise */
1630                 if (DRXDAP_FASI_LONG_FORMAT(addr)) {
1631 #endif
1632 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1)
1633                         buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
1634                         buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
1635                         buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
1636                         buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
1637 #endif
1638 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1639                 } else {
1640 #endif
1641 #if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)
1642                         buf[bufx++] = (u8) ((addr << 1) & 0xFF);
1643                         buf[bufx++] =
1644                             (u8) (((addr >> 16) & 0x0F) |
1645                                     ((addr >> 18) & 0xF0));
1646 #endif
1647 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1648                 }
1649 #endif
1650
1651                 /*
1652                    In single master mode block_size can be 0. In such a case this I2C
1653                    sequense will be visible: (1) write address {i2c addr,
1654                    4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
1655                    (3) write address (4) write data etc...
1656                    Addres must be rewriten because HI is reset after data transport and
1657                    expects an address.
1658                  */
1659                 todo = (block_size < datasize ? block_size : datasize);
1660                 if (todo == 0) {
1661                         u16 overhead_size_i2c_addr = 0;
1662                         u16 data_block_size = 0;
1663
1664                         overhead_size_i2c_addr =
1665                             (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1);
1666                         data_block_size =
1667                             (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1;
1668
1669                         /* write device address */
1670                         st = drxbsp_i2c_write_read(dev_addr,
1671                                                   (u16) (bufx),
1672                                                   buf,
1673                                                   (struct i2c_device_addr *)(NULL),
1674                                                   0, (u8 *)(NULL));
1675
1676                         if ((st != 0) && (first_err == 0)) {
1677                                 /* at the end, return the first error encountered */
1678                                 first_err = st;
1679                         }
1680                         bufx = 0;
1681                         todo =
1682                             (data_block_size <
1683                              datasize ? data_block_size : datasize);
1684                 }
1685                 memcpy(&buf[bufx], data, todo);
1686                 /* write (address if can do and) data */
1687                 st = drxbsp_i2c_write_read(dev_addr,
1688                                           (u16) (bufx + todo),
1689                                           buf,
1690                                           (struct i2c_device_addr *)(NULL),
1691                                           0, (u8 *)(NULL));
1692
1693                 if ((st != 0) && (first_err == 0)) {
1694                         /* at the end, return the first error encountered */
1695                         first_err = st;
1696                 }
1697                 datasize -= todo;
1698                 data += todo;
1699                 addr += (todo >> 1);
1700         } while (datasize);
1701
1702         return first_err;
1703 }
1704
1705 /******************************
1706 *
1707 * int drxdap_fasi_write_reg16 (
1708 *     struct i2c_device_addr *dev_addr, -- address of I2C device
1709 *     u32 addr,    -- address of chip register/memory
1710 *     u16            data,    -- data to send
1711 *     u32 flags)   -- special device flags
1712 *
1713 * Write one 16-bit register or memory location. The data being written is
1714 * converted from the target platform's endianness to little endian.
1715 *
1716 * Output:
1717 * - 0     if writing was successful
1718 * - -EIO  if anything went wrong
1719 *
1720 ******************************/
1721
1722 static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr,
1723                                           u32 addr,
1724                                           u16 data, u32 flags)
1725 {
1726         u8 buf[sizeof(data)];
1727
1728         buf[0] = (u8) ((data >> 0) & 0xFF);
1729         buf[1] = (u8) ((data >> 8) & 0xFF);
1730
1731         return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1732 }
1733
1734 /******************************
1735 *
1736 * int drxdap_fasi_read_modify_write_reg16 (
1737 *      struct i2c_device_addr *dev_addr,   -- address of I2C device
1738 *      u32 waddr,     -- address of chip register/memory
1739 *      u32 raddr,     -- chip address to read back from
1740 *      u16            wdata,     -- data to send
1741 *      u16 *rdata)     -- data to receive back
1742 *
1743 * Write 16-bit data, then read back the original contents of that location.
1744 * Requires long addressing format to be allowed.
1745 *
1746 * Before sending data, the data is converted to little endian. The
1747 * data received back is converted back to the target platform's endianness.
1748 *
1749 * WARNING: This function is only guaranteed to work if there is one
1750 * master on the I2C bus.
1751 *
1752 * Output:
1753 * - 0     if reading was successful
1754 *                  in that case: read back data is at *rdata
1755 * - -EIO  if anything went wrong
1756 *
1757 ******************************/
1758
1759 static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
1760                                                     u32 waddr,
1761                                                     u32 raddr,
1762                                                     u16 wdata, u16 *rdata)
1763 {
1764         int rc = -EIO;
1765
1766 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1767         if (rdata == NULL)
1768                 return -EINVAL;
1769
1770         rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);
1771         if (rc == 0)
1772                 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);
1773 #endif
1774
1775         return rc;
1776 }
1777
1778 /******************************
1779 *
1780 * int drxdap_fasi_write_reg32 (
1781 *     struct i2c_device_addr *dev_addr, -- address of I2C device
1782 *     u32 addr,    -- address of chip register/memory
1783 *     u32            data,    -- data to send
1784 *     u32 flags)   -- special device flags
1785 *
1786 * Write one 32-bit register or memory location. The data being written is
1787 * converted from the target platform's endianness to little endian.
1788 *
1789 * Output:
1790 * - 0     if writing was successful
1791 * - -EIO  if anything went wrong
1792 *
1793 ******************************/
1794
1795 static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
1796                                           u32 addr,
1797                                           u32 data, u32 flags)
1798 {
1799         u8 buf[sizeof(data)];
1800
1801         buf[0] = (u8) ((data >> 0) & 0xFF);
1802         buf[1] = (u8) ((data >> 8) & 0xFF);
1803         buf[2] = (u8) ((data >> 16) & 0xFF);
1804         buf[3] = (u8) ((data >> 24) & 0xFF);
1805
1806         return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1807 }
1808
1809 /*============================================================================*/
1810
1811 /**
1812 * \fn int drxj_dap_rm_write_reg16short
1813 * \brief Read modify write 16 bits audio register using short format only.
1814 * \param dev_addr
1815 * \param waddr    Address to write to
1816 * \param raddr    Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A)
1817 * \param wdata    Data to write
1818 * \param rdata    Buffer for data to read
1819 * \return int
1820 * \retval 0 Succes
1821 * \retval -EIO Timeout, I2C error, illegal bank
1822 *
1823 * 16 bits register read modify write access using short addressing format only.
1824 * Requires knowledge of the registermap, thus device dependent.
1825 * Using DAP FASI directly to avoid endless recursion of RMWs to audio registers.
1826 *
1827 */
1828
1829 /* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 )
1830    See comments drxj_dap_read_modify_write_reg16 */
1831 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)
1832 static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr,
1833                                               u32 waddr,
1834                                               u32 raddr,
1835                                               u16 wdata, u16 *rdata)
1836 {
1837         int rc;
1838
1839         if (rdata == NULL)
1840                 return -EINVAL;
1841
1842         /* Set RMW flag */
1843         rc = drxdap_fasi_write_reg16(dev_addr,
1844                                               SIO_HI_RA_RAM_S0_FLG_ACC__A,
1845                                               SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M,
1846                                               0x0000);
1847         if (rc == 0) {
1848                 /* Write new data: triggers RMW */
1849                 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata,
1850                                                       0x0000);
1851         }
1852         if (rc == 0) {
1853                 /* Read old data */
1854                 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata,
1855                                                      0x0000);
1856         }
1857         if (rc == 0) {
1858                 /* Reset RMW flag */
1859                 rc = drxdap_fasi_write_reg16(dev_addr,
1860                                                       SIO_HI_RA_RAM_S0_FLG_ACC__A,
1861                                                       0, 0x0000);
1862         }
1863
1864         return rc;
1865 }
1866 #endif
1867
1868 /*============================================================================*/
1869
1870 static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
1871                                                  u32 waddr,
1872                                                  u32 raddr,
1873                                                  u16 wdata, u16 *rdata)
1874 {
1875         /* TODO: correct short/long addressing format decision,
1876            now long format has higher prio then short because short also
1877            needs virt bnks (not impl yet) for certain audio registers */
1878 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1879         return drxdap_fasi_read_modify_write_reg16(dev_addr,
1880                                                           waddr,
1881                                                           raddr, wdata, rdata);
1882 #else
1883         return drxj_dap_rm_write_reg16short(dev_addr, waddr, raddr, wdata, rdata);
1884 #endif
1885 }
1886
1887
1888 /*============================================================================*/
1889
1890 /**
1891 * \fn int drxj_dap_read_aud_reg16
1892 * \brief Read 16 bits audio register
1893 * \param dev_addr
1894 * \param addr
1895 * \param data
1896 * \return int
1897 * \retval 0 Succes
1898 * \retval -EIO Timeout, I2C error, illegal bank
1899 *
1900 * 16 bits register read access via audio token ring interface.
1901 *
1902 */
1903 static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr,
1904                                          u32 addr, u16 *data)
1905 {
1906         u32 start_timer = 0;
1907         u32 current_timer = 0;
1908         u32 delta_timer = 0;
1909         u16 tr_status = 0;
1910         int stat = -EIO;
1911
1912         /* No read possible for bank 3, return with error */
1913         if (DRXDAP_FASI_ADDR2BANK(addr) == 3) {
1914                 stat = -EINVAL;
1915         } else {
1916                 const u32 write_bit = ((dr_xaddr_t) 1) << 16;
1917
1918                 /* Force reset write bit */
1919                 addr &= (~write_bit);
1920
1921                 /* Set up read */
1922                 start_timer = jiffies_to_msecs(jiffies);
1923                 do {
1924                         /* RMW to aud TR IF until request is granted or timeout */
1925                         stat = drxj_dap_read_modify_write_reg16(dev_addr,
1926                                                              addr,
1927                                                              SIO_HI_RA_RAM_S0_RMWBUF__A,
1928                                                              0x0000, &tr_status);
1929
1930                         if (stat != 0)
1931                                 break;
1932
1933                         current_timer = jiffies_to_msecs(jiffies);
1934                         delta_timer = current_timer - start_timer;
1935                         if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
1936                                 stat = -EIO;
1937                                 break;
1938                         }
1939
1940                 } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
1941                           AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
1942                          ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
1943                           AUD_TOP_TR_CTR_FIFO_FULL_FULL));
1944         }                       /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */
1945
1946         /* Wait for read ready status or timeout */
1947         if (stat == 0) {
1948                 start_timer = jiffies_to_msecs(jiffies);
1949
1950                 while ((tr_status & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) !=
1951                        AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) {
1952                         stat = drxj_dap_read_reg16(dev_addr,
1953                                                   AUD_TOP_TR_CTR__A,
1954                                                   &tr_status, 0x0000);
1955                         if (stat != 0)
1956                                 break;
1957
1958                         current_timer = jiffies_to_msecs(jiffies);
1959                         delta_timer = current_timer - start_timer;
1960                         if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
1961                                 stat = -EIO;
1962                                 break;
1963                         }
1964                 }               /* while ( ... ) */
1965         }
1966
1967         /* Read value */
1968         if (stat == 0)
1969                 stat = drxj_dap_read_modify_write_reg16(dev_addr,
1970                                                      AUD_TOP_TR_RD_REG__A,
1971                                                      SIO_HI_RA_RAM_S0_RMWBUF__A,
1972                                                      0x0000, data);
1973         return stat;
1974 }
1975
1976 /*============================================================================*/
1977
1978 static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
1979                                       u32 addr,
1980                                       u16 *data, u32 flags)
1981 {
1982         int stat = -EIO;
1983
1984         /* Check param */
1985         if ((dev_addr == NULL) || (data == NULL))
1986                 return -EINVAL;
1987
1988         if (is_handled_by_aud_tr_if(addr))
1989                 stat = drxj_dap_read_aud_reg16(dev_addr, addr, data);
1990         else
1991                 stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags);
1992
1993         return stat;
1994 }
1995 /*============================================================================*/
1996
1997 /**
1998 * \fn int drxj_dap_write_aud_reg16
1999 * \brief Write 16 bits audio register
2000 * \param dev_addr
2001 * \param addr
2002 * \param data
2003 * \return int
2004 * \retval 0 Succes
2005 * \retval -EIO Timeout, I2C error, illegal bank
2006 *
2007 * 16 bits register write access via audio token ring interface.
2008 *
2009 */
2010 static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr,
2011                                           u32 addr, u16 data)
2012 {
2013         int stat = -EIO;
2014
2015         /* No write possible for bank 2, return with error */
2016         if (DRXDAP_FASI_ADDR2BANK(addr) == 2) {
2017                 stat = -EINVAL;
2018         } else {
2019                 u32 start_timer = 0;
2020                 u32 current_timer = 0;
2021                 u32 delta_timer = 0;
2022                 u16 tr_status = 0;
2023                 const u32 write_bit = ((dr_xaddr_t) 1) << 16;
2024
2025                 /* Force write bit */
2026                 addr |= write_bit;
2027                 start_timer = jiffies_to_msecs(jiffies);
2028                 do {
2029                         /* RMW to aud TR IF until request is granted or timeout */
2030                         stat = drxj_dap_read_modify_write_reg16(dev_addr,
2031                                                              addr,
2032                                                              SIO_HI_RA_RAM_S0_RMWBUF__A,
2033                                                              data, &tr_status);
2034                         if (stat != 0)
2035                                 break;
2036
2037                         current_timer = jiffies_to_msecs(jiffies);
2038                         delta_timer = current_timer - start_timer;
2039                         if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
2040                                 stat = -EIO;
2041                                 break;
2042                         }
2043
2044                 } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
2045                           AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
2046                          ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
2047                           AUD_TOP_TR_CTR_FIFO_FULL_FULL));
2048
2049         }                       /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */
2050
2051         return stat;
2052 }
2053
2054 /*============================================================================*/
2055
2056 static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
2057                                        u32 addr,
2058                                        u16 data, u32 flags)
2059 {
2060         int stat = -EIO;
2061
2062         /* Check param */
2063         if (dev_addr == NULL)
2064                 return -EINVAL;
2065
2066         if (is_handled_by_aud_tr_if(addr))
2067                 stat = drxj_dap_write_aud_reg16(dev_addr, addr, data);
2068         else
2069                 stat = drxdap_fasi_write_reg16(dev_addr,
2070                                                             addr, data, flags);
2071
2072         return stat;
2073 }
2074
2075 /*============================================================================*/
2076
2077 /* Free data ram in SIO HI */
2078 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2079 #define SIO_HI_RA_RAM_USR_END__A   0x420060
2080
2081 #define DRXJ_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2082 #define DRXJ_HI_ATOMIC_BUF_END   (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2083 #define DRXJ_HI_ATOMIC_READ      SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2084 #define DRXJ_HI_ATOMIC_WRITE     SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2085
2086 /**
2087 * \fn int drxj_dap_atomic_read_write_block()
2088 * \brief Basic access routine for atomic read or write access
2089 * \param dev_addr  pointer to i2c dev address
2090 * \param addr     destination/source address
2091 * \param datasize size of data buffer in bytes
2092 * \param data     pointer to data buffer
2093 * \return int
2094 * \retval 0 Succes
2095 * \retval -EIO Timeout, I2C error, illegal bank
2096 *
2097 */
2098 static
2099 int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr,
2100                                           u32 addr,
2101                                           u16 datasize,
2102                                           u8 *data, bool read_flag)
2103 {
2104         struct drxj_hi_cmd hi_cmd;
2105         int rc;
2106         u16 word;
2107         u16 dummy = 0;
2108         u16 i = 0;
2109
2110         /* Parameter check */
2111         if (!data || !dev_addr || ((datasize % 2)) || ((datasize / 2) > 8))
2112                 return -EINVAL;
2113
2114         /* Set up HI parameters to read or write n bytes */
2115         hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY;
2116         hi_cmd.param1 =
2117             (u16) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) +
2118                      DRXDAP_FASI_ADDR2BANK(DRXJ_HI_ATOMIC_BUF_START));
2119         hi_cmd.param2 =
2120             (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START);
2121         hi_cmd.param3 = (u16) ((datasize / 2) - 1);
2122         if (!read_flag)
2123                 hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE;
2124         else
2125                 hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ;
2126         hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) +
2127                                 DRXDAP_FASI_ADDR2BANK(addr));
2128         hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr);
2129
2130         if (!read_flag) {
2131                 /* write data to buffer */
2132                 for (i = 0; i < (datasize / 2); i++) {
2133
2134                         word = ((u16) data[2 * i]);
2135                         word += (((u16) data[(2 * i) + 1]) << 8);
2136                         drxj_dap_write_reg16(dev_addr,
2137                                              (DRXJ_HI_ATOMIC_BUF_START + i),
2138                                             word, 0);
2139                 }
2140         }
2141
2142         rc = hi_command(dev_addr, &hi_cmd, &dummy);
2143         if (rc != 0) {
2144                 pr_err("error %d\n", rc);
2145                 goto rw_error;
2146         }
2147
2148         if (read_flag) {
2149                 /* read data from buffer */
2150                 for (i = 0; i < (datasize / 2); i++) {
2151                         drxj_dap_read_reg16(dev_addr,
2152                                             (DRXJ_HI_ATOMIC_BUF_START + i),
2153                                            &word, 0);
2154                         data[2 * i] = (u8) (word & 0xFF);
2155                         data[(2 * i) + 1] = (u8) (word >> 8);
2156                 }
2157         }
2158
2159         return 0;
2160
2161 rw_error:
2162         return rc;
2163
2164 }
2165
2166 /*============================================================================*/
2167
2168 /**
2169 * \fn int drxj_dap_atomic_read_reg32()
2170 * \brief Atomic read of 32 bits words
2171 */
2172 static
2173 int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr,
2174                                      u32 addr,
2175                                      u32 *data, u32 flags)
2176 {
2177         u8 buf[sizeof(*data)] = { 0 };
2178         int rc = -EIO;
2179         u32 word = 0;
2180
2181         if (!data)
2182                 return -EINVAL;
2183
2184         rc = drxj_dap_atomic_read_write_block(dev_addr, addr,
2185                                               sizeof(*data), buf, true);
2186
2187         if (rc < 0)
2188                 return 0;
2189
2190         word = (u32) buf[3];
2191         word <<= 8;
2192         word |= (u32) buf[2];
2193         word <<= 8;
2194         word |= (u32) buf[1];
2195         word <<= 8;
2196         word |= (u32) buf[0];
2197
2198         *data = word;
2199
2200         return rc;
2201 }
2202
2203 /*============================================================================*/
2204
2205 /*============================================================================*/
2206 /*==                        END DRXJ DAP FUNCTIONS                          ==*/
2207 /*============================================================================*/
2208
2209 /*============================================================================*/
2210 /*============================================================================*/
2211 /*==                      HOST INTERFACE FUNCTIONS                          ==*/
2212 /*============================================================================*/
2213 /*============================================================================*/
2214
2215 /**
2216 * \fn int hi_cfg_command()
2217 * \brief Configure HI with settings stored in the demod structure.
2218 * \param demod Demodulator.
2219 * \return int.
2220 *
2221 * This routine was created because to much orthogonal settings have
2222 * been put into one HI API function (configure). Especially the I2C bridge
2223 * enable/disable should not need re-configuration of the HI.
2224 *
2225 */
2226 static int hi_cfg_command(const struct drx_demod_instance *demod)
2227 {
2228         struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2229         struct drxj_hi_cmd hi_cmd;
2230         u16 result = 0;
2231         int rc;
2232
2233         ext_attr = (struct drxj_data *) demod->my_ext_attr;
2234
2235         hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG;
2236         hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
2237         hi_cmd.param2 = ext_attr->hi_cfg_timing_div;
2238         hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay;
2239         hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key;
2240         hi_cmd.param5 = ext_attr->hi_cfg_ctrl;
2241         hi_cmd.param6 = ext_attr->hi_cfg_transmit;
2242
2243         rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
2244         if (rc != 0) {
2245                 pr_err("error %d\n", rc);
2246                 goto rw_error;
2247         }
2248
2249         /* Reset power down flag (set one call only) */
2250         ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
2251
2252         return 0;
2253
2254 rw_error:
2255         return rc;
2256 }
2257
2258 /**
2259 * \fn int hi_command()
2260 * \brief Configure HI with settings stored in the demod structure.
2261 * \param dev_addr I2C address.
2262 * \param cmd HI command.
2263 * \param result HI command result.
2264 * \return int.
2265 *
2266 * Sends command to HI
2267 *
2268 */
2269 static int
2270 hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 *result)
2271 {
2272         u16 wait_cmd = 0;
2273         u16 nr_retries = 0;
2274         bool powerdown_cmd = false;
2275         int rc;
2276
2277         /* Write parameters */
2278         switch (cmd->cmd) {
2279
2280         case SIO_HI_RA_RAM_CMD_CONFIG:
2281         case SIO_HI_RA_RAM_CMD_ATOMIC_COPY:
2282                 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0);
2283                 if (rc != 0) {
2284                         pr_err("error %d\n", rc);
2285                         goto rw_error;
2286                 }
2287                 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0);
2288                 if (rc != 0) {
2289                         pr_err("error %d\n", rc);
2290                         goto rw_error;
2291                 }
2292                 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0);
2293                 if (rc != 0) {
2294                         pr_err("error %d\n", rc);
2295                         goto rw_error;
2296                 }
2297                 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0);
2298                 if (rc != 0) {
2299                         pr_err("error %d\n", rc);
2300                         goto rw_error;
2301                 }
2302                 /* fallthrough */
2303         case SIO_HI_RA_RAM_CMD_BRDCTRL:
2304                 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);
2305                 if (rc != 0) {
2306                         pr_err("error %d\n", rc);
2307                         goto rw_error;
2308                 }
2309                 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0);
2310                 if (rc != 0) {
2311                         pr_err("error %d\n", rc);
2312                         goto rw_error;
2313                 }
2314                 /* fallthrough */
2315         case SIO_HI_RA_RAM_CMD_NULL:
2316                 /* No parameters */
2317                 break;
2318
2319         default:
2320                 return -EINVAL;
2321                 break;
2322         }
2323
2324         /* Write command */
2325         rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0);
2326         if (rc != 0) {
2327                 pr_err("error %d\n", rc);
2328                 goto rw_error;
2329         }
2330
2331         if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET)
2332                 msleep(1);
2333
2334         /* Detect power down to ommit reading result */
2335         powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
2336                                   (((cmd->
2337                                      param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M)
2338                                    == SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
2339         if (!powerdown_cmd) {
2340                 /* Wait until command rdy */
2341                 do {
2342                         nr_retries++;
2343                         if (nr_retries > DRXJ_MAX_RETRIES) {
2344                                 pr_err("timeout\n");
2345                                 goto rw_error;
2346                         }
2347
2348                         rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0);
2349                         if (rc != 0) {
2350                                 pr_err("error %d\n", rc);
2351                                 goto rw_error;
2352                         }
2353                 } while (wait_cmd != 0);
2354
2355                 /* Read result */
2356                 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0);
2357                 if (rc != 0) {
2358                         pr_err("error %d\n", rc);
2359                         goto rw_error;
2360                 }
2361
2362         }
2363         /* if ( powerdown_cmd == true ) */
2364         return 0;
2365 rw_error:
2366         return rc;
2367 }
2368
2369 /**
2370 * \fn int init_hi( const struct drx_demod_instance *demod )
2371 * \brief Initialise and configurate HI.
2372 * \param demod pointer to demod data.
2373 * \return int Return status.
2374 * \retval 0 Success.
2375 * \retval -EIO Failure.
2376 *
2377 * Needs to know Psys (System Clock period) and Posc (Osc Clock period)
2378 * Need to store configuration in driver because of the way I2C
2379 * bridging is controlled.
2380 *
2381 */
2382 static int init_hi(const struct drx_demod_instance *demod)
2383 {
2384         struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2385         struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2386         struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2387         int rc;
2388
2389         ext_attr = (struct drxj_data *) demod->my_ext_attr;
2390         common_attr = (struct drx_common_attr *) demod->my_common_attr;
2391         dev_addr = demod->my_i2c_dev_addr;
2392
2393         /* PATCH for bug 5003, HI ucode v3.1.0 */
2394         rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0);
2395         if (rc != 0) {
2396                 pr_err("error %d\n", rc);
2397                 goto rw_error;
2398         }
2399
2400         /* Timing div, 250ns/Psys */
2401         /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2402         ext_attr->hi_cfg_timing_div =
2403             (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000;
2404         /* Clipping */
2405         if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
2406                 ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
2407         /* Bridge delay, uses oscilator clock */
2408         /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2409         /* SDA brdige delay */
2410         ext_attr->hi_cfg_bridge_delay =
2411             (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) /
2412             1000;
2413         /* Clipping */
2414         if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M)
2415                 ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
2416         /* SCL bridge delay, same as SDA for now */
2417         ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) <<
2418                                       SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B);
2419         /* Wakeup key, setting the read flag (as suggest in the documentation) does
2420            not always result into a working solution (barebones worked VI2C failed).
2421            Not setting the bit works in all cases . */
2422         ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY;
2423         /* port/bridge/power down ctrl */
2424         ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE);
2425         /* transit mode time out delay and watch dog divider */
2426         ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE;
2427
2428         rc = hi_cfg_command(demod);
2429         if (rc != 0) {
2430                 pr_err("error %d\n", rc);
2431                 goto rw_error;
2432         }
2433
2434         return 0;
2435
2436 rw_error:
2437         return rc;
2438 }
2439
2440 /*============================================================================*/
2441 /*==                   END HOST INTERFACE FUNCTIONS                         ==*/
2442 /*============================================================================*/
2443
2444 /*============================================================================*/
2445 /*============================================================================*/
2446 /*==                        AUXILIARY FUNCTIONS                             ==*/
2447 /*============================================================================*/
2448 /*============================================================================*/
2449
2450 /**
2451 * \fn int get_device_capabilities()
2452 * \brief Get and store device capabilities.
2453 * \param demod  Pointer to demodulator instance.
2454 * \return int.
2455 * \return 0    Success
2456 * \retval -EIO Failure
2457 *
2458 * Depending on pulldowns on MDx pins the following internals are set:
2459 *  * common_attr->osc_clock_freq
2460 *  * ext_attr->has_lna
2461 *  * ext_attr->has_ntsc
2462 *  * ext_attr->has_btsc
2463 *  * ext_attr->has_oob
2464 *
2465 */
2466 static int get_device_capabilities(struct drx_demod_instance *demod)
2467 {
2468         struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2469         struct drxj_data *ext_attr = (struct drxj_data *) NULL;
2470         struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2471         u16 sio_pdr_ohw_cfg = 0;
2472         u32 sio_top_jtagid_lo = 0;
2473         u16 bid = 0;
2474         int rc;
2475
2476         common_attr = (struct drx_common_attr *) demod->my_common_attr;
2477         ext_attr = (struct drxj_data *) demod->my_ext_attr;
2478         dev_addr = demod->my_i2c_dev_addr;
2479
2480         rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2481         if (rc != 0) {
2482                 pr_err("error %d\n", rc);
2483                 goto rw_error;
2484         }
2485         rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0);
2486         if (rc != 0) {
2487                 pr_err("error %d\n", rc);
2488                 goto rw_error;
2489         }
2490         rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2491         if (rc != 0) {
2492                 pr_err("error %d\n", rc);
2493                 goto rw_error;
2494         }
2495
2496         switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
2497         case 0:
2498                 /* ignore (bypass ?) */
2499                 break;
2500         case 1:
2501                 /* 27 MHz */
2502                 common_attr->osc_clock_freq = 27000;
2503                 break;
2504         case 2:
2505                 /* 20.25 MHz */
2506                 common_attr->osc_clock_freq = 20250;
2507                 break;
2508         case 3:
2509                 /* 4 MHz */
2510                 common_attr->osc_clock_freq = 4000;
2511                 break;
2512         default:
2513                 return -EIO;
2514         }
2515
2516         /*
2517            Determine device capabilities
2518            Based on pinning v47
2519          */
2520         rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0);
2521         if (rc != 0) {
2522                 pr_err("error %d\n", rc);
2523                 goto rw_error;
2524         }
2525         ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF);
2526
2527         switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
2528         case 0x31:
2529                 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2530                 if (rc != 0) {
2531                         pr_err("error %d\n", rc);
2532                         goto rw_error;
2533                 }
2534                 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0);
2535                 if (rc != 0) {
2536                         pr_err("error %d\n", rc);
2537                         goto rw_error;
2538                 }
2539                 bid = (bid >> 10) & 0xf;
2540                 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2541                 if (rc != 0) {
2542                         pr_err("error %d\n", rc);
2543                         goto rw_error;
2544                 }
2545
2546                 ext_attr->has_lna = true;
2547                 ext_attr->has_ntsc = false;
2548                 ext_attr->has_btsc = false;
2549                 ext_attr->has_oob = false;
2550                 ext_attr->has_smatx = true;
2551                 ext_attr->has_smarx = false;
2552                 ext_attr->has_gpio = false;
2553                 ext_attr->has_irqn = false;
2554                 break;
2555         case 0x33:
2556                 ext_attr->has_lna = false;
2557                 ext_attr->has_ntsc = false;
2558                 ext_attr->has_btsc = false;
2559                 ext_attr->has_oob = false;
2560                 ext_attr->has_smatx = true;
2561                 ext_attr->has_smarx = false;
2562                 ext_attr->has_gpio = false;
2563                 ext_attr->has_irqn = false;
2564                 break;
2565         case 0x45:
2566                 ext_attr->has_lna = true;
2567                 ext_attr->has_ntsc = true;
2568                 ext_attr->has_btsc = false;
2569                 ext_attr->has_oob = false;
2570                 ext_attr->has_smatx = true;
2571                 ext_attr->has_smarx = true;
2572                 ext_attr->has_gpio = true;
2573                 ext_attr->has_irqn = false;
2574                 break;
2575         case 0x46:
2576                 ext_attr->has_lna = false;
2577                 ext_attr->has_ntsc = true;
2578                 ext_attr->has_btsc = false;
2579                 ext_attr->has_oob = false;
2580                 ext_attr->has_smatx = true;
2581                 ext_attr->has_smarx = true;
2582                 ext_attr->has_gpio = true;
2583                 ext_attr->has_irqn = false;
2584                 break;
2585         case 0x41:
2586                 ext_attr->has_lna = true;
2587                 ext_attr->has_ntsc = true;
2588                 ext_attr->has_btsc = true;
2589                 ext_attr->has_oob = false;
2590                 ext_attr->has_smatx = true;
2591                 ext_attr->has_smarx = true;
2592                 ext_attr->has_gpio = true;
2593                 ext_attr->has_irqn = false;
2594                 break;
2595         case 0x43:
2596                 ext_attr->has_lna = false;
2597                 ext_attr->has_ntsc = true;
2598                 ext_attr->has_btsc = true;
2599                 ext_attr->has_oob = false;
2600                 ext_attr->has_smatx = true;
2601                 ext_attr->has_smarx = true;
2602                 ext_attr->has_gpio = true;
2603                 ext_attr->has_irqn = false;
2604                 break;
2605         case 0x32:
2606                 ext_attr->has_lna = true;
2607                 ext_attr->has_ntsc = false;
2608                 ext_attr->has_btsc = false;
2609                 ext_attr->has_oob = true;
2610                 ext_attr->has_smatx = true;
2611                 ext_attr->has_smarx = true;
2612                 ext_attr->has_gpio = true;
2613                 ext_attr->has_irqn = true;
2614                 break;
2615         case 0x34:
2616                 ext_attr->has_lna = false;
2617                 ext_attr->has_ntsc = true;
2618                 ext_attr->has_btsc = true;
2619                 ext_attr->has_oob = true;
2620                 ext_attr->has_smatx = true;
2621                 ext_attr->has_smarx = true;
2622                 ext_attr->has_gpio = true;
2623                 ext_attr->has_irqn = true;
2624                 break;
2625         case 0x42:
2626                 ext_attr->has_lna = true;
2627                 ext_attr->has_ntsc = true;
2628                 ext_attr->has_btsc = true;
2629                 ext_attr->has_oob = true;
2630                 ext_attr->has_smatx = true;
2631                 ext_attr->has_smarx = true;
2632                 ext_attr->has_gpio = true;
2633                 ext_attr->has_irqn = true;
2634                 break;
2635         case 0x44:
2636                 ext_attr->has_lna = false;
2637                 ext_attr->has_ntsc = true;
2638                 ext_attr->has_btsc = true;
2639                 ext_attr->has_oob = true;
2640                 ext_attr->has_smatx = true;
2641                 ext_attr->has_smarx = true;
2642                 ext_attr->has_gpio = true;
2643                 ext_attr->has_irqn = true;
2644                 break;
2645         default:
2646                 /* Unknown device variant */
2647                 return -EIO;
2648                 break;
2649         }
2650
2651         return 0;
2652 rw_error:
2653         return rc;
2654 }
2655
2656 /**
2657 * \fn int power_up_device()
2658 * \brief Power up device.
2659 * \param demod  Pointer to demodulator instance.
2660 * \return int.
2661 * \return 0    Success
2662 * \retval -EIO Failure, I2C or max retries reached
2663 *
2664 */
2665
2666 #ifndef DRXJ_MAX_RETRIES_POWERUP
2667 #define DRXJ_MAX_RETRIES_POWERUP 10
2668 #endif
2669
2670 static int power_up_device(struct drx_demod_instance *demod)
2671 {
2672         struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2673         u8 data = 0;
2674         u16 retry_count = 0;
2675         struct i2c_device_addr wake_up_addr;
2676
2677         dev_addr = demod->my_i2c_dev_addr;
2678         wake_up_addr.i2c_addr = DRXJ_WAKE_UP_KEY;
2679         wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id;
2680         wake_up_addr.user_data = dev_addr->user_data;
2681         /*
2682          * I2C access may fail in this case: no ack
2683          * dummy write must be used to wake uop device, dummy read must be used to
2684          * reset HI state machine (avoiding actual writes)
2685          */
2686         do {
2687                 data = 0;
2688                 drxbsp_i2c_write_read(&wake_up_addr, 1, &data,
2689                                       (struct i2c_device_addr *)(NULL), 0,
2690                                      (u8 *)(NULL));
2691                 msleep(10);
2692                 retry_count++;
2693         } while ((drxbsp_i2c_write_read
2694                   ((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1,
2695                    &data)
2696                   != 0) && (retry_count < DRXJ_MAX_RETRIES_POWERUP));
2697
2698         /* Need some recovery time .... */
2699         msleep(10);
2700
2701         if (retry_count == DRXJ_MAX_RETRIES_POWERUP)
2702                 return -EIO;
2703
2704         return 0;
2705 }
2706
2707 /*----------------------------------------------------------------------------*/
2708 /* MPEG Output Configuration Functions - begin                                */
2709 /*----------------------------------------------------------------------------*/
2710 /**
2711 * \fn int ctrl_set_cfg_mpeg_output()
2712 * \brief Set MPEG output configuration of the device.
2713 * \param devmod  Pointer to demodulator instance.
2714 * \param cfg_data Pointer to mpeg output configuaration.
2715 * \return int.
2716 *
2717 *  Configure MPEG output parameters.
2718 *
2719 */
2720 static int
2721 ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data)
2722 {
2723         struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2724         struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2725         struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2726         int rc;
2727         u16 fec_oc_reg_mode = 0;
2728         u16 fec_oc_reg_ipr_mode = 0;
2729         u16 fec_oc_reg_ipr_invert = 0;
2730         u32 max_bit_rate = 0;
2731         u32 rcn_rate = 0;
2732         u32 nr_bits = 0;
2733         u16 sio_pdr_md_cfg = 0;
2734         /* data mask for the output data byte */
2735         u16 invert_data_mask =
2736             FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2737             FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2738             FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2739             FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2740
2741         /* check arguments */
2742         if ((demod == NULL) || (cfg_data == NULL))
2743                 return -EINVAL;
2744
2745         dev_addr = demod->my_i2c_dev_addr;
2746         ext_attr = (struct drxj_data *) demod->my_ext_attr;
2747         common_attr = (struct drx_common_attr *) demod->my_common_attr;
2748
2749         if (cfg_data->enable_mpeg_output == true) {
2750                 /* quick and dirty patch to set MPEG incase current std is not
2751                    producing MPEG */
2752                 switch (ext_attr->standard) {
2753                 case DRX_STANDARD_8VSB:
2754                 case DRX_STANDARD_ITU_A:
2755                 case DRX_STANDARD_ITU_B:
2756                 case DRX_STANDARD_ITU_C:
2757                         break;
2758                 default:
2759                         return 0;
2760                 }
2761
2762                 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0);
2763                 if (rc != 0) {
2764                         pr_err("error %d\n", rc);
2765                         goto rw_error;
2766                 }
2767                 switch (ext_attr->standard) {
2768                 case DRX_STANDARD_8VSB:
2769                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0);
2770                         if (rc != 0) {
2771                                 pr_err("error %d\n", rc);
2772                                 goto rw_error;
2773                         }       /* 2048 bytes fifo ram */
2774                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0);
2775                         if (rc != 0) {
2776                                 pr_err("error %d\n", rc);
2777                                 goto rw_error;
2778                         }
2779                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0);
2780                         if (rc != 0) {
2781                                 pr_err("error %d\n", rc);
2782                                 goto rw_error;
2783                         }
2784                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0);
2785                         if (rc != 0) {
2786                                 pr_err("error %d\n", rc);
2787                                 goto rw_error;
2788                         }
2789                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0);
2790                         if (rc != 0) {
2791                                 pr_err("error %d\n", rc);
2792                                 goto rw_error;
2793                         }
2794                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0);
2795                         if (rc != 0) {
2796                                 pr_err("error %d\n", rc);
2797                                 goto rw_error;
2798                         }
2799                         /* Low Water Mark for synchronization  */
2800                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0);
2801                         if (rc != 0) {
2802                                 pr_err("error %d\n", rc);
2803                                 goto rw_error;
2804                         }
2805                         /* High Water Mark for synchronization */
2806                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0);
2807                         if (rc != 0) {
2808                                 pr_err("error %d\n", rc);
2809                                 goto rw_error;
2810                         }
2811                         break;
2812                 case DRX_STANDARD_ITU_A:
2813                 case DRX_STANDARD_ITU_C:
2814                         switch (ext_attr->constellation) {
2815                         case DRX_CONSTELLATION_QAM256:
2816                                 nr_bits = 8;
2817                                 break;
2818                         case DRX_CONSTELLATION_QAM128:
2819                                 nr_bits = 7;
2820                                 break;
2821                         case DRX_CONSTELLATION_QAM64:
2822                                 nr_bits = 6;
2823                                 break;
2824                         case DRX_CONSTELLATION_QAM32:
2825                                 nr_bits = 5;
2826                                 break;
2827                         case DRX_CONSTELLATION_QAM16:
2828                                 nr_bits = 4;
2829                                 break;
2830                         default:
2831                                 return -EIO;
2832                         }       /* ext_attr->constellation */
2833                         /* max_bit_rate = symbol_rate * nr_bits * coef */
2834                         /* coef = 188/204                          */
2835                         max_bit_rate =
2836                             (ext_attr->curr_symbol_rate / 8) * nr_bits * 188;
2837                         /* pass through b/c Annex A/c need following settings */
2838                 case DRX_STANDARD_ITU_B:
2839                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);
2840                         if (rc != 0) {
2841                                 pr_err("error %d\n", rc);
2842                                 goto rw_error;
2843                         }
2844                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0);
2845                         if (rc != 0) {
2846                                 pr_err("error %d\n", rc);
2847                                 goto rw_error;
2848                         }
2849                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0);
2850                         if (rc != 0) {
2851                                 pr_err("error %d\n", rc);
2852                                 goto rw_error;
2853                         }
2854                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0);
2855                         if (rc != 0) {
2856                                 pr_err("error %d\n", rc);
2857                                 goto rw_error;
2858                         }
2859                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0);
2860                         if (rc != 0) {
2861                                 pr_err("error %d\n", rc);
2862                                 goto rw_error;
2863                         }
2864                         if (cfg_data->static_clk == true) {
2865                                 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0);
2866                                 if (rc != 0) {
2867                                         pr_err("error %d\n", rc);
2868                                         goto rw_error;
2869                                 }
2870                         } else {
2871                                 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0);
2872                                 if (rc != 0) {
2873                                         pr_err("error %d\n", rc);
2874                                         goto rw_error;
2875                                 }
2876                         }
2877                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0);
2878                         if (rc != 0) {
2879                                 pr_err("error %d\n", rc);
2880                                 goto rw_error;
2881                         }
2882                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0);
2883                         if (rc != 0) {
2884                                 pr_err("error %d\n", rc);
2885                                 goto rw_error;
2886                         }
2887                         break;
2888                 default:
2889                         break;
2890                 }               /* swtich (standard) */
2891
2892                 /* Check insertion of the Reed-Solomon parity bytes */
2893                 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
2894                 if (rc != 0) {
2895                         pr_err("error %d\n", rc);
2896                         goto rw_error;
2897                 }
2898                 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0);
2899                 if (rc != 0) {
2900                         pr_err("error %d\n", rc);
2901                         goto rw_error;
2902                 }
2903                 if (cfg_data->insert_rs_byte == true) {
2904                         /* enable parity symbol forward */
2905                         fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
2906                         /* MVAL disable during parity bytes */
2907                         fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2908                         switch (ext_attr->standard) {
2909                         case DRX_STANDARD_8VSB:
2910                                 rcn_rate = 0x004854D3;
2911                                 break;
2912                         case DRX_STANDARD_ITU_B:
2913                                 fec_oc_reg_mode |= FEC_OC_MODE_TRANSPARENT__M;
2914                                 switch (ext_attr->constellation) {
2915                                 case DRX_CONSTELLATION_QAM256:
2916                                         rcn_rate = 0x008945E7;
2917                                         break;
2918                                 case DRX_CONSTELLATION_QAM64:
2919                                         rcn_rate = 0x005F64D4;
2920                                         break;
2921                                 default:
2922                                         return -EIO;
2923                                 }
2924                                 break;
2925                         case DRX_STANDARD_ITU_A:
2926                         case DRX_STANDARD_ITU_C:
2927                                 /* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */
2928                                 rcn_rate =
2929                                     (frac28
2930                                      (max_bit_rate,
2931                                       (u32) (common_attr->sys_clock_freq / 8))) /
2932                                     188;
2933                                 break;
2934                         default:
2935                                 return -EIO;
2936                         }       /* ext_attr->standard */
2937                 } else {        /* insert_rs_byte == false */
2938
2939                         /* disable parity symbol forward */
2940                         fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
2941                         /* MVAL enable during parity bytes */
2942                         fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2943                         switch (ext_attr->standard) {
2944                         case DRX_STANDARD_8VSB:
2945                                 rcn_rate = 0x0041605C;
2946                                 break;
2947                         case DRX_STANDARD_ITU_B:
2948                                 fec_oc_reg_mode &= (~FEC_OC_MODE_TRANSPARENT__M);
2949                                 switch (ext_attr->constellation) {
2950                                 case DRX_CONSTELLATION_QAM256:
2951                                         rcn_rate = 0x0082D6A0;
2952                                         break;
2953                                 case DRX_CONSTELLATION_QAM64:
2954                                         rcn_rate = 0x005AEC1A;
2955                                         break;
2956                                 default:
2957                                         return -EIO;
2958                                 }
2959                                 break;
2960                         case DRX_STANDARD_ITU_A:
2961                         case DRX_STANDARD_ITU_C:
2962                                 /* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */
2963                                 rcn_rate =
2964                                     (frac28
2965                                      (max_bit_rate,
2966                                       (u32) (common_attr->sys_clock_freq / 8))) /
2967                                     204;
2968                                 break;
2969                         default:
2970                                 return -EIO;
2971                         }       /* ext_attr->standard */
2972                 }
2973
2974                 if (cfg_data->enable_parallel == true) {        /* MPEG data output is paralel -> clear ipr_mode[0] */
2975                         fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2976                 } else {        /* MPEG data output is serial -> set ipr_mode[0] */
2977                         fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2978                 }
2979
2980                 /* Control slective inversion of output bits */
2981                 if (cfg_data->invert_data == true)
2982                         fec_oc_reg_ipr_invert |= invert_data_mask;
2983                 else
2984                         fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2985
2986                 if (cfg_data->invert_err == true)
2987                         fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2988                 else
2989                         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2990
2991                 if (cfg_data->invert_str == true)
2992                         fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2993                 else
2994                         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2995
2996                 if (cfg_data->invert_val == true)
2997                         fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
2998                 else
2999                         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
3000
3001                 if (cfg_data->invert_clk == true)
3002                         fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
3003                 else
3004                         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
3005
3006
3007                 if (cfg_data->static_clk == true) {     /* Static mode */
3008                         u32 dto_rate = 0;
3009                         u32 bit_rate = 0;
3010                         u16 fec_oc_dto_burst_len = 0;
3011                         u16 fec_oc_dto_period = 0;
3012
3013                         fec_oc_dto_burst_len = FEC_OC_DTO_BURST_LEN__PRE;
3014
3015                         switch (ext_attr->standard) {
3016                         case DRX_STANDARD_8VSB:
3017                                 fec_oc_dto_period = 4;
3018                                 if (cfg_data->insert_rs_byte == true)
3019                                         fec_oc_dto_burst_len = 208;
3020                                 break;
3021                         case DRX_STANDARD_ITU_A:
3022                                 {
3023                                         u32 symbol_rate_th = 6400000;
3024                                         if (cfg_data->insert_rs_byte == true) {
3025                                                 fec_oc_dto_burst_len = 204;
3026                                                 symbol_rate_th = 5900000;
3027                                         }
3028                                         if (ext_attr->curr_symbol_rate >=
3029                                             symbol_rate_th) {
3030                                                 fec_oc_dto_period = 0;
3031                                         } else {
3032                                                 fec_oc_dto_period = 1;
3033                                         }
3034                                 }
3035                                 break;
3036                         case DRX_STANDARD_ITU_B:
3037                                 fec_oc_dto_period = 1;
3038                                 if (cfg_data->insert_rs_byte == true)
3039                                         fec_oc_dto_burst_len = 128;
3040                                 break;
3041                         case DRX_STANDARD_ITU_C:
3042                                 fec_oc_dto_period = 1;
3043                                 if (cfg_data->insert_rs_byte == true)
3044                                         fec_oc_dto_burst_len = 204;
3045                                 break;
3046                         default:
3047                                 return -EIO;
3048                         }
3049                         bit_rate =
3050                             common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period +
3051                                                                2);
3052                         dto_rate =
3053                             frac28(bit_rate, common_attr->sys_clock_freq * 1000);
3054                         dto_rate >>= 3;
3055                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0);
3056                         if (rc != 0) {
3057                                 pr_err("error %d\n", rc);
3058                                 goto rw_error;
3059                         }
3060                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0);
3061                         if (rc != 0) {
3062                                 pr_err("error %d\n", rc);
3063                                 goto rw_error;
3064                         }
3065                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0);
3066                         if (rc != 0) {
3067                                 pr_err("error %d\n", rc);
3068                                 goto rw_error;
3069                         }
3070                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0);
3071                         if (rc != 0) {
3072                                 pr_err("error %d\n", rc);
3073                                 goto rw_error;
3074                         }
3075                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0);
3076                         if (rc != 0) {
3077                                 pr_err("error %d\n", rc);
3078                                 goto rw_error;
3079                         }
3080                         if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO)
3081                                 fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1;
3082                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0);
3083                         if (rc != 0) {
3084                                 pr_err("error %d\n", rc);
3085                                 goto rw_error;
3086                         }
3087                 } else {        /* Dynamic mode */
3088
3089                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0);
3090                         if (rc != 0) {
3091                                 pr_err("error %d\n", rc);
3092                                 goto rw_error;
3093                         }
3094                         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0);
3095                         if (rc != 0) {
3096                                 pr_err("error %d\n", rc);
3097                                 goto rw_error;
3098                         }
3099                 }
3100
3101                 rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0);
3102                 if (rc != 0) {
3103                         pr_err("error %d\n", rc);
3104                         goto rw_error;
3105                 }
3106
3107                 /* Write appropriate registers with requested configuration */
3108                 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0);
3109                 if (rc != 0) {
3110                         pr_err("error %d\n", rc);
3111                         goto rw_error;
3112                 }
3113                 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0);
3114                 if (rc != 0) {
3115                         pr_err("error %d\n", rc);
3116                         goto rw_error;
3117                 }
3118                 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0);
3119                 if (rc != 0) {
3120                         pr_err("error %d\n", rc);
3121                         goto rw_error;
3122                 }
3123
3124                 /* enabling for both parallel and serial now */
3125                 /*  Write magic word to enable pdr reg write */
3126                 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3127                 if (rc != 0) {
3128                         pr_err("error %d\n", rc);
3129                         goto rw_error;
3130                 }
3131                 /*  Set MPEG TS pads to outputmode */
3132                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0);
3133                 if (rc != 0) {
3134                         pr_err("error %d\n", rc);
3135                         goto rw_error;
3136                 }
3137                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0);
3138                 if (rc != 0) {
3139                         pr_err("error %d\n", rc);
3140                         goto rw_error;
3141                 }
3142                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0);
3143                 if (rc != 0) {
3144                         pr_err("error %d\n", rc);
3145                         goto rw_error;
3146                 }
3147                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0);
3148                 if (rc != 0) {
3149                         pr_err("error %d\n", rc);
3150                         goto rw_error;
3151                 }
3152                 sio_pdr_md_cfg =
3153                     MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH <<
3154                     SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B;
3155                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3156                 if (rc != 0) {
3157                         pr_err("error %d\n", rc);
3158                         goto rw_error;
3159                 }
3160                 if (cfg_data->enable_parallel == true) {        /* MPEG data output is paralel -> set MD1 to MD7 to output mode */
3161                         sio_pdr_md_cfg =
3162                             MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH <<
3163                             SIO_PDR_MD0_CFG_DRIVE__B | 0x03 <<
3164                             SIO_PDR_MD0_CFG_MODE__B;
3165                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3166                         if (rc != 0) {
3167                                 pr_err("error %d\n", rc);
3168                                 goto rw_error;
3169                         }
3170                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0);
3171                         if (rc != 0) {
3172                                 pr_err("error %d\n", rc);
3173                                 goto rw_error;
3174                         }
3175                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0);
3176                         if (rc != 0) {
3177                                 pr_err("error %d\n", rc);
3178                                 goto rw_error;
3179                         }
3180                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0);
3181                         if (rc != 0) {
3182                                 pr_err("error %d\n", rc);
3183                                 goto rw_error;
3184                         }
3185                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0);
3186                         if (rc != 0) {
3187                                 pr_err("error %d\n", rc);
3188                                 goto rw_error;
3189                         }
3190                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0);
3191                         if (rc != 0) {
3192                                 pr_err("error %d\n", rc);
3193                                 goto rw_error;
3194                         }
3195                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0);
3196                         if (rc != 0) {
3197                                 pr_err("error %d\n", rc);
3198                                 goto rw_error;
3199                         }
3200                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0);
3201                         if (rc != 0) {
3202                                 pr_err("error %d\n", rc);
3203                                 goto rw_error;
3204                         }
3205                 } else {        /* MPEG data output is serial -> set MD1 to MD7 to tri-state */
3206                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3207                         if (rc != 0) {
3208                                 pr_err("error %d\n", rc);
3209                                 goto rw_error;
3210                         }
3211                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3212                         if (rc != 0) {
3213                                 pr_err("error %d\n", rc);
3214                                 goto rw_error;
3215                         }
3216                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3217                         if (rc != 0) {
3218                                 pr_err("error %d\n", rc);
3219                                 goto rw_error;
3220                         }
3221                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3222                         if (rc != 0) {
3223                                 pr_err("error %d\n", rc);
3224                                 goto rw_error;
3225                         }
3226                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3227                         if (rc != 0) {
3228                                 pr_err("error %d\n", rc);
3229                                 goto rw_error;
3230                         }
3231                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3232                         if (rc != 0) {
3233                                 pr_err("error %d\n", rc);
3234                                 goto rw_error;
3235                         }
3236                         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3237                         if (rc != 0) {
3238                                 pr_err("error %d\n", rc);
3239                                 goto rw_error;
3240                         }
3241                 }
3242                 /*  Enable Monitor Bus output over MPEG pads and ctl input */
3243                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3244                 if (rc != 0) {
3245                         pr_err("error %d\n", rc);
3246                         goto rw_error;
3247                 }
3248                 /*  Write nomagic word to enable pdr reg write */
3249                 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3250                 if (rc != 0) {
3251                         pr_err("error %d\n", rc);
3252                         goto rw_error;
3253                 }
3254         } else {
3255                 /*  Write magic word to enable pdr reg write */
3256                 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3257                 if (rc != 0) {
3258                         pr_err("error %d\n", rc);
3259                         goto rw_error;
3260                 }
3261                 /*  Set MPEG TS pads to inputmode */
3262                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0);
3263                 if (rc != 0) {
3264                         pr_err("error %d\n", rc);
3265                         goto rw_error;
3266                 }
3267                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0);
3268                 if (rc != 0) {
3269                         pr_err("error %d\n", rc);
3270                         goto rw_error;
3271                 }
3272                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0);
3273                 if (rc != 0) {
3274                         pr_err("error %d\n", rc);
3275                         goto rw_error;
3276                 }
3277                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0);
3278                 if (rc != 0) {
3279                         pr_err("error %d\n", rc);
3280                         goto rw_error;
3281                 }
3282                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0);
3283                 if (rc != 0) {
3284                         pr_err("error %d\n", rc);
3285                         goto rw_error;
3286                 }
3287                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3288                 if (rc != 0) {
3289                         pr_err("error %d\n", rc);
3290                         goto rw_error;
3291                 }
3292                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3293                 if (rc != 0) {
3294                         pr_err("error %d\n", rc);
3295                         goto rw_error;
3296                 }
3297                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3298                 if (rc != 0) {
3299                         pr_err("error %d\n", rc);
3300                         goto rw_error;
3301                 }
3302                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3303                 if (rc != 0) {
3304                         pr_err("error %d\n", rc);
3305                         goto rw_error;
3306                 }
3307                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3308                 if (rc != 0) {
3309                         pr_err("error %d\n", rc);
3310                         goto rw_error;
3311                 }
3312                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3313                 if (rc != 0) {
3314                         pr_err("error %d\n", rc);
3315                         goto rw_error;
3316                 }
3317                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3318                 if (rc != 0) {
3319                         pr_err("error %d\n", rc);
3320                         goto rw_error;
3321                 }
3322                 /* Enable Monitor Bus output over MPEG pads and ctl input */
3323                 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3324                 if (rc != 0) {
3325                         pr_err("error %d\n", rc);
3326                         goto rw_error;
3327                 }
3328                 /* Write nomagic word to enable pdr reg write */
3329                 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3330                 if (rc != 0) {
3331                         pr_err("error %d\n", rc);
3332                         goto rw_error;
3333                 }
3334         }
3335
3336         /* save values for restore after re-acquire */
3337         common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output;
3338
3339         return 0;
3340 rw_error:
3341         return rc;
3342 }
3343
3344 /*----------------------------------------------------------------------------*/
3345
3346
3347 /*----------------------------------------------------------------------------*/
3348 /* MPEG Output Configuration Functions - end                                  */
3349 /*----------------------------------------------------------------------------*/
3350
3351 /*----------------------------------------------------------------------------*/
3352 /* miscellaneous configuartions - begin                           */
3353 /*----------------------------------------------------------------------------*/
3354
3355 /**
3356 * \fn int set_mpegtei_handling()
3357 * \brief Activate MPEG TEI handling settings.
3358 * \param devmod  Pointer to demodulator instance.
3359 * \return int.
3360 *
3361 * This routine should be called during a set channel of QAM/VSB
3362 *
3363 */
3364 static int set_mpegtei_handling(struct drx_demod_instance *demod)
3365 {
3366         struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3367         struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3368         int rc;
3369         u16 fec_oc_dpr_mode = 0;
3370         u16 fec_oc_snc_mode = 0;
3371         u16 fec_oc_ems_mode = 0;
3372
3373         dev_addr = demod->my_i2c_dev_addr;
3374         ext_attr = (struct drxj_data *) demod->my_ext_attr;
3375
3376         rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0);
3377         if (rc != 0) {
3378                 pr_err("error %d\n", rc);
3379                 goto rw_error;
3380         }
3381         rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
3382         if (rc != 0) {
3383                 pr_err("error %d\n", rc);
3384                 goto rw_error;
3385         }
3386         rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0);
3387         if (rc != 0) {
3388                 pr_err("error %d\n", rc);
3389                 goto rw_error;
3390         }
3391
3392         /* reset to default, allow TEI bit to be changed */
3393         fec_oc_dpr_mode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M);
3394         fec_oc_snc_mode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M |
3395                            FEC_OC_SNC_MODE_CORR_DISABLE__M));
3396         fec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M);
3397
3398         if (ext_attr->disable_te_ihandling) {
3399                 /* do not change TEI bit */
3400                 fec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M;
3401                 fec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M |
3402                     ((0x2) << (FEC_OC_SNC_MODE_ERROR_CTL__B));
3403                 fec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B));
3404         }
3405
3406         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0);
3407         if (rc != 0) {
3408                 pr_err("error %d\n", rc);
3409                 goto rw_error;
3410         }
3411         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0);
3412         if (rc != 0) {
3413                 pr_err("error %d\n", rc);
3414                 goto rw_error;
3415         }
3416         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0);
3417         if (rc != 0) {
3418                 pr_err("error %d\n", rc);
3419                 goto rw_error;
3420         }
3421
3422         return 0;
3423 rw_error:
3424         return rc;
3425 }
3426
3427 /*----------------------------------------------------------------------------*/
3428 /**
3429 * \fn int bit_reverse_mpeg_output()
3430 * \brief Set MPEG output bit-endian settings.
3431 * \param devmod  Pointer to demodulator instance.
3432 * \return int.
3433 *
3434 * This routine should be called during a set channel of QAM/VSB
3435 *
3436 */
3437 static int bit_reverse_mpeg_output(struct drx_demod_instance *demod)
3438 {
3439         struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3440         struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3441         int rc;
3442         u16 fec_oc_ipr_mode = 0;
3443
3444         dev_addr = demod->my_i2c_dev_addr;
3445         ext_attr = (struct drxj_data *) demod->my_ext_attr;
3446
3447         rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0);
3448         if (rc != 0) {
3449                 pr_err("error %d\n", rc);
3450                 goto rw_error;
3451         }
3452
3453         /* reset to default (normal bit order) */
3454         fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M);
3455
3456         if (ext_attr->bit_reverse_mpeg_outout)
3457                 fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M;
3458
3459         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0);
3460         if (rc != 0) {
3461                 pr_err("error %d\n", rc);
3462                 goto rw_error;
3463         }
3464
3465         return 0;
3466 rw_error:
3467         return rc;
3468 }
3469
3470 /*----------------------------------------------------------------------------*/
3471 /**
3472 * \fn int set_mpeg_start_width()
3473 * \brief Set MPEG start width.
3474 * \param devmod  Pointer to demodulator instance.
3475 * \return int.
3476 *
3477 * This routine should be called during a set channel of QAM/VSB
3478 *
3479 */
3480 static int set_mpeg_start_width(struct drx_demod_instance *demod)
3481 {
3482         struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3483         struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3484         struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
3485         int rc;
3486         u16 fec_oc_comm_mb = 0;
3487
3488         dev_addr = demod->my_i2c_dev_addr;
3489         ext_attr = (struct drxj_data *) demod->my_ext_attr;
3490         common_attr = demod->my_common_attr;
3491
3492         if ((common_attr->mpeg_cfg.static_clk == true)
3493             && (common_attr->mpeg_cfg.enable_parallel == false)) {
3494                 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0);
3495                 if (rc != 0) {
3496                         pr_err("error %d\n", rc);
3497                         goto rw_error;
3498                 }
3499                 fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON;
3500                 if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC)
3501                         fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON;
3502                 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0);
3503                 if (rc != 0) {
3504                         pr_err("error %d\n", rc);
3505                         goto rw_error;
3506                 }
3507         }
3508
3509         return 0;
3510 rw_error:
3511         return rc;
3512 }
3513
3514 /*----------------------------------------------------------------------------*/
3515 /* miscellaneous configuartions - end                             */
3516 /*----------------------------------------------------------------------------*/
3517
3518 /*----------------------------------------------------------------------------*/
3519 /* UIO Configuration Functions - begin                                        */
3520 /*----------------------------------------------------------------------------*/
3521 /**
3522 * \fn int ctrl_set_uio_cfg()
3523 * \brief Configure modus oprandi UIO.
3524 * \param demod Pointer to demodulator instance.
3525 * \param uio_cfg Pointer to a configuration setting for a certain UIO.
3526 * \return int.
3527 */
3528 static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg)
3529 {
3530         struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3531         int rc;
3532
3533         if ((uio_cfg == NULL) || (demod == NULL))
3534                 return -EINVAL;
3535
3536         ext_attr = (struct drxj_data *) demod->my_ext_attr;
3537
3538         /*  Write magic word to enable pdr reg write               */
3539         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3540         if (rc != 0) {
3541                 pr_err("error %d\n", rc);
3542                 goto rw_error;
3543         }
3544         switch (uio_cfg->uio) {
3545       /*====================================================================*/
3546         case DRX_UIO1:
3547                 /* DRX_UIO1: SMA_TX UIO-1 */
3548                 if (!ext_attr->has_smatx)
3549                         return -EIO;
3550                 switch (uio_cfg->mode) {
3551                 case DRX_UIO_MODE_FIRMWARE_SMA: /* falltrough */
3552                 case DRX_UIO_MODE_FIRMWARE_SAW: /* falltrough */
3553                 case DRX_UIO_MODE_READWRITE:
3554                         ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3555                         break;
3556                 case DRX_UIO_MODE_DISABLE:
3557                         ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3558                         /* pad configuration register is set 0 - input mode */
3559                         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0);
3560                         if (rc != 0) {
3561                                 pr_err("error %d\n", rc);
3562                                 goto rw_error;
3563                         }
3564                         break;
3565                 default:
3566                         return -EINVAL;
3567                 }               /* switch ( uio_cfg->mode ) */
3568                 break;
3569       /*====================================================================*/
3570         case DRX_UIO2:
3571                 /* DRX_UIO2: SMA_RX UIO-2 */
3572                 if (!ext_attr->has_smarx)
3573                         return -EIO;
3574                 switch (uio_cfg->mode) {
3575                 case DRX_UIO_MODE_FIRMWARE0:    /* falltrough */
3576                 case DRX_UIO_MODE_READWRITE:
3577                         ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3578                         break;
3579                 case DRX_UIO_MODE_DISABLE:
3580                         ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3581                         /* pad configuration register is set 0 - input mode */
3582                         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0);
3583                         if (rc != 0) {
3584                                 pr_err("error %d\n", rc);
3585                                 goto rw_error;
3586                         }
3587                         break;
3588                 default:
3589                         return -EINVAL;
3590                         break;
3591                 }               /* switch ( uio_cfg->mode ) */
3592                 break;
3593       /*====================================================================*/
3594         case DRX_UIO3:
3595                 /* DRX_UIO3: GPIO UIO-3 */
3596                 if (!ext_attr->has_gpio)
3597                         return -EIO;
3598                 switch (uio_cfg->mode) {
3599                 case DRX_UIO_MODE_FIRMWARE0:    /* falltrough */
3600                 case DRX_UIO_MODE_READWRITE:
3601                         ext_attr->uio_gpio_mode = uio_cfg->mode;
3602                         break;
3603                 case DRX_UIO_MODE_DISABLE:
3604                         ext_attr->uio_gpio_mode = uio_cfg->mode;
3605                         /* pad configuration register is set 0 - input mode */
3606                         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0);
3607                         if (rc != 0) {
3608                                 pr_err("error %d\n", rc);
3609                                 goto rw_error;
3610                         }
3611                         break;
3612                 default:
3613                         return -EINVAL;
3614                         break;
3615                 }               /* switch ( uio_cfg->mode ) */
3616                 break;
3617       /*====================================================================*/
3618         case DRX_UIO4:
3619                 /* DRX_UIO4: IRQN UIO-4 */
3620                 if (!ext_attr->has_irqn)
3621                         return -EIO;
3622                 switch (uio_cfg->mode) {
3623                 case DRX_UIO_MODE_READWRITE:
3624                         ext_attr->uio_irqn_mode = uio_cfg->mode;
3625                         break;
3626                 case DRX_UIO_MODE_DISABLE:
3627                         /* pad configuration register is set 0 - input mode */
3628                         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0);
3629                         if (rc != 0) {
3630                                 pr_err("error %d\n", rc);
3631                                 goto rw_error;
3632                         }
3633                         ext_attr->uio_irqn_mode = uio_cfg->mode;
3634                         break;
3635                 case DRX_UIO_MODE_FIRMWARE0:    /* falltrough */
3636                 default:
3637                         return -EINVAL;
3638                         break;
3639                 }               /* switch ( uio_cfg->mode ) */
3640                 break;
3641       /*====================================================================*/
3642         default:
3643                 return -EINVAL;
3644         }                       /* switch ( uio_cfg->uio ) */
3645
3646         /*  Write magic word to disable pdr reg write               */
3647         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3648         if (rc != 0) {
3649                 pr_err("error %d\n", rc);
3650                 goto rw_error;
3651         }
3652
3653         return 0;
3654 rw_error:
3655         return rc;
3656 }
3657
3658 /**
3659 * \fn int ctrl_uio_write()
3660 * \brief Write to a UIO.
3661 * \param demod Pointer to demodulator instance.
3662 * \param uio_data Pointer to data container for a certain UIO.
3663 * \return int.
3664 */
3665 static int
3666 ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data)
3667 {
3668         struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3669         int rc;
3670         u16 pin_cfg_value = 0;
3671         u16 value = 0;
3672
3673         if ((uio_data == NULL) || (demod == NULL))
3674                 return -EINVAL;
3675
3676         ext_attr = (struct drxj_data *) demod->my_ext_attr;
3677
3678         /*  Write magic word to enable pdr reg write               */
3679         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3680         if (rc != 0) {
3681                 pr_err("error %d\n", rc);
3682                 goto rw_error;
3683         }
3684         switch (uio_data->uio) {
3685       /*====================================================================*/
3686         case DRX_UIO1:
3687                 /* DRX_UIO1: SMA_TX UIO-1 */
3688                 if (!ext_attr->has_smatx)
3689                         return -EIO;
3690                 if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE)
3691                     && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) {
3692                         return -EIO;
3693                 }
3694                 pin_cfg_value = 0;
3695                 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3696                 pin_cfg_value |= 0x0113;
3697                 /* io_pad_cfg_mode output mode is drive always */
3698                 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3699
3700                 /* write to io pad configuration register - output mode */
3701                 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);
3702                 if (rc != 0) {
3703                         pr_err("error %d\n", rc);
3704                         goto rw_error;
3705                 }
3706
3707                 /* use corresponding bit in io data output registar */
3708                 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3709                 if (rc != 0) {
3710                         pr_err("error %d\n", rc);
3711                         goto rw_error;
3712                 }
3713                 if (!uio_data->value)
3714                         value &= 0x7FFF;        /* write zero to 15th bit - 1st UIO */
3715                 else
3716                         value |= 0x8000;        /* write one to 15th bit - 1st UIO */
3717
3718                 /* write back to io data output register */
3719                 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3720                 if (rc != 0) {
3721                         pr_err("error %d\n", rc);
3722                         goto rw_error;
3723                 }
3724                 break;
3725    /*======================================================================*/
3726         case DRX_UIO2:
3727                 /* DRX_UIO2: SMA_RX UIO-2 */
3728                 if (!ext_attr->has_smarx)
3729                         return -EIO;
3730                 if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE)
3731                         return -EIO;
3732
3733                 pin_cfg_value = 0;
3734                 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3735                 pin_cfg_value |= 0x0113;
3736                 /* io_pad_cfg_mode output mode is drive always */
3737                 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3738
3739                 /* write to io pad configuration register - output mode */
3740                 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);
3741                 if (rc != 0) {
3742                         pr_err("error %d\n", rc);
3743                         goto rw_error;
3744                 }
3745
3746                 /* use corresponding bit in io data output registar */
3747                 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3748                 if (rc != 0) {
3749                         pr_err("error %d\n", rc);
3750                         goto rw_error;
3751                 }
3752                 if (!uio_data->value)
3753                         value &= 0xBFFF;        /* write zero to 14th bit - 2nd UIO */
3754                 else
3755                         value |= 0x4000;        /* write one to 14th bit - 2nd UIO */
3756
3757                 /* write back to io data output register */
3758                 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3759                 if (rc != 0) {
3760                         pr_err("error %d\n", rc);
3761                         goto rw_error;
3762                 }
3763                 break;
3764    /*====================================================================*/
3765         case DRX_UIO3:
3766                 /* DRX_UIO3: ASEL UIO-3 */
3767                 if (!ext_attr->has_gpio)
3768                         return -EIO;
3769                 if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE)
3770                         return -EIO;
3771
3772                 pin_cfg_value = 0;
3773                 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3774                 pin_cfg_value |= 0x0113;
3775                 /* io_pad_cfg_mode output mode is drive always */
3776                 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3777
3778                 /* write to io pad configuration register - output mode */
3779                 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0);
3780                 if (rc != 0) {
3781                         pr_err("error %d\n", rc);
3782                         goto rw_error;
3783                 }
3784
3785                 /* use corresponding bit in io data output registar */
3786                 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0);
3787                 if (rc != 0) {
3788                         pr_err("error %d\n", rc);
3789                         goto rw_error;
3790                 }
3791                 if (!uio_data->value)
3792                         value &= 0xFFFB;        /* write zero to 2nd bit - 3rd UIO */
3793                 else
3794                         value |= 0x0004;        /* write one to 2nd bit - 3rd UIO */
3795
3796                 /* write back to io data output register */
3797                 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0);
3798                 if (rc != 0) {
3799                         pr_err("error %d\n", rc);
3800                         goto rw_error;
3801                 }
3802                 break;
3803    /*=====================================================================*/
3804         case DRX_UIO4:
3805                 /* DRX_UIO4: IRQN UIO-4 */
3806                 if (!ext_attr->has_irqn)
3807                         return -EIO;
3808
3809                 if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE)
3810                         return -EIO;
3811
3812                 pin_cfg_value = 0;
3813                 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3814                 pin_cfg_value |= 0x0113;
3815                 /* io_pad_cfg_mode output mode is drive always */
3816                 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3817
3818                 /* write to io pad configuration register - output mode */
3819                 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0);
3820                 if (rc != 0) {
3821                         pr_err("error %d\n", rc);
3822                         goto rw_error;
3823                 }
3824
3825                 /* use corresponding bit in io data output registar */
3826                 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3827                 if (rc != 0) {
3828                         pr_err("error %d\n", rc);
3829                         goto rw_error;
3830                 }
3831                 if (uio_data->value == false)
3832                         value &= 0xEFFF;        /* write zero to 12th bit - 4th UIO */
3833                 else
3834                         value |= 0x1000;        /* write one to 12th bit - 4th UIO */
3835
3836                 /* write back to io data output register */
3837                 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3838                 if (rc != 0) {
3839                         pr_err("error %d\n", rc);
3840                         goto rw_error;
3841                 }
3842                 break;
3843       /*=====================================================================*/
3844         default:
3845                 return -EINVAL;
3846         }                       /* switch ( uio_data->uio ) */
3847
3848         /*  Write magic word to disable pdr reg write               */
3849         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3850         if (rc != 0) {
3851                 pr_err("error %d\n", rc);
3852                 goto rw_error;
3853         }
3854
3855         return 0;
3856 rw_error:
3857         return rc;
3858 }
3859
3860 /*---------------------------------------------------------------------------*/
3861 /* UIO Configuration Functions - end                                         */
3862 /*---------------------------------------------------------------------------*/
3863
3864 /*----------------------------------------------------------------------------*/
3865 /* I2C Bridge Functions - begin                                               */
3866 /*----------------------------------------------------------------------------*/
3867 /**
3868 * \fn int ctrl_i2c_bridge()
3869 * \brief Open or close the I2C switch to tuner.
3870 * \param demod Pointer to demodulator instance.
3871 * \param bridge_closed Pointer to bool indication if bridge is closed not.
3872 * \return int.
3873
3874 */
3875 static int
3876 ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed)
3877 {
3878         struct drxj_hi_cmd hi_cmd;
3879         u16 result = 0;
3880
3881         /* check arguments */
3882         if (bridge_closed == NULL)
3883                 return -EINVAL;
3884
3885         hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL;
3886         hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
3887         if (*bridge_closed)
3888                 hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED;
3889         else
3890                 hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN;
3891
3892         return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
3893 }
3894
3895 /*----------------------------------------------------------------------------*/
3896 /* I2C Bridge Functions - end                                                 */
3897 /*----------------------------------------------------------------------------*/
3898
3899 /*----------------------------------------------------------------------------*/
3900 /* Smart antenna Functions - begin                                            */
3901 /*----------------------------------------------------------------------------*/
3902 /**
3903 * \fn int smart_ant_init()
3904 * \brief Initialize Smart Antenna.
3905 * \param pointer to struct drx_demod_instance.
3906 * \return int.
3907 *
3908 */
3909 static int smart_ant_init(struct drx_demod_instance *demod)
3910 {
3911         struct drxj_data *ext_attr = NULL;
3912         struct i2c_device_addr *dev_addr = NULL;
3913         struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA };
3914         int rc;
3915         u16 data = 0;
3916
3917         dev_addr = demod->my_i2c_dev_addr;
3918         ext_attr = (struct drxj_data *) demod->my_ext_attr;
3919
3920         /*  Write magic word to enable pdr reg write               */
3921         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3922         if (rc != 0) {
3923                 pr_err("error %d\n", rc);
3924                 goto rw_error;
3925         }
3926         /* init smart antenna */
3927         rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0);
3928         if (rc != 0) {
3929                 pr_err("error %d\n", rc);
3930                 goto rw_error;
3931         }
3932         if (ext_attr->smart_ant_inverted) {
3933                 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3934                 if (rc != 0) {
3935                         pr_err("error %d\n", rc);
3936                         goto rw_error;
3937                 }
3938         } else {
3939                 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3940                 if (rc != 0) {
3941                         pr_err("error %d\n", rc);
3942                         goto rw_error;
3943                 }
3944         }
3945
3946         /* config SMA_TX pin to smart antenna mode */
3947         rc = ctrl_set_uio_cfg(demod, &uio_cfg);
3948         if (rc != 0) {
3949                 pr_err("error %d\n", rc);
3950                 goto rw_error;
3951         }
3952         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0);
3953         if (rc != 0) {
3954                 pr_err("error %d\n", rc);
3955                 goto rw_error;
3956         }
3957         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0);
3958         if (rc != 0) {
3959                 pr_err("error %d\n", rc);
3960                 goto rw_error;
3961         }
3962
3963         /*  Write magic word to disable pdr reg write               */
3964         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3965         if (rc != 0) {
3966                 pr_err("error %d\n", rc);
3967                 goto rw_error;
3968         }
3969
3970         return 0;
3971 rw_error:
3972         return rc;
3973 }
3974
3975 static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd)
3976 {
3977         int rc;
3978         u16 cur_cmd = 0;
3979         unsigned long timeout;
3980
3981         /* Check param */
3982         if (cmd == NULL)
3983                 return -EINVAL;
3984
3985         /* Wait until SCU command interface is ready to receive command */
3986         rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
3987         if (rc != 0) {
3988                 pr_err("error %d\n", rc);
3989                 goto rw_error;
3990         }
3991         if (cur_cmd != DRX_SCU_READY)
3992                 return -EIO;
3993
3994         switch (cmd->parameter_len) {
3995         case 5:
3996                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0);
3997                 if (rc != 0) {
3998                         pr_err("error %d\n", rc);
3999                         goto rw_error;
4000                 }       /* fallthrough */
4001         case 4:
4002                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);
4003                 if (rc != 0) {
4004                         pr_err("error %d\n", rc);
4005                         goto rw_error;
4006                 }       /* fallthrough */
4007         case 3:
4008                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);
4009                 if (rc != 0) {
4010                         pr_err("error %d\n", rc);
4011                         goto rw_error;
4012                 }       /* fallthrough */
4013         case 2:
4014                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);
4015                 if (rc != 0) {
4016                         pr_err("error %d\n", rc);
4017                         goto rw_error;
4018                 }       /* fallthrough */
4019         case 1:
4020                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);
4021                 if (rc != 0) {
4022                         pr_err("error %d\n", rc);
4023                         goto rw_error;
4024                 }       /* fallthrough */
4025         case 0:
4026                 /* do nothing */
4027                 break;
4028         default:
4029                 /* this number of parameters is not supported */
4030                 return -EIO;
4031         }
4032         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0);
4033         if (rc != 0) {
4034                 pr_err("error %d\n", rc);
4035                 goto rw_error;
4036         }
4037
4038         /* Wait until SCU has processed command */
4039         timeout = jiffies + msecs_to_jiffies(DRXJ_MAX_WAITTIME);
4040         while (time_is_after_jiffies(timeout)) {
4041                 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
4042                 if (rc != 0) {
4043                         pr_err("error %d\n", rc);
4044                         goto rw_error;
4045                 }
4046                 if (cur_cmd == DRX_SCU_READY)
4047                         break;
4048                 usleep_range(1000, 2000);
4049         }
4050
4051         if (cur_cmd != DRX_SCU_READY)
4052                 return -EIO;
4053
4054         /* read results */
4055         if ((cmd->result_len > 0) && (cmd->result != NULL)) {
4056                 s16 err;
4057
4058                 switch (cmd->result_len) {
4059                 case 4:
4060                         rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0);
4061                         if (rc != 0) {
4062                                 pr_err("error %d\n", rc);
4063                                 goto rw_error;
4064                         }       /* fallthrough */
4065                 case 3:
4066                         rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);
4067                         if (rc != 0) {
4068                                 pr_err("error %d\n", rc);
4069                                 goto rw_error;
4070                         }       /* fallthrough */
4071                 case 2:
4072                         rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);
4073                         if (rc != 0) {
4074                                 pr_err("error %d\n", rc);
4075                                 goto rw_error;
4076                         }       /* fallthrough */
4077                 case 1:
4078                         rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);
4079                         if (rc != 0) {
4080                                 pr_err("error %d\n", rc);
4081                                 goto rw_error;
4082                         }       /* fallthrough */
4083                 case 0:
4084                         /* do nothing */
4085                         break;
4086                 default:
4087                         /* this number of parameters is not supported */
4088                         return -EIO;
4089                 }
4090
4091                 /* Check if an error was reported by SCU */
4092                 err = cmd->result[0];
4093
4094                 /* check a few fixed error codes */
4095                 if ((err == (s16) SCU_RAM_PARAM_0_RESULT_UNKSTD)
4096                     || (err == (s16) SCU_RAM_PARAM_0_RESULT_UNKCMD)
4097                     || (err == (s16) SCU_RAM_PARAM_0_RESULT_INVPAR)
4098                     || (err == (s16) SCU_RAM_PARAM_0_RESULT_SIZE)
4099                     ) {
4100                         return -EINVAL;
4101                 }
4102                 /* here it is assumed that negative means error, and positive no error */
4103                 else if (err < 0)
4104                         return -EIO;
4105                 else
4106                         return 0;
4107         }
4108
4109         return 0;
4110
4111 rw_error:
4112         return rc;
4113 }
4114
4115 /**
4116 * \fn int DRXJ_DAP_SCUAtomicReadWriteBlock()
4117 * \brief Basic access routine for SCU atomic read or write access
4118 * \param dev_addr  pointer to i2c dev address
4119 * \param addr     destination/source address
4120 * \param datasize size of data buffer in bytes
4121 * \param data     pointer to data buffer
4122 * \return int
4123 * \retval 0 Succes
4124 * \retval -EIO Timeout, I2C error, illegal bank
4125 *
4126 */
4127 #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2)
4128 static
4129 int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize,      /* max 30 bytes because the limit of SCU parameter */
4130                                               u8 *data, bool read_flag)
4131 {
4132         struct drxjscu_cmd scu_cmd;
4133         int rc;
4134         u16 set_param_parameters[15];
4135         u16 cmd_result[15];
4136
4137         /* Parameter check */
4138         if (!data || !dev_addr || (datasize % 2) || ((datasize / 2) > 16))
4139                 return -EINVAL;
4140
4141         set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr);
4142         if (read_flag) {                /* read */
4143                 set_param_parameters[0] = ((~(0x0080)) & datasize);
4144                 scu_cmd.parameter_len = 2;
4145                 scu_cmd.result_len = datasize / 2 + 2;
4146         } else {
4147                 int i = 0;
4148
4149                 set_param_parameters[0] = 0x0080 | datasize;
4150                 for (i = 0; i < (datasize / 2); i++) {
4151                         set_param_parameters[i + 2] =
4152                             (data[2 * i] | (data[(2 * i) + 1] << 8));
4153                 }
4154                 scu_cmd.parameter_len = datasize / 2 + 2;
4155                 scu_cmd.result_len = 1;
4156         }
4157
4158         scu_cmd.command =
4159             SCU_RAM_COMMAND_STANDARD_TOP |
4160             SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS;
4161         scu_cmd.result = cmd_result;
4162         scu_cmd.parameter = set_param_parameters;
4163         rc = scu_command(dev_addr, &scu_cmd);
4164         if (rc != 0) {
4165                 pr_err("error %d\n", rc);
4166                 goto rw_error;
4167         }
4168
4169         if (read_flag) {
4170                 int i = 0;
4171                 /* read data from buffer */
4172                 for (i = 0; i < (datasize / 2); i++) {
4173                         data[2 * i] = (u8) (scu_cmd.result[i + 2] & 0xFF);
4174                         data[(2 * i) + 1] = (u8) (scu_cmd.result[i + 2] >> 8);
4175                 }
4176         }
4177
4178         return 0;
4179
4180 rw_error:
4181         return rc;
4182
4183 }
4184
4185 /*============================================================================*/
4186
4187 /**
4188 * \fn int DRXJ_DAP_AtomicReadReg16()
4189 * \brief Atomic read of 16 bits words
4190 */
4191 static
4192 int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr,
4193                                          u32 addr,
4194                                          u16 *data, u32 flags)
4195 {
4196         u8 buf[2] = { 0 };
4197         int rc = -EIO;
4198         u16 word = 0;
4199
4200         if (!data)
4201                 return -EINVAL;
4202
4203         rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true);
4204         if (rc < 0)
4205                 return rc;
4206
4207         word = (u16) (buf[0] + (buf[1] << 8));
4208
4209         *data = word;
4210
4211         return rc;
4212 }
4213
4214 /*============================================================================*/
4215 /**
4216 * \fn int drxj_dap_scu_atomic_write_reg16()
4217 * \brief Atomic read of 16 bits words
4218 */
4219 static
4220 int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr,
4221                                           u32 addr,
4222                                           u16 data, u32 flags)
4223 {
4224         u8 buf[2];
4225         int rc = -EIO;
4226
4227         buf[0] = (u8) (data & 0xff);
4228         buf[1] = (u8) ((data >> 8) & 0xff);
4229
4230         rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false);
4231
4232         return rc;
4233 }
4234
4235 /* -------------------------------------------------------------------------- */
4236 /**
4237 * \brief Measure result of ADC synchronisation
4238 * \param demod demod instance
4239 * \param count (returned) count
4240 * \return int.
4241 * \retval 0    Success
4242 * \retval -EIO Failure: I2C error
4243 *
4244 */
4245 static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count)
4246 {
4247         struct i2c_device_addr *dev_addr = NULL;
4248         int rc;
4249         u16 data = 0;
4250
4251         dev_addr = demod->my_i2c_dev_addr;
4252
4253         /* Start measurement */
4254         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0);
4255         if (rc != 0) {
4256                 pr_err("error %d\n", rc);
4257                 goto rw_error;
4258         }
4259         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0);
4260         if (rc != 0) {
4261                 pr_err("error %d\n", rc);
4262                 goto rw_error;
4263         }
4264
4265         /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */
4266         msleep(1);
4267
4268         *count = 0;
4269         rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0);
4270         if (rc != 0) {
4271                 pr_err("error %d\n", rc);
4272                 goto rw_error;
4273         }
4274         if (data == 127)
4275                 *count = *count + 1;
4276         rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0);
4277         if (rc != 0) {
4278                 pr_err("error %d\n", rc);
4279                 goto rw_error;
4280         }
4281         if (data == 127)
4282                 *count = *count + 1;
4283         rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0);
4284         if (rc != 0) {
4285                 pr_err("error %d\n", rc);
4286                 goto rw_error;
4287         }
4288         if (data == 127)
4289                 *count = *count + 1;
4290
4291         return 0;
4292 rw_error:
4293         return rc;
4294 }
4295
4296 /**
4297 * \brief Synchronize analog and digital clock domains
4298 * \param demod demod instance
4299 * \return int.
4300 * \retval 0    Success
4301 * \retval -EIO Failure: I2C error or failure to synchronize
4302 *
4303 * An IQM reset will also reset the results of this synchronization.
4304 * After an IQM reset this routine needs to be called again.
4305 *
4306 */
4307
4308 static int adc_synchronization(struct drx_demod_instance *demod)
4309 {
4310         struct i2c_device_addr *dev_addr = NULL;
4311         int rc;
4312         u16 count = 0;
4313
4314         dev_addr = demod->my_i2c_dev_addr;
4315
4316         rc = adc_sync_measurement(demod, &count);
4317         if (rc != 0) {
4318                 pr_err("error %d\n", rc);
4319                 goto rw_error;
4320         }
4321
4322         if (count == 1) {
4323                 /* Try sampling on a diffrent edge */
4324                 u16 clk_neg = 0;
4325
4326                 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0);
4327                 if (rc != 0) {
4328                         pr_err("error %d\n", rc);
4329                         goto rw_error;
4330                 }
4331
4332                 clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M;
4333                 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0);
4334                 if (rc != 0) {
4335                         pr_err("error %d\n", rc);
4336                         goto rw_error;
4337                 }
4338
4339                 rc = adc_sync_measurement(demod, &count);
4340                 if (rc != 0) {
4341                         pr_err("error %d\n", rc);
4342                         goto rw_error;
4343                 }
4344         }
4345
4346         /* TODO: implement fallback scenarios */
4347         if (count < 2)
4348                 return -EIO;
4349
4350         return 0;
4351 rw_error:
4352         return rc;
4353 }
4354
4355 /*============================================================================*/
4356 /*==                      END AUXILIARY FUNCTIONS                           ==*/
4357 /*============================================================================*/
4358
4359 /*============================================================================*/
4360 /*============================================================================*/
4361 /*==                8VSB & QAM COMMON DATAPATH FUNCTIONS                    ==*/
4362 /*============================================================================*/
4363 /*============================================================================*/
4364 /**
4365 * \fn int init_agc ()
4366 * \brief Initialize AGC for all standards.
4367 * \param demod instance of demodulator.
4368 * \param channel pointer to channel data.
4369 * \return int.
4370 */
4371 static int init_agc(struct drx_demod_instance *demod)
4372 {
4373         struct i2c_device_addr *dev_addr = NULL;
4374         struct drx_common_attr *common_attr = NULL;
4375         struct drxj_data *ext_attr = NULL;
4376         struct drxj_cfg_agc *p_agc_rf_settings = NULL;
4377         struct drxj_cfg_agc *p_agc_if_settings = NULL;
4378         int rc;
4379         u16 ingain_tgt_max = 0;
4380         u16 clp_dir_to = 0;
4381         u16 sns_sum_max = 0;
4382         u16 clp_sum_max = 0;
4383         u16 sns_dir_to = 0;
4384         u16 ki_innergain_min = 0;
4385         u16 agc_ki = 0;
4386         u16 ki_max = 0;
4387         u16 if_iaccu_hi_tgt_min = 0;
4388         u16 data = 0;
4389         u16 agc_ki_dgain = 0;
4390         u16 ki_min = 0;
4391         u16 clp_ctrl_mode = 0;
4392         u16 agc_rf = 0;
4393         u16 agc_if = 0;
4394
4395         dev_addr = demod->my_i2c_dev_addr;
4396         common_attr = (struct drx_common_attr *) demod->my_common_attr;
4397         ext_attr = (struct drxj_data *) demod->my_ext_attr;
4398
4399         switch (ext_attr->standard) {
4400         case DRX_STANDARD_8VSB:
4401                 clp_sum_max = 1023;
4402                 clp_dir_to = (u16) (-9);
4403                 sns_sum_max = 1023;
4404                 sns_dir_to = (u16) (-9);
4405                 ki_innergain_min = (u16) (-32768);
4406                 ki_max = 0x032C;
4407                 agc_ki_dgain = 0xC;
4408                 if_iaccu_hi_tgt_min = 2047;
4409                 ki_min = 0x0117;
4410                 ingain_tgt_max = 16383;
4411                 clp_ctrl_mode = 0;
4412                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4413                 if (rc != 0) {
4414                         pr_err("error %d\n", rc);
4415                         goto rw_error;
4416                 }
4417                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4418                 if (rc != 0) {
4419                         pr_err("error %d\n", rc);
4420                         goto rw_error;
4421                 }
4422                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4423                 if (rc != 0) {
4424                         pr_err("error %d\n", rc);
4425                         goto rw_error;
4426                 }
4427                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4428                 if (rc != 0) {
4429                         pr_err("error %d\n", rc);
4430                         goto rw_error;
4431                 }
4432                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4433                 if (rc != 0) {
4434                         pr_err("error %d\n", rc);
4435                         goto rw_error;
4436                 }
4437                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4438                 if (rc != 0) {
4439                         pr_err("error %d\n", rc);
4440                         goto rw_error;
4441                 }
4442                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4443                 if (rc != 0) {
4444                         pr_err("error %d\n", rc);
4445                         goto rw_error;
4446                 }
4447                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4448                 if (rc != 0) {
4449                         pr_err("error %d\n", rc);
4450                         goto rw_error;
4451                 }
4452                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4453                 if (rc != 0) {
4454                         pr_err("error %d\n", rc);
4455                         goto rw_error;
4456                 }
4457                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4458                 if (rc != 0) {
4459                         pr_err("error %d\n", rc);
4460                         goto rw_error;
4461                 }
4462                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0);
4463                 if (rc != 0) {
4464                         pr_err("error %d\n", rc);
4465                         goto rw_error;
4466                 }
4467                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0);
4468                 if (rc != 0) {
4469                         pr_err("error %d\n", rc);
4470                         goto rw_error;
4471                 }
4472                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0);
4473                 if (rc != 0) {
4474                         pr_err("error %d\n", rc);
4475                         goto rw_error;
4476                 }
4477                 p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg);
4478                 p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg);
4479                 break;
4480 #ifndef DRXJ_VSB_ONLY
4481         case DRX_STANDARD_ITU_A:
4482         case DRX_STANDARD_ITU_C:
4483         case DRX_STANDARD_ITU_B:
4484                 ingain_tgt_max = 5119;
4485                 clp_sum_max = 1023;
4486                 clp_dir_to = (u16) (-5);
4487                 sns_sum_max = 127;
4488                 sns_dir_to = (u16) (-3);
4489                 ki_innergain_min = 0;
4490                 ki_max = 0x0657;
4491                 if_iaccu_hi_tgt_min = 2047;
4492                 agc_ki_dgain = 0x7;
4493                 ki_min = 0x0117;
4494                 clp_ctrl_mode = 0;
4495                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4496                 if (rc != 0) {
4497                         pr_err("error %d\n", rc);
4498                         goto rw_error;
4499                 }
4500                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4501                 if (rc != 0) {
4502                         pr_err("error %d\n", rc);
4503                         goto rw_error;
4504                 }
4505                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4506                 if (rc != 0) {
4507                         pr_err("error %d\n", rc);
4508                         goto rw_error;
4509                 }
4510                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4511                 if (rc != 0) {
4512                         pr_err("error %d\n", rc);
4513                         goto rw_error;
4514                 }
4515                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4516                 if (rc != 0) {
4517                         pr_err("error %d\n", rc);
4518                         goto rw_error;
4519                 }
4520                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4521                 if (rc != 0) {
4522                         pr_err("error %d\n", rc);
4523                         goto rw_error;
4524                 }
4525                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4526                 if (rc != 0) {
4527                         pr_err("error %d\n", rc);
4528                         goto rw_error;
4529                 }
4530                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4531                 if (rc != 0) {
4532                         pr_err("error %d\n", rc);
4533                         goto rw_error;
4534                 }
4535                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4536                 if (rc != 0) {
4537                         pr_err("error %d\n", rc);
4538                         goto rw_error;
4539                 }
4540                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4541                 if (rc != 0) {
4542                         pr_err("error %d\n", rc);
4543                         goto rw_error;
4544                 }
4545                 p_agc_if_settings = &(ext_attr->qam_if_agc_cfg);
4546                 p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg);
4547                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0);
4548                 if (rc != 0) {
4549                         pr_err("error %d\n", rc);
4550                         goto rw_error;
4551                 }
4552
4553                 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0);
4554                 if (rc != 0) {
4555                         pr_err("error %d\n", rc);
4556                         goto rw_error;
4557                 }
4558                 agc_ki &= 0xf000;
4559                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0);
4560                 if (rc != 0) {
4561                         pr_err("error %d\n", rc);
4562                         goto rw_error;
4563                 }
4564                 break;
4565 #endif
4566         default:
4567                 return -EINVAL;
4568         }
4569
4570         /* for new AGC interface */
4571         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);
4572         if (rc != 0) {
4573                 pr_err("error %d\n", rc);
4574                 goto rw_error;
4575         }
4576         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0);
4577         if (rc != 0) {
4578                 pr_err("error %d\n", rc);
4579                 goto rw_error;
4580         }       /* Gain fed from inner to outer AGC */
4581         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0);
4582         if (rc != 0) {
4583                 pr_err("error %d\n", rc);
4584                 goto rw_error;
4585         }
4586         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0);
4587         if (rc != 0) {
4588                 pr_err("error %d\n", rc);
4589                 goto rw_error;
4590         }
4591         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0);
4592         if (rc != 0) {
4593                 pr_err("error %d\n", rc);
4594                 goto rw_error;
4595         }       /* set to p_agc_settings->top before */
4596         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0);
4597         if (rc != 0) {
4598                 pr_err("error %d\n", rc);
4599                 goto rw_error;
4600         }
4601         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0);
4602         if (rc != 0) {
4603                 pr_err("error %d\n", rc);
4604                 goto rw_error;
4605         }
4606         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0);
4607         if (rc != 0) {
4608                 pr_err("error %d\n", rc);
4609                 goto rw_error;
4610         }
4611         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0);
4612         if (rc != 0) {
4613                 pr_err("error %d\n", rc);
4614                 goto rw_error;
4615         }
4616         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0);
4617         if (rc != 0) {
4618                 pr_err("error %d\n", rc);
4619                 goto rw_error;
4620         }
4621         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0);
4622         if (rc != 0) {
4623                 pr_err("error %d\n", rc);
4624                 goto rw_error;
4625         }
4626         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0);
4627         if (rc != 0) {
4628                 pr_err("error %d\n", rc);
4629                 goto rw_error;
4630         }
4631         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0);
4632         if (rc != 0) {
4633                 pr_err("error %d\n", rc);
4634                 goto rw_error;
4635         }
4636         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0);
4637         if (rc != 0) {
4638                 pr_err("error %d\n", rc);
4639                 goto rw_error;
4640         }
4641         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0);
4642         if (rc != 0) {
4643                 pr_err("error %d\n", rc);
4644                 goto rw_error;
4645         }
4646         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0);
4647         if (rc != 0) {
4648                 pr_err("error %d\n", rc);
4649                 goto rw_error;
4650         }
4651         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0);
4652         if (rc != 0) {
4653                 pr_err("error %d\n", rc);
4654                 goto rw_error;
4655         }
4656         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0);
4657         if (rc != 0) {
4658                 pr_err("error %d\n", rc);
4659                 goto rw_error;
4660         }
4661         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0);
4662         if (rc != 0) {
4663                 pr_err("error %d\n", rc);
4664                 goto rw_error;
4665         }
4666         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0);
4667         if (rc != 0) {
4668                 pr_err("error %d\n", rc);
4669                 goto rw_error;
4670         }
4671         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0);
4672         if (rc != 0) {
4673                 pr_err("error %d\n", rc);
4674                 goto rw_error;
4675         }
4676         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0);
4677         if (rc != 0) {
4678                 pr_err("error %d\n", rc);
4679                 goto rw_error;
4680         }
4681         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0);
4682         if (rc != 0) {
4683                 pr_err("error %d\n", rc);
4684                 goto rw_error;
4685         }
4686         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0);
4687         if (rc != 0) {
4688                 pr_err("error %d\n", rc);
4689                 goto rw_error;
4690         }
4691         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0);
4692         if (rc != 0) {
4693                 pr_err("error %d\n", rc);
4694                 goto rw_error;
4695         }
4696         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0);
4697         if (rc != 0) {
4698                 pr_err("error %d\n", rc);
4699                 goto rw_error;
4700         }
4701
4702         agc_rf = 0x800 + p_agc_rf_settings->cut_off_current;
4703         if (common_attr->tuner_rf_agc_pol == true)
4704                 agc_rf = 0x87ff - agc_rf;
4705
4706         agc_if = 0x800;
4707         if (common_attr->tuner_if_agc_pol == true)
4708                 agc_rf = 0x87ff - agc_rf;
4709
4710         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0);
4711         if (rc != 0) {
4712                 pr_err("error %d\n", rc);
4713                 goto rw_error;
4714         }
4715         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0);
4716         if (rc != 0) {
4717                 pr_err("error %d\n", rc);
4718                 goto rw_error;
4719         }
4720
4721         /* Set/restore Ki DGAIN factor */
4722         rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4723         if (rc != 0) {
4724                 pr_err("error %d\n", rc);
4725                 goto rw_error;
4726         }
4727         data &= ~SCU_RAM_AGC_KI_DGAIN__M;
4728         data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B);
4729         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4730         if (rc != 0) {
4731                 pr_err("error %d\n", rc);
4732                 goto rw_error;
4733         }
4734
4735         return 0;
4736 rw_error:
4737         return rc;
4738 }
4739
4740 /**
4741 * \fn int set_frequency ()
4742 * \brief Set frequency shift.
4743 * \param demod instance of demodulator.
4744 * \param channel pointer to channel data.
4745 * \param tuner_freq_offset residual frequency from tuner.
4746 * \return int.
4747 */
4748 static int
4749 set_frequency(struct drx_demod_instance *demod,
4750               struct drx_channel *channel, s32 tuner_freq_offset)
4751 {
4752         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
4753         struct drxj_data *ext_attr = demod->my_ext_attr;
4754         int rc;
4755         s32 sampling_frequency = 0;
4756         s32 frequency_shift = 0;
4757         s32 if_freq_actual = 0;
4758         s32 rf_freq_residual = -1 * tuner_freq_offset;
4759         s32 adc_freq = 0;
4760         s32 intermediate_freq = 0;
4761         u32 iqm_fs_rate_ofs = 0;
4762         bool adc_flip = true;
4763         bool select_pos_image = false;
4764         bool rf_mirror;
4765         bool tuner_mirror;
4766         bool image_to_select = true;
4767         s32 fm_frequency_shift = 0;
4768
4769         rf_mirror = (ext_attr->mirror == DRX_MIRROR_YES) ? true : false;
4770         tuner_mirror = demod->my_common_attr->mirror_freq_spect ? false : true;
4771         /*
4772            Program frequency shifter
4773            No need to account for mirroring on RF
4774          */
4775         switch (ext_attr->standard) {
4776         case DRX_STANDARD_ITU_A:        /* fallthrough */
4777         case DRX_STANDARD_ITU_C:        /* fallthrough */
4778         case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */
4779         case DRX_STANDARD_8VSB:
4780                 select_pos_image = true;
4781                 break;
4782         case DRX_STANDARD_FM:
4783                 /* After IQM FS sound carrier must appear at 4 Mhz in spect.
4784                    Sound carrier is already 3Mhz above centre frequency due
4785                    to tuner setting so now add an extra shift of 1MHz... */
4786                 fm_frequency_shift = 1000;
4787         case DRX_STANDARD_ITU_B:        /* fallthrough */
4788         case DRX_STANDARD_NTSC: /* fallthrough */
4789         case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */
4790         case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */
4791         case DRX_STANDARD_PAL_SECAM_I:  /* fallthrough */
4792         case DRX_STANDARD_PAL_SECAM_L:
4793                 select_pos_image = false;
4794                 break;
4795         default:
4796                 return -EINVAL;
4797         }
4798         intermediate_freq = demod->my_common_attr->intermediate_freq;
4799         sampling_frequency = demod->my_common_attr->sys_clock_freq / 3;
4800         if (tuner_mirror)
4801                 if_freq_actual = intermediate_freq + rf_freq_residual + fm_frequency_shift;
4802         else
4803                 if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift;
4804         if (if_freq_actual > sampling_frequency / 2) {
4805                 /* adc mirrors */
4806                 adc_freq = sampling_frequency - if_freq_actual;
4807                 adc_flip = true;
4808         } else {
4809                 /* adc doesn't mirror */
4810                 adc_freq = if_freq_actual;
4811                 adc_flip = false;
4812         }
4813
4814         frequency_shift = adc_freq;
4815         image_to_select =
4816             (bool) (rf_mirror ^ tuner_mirror ^ adc_flip ^ select_pos_image);
4817         iqm_fs_rate_ofs = frac28(frequency_shift, sampling_frequency);
4818
4819         if (image_to_select)
4820                 iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
4821
4822         /* Program frequency shifter with tuner offset compensation */
4823         /* frequency_shift += tuner_freq_offset; TODO */
4824         rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
4825         if (rc != 0) {
4826                 pr_err("error %d\n", rc);
4827                 goto rw_error;
4828         }
4829         ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
4830         ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image);
4831
4832         return 0;
4833 rw_error:
4834         return rc;
4835 }
4836
4837 /**
4838 * \fn int get_acc_pkt_err()
4839 * \brief Retrieve signal strength for VSB and QAM.
4840 * \param demod Pointer to demod instance
4841 * \param packet_err Pointer to packet error
4842 * \return int.
4843 * \retval 0 sig_strength contains valid data.
4844 * \retval -EINVAL sig_strength is NULL.
4845 * \retval -EIO Erroneous data, sig_strength contains invalid data.
4846 */
4847 #ifdef DRXJ_SIGNAL_ACCUM_ERR
4848 static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err)
4849 {
4850         int rc;
4851         static u16 pkt_err;
4852         static u16 last_pkt_err;
4853         u16 data = 0;
4854         struct drxj_data *ext_attr = NULL;
4855         struct i2c_device_addr *dev_addr = NULL;
4856
4857         ext_attr = (struct drxj_data *) demod->my_ext_attr;
4858         dev_addr = demod->my_i2c_dev_addr;
4859
4860         rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0);
4861         if (rc != 0) {
4862                 pr_err("error %d\n", rc);
4863                 goto rw_error;
4864         }
4865         if (ext_attr->reset_pkt_err_acc) {
4866                 last_pkt_err = data;
4867                 pkt_err = 0;
4868                 ext_attr->reset_pkt_err_acc = false;
4869         }
4870
4871         if (data < last_pkt_err) {
4872                 pkt_err += 0xffff - last_pkt_err;
4873                 pkt_err += data;
4874         } else {
4875                 pkt_err += (data - last_pkt_err);
4876         }
4877         *packet_err = pkt_err;
4878         last_pkt_err = data;
4879
4880         return 0;
4881 rw_error:
4882         return rc;
4883 }
4884 #endif
4885
4886
4887 /*============================================================================*/
4888
4889 /**
4890 * \fn int set_agc_rf ()
4891 * \brief Configure RF AGC
4892 * \param demod instance of demodulator.
4893 * \param agc_settings AGC configuration structure
4894 * \return int.
4895 */
4896 static int
4897 set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
4898 {
4899         struct i2c_device_addr *dev_addr = NULL;
4900         struct drxj_data *ext_attr = NULL;
4901         struct drxj_cfg_agc *p_agc_settings = NULL;
4902         struct drx_common_attr *common_attr = NULL;
4903         int rc;
4904         drx_write_reg16func_t scu_wr16 = NULL;
4905         drx_read_reg16func_t scu_rr16 = NULL;
4906
4907         common_attr = (struct drx_common_attr *) demod->my_common_attr;
4908         dev_addr = demod->my_i2c_dev_addr;
4909         ext_attr = (struct drxj_data *) demod->my_ext_attr;
4910
4911         if (atomic) {
4912                 scu_rr16 = drxj_dap_scu_atomic_read_reg16;
4913                 scu_wr16 = drxj_dap_scu_atomic_write_reg16;
4914         } else {
4915                 scu_rr16 = drxj_dap_read_reg16;
4916                 scu_wr16 = drxj_dap_write_reg16;
4917         }
4918
4919         /* Configure AGC only if standard is currently active */
4920         if ((ext_attr->standard == agc_settings->standard) ||
4921             (DRXJ_ISQAMSTD(ext_attr->standard) &&
4922              DRXJ_ISQAMSTD(agc_settings->standard)) ||
4923             (DRXJ_ISATVSTD(ext_attr->standard) &&
4924              DRXJ_ISATVSTD(agc_settings->standard))) {
4925                 u16 data = 0;
4926
4927                 switch (agc_settings->ctrl_mode) {
4928                 case DRX_AGC_CTRL_AUTO:
4929
4930                         /* Enable RF AGC DAC */
4931                         rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
4932                         if (rc != 0) {
4933                                 pr_err("error %d\n", rc);
4934                                 goto rw_error;
4935                         }
4936                         data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
4937                         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
4938                         if (rc != 0) {
4939                                 pr_err("error %d\n", rc);
4940                                 goto rw_error;
4941                         }
4942
4943                         /* Enable SCU RF AGC loop */
4944                         rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4945                         if (rc != 0) {
4946                                 pr_err("error %d\n", rc);
4947                                 goto rw_error;
4948                         }
4949                         data &= ~SCU_RAM_AGC_KI_RF__M;
4950                         if (ext_attr->standard == DRX_STANDARD_8VSB)
4951                                 data |= (2 << SCU_RAM_AGC_KI_RF__B);
4952                         else if (DRXJ_ISQAMSTD(ext_attr->standard))
4953                                 data |= (5 << SCU_RAM_AGC_KI_RF__B);
4954                         else
4955                                 data |= (4 << SCU_RAM_AGC_KI_RF__B);
4956
4957                         if (common_attr->tuner_rf_agc_pol)
4958                                 data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
4959                         else
4960                                 data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
4961                         rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4962                         if (rc != 0) {
4963                                 pr_err("error %d\n", rc);
4964                                 goto rw_error;
4965                         }
4966
4967                         /* Set speed ( using complementary reduction value ) */
4968                         rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
4969                         if (rc != 0) {
4970                                 pr_err("error %d\n", rc);
4971                                 goto rw_error;
4972                         }
4973                         data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
4974                         rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0);
4975                         if (rc != 0) {
4976                                 pr_err("error %d\n", rc);
4977                                 goto rw_error;
4978                         }
4979
4980                         if (agc_settings->standard == DRX_STANDARD_8VSB)
4981                                 p_agc_settings = &(ext_attr->vsb_if_agc_cfg);
4982                         else if (DRXJ_ISQAMSTD(agc_settings->standard))
4983                                 p_agc_settings = &(ext_attr->qam_if_agc_cfg);
4984                         else if (DRXJ_ISATVSTD(agc_settings->standard))
4985                                 p_agc_settings = &(ext_attr->atv_if_agc_cfg);
4986                         else
4987                                 return -EINVAL;
4988
4989                         /* Set TOP, only if IF-AGC is in AUTO mode */
4990                         if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
4991                                 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0);
4992                                 if (rc != 0) {
4993                                         pr_err("error %d\n", rc);
4994                                         goto rw_error;
4995                                 }
4996                                 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0);
4997                                 if (rc != 0) {
4998                                         pr_err("error %d\n", rc);
4999                                         goto rw_error;
5000                                 }
5001                         }
5002
5003                         /* Cut-Off current */
5004                         rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0);
5005                         if (rc != 0) {
5006                                 pr_err("error %d\n", rc);
5007                                 goto rw_error;
5008                         }
5009                         break;
5010                 case DRX_AGC_CTRL_USER:
5011
5012                         /* Enable RF AGC DAC */
5013                         rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5014                         if (rc != 0) {
5015                                 pr_err("error %d\n", rc);
5016                                 goto rw_error;
5017                         }
5018                         data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
5019                         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5020                         if (rc != 0) {
5021                                 pr_err("error %d\n", rc);
5022                                 goto rw_error;
5023                         }
5024
5025                         /* Disable SCU RF AGC loop */
5026                         rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5027                         if (rc != 0) {
5028                                 pr_err("error %d\n", rc);
5029                                 goto rw_error;
5030                         }
5031                         data &= ~SCU_RAM_AGC_KI_RF__M;
5032                         if (common_attr->tuner_rf_agc_pol)
5033                                 data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
5034                         else
5035                                 data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
5036                         rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5037                         if (rc != 0) {
5038                                 pr_err("error %d\n", rc);
5039                                 goto rw_error;
5040                         }
5041
5042                         /* Write value to output pin */
5043                         rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0);
5044                         if (rc != 0) {
5045                                 pr_err("error %d\n", rc);
5046                                 goto rw_error;
5047                         }
5048                         break;
5049                 case DRX_AGC_CTRL_OFF:
5050
5051                         /* Disable RF AGC DAC */
5052                         rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5053                         if (rc != 0) {
5054                                 pr_err("error %d\n", rc);
5055                                 goto rw_error;
5056                         }
5057                         data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
5058                         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5059                         if (rc != 0) {
5060                                 pr_err("error %d\n", rc);
5061                                 goto rw_error;
5062                         }
5063
5064                         /* Disable SCU RF AGC loop */
5065                         rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5066                         if (rc != 0) {
5067                                 pr_err("error %d\n", rc);
5068                                 goto rw_error;
5069                         }
5070                         data &= ~SCU_RAM_AGC_KI_RF__M;
5071                         rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5072                         if (rc != 0) {
5073                                 pr_err("error %d\n", rc);
5074                                 goto rw_error;
5075                         }
5076                         break;
5077                 default:
5078                         return -EINVAL;
5079                 }               /* switch ( agcsettings->ctrl_mode ) */
5080         }
5081
5082         /* Store rf agc settings */
5083         switch (agc_settings->standard) {
5084         case DRX_STANDARD_8VSB:
5085                 ext_attr->vsb_rf_agc_cfg = *agc_settings;
5086                 break;
5087 #ifndef DRXJ_VSB_ONLY
5088         case DRX_STANDARD_ITU_A:
5089         case DRX_STANDARD_ITU_B:
5090         case DRX_STANDARD_ITU_C:
5091                 ext_attr->qam_rf_agc_cfg = *agc_settings;
5092                 break;
5093 #endif
5094         default:
5095                 return -EIO;
5096         }
5097
5098         return 0;
5099 rw_error:
5100         return rc;
5101 }
5102
5103 /**
5104 * \fn int set_agc_if ()
5105 * \brief Configure If AGC
5106 * \param demod instance of demodulator.
5107 * \param agc_settings AGC configuration structure
5108 * \return int.
5109 */
5110 static int
5111 set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
5112 {
5113         struct i2c_device_addr *dev_addr = NULL;
5114         struct drxj_data *ext_attr = NULL;
5115         struct drxj_cfg_agc *p_agc_settings = NULL;
5116         struct drx_common_attr *common_attr = NULL;
5117         drx_write_reg16func_t scu_wr16 = NULL;
5118         drx_read_reg16func_t scu_rr16 = NULL;
5119         int rc;
5120
5121         common_attr = (struct drx_common_attr *) demod->my_common_attr;
5122         dev_addr = demod->my_i2c_dev_addr;
5123         ext_attr = (struct drxj_data *) demod->my_ext_attr;
5124
5125         if (atomic) {
5126                 scu_rr16 = drxj_dap_scu_atomic_read_reg16;
5127                 scu_wr16 = drxj_dap_scu_atomic_write_reg16;
5128         } else {
5129                 scu_rr16 = drxj_dap_read_reg16;
5130                 scu_wr16 = drxj_dap_write_reg16;
5131         }
5132
5133         /* Configure AGC only if standard is currently active */
5134         if ((ext_attr->standard == agc_settings->standard) ||
5135             (DRXJ_ISQAMSTD(ext_attr->standard) &&
5136              DRXJ_ISQAMSTD(agc_settings->standard)) ||
5137             (DRXJ_ISATVSTD(ext_attr->standard) &&
5138              DRXJ_ISATVSTD(agc_settings->standard))) {
5139                 u16 data = 0;
5140
5141                 switch (agc_settings->ctrl_mode) {
5142                 case DRX_AGC_CTRL_AUTO:
5143                         /* Enable IF AGC DAC */
5144                         rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5145                         if (rc != 0) {
5146                                 pr_err("error %d\n", rc);
5147                                 goto rw_error;
5148                         }
5149                         data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
5150                         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5151                         if (rc != 0) {
5152                                 pr_err("error %d\n", rc);
5153                                 goto rw_error;
5154                         }
5155
5156                         /* Enable SCU IF AGC loop */
5157                         rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5158                         if (rc != 0) {
5159                                 pr_err("error %d\n", rc);
5160                                 goto rw_error;
5161                         }
5162                         data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5163                         data &= ~SCU_RAM_AGC_KI_IF__M;
5164                         if (ext_attr->standard == DRX_STANDARD_8VSB)
5165                                 data |= (3 << SCU_RAM_AGC_KI_IF__B);
5166                         else if (DRXJ_ISQAMSTD(ext_attr->standard))
5167                                 data |= (6 << SCU_RAM_AGC_KI_IF__B);
5168                         else
5169                                 data |= (5 << SCU_RAM_AGC_KI_IF__B);
5170
5171                         if (common_attr->tuner_if_agc_pol)
5172                                 data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
5173                         else
5174                                 data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
5175                         rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5176                         if (rc != 0) {
5177                                 pr_err("error %d\n", rc);
5178                                 goto rw_error;
5179                         }
5180
5181                         /* Set speed (using complementary reduction value) */
5182                         rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
5183                         if (rc != 0) {
5184                                 pr_err("error %d\n", rc);
5185                                 goto rw_error;
5186                         }
5187                         data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
5188                         rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0);
5189                         if (rc != 0) {
5190                                 pr_err("error %d\n", rc);
5191                                 goto rw_error;
5192                         }
5193
5194                         if (agc_settings->standard == DRX_STANDARD_8VSB)
5195                                 p_agc_settings = &(ext_attr->vsb_rf_agc_cfg);
5196                         else if (DRXJ_ISQAMSTD(agc_settings->standard))
5197                                 p_agc_settings = &(ext_attr->qam_rf_agc_cfg);
5198                         else if (DRXJ_ISATVSTD(agc_settings->standard))
5199                                 p_agc_settings = &(ext_attr->atv_rf_agc_cfg);
5200                         else
5201                                 return -EINVAL;
5202
5203                         /* Restore TOP */
5204                         if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
5205                                 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0);
5206                                 if (rc != 0) {
5207                                         pr_err("error %d\n", rc);
5208                                         goto rw_error;
5209                                 }
5210                                 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0);
5211                                 if (rc != 0) {
5212                                         pr_err("error %d\n", rc);
5213                                         goto rw_error;
5214                                 }
5215                         } else {
5216                                 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0);
5217                                 if (rc != 0) {
5218                                         pr_err("error %d\n", rc);
5219                                         goto rw_error;
5220                                 }
5221                                 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0);
5222                                 if (rc != 0) {
5223                                         pr_err("error %d\n", rc);
5224                                         goto rw_error;
5225                                 }
5226                         }
5227                         break;
5228
5229                 case DRX_AGC_CTRL_USER:
5230
5231                         /* Enable IF AGC DAC */
5232                         rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5233                         if (rc != 0) {
5234                                 pr_err("error %d\n", rc);
5235                                 goto rw_error;
5236                         }
5237                         data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
5238                         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5239                         if (rc != 0) {
5240                                 pr_err("error %d\n", rc);
5241                                 goto rw_error;
5242                         }
5243
5244                         /* Disable SCU IF AGC loop */
5245                         rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5246                         if (rc != 0) {
5247                                 pr_err("error %d\n", rc);
5248                                 goto rw_error;
5249                         }
5250                         data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5251                         data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5252                         if (common_attr->tuner_if_agc_pol)
5253                                 data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
5254                         else
5255                                 data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
5256                         rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5257                         if (rc != 0) {
5258                                 pr_err("error %d\n", rc);
5259                                 goto rw_error;
5260                         }
5261
5262                         /* Write value to output pin */
5263                         rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0);
5264                         if (rc != 0) {
5265                                 pr_err("error %d\n", rc);
5266                                 goto rw_error;
5267                         }
5268                         break;
5269
5270                 case DRX_AGC_CTRL_OFF:
5271
5272                         /* Disable If AGC DAC */
5273                         rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5274                         if (rc != 0) {
5275                                 pr_err("error %d\n", rc);
5276                                 goto rw_error;
5277                         }
5278                         data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE);
5279                         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5280                         if (rc != 0) {
5281                                 pr_err("error %d\n", rc);
5282                                 goto rw_error;
5283                         }
5284
5285                         /* Disable SCU IF AGC loop */
5286                         rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5287                         if (rc != 0) {
5288                                 pr_err("error %d\n", rc);
5289                                 goto rw_error;
5290                         }
5291                         data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5292                         data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5293                         rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5294                         if (rc != 0) {
5295                                 pr_err("error %d\n", rc);
5296                                 goto rw_error;
5297                         }
5298                         break;
5299                 default:
5300                         return -EINVAL;
5301                 }               /* switch ( agcsettings->ctrl_mode ) */
5302
5303                 /* always set the top to support configurations without if-loop */
5304                 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0);
5305                 if (rc != 0) {
5306                         pr_err("error %d\n", rc);
5307                         goto rw_error;
5308                 }
5309         }
5310
5311         /* Store if agc settings */
5312         switch (agc_settings->standard) {
5313         case DRX_STANDARD_8VSB:
5314                 ext_attr->vsb_if_agc_cfg = *agc_settings;
5315                 break;
5316 #ifndef DRXJ_VSB_ONLY
5317         case DRX_STANDARD_ITU_A:
5318         case DRX_STANDARD_ITU_B:
5319         case DRX_STANDARD_ITU_C:
5320                 ext_attr->qam_if_agc_cfg = *agc_settings;
5321                 break;
5322 #endif
5323         default:
5324                 return -EIO;
5325         }
5326
5327         return 0;
5328 rw_error:
5329         return rc;
5330 }
5331
5332 /**
5333 * \fn int set_iqm_af ()
5334 * \brief Configure IQM AF registers
5335 * \param demod instance of demodulator.
5336 * \param active
5337 * \return int.
5338 */
5339 static int set_iqm_af(struct drx_demod_instance *demod, bool active)
5340 {
5341         u16 data = 0;
5342         struct i2c_device_addr *dev_addr = NULL;
5343         int rc;
5344
5345         dev_addr = demod->my_i2c_dev_addr;
5346
5347         /* Configure IQM */
5348         rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5349         if (rc != 0) {
5350                 pr_err("error %d\n", rc);
5351                 goto rw_error;
5352         }
5353         if (!active)
5354                 data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE));
5355         else
5356                 data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
5357         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5358         if (rc != 0) {
5359                 pr_err("error %d\n", rc);
5360                 goto rw_error;
5361         }
5362
5363         return 0;
5364 rw_error:
5365         return rc;
5366 }
5367
5368 /*============================================================================*/
5369 /*==              END 8VSB & QAM COMMON DATAPATH FUNCTIONS                  ==*/
5370 /*============================================================================*/
5371
5372 /*============================================================================*/
5373 /*============================================================================*/
5374 /*==                       8VSB DATAPATH FUNCTIONS                          ==*/
5375 /*============================================================================*/
5376 /*============================================================================*/
5377
5378 /**
5379 * \fn int power_down_vsb ()
5380 * \brief Powr down QAM related blocks.
5381 * \param demod instance of demodulator.
5382 * \param channel pointer to channel data.
5383 * \return int.
5384 */
5385 static int power_down_vsb(struct drx_demod_instance *demod, bool primary)
5386 {
5387         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
5388         struct drxjscu_cmd cmd_scu = { /* command     */ 0,
5389                 /* parameter_len */ 0,
5390                 /* result_len    */ 0,
5391                 /* *parameter   */ NULL,
5392                 /* *result      */ NULL
5393         };
5394         struct drx_cfg_mpeg_output cfg_mpeg_output;
5395         int rc;
5396         u16 cmd_result = 0;
5397
5398         /*
5399            STOP demodulator
5400            reset of FEC and VSB HW
5401          */
5402         cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
5403             SCU_RAM_COMMAND_CMD_DEMOD_STOP;
5404         cmd_scu.parameter_len = 0;
5405         cmd_scu.result_len = 1;
5406         cmd_scu.parameter = NULL;
5407         cmd_scu.result = &cmd_result;
5408         rc = scu_command(dev_addr, &cmd_scu);
5409         if (rc != 0) {
5410                 pr_err("error %d\n", rc);
5411                 goto rw_error;
5412         }
5413
5414         /* stop all comm_exec */
5415         rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5416         if (rc != 0) {
5417                 pr_err("error %d\n", rc);
5418                 goto rw_error;
5419         }
5420         rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5421         if (rc != 0) {
5422                 pr_err("error %d\n", rc);
5423                 goto rw_error;
5424         }
5425         if (primary) {
5426                 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
5427                 if (rc != 0) {
5428                         pr_err("error %d\n", rc);
5429                         goto rw_error;
5430                 }
5431                 rc = set_iqm_af(demod, false);
5432                 if (rc != 0) {
5433                         pr_err("error %d\n", rc);
5434                         goto rw_error;
5435                 }
5436         } else {
5437                 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5438                 if (rc != 0) {
5439                         pr_err("error %d\n", rc);
5440                         goto rw_error;
5441                 }
5442                 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5443                 if (rc != 0) {
5444                         pr_err("error %d\n", rc);
5445                         goto rw_error;
5446                 }
5447                 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5448                 if (rc != 0) {
5449                         pr_err("error %d\n", rc);
5450                         goto rw_error;
5451                 }
5452                 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5453                 if (rc != 0) {
5454                         pr_err("error %d\n", rc);
5455                         goto rw_error;
5456                 }
5457                 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5458                 if (rc != 0) {
5459                         pr_err("error %d\n", rc);
5460                         goto rw_error;
5461                 }
5462         }
5463
5464         cfg_mpeg_output.enable_mpeg_output = false;
5465         rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
5466         if (rc != 0) {
5467                 pr_err("error %d\n", rc);
5468                 goto rw_error;
5469         }
5470
5471         return 0;
5472 rw_error:
5473         return rc;
5474 }
5475
5476 /**
5477 * \fn int set_vsb_leak_n_gain ()
5478 * \brief Set ATSC demod.
5479 * \param demod instance of demodulator.
5480 * \return int.
5481 */
5482 static int set_vsb_leak_n_gain(struct drx_demod_instance *demod)
5483 {
5484         struct i2c_device_addr *dev_addr = NULL;
5485         int rc;
5486
5487         const u8 vsb_ffe_leak_gain_ram0[] = {
5488                 DRXJ_16TO8(0x8),        /* FFETRAINLKRATIO1  */
5489                 DRXJ_16TO8(0x8),        /* FFETRAINLKRATIO2  */
5490                 DRXJ_16TO8(0x8),        /* FFETRAINLKRATIO3  */
5491                 DRXJ_16TO8(0xf),        /* FFETRAINLKRATIO4  */
5492                 DRXJ_16TO8(0xf),        /* FFETRAINLKRATIO5  */
5493                 DRXJ_16TO8(0xf),        /* FFETRAINLKRATIO6  */
5494                 DRXJ_16TO8(0xf),        /* FFETRAINLKRATIO7  */
5495                 DRXJ_16TO8(0xf),        /* FFETRAINLKRATIO8  */
5496                 DRXJ_16TO8(0xf),        /* FFETRAINLKRATIO9  */
5497                 DRXJ_16TO8(0x8),        /* FFETRAINLKRATIO10  */
5498                 DRXJ_16TO8(0x8),        /* FFETRAINLKRATIO11 */
5499                 DRXJ_16TO8(0x8),        /* FFETRAINLKRATIO12 */
5500                 DRXJ_16TO8(0x10),       /* FFERCA1TRAINLKRATIO1 */
5501                 DRXJ_16TO8(0x10),       /* FFERCA1TRAINLKRATIO2 */
5502                 DRXJ_16TO8(0x10),       /* FFERCA1TRAINLKRATIO3 */
5503                 DRXJ_16TO8(0x20),       /* FFERCA1TRAINLKRATIO4 */
5504                 DRXJ_16TO8(0x20),       /* FFERCA1TRAINLKRATIO5 */
5505                 DRXJ_16TO8(0x20),       /* FFERCA1TRAINLKRATIO6 */
5506                 DRXJ_16TO8(0x20),       /* FFERCA1TRAINLKRATIO7 */
5507                 DRXJ_16TO8(0x20),       /* FFERCA1TRAINLKRATIO8 */
5508                 DRXJ_16TO8(0x20),       /* FFERCA1TRAINLKRATIO9 */
5509                 DRXJ_16TO8(0x10),       /* FFERCA1TRAINLKRATIO10 */
5510                 DRXJ_16TO8(0x10),       /* FFERCA1TRAINLKRATIO11 */
5511                 DRXJ_16TO8(0x10),       /* FFERCA1TRAINLKRATIO12 */
5512                 DRXJ_16TO8(0x10),       /* FFERCA1DATALKRATIO1 */
5513                 DRXJ_16TO8(0x10),       /* FFERCA1DATALKRATIO2 */
5514                 DRXJ_16TO8(0x10),       /* FFERCA1DATALKRATIO3 */
5515                 DRXJ_16TO8(0x20),       /* FFERCA1DATALKRATIO4 */
5516                 DRXJ_16TO8(0x20),       /* FFERCA1DATALKRATIO5 */
5517                 DRXJ_16TO8(0x20),       /* FFERCA1DATALKRATIO6 */
5518                 DRXJ_16TO8(0x20),       /* FFERCA1DATALKRATIO7 */
5519                 DRXJ_16TO8(0x20),       /* FFERCA1DATALKRATIO8 */
5520                 DRXJ_16TO8(0x20),       /* FFERCA1DATALKRATIO9 */
5521                 DRXJ_16TO8(0x10),       /* FFERCA1DATALKRATIO10 */
5522                 DRXJ_16TO8(0x10),       /* FFERCA1DATALKRATIO11 */
5523                 DRXJ_16TO8(0x10),       /* FFERCA1DATALKRATIO12 */
5524                 DRXJ_16TO8(0x10),       /* FFERCA2TRAINLKRATIO1 */
5525                 DRXJ_16TO8(0x10),       /* FFERCA2TRAINLKRATIO2 */
5526                 DRXJ_16TO8(0x10),       /* FFERCA2TRAINLKRATIO3 */
5527                 DRXJ_16TO8(0x20),       /* FFERCA2TRAINLKRATIO4 */
5528                 DRXJ_16TO8(0x20),       /* FFERCA2TRAINLKRATIO5 */
5529                 DRXJ_16TO8(0x20),       /* FFERCA2TRAINLKRATIO6 */
5530                 DRXJ_16TO8(0x20),       /* FFERCA2TRAINLKRATIO7 */
5531                 DRXJ_16TO8(0x20),       /* FFERCA2TRAINLKRATIO8 */
5532                 DRXJ_16TO8(0x20),       /* FFERCA2TRAINLKRATIO9 */
5533                 DRXJ_16TO8(0x10),       /* FFERCA2TRAINLKRATIO10 */
5534                 DRXJ_16TO8(0x10),       /* FFERCA2TRAINLKRATIO11 */
5535                 DRXJ_16TO8(0x10),       /* FFERCA2TRAINLKRATIO12 */
5536                 DRXJ_16TO8(0x10),       /* FFERCA2DATALKRATIO1 */
5537                 DRXJ_16TO8(0x10),       /* FFERCA2DATALKRATIO2 */
5538                 DRXJ_16TO8(0x10),       /* FFERCA2DATALKRATIO3 */
5539                 DRXJ_16TO8(0x20),       /* FFERCA2DATALKRATIO4 */
5540                 DRXJ_16TO8(0x20),       /* FFERCA2DATALKRATIO5 */
5541                 DRXJ_16TO8(0x20),       /* FFERCA2DATALKRATIO6 */
5542                 DRXJ_16TO8(0x20),       /* FFERCA2DATALKRATIO7 */
5543                 DRXJ_16TO8(0x20),       /* FFERCA2DATALKRATIO8 */
5544                 DRXJ_16TO8(0x20),       /* FFERCA2DATALKRATIO9 */
5545                 DRXJ_16TO8(0x10),       /* FFERCA2DATALKRATIO10 */
5546                 DRXJ_16TO8(0x10),       /* FFERCA2DATALKRATIO11 */
5547                 DRXJ_16TO8(0x10),       /* FFERCA2DATALKRATIO12 */
5548                 DRXJ_16TO8(0x07),       /* FFEDDM1TRAINLKRATIO1 */
5549                 DRXJ_16TO8(0x07),       /* FFEDDM1TRAINLKRATIO2 */
5550                 DRXJ_16TO8(0x07),       /* FFEDDM1TRAINLKRATIO3 */
5551                 DRXJ_16TO8(0x0e),       /* FFEDDM1TRAINLKRATIO4 */
5552                 DRXJ_16TO8(0x0e),       /* FFEDDM1TRAINLKRATIO5 */
5553                 DRXJ_16TO8(0x0e),       /* FFEDDM1TRAINLKRATIO6 */
5554                 DRXJ_16TO8(0x0e),       /* FFEDDM1TRAINLKRATIO7 */
5555                 DRXJ_16TO8(0x0e),       /* FFEDDM1TRAINLKRATIO8 */
5556                 DRXJ_16TO8(0x0e),       /* FFEDDM1TRAINLKRATIO9 */
5557                 DRXJ_16TO8(0x07),       /* FFEDDM1TRAINLKRATIO10 */
5558                 DRXJ_16TO8(0x07),       /* FFEDDM1TRAINLKRATIO11 */
5559                 DRXJ_16TO8(0x07),       /* FFEDDM1TRAINLKRATIO12 */
5560                 DRXJ_16TO8(0x07),       /* FFEDDM1DATALKRATIO1 */
5561                 DRXJ_16TO8(0x07),       /* FFEDDM1DATALKRATIO2 */
5562                 DRXJ_16TO8(0x07),       /* FFEDDM1DATALKRATIO3 */
5563                 DRXJ_16TO8(0x0e),       /* FFEDDM1DATALKRATIO4 */
5564                 DRXJ_16TO8(0x0e),       /* FFEDDM1DATALKRATIO5 */
5565                 DRXJ_16TO8(0x0e),       /* FFEDDM1DATALKRATIO6 */
5566                 DRXJ_16TO8(0x0e),       /* FFEDDM1DATALKRATIO7 */
5567                 DRXJ_16TO8(0x0e),       /* FFEDDM1DATALKRATIO8 */
5568                 DRXJ_16TO8(0x0e),       /* FFEDDM1DATALKRATIO9 */
5569                 DRXJ_16TO8(0x07),       /* FFEDDM1DATALKRATIO10 */
5570                 DRXJ_16TO8(0x07),       /* FFEDDM1DATALKRATIO11 */
5571                 DRXJ_16TO8(0x07),       /* FFEDDM1DATALKRATIO12 */
5572                 DRXJ_16TO8(0x06),       /* FFEDDM2TRAINLKRATIO1 */
5573                 DRXJ_16TO8(0x06),       /* FFEDDM2TRAINLKRATIO2 */
5574                 DRXJ_16TO8(0x06),       /* FFEDDM2TRAINLKRATIO3 */
5575                 DRXJ_16TO8(0x0c),       /* FFEDDM2TRAINLKRATIO4 */
5576                 DRXJ_16TO8(0x0c),       /* FFEDDM2TRAINLKRATIO5 */
5577                 DRXJ_16TO8(0x0c),       /* FFEDDM2TRAINLKRATIO6 */
5578                 DRXJ_16TO8(0x0c),       /* FFEDDM2TRAINLKRATIO7 */
5579                 DRXJ_16TO8(0x0c),       /* FFEDDM2TRAINLKRATIO8 */
5580                 DRXJ_16TO8(0x0c),       /* FFEDDM2TRAINLKRATIO9 */
5581                 DRXJ_16TO8(0x06),       /* FFEDDM2TRAINLKRATIO10 */
5582                 DRXJ_16TO8(0x06),       /* FFEDDM2TRAINLKRATIO11 */
5583                 DRXJ_16TO8(0x06),       /* FFEDDM2TRAINLKRATIO12 */
5584                 DRXJ_16TO8(0x06),       /* FFEDDM2DATALKRATIO1 */
5585                 DRXJ_16TO8(0x06),       /* FFEDDM2DATALKRATIO2 */
5586                 DRXJ_16TO8(0x06),       /* FFEDDM2DATALKRATIO3 */
5587                 DRXJ_16TO8(0x0c),       /* FFEDDM2DATALKRATIO4 */
5588                 DRXJ_16TO8(0x0c),       /* FFEDDM2DATALKRATIO5 */
5589                 DRXJ_16TO8(0x0c),       /* FFEDDM2DATALKRATIO6 */
5590                 DRXJ_16TO8(0x0c),       /* FFEDDM2DATALKRATIO7 */
5591                 DRXJ_16TO8(0x0c),       /* FFEDDM2DATALKRATIO8 */
5592                 DRXJ_16TO8(0x0c),       /* FFEDDM2DATALKRATIO9 */
5593                 DRXJ_16TO8(0x06),       /* FFEDDM2DATALKRATIO10 */
5594                 DRXJ_16TO8(0x06),       /* FFEDDM2DATALKRATIO11 */
5595                 DRXJ_16TO8(0x06),       /* FFEDDM2DATALKRATIO12 */
5596                 DRXJ_16TO8(0x2020),     /* FIRTRAINGAIN1 */
5597                 DRXJ_16TO8(0x2020),     /* FIRTRAINGAIN2 */
5598                 DRXJ_16TO8(0x2020),     /* FIRTRAINGAIN3 */
5599                 DRXJ_16TO8(0x4040),     /* FIRTRAINGAIN4 */
5600                 DRXJ_16TO8(0x4040),     /* FIRTRAINGAIN5 */
5601                 DRXJ_16TO8(0x4040),     /* FIRTRAINGAIN6 */
5602                 DRXJ_16TO8(0x4040),     /* FIRTRAINGAIN7 */
5603                 DRXJ_16TO8(0x4040),     /* FIRTRAINGAIN8 */
5604                 DRXJ_16TO8(0x4040),     /* FIRTRAINGAIN9 */
5605                 DRXJ_16TO8(0x2020),     /* FIRTRAINGAIN10 */
5606                 DRXJ_16TO8(0x2020),     /* FIRTRAINGAIN11 */
5607                 DRXJ_16TO8(0x2020),     /* FIRTRAINGAIN12 */
5608                 DRXJ_16TO8(0x0808),     /* FIRRCA1GAIN1 */
5609                 DRXJ_16TO8(0x0808),     /* FIRRCA1GAIN2 */
5610                 DRXJ_16TO8(0x0808),     /* FIRRCA1GAIN3 */
5611                 DRXJ_16TO8(0x1010),     /* FIRRCA1GAIN4 */
5612                 DRXJ_16TO8(0x1010),     /* FIRRCA1GAIN5 */
5613                 DRXJ_16TO8(0x1010),     /* FIRRCA1GAIN6 */
5614                 DRXJ_16TO8(0x1010),     /* FIRRCA1GAIN7 */
5615                 DRXJ_16TO8(0x1010)      /* FIRRCA1GAIN8 */
5616         };
5617
5618         const u8 vsb_ffe_leak_gain_ram1[] = {
5619                 DRXJ_16TO8(0x1010),     /* FIRRCA1GAIN9 */
5620                 DRXJ_16TO8(0x0808),     /* FIRRCA1GAIN10 */
5621                 DRXJ_16TO8(0x0808),     /* FIRRCA1GAIN11 */
5622                 DRXJ_16TO8(0x0808),     /* FIRRCA1GAIN12 */
5623                 DRXJ_16TO8(0x0808),     /* FIRRCA2GAIN1 */
5624                 DRXJ_16TO8(0x0808),     /* FIRRCA2GAIN2 */
5625                 DRXJ_16TO8(0x0808),     /* FIRRCA2GAIN3 */
5626                 DRXJ_16TO8(0x1010),     /* FIRRCA2GAIN4 */
5627                 DRXJ_16TO8(0x1010),     /* FIRRCA2GAIN5 */
5628                 DRXJ_16TO8(0x1010),     /* FIRRCA2GAIN6 */
5629                 DRXJ_16TO8(0x1010),     /* FIRRCA2GAIN7 */
5630                 DRXJ_16TO8(0x1010),     /* FIRRCA2GAIN8 */
5631                 DRXJ_16TO8(0x1010),     /* FIRRCA2GAIN9 */
5632                 DRXJ_16TO8(0x0808),     /* FIRRCA2GAIN10 */
5633                 DRXJ_16TO8(0x0808),     /* FIRRCA2GAIN11 */
5634                 DRXJ_16TO8(0x0808),     /* FIRRCA2GAIN12 */
5635                 DRXJ_16TO8(0x0303),     /* FIRDDM1GAIN1 */
5636                 DRXJ_16TO8(0x0303),     /* FIRDDM1GAIN2 */
5637                 DRXJ_16TO8(0x0303),     /* FIRDDM1GAIN3 */
5638                 DRXJ_16TO8(0x0606),     /* FIRDDM1GAIN4 */
5639                 DRXJ_16TO8(0x0606),     /* FIRDDM1GAIN5 */
5640                 DRXJ_16TO8(0x0606),     /* FIRDDM1GAIN6 */
5641                 DRXJ_16TO8(0x0606),     /* FIRDDM1GAIN7 */
5642                 DRXJ_16TO8(0x0606),     /* FIRDDM1GAIN8 */
5643                 DRXJ_16TO8(0x0606),     /* FIRDDM1GAIN9 */
5644                 DRXJ_16TO8(0x0303),     /* FIRDDM1GAIN10 */
5645                 DRXJ_16TO8(0x0303),     /* FIRDDM1GAIN11 */
5646                 DRXJ_16TO8(0x0303),     /* FIRDDM1GAIN12 */
5647                 DRXJ_16TO8(0x0303),     /* FIRDDM2GAIN1 */
5648                 DRXJ_16TO8(0x0303),     /* FIRDDM2GAIN2 */
5649                 DRXJ_16TO8(0x0303),     /* FIRDDM2GAIN3 */
5650                 DRXJ_16TO8(0x0505),     /* FIRDDM2GAIN4 */
5651                 DRXJ_16TO8(0x0505),     /* FIRDDM2GAIN5 */
5652                 DRXJ_16TO8(0x0505),     /* FIRDDM2GAIN6 */
5653                 DRXJ_16TO8(0x0505),     /* FIRDDM2GAIN7 */
5654                 DRXJ_16TO8(0x0505),     /* FIRDDM2GAIN8 */
5655                 DRXJ_16TO8(0x0505),     /* FIRDDM2GAIN9 */
5656                 DRXJ_16TO8(0x0303),     /* FIRDDM2GAIN10 */
5657                 DRXJ_16TO8(0x0303),     /* FIRDDM2GAIN11 */
5658                 DRXJ_16TO8(0x0303),     /* FIRDDM2GAIN12 */
5659                 DRXJ_16TO8(0x001f),     /* DFETRAINLKRATIO */
5660                 DRXJ_16TO8(0x01ff),     /* DFERCA1TRAINLKRATIO */
5661                 DRXJ_16TO8(0x01ff),     /* DFERCA1DATALKRATIO */
5662                 DRXJ_16TO8(0x004f),     /* DFERCA2TRAINLKRATIO */
5663                 DRXJ_16TO8(0x004f),     /* DFERCA2DATALKRATIO */
5664                 DRXJ_16TO8(0x01ff),     /* DFEDDM1TRAINLKRATIO */
5665                 DRXJ_16TO8(0x01ff),     /* DFEDDM1DATALKRATIO */
5666                 DRXJ_16TO8(0x0352),     /* DFEDDM2TRAINLKRATIO */
5667                 DRXJ_16TO8(0x0352),     /* DFEDDM2DATALKRATIO */
5668                 DRXJ_16TO8(0x0000),     /* DFETRAINGAIN */
5669                 DRXJ_16TO8(0x2020),     /* DFERCA1GAIN */
5670                 DRXJ_16TO8(0x1010),     /* DFERCA2GAIN */
5671                 DRXJ_16TO8(0x1818),     /* DFEDDM1GAIN */
5672                 DRXJ_16TO8(0x1212)      /* DFEDDM2GAIN */
5673         };
5674
5675         dev_addr = demod->my_i2c_dev_addr;
5676         rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0);
5677         if (rc != 0) {
5678                 pr_err("error %d\n", rc);
5679                 goto rw_error;
5680         }
5681         rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0);
5682         if (rc != 0) {
5683                 pr_err("error %d\n", rc);
5684                 goto rw_error;
5685         }
5686
5687         return 0;
5688 rw_error:
5689         return rc;
5690 }
5691
5692 /**
5693 * \fn int set_vsb()
5694 * \brief Set 8VSB demod.
5695 * \param demod instance of demodulator.
5696 * \return int.
5697 *
5698 */
5699 static int set_vsb(struct drx_demod_instance *demod)
5700 {
5701         struct i2c_device_addr *dev_addr = NULL;
5702         int rc;
5703         struct drx_common_attr *common_attr = NULL;
5704         struct drxjscu_cmd cmd_scu;
5705         struct drxj_data *ext_attr = NULL;
5706         u16 cmd_result = 0;
5707         u16 cmd_param = 0;
5708         const u8 vsb_taps_re[] = {
5709                 DRXJ_16TO8(-2), /* re0  */
5710                 DRXJ_16TO8(4),  /* re1  */
5711                 DRXJ_16TO8(1),  /* re2  */
5712                 DRXJ_16TO8(-4), /* re3  */
5713                 DRXJ_16TO8(1),  /* re4  */
5714                 DRXJ_16TO8(4),  /* re5  */
5715                 DRXJ_16TO8(-3), /* re6  */
5716                 DRXJ_16TO8(-3), /* re7  */
5717                 DRXJ_16TO8(6),  /* re8  */
5718                 DRXJ_16TO8(1),  /* re9  */
5719                 DRXJ_16TO8(-9), /* re10 */
5720                 DRXJ_16TO8(3),  /* re11 */
5721                 DRXJ_16TO8(12), /* re12 */
5722                 DRXJ_16TO8(-9), /* re13 */
5723                 DRXJ_16TO8(-15),        /* re14 */
5724                 DRXJ_16TO8(17), /* re15 */
5725                 DRXJ_16TO8(19), /* re16 */
5726                 DRXJ_16TO8(-29),        /* re17 */
5727                 DRXJ_16TO8(-22),        /* re18 */
5728                 DRXJ_16TO8(45), /* re19 */
5729                 DRXJ_16TO8(25), /* re20 */
5730                 DRXJ_16TO8(-70),        /* re21 */
5731                 DRXJ_16TO8(-28),        /* re22 */
5732                 DRXJ_16TO8(111),        /* re23 */
5733                 DRXJ_16TO8(30), /* re24 */
5734                 DRXJ_16TO8(-201),       /* re25 */
5735                 DRXJ_16TO8(-31),        /* re26 */
5736                 DRXJ_16TO8(629) /* re27 */
5737         };
5738
5739         dev_addr = demod->my_i2c_dev_addr;
5740         common_attr = (struct drx_common_attr *) demod->my_common_attr;
5741         ext_attr = (struct drxj_data *) demod->my_ext_attr;
5742
5743         /* stop all comm_exec */
5744         rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5745         if (rc != 0) {
5746                 pr_err("error %d\n", rc);
5747                 goto rw_error;
5748         }
5749         rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5750         if (rc != 0) {
5751                 pr_err("error %d\n", rc);
5752                 goto rw_error;
5753         }
5754         rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5755         if (rc != 0) {
5756                 pr_err("error %d\n", rc);
5757                 goto rw_error;
5758         }
5759         rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5760         if (rc != 0) {
5761                 pr_err("error %d\n", rc);
5762                 goto rw_error;
5763         }
5764         rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5765         if (rc != 0) {
5766                 pr_err("error %d\n", rc);
5767                 goto rw_error;
5768         }
5769         rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5770         if (rc != 0) {
5771                 pr_err("error %d\n", rc);
5772                 goto rw_error;
5773         }
5774         rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5775         if (rc != 0) {
5776                 pr_err("error %d\n", rc);
5777                 goto rw_error;
5778         }
5779
5780         /* reset demodulator */
5781         cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
5782             | SCU_RAM_COMMAND_CMD_DEMOD_RESET;
5783         cmd_scu.parameter_len = 0;
5784         cmd_scu.result_len = 1;
5785         cmd_scu.parameter = NULL;
5786         cmd_scu.result = &cmd_result;
5787         rc = scu_command(dev_addr, &cmd_scu);
5788         if (rc != 0) {
5789                 pr_err("error %d\n", rc);
5790                 goto rw_error;
5791         }
5792
5793         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0);
5794         if (rc != 0) {
5795                 pr_err("error %d\n", rc);
5796                 goto rw_error;
5797         }
5798         rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0);
5799         if (rc != 0) {
5800                 pr_err("error %d\n", rc);
5801                 goto rw_error;
5802         }
5803         rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0);
5804         if (rc != 0) {
5805                 pr_err("error %d\n", rc);
5806                 goto rw_error;
5807         }
5808         ext_attr->iqm_rc_rate_ofs = 0x00AD0D79;
5809         rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);
5810         if (rc != 0) {
5811                 pr_err("error %d\n", rc);
5812                 goto rw_error;
5813         }
5814         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0);
5815         if (rc != 0) {
5816                 pr_err("error %d\n", rc);
5817                 goto rw_error;
5818         }
5819         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0);
5820         if (rc != 0) {
5821                 pr_err("error %d\n", rc);
5822                 goto rw_error;
5823         }
5824
5825         rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0);
5826         if (rc != 0) {
5827                 pr_err("error %d\n", rc);
5828                 goto rw_error;
5829         }
5830         rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0);
5831         if (rc != 0) {
5832                 pr_err("error %d\n", rc);
5833                 goto rw_error;
5834         }
5835         rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0);
5836         if (rc != 0) {
5837                 pr_err("error %d\n", rc);
5838                 goto rw_error;
5839         }
5840         rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
5841         if (rc != 0) {
5842                 pr_err("error %d\n", rc);
5843                 goto rw_error;
5844         }
5845         rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
5846         if (rc != 0) {
5847                 pr_err("error %d\n", rc);
5848                 goto rw_error;
5849         }
5850         rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0);
5851         if (rc != 0) {
5852                 pr_err("error %d\n", rc);
5853                 goto rw_error;
5854         }
5855         rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0);
5856         if (rc != 0) {
5857                 pr_err("error %d\n", rc);
5858                 goto rw_error;
5859         }
5860         rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
5861         if (rc != 0) {
5862                 pr_err("error %d\n", rc);
5863                 goto rw_error;
5864         }
5865         rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
5866         if (rc != 0) {
5867                 pr_err("error %d\n", rc);
5868                 goto rw_error;
5869         }
5870
5871         rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5872         if (rc != 0) {
5873                 pr_err("error %d\n", rc);
5874                 goto rw_error;
5875         }
5876         rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5877         if (rc != 0) {
5878                 pr_err("error %d\n", rc);
5879                 goto rw_error;
5880         }
5881
5882         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0);
5883         if (rc != 0) {
5884                 pr_err("error %d\n", rc);
5885                 goto rw_error;
5886         }       /* set higher threshold */
5887         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0);
5888         if (rc != 0) {
5889                 pr_err("error %d\n", rc);
5890                 goto rw_error;
5891         }       /* burst detection on   */
5892         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0);
5893         if (rc != 0) {
5894                 pr_err("error %d\n", rc);
5895                 goto rw_error;
5896         }       /* drop thresholds by 1 dB */
5897         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0);
5898         if (rc != 0) {
5899                 pr_err("error %d\n", rc);
5900                 goto rw_error;
5901         }       /* drop thresholds by 2 dB */
5902         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0);
5903         if (rc != 0) {
5904                 pr_err("error %d\n", rc);
5905                 goto rw_error;
5906         }       /* cma on               */
5907         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
5908         if (rc != 0) {
5909                 pr_err("error %d\n", rc);
5910                 goto rw_error;
5911         }       /* GPIO               */
5912
5913         /* Initialize the FEC Subsystem */
5914         rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0);
5915         if (rc != 0) {
5916                 pr_err("error %d\n", rc);
5917                 goto rw_error;
5918         }
5919         {
5920                 u16 fec_oc_snc_mode = 0;
5921                 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
5922                 if (rc != 0) {
5923                         pr_err("error %d\n", rc);
5924                         goto rw_error;
5925                 }
5926                 /* output data even when not locked */
5927                 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0);
5928                 if (rc != 0) {
5929                         pr_err("error %d\n", rc);
5930                         goto rw_error;
5931                 }
5932         }
5933
5934         /* set clip */
5935         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
5936         if (rc != 0) {
5937                 pr_err("error %d\n", rc);
5938                 goto rw_error;
5939         }
5940         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0);
5941         if (rc != 0) {
5942                 pr_err("error %d\n", rc);
5943                 goto rw_error;
5944         }
5945         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
5946         if (rc != 0) {
5947                 pr_err("error %d\n", rc);
5948                 goto rw_error;
5949         }
5950         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0);
5951         if (rc != 0) {
5952                 pr_err("error %d\n", rc);
5953                 goto rw_error;
5954         }
5955         /* no transparent, no A&C framing; parity is set in mpegoutput */
5956         {
5957                 u16 fec_oc_reg_mode = 0;
5958                 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
5959                 if (rc != 0) {
5960                         pr_err("error %d\n", rc);
5961                         goto rw_error;
5962                 }
5963                 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0);
5964                 if (rc != 0) {
5965                         pr_err("error %d\n", rc);
5966                         goto rw_error;
5967                 }
5968         }
5969
5970         rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0);
5971         if (rc != 0) {
5972                 pr_err("error %d\n", rc);
5973                 goto rw_error;
5974         }       /* timeout counter for restarting */
5975         rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0);
5976         if (rc != 0) {
5977                 pr_err("error %d\n", rc);
5978                 goto rw_error;
5979         }
5980         rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0);
5981         if (rc != 0) {
5982                 pr_err("error %d\n", rc);
5983                 goto rw_error;
5984         }       /* bypass disabled */
5985         /* initialize RS packet error measurement parameters */
5986         rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);
5987         if (rc != 0) {
5988                 pr_err("error %d\n", rc);
5989                 goto rw_error;
5990         }
5991         rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0);
5992         if (rc != 0) {
5993                 pr_err("error %d\n", rc);
5994                 goto rw_error;
5995         }
5996
5997         /* init measurement period of MER/SER */
5998         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);
5999         if (rc != 0) {
6000                 pr_err("error %d\n", rc);
6001                 goto rw_error;
6002         }
6003         rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6004         if (rc != 0) {
6005                 pr_err("error %d\n", rc);
6006                 goto rw_error;
6007         }
6008         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6009         if (rc != 0) {
6010                 pr_err("error %d\n", rc);
6011                 goto rw_error;
6012         }
6013         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6014         if (rc != 0) {
6015                 pr_err("error %d\n", rc);
6016                 goto rw_error;
6017         }
6018
6019         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0);
6020         if (rc != 0) {
6021                 pr_err("error %d\n", rc);
6022                 goto rw_error;
6023         }
6024         /* B-Input to ADC, PGA+filter in standby */
6025         if (!ext_attr->has_lna) {
6026                 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
6027                 if (rc != 0) {
6028                         pr_err("error %d\n", rc);
6029                         goto rw_error;
6030                 }
6031         }
6032
6033         /* turn on IQMAF. It has to be in front of setAgc**() */
6034         rc = set_iqm_af(demod, true);
6035         if (rc != 0) {
6036                 pr_err("error %d\n", rc);
6037                 goto rw_error;
6038         }
6039         rc = adc_synchronization(demod);
6040         if (rc != 0) {
6041                 pr_err("error %d\n", rc);
6042                 goto rw_error;
6043         }
6044
6045         rc = init_agc(demod);
6046         if (rc != 0) {
6047                 pr_err("error %d\n", rc);
6048                 goto rw_error;
6049         }
6050         rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);
6051         if (rc != 0) {
6052                 pr_err("error %d\n", rc);
6053                 goto rw_error;
6054         }
6055         rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);
6056         if (rc != 0) {
6057                 pr_err("error %d\n", rc);
6058                 goto rw_error;
6059         }
6060         {
6061                 /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
6062                    of only the gain */
6063                 struct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 };
6064
6065                 vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg;
6066                 rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg);
6067                 if (rc != 0) {
6068                         pr_err("error %d\n", rc);
6069                         goto rw_error;
6070                 }
6071         }
6072         rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));
6073         if (rc != 0) {
6074                 pr_err("error %d\n", rc);
6075                 goto rw_error;
6076         }
6077
6078         /* Mpeg output has to be in front of FEC active */
6079         rc = set_mpegtei_handling(demod);
6080         if (rc != 0) {
6081                 pr_err("error %d\n", rc);
6082                 goto rw_error;
6083         }
6084         rc = bit_reverse_mpeg_output(demod);
6085         if (rc != 0) {
6086                 pr_err("error %d\n", rc);
6087                 goto rw_error;
6088         }
6089         rc = set_mpeg_start_width(demod);
6090         if (rc != 0) {
6091                 pr_err("error %d\n", rc);
6092                 goto rw_error;
6093         }
6094         {
6095                 /* TODO: move to set_standard after hardware reset value problem is solved */
6096                 /* Configure initial MPEG output */
6097                 struct drx_cfg_mpeg_output cfg_mpeg_output;
6098
6099                 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
6100                 cfg_mpeg_output.enable_mpeg_output = true;
6101
6102                 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6103                 if (rc != 0) {
6104                         pr_err("error %d\n", rc);
6105                         goto rw_error;
6106                 }
6107         }
6108
6109         /* TBD: what parameters should be set */
6110         cmd_param = 0x00;       /* Default mode AGC on, etc */
6111         cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
6112             | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
6113         cmd_scu.parameter_len = 1;
6114         cmd_scu.result_len = 1;
6115         cmd_scu.parameter = &cmd_param;
6116         cmd_scu.result = &cmd_result;
6117         rc = scu_command(dev_addr, &cmd_scu);
6118         if (rc != 0) {
6119                 pr_err("error %d\n", rc);
6120                 goto rw_error;
6121         }
6122
6123         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0);
6124         if (rc != 0) {
6125                 pr_err("error %d\n", rc);
6126                 goto rw_error;
6127         }
6128         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0);
6129         if (rc != 0) {
6130                 pr_err("error %d\n", rc);
6131                 goto rw_error;
6132         }
6133         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0);
6134         if (rc != 0) {
6135                 pr_err("error %d\n", rc);
6136                 goto rw_error;
6137         }
6138         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0);
6139         if (rc != 0) {
6140                 pr_err("error %d\n", rc);
6141                 goto rw_error;
6142         }
6143         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0);
6144         if (rc != 0) {
6145                 pr_err("error %d\n", rc);
6146                 goto rw_error;
6147         }
6148         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0);
6149         if (rc != 0) {
6150                 pr_err("error %d\n", rc);
6151                 goto rw_error;
6152         }
6153         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0);
6154         if (rc != 0) {
6155                 pr_err("error %d\n", rc);
6156                 goto rw_error;
6157         }
6158         rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0);
6159         if (rc != 0) {
6160                 pr_err("error %d\n", rc);
6161                 goto rw_error;
6162         }
6163
6164         /* start demodulator */
6165         cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
6166             | SCU_RAM_COMMAND_CMD_DEMOD_START;
6167         cmd_scu.parameter_len = 0;
6168         cmd_scu.result_len = 1;
6169         cmd_scu.parameter = NULL;
6170         cmd_scu.result = &cmd_result;
6171         rc = scu_command(dev_addr, &cmd_scu);
6172         if (rc != 0) {
6173                 pr_err("error %d\n", rc);
6174                 goto rw_error;
6175         }
6176
6177         rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
6178         if (rc != 0) {
6179                 pr_err("error %d\n", rc);
6180                 goto rw_error;
6181         }
6182         rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0);
6183         if (rc != 0) {
6184                 pr_err("error %d\n", rc);
6185                 goto rw_error;
6186         }
6187         rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
6188         if (rc != 0) {
6189                 pr_err("error %d\n", rc);
6190                 goto rw_error;
6191         }
6192
6193         return 0;
6194 rw_error:
6195         return rc;
6196 }
6197
6198 /**
6199 * \fn static short get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *PckErrs)
6200 * \brief Get the values of packet error in 8VSB mode
6201 * \return Error code
6202 */
6203 static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr,
6204                                    u32 *pck_errs, u32 *pck_count)
6205 {
6206         int rc;
6207         u16 data = 0;
6208         u16 period = 0;
6209         u16 prescale = 0;
6210         u16 packet_errors_mant = 0;
6211         u16 packet_errors_exp = 0;
6212
6213         rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0);
6214         if (rc != 0) {
6215                 pr_err("error %d\n", rc);
6216                 goto rw_error;
6217         }
6218         packet_errors_mant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M;
6219         packet_errors_exp = (data & FEC_RS_NR_FAILURES_EXP__M)
6220             >> FEC_RS_NR_FAILURES_EXP__B;
6221         period = FEC_RS_MEASUREMENT_PERIOD;
6222         prescale = FEC_RS_MEASUREMENT_PRESCALE;
6223         /* packet error rate = (error packet number) per second */
6224         /* 77.3 us is time for per packet */
6225         if (period * prescale == 0) {
6226                 pr_err("error: period and/or prescale is zero!\n");
6227                 return -EIO;
6228         }
6229         *pck_errs = packet_errors_mant * (1 << packet_errors_exp);
6230         *pck_count = period * prescale * 77;
6231
6232         return 0;
6233 rw_error:
6234         return rc;
6235 }
6236
6237 /**
6238 * \fn static short GetVSBBer(struct i2c_device_addr *dev_addr, u32 *ber)
6239 * \brief Get the values of ber in VSB mode
6240 * \return Error code
6241 */
6242 static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr,
6243                                     u32 *ber, u32 *cnt)
6244 {
6245         int rc;
6246         u16 data = 0;
6247         u16 period = 0;
6248         u16 prescale = 0;
6249         u16 bit_errors_mant = 0;
6250         u16 bit_errors_exp = 0;
6251
6252         rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0);
6253         if (rc != 0) {
6254                 pr_err("error %d\n", rc);
6255                 goto rw_error;
6256         }
6257         period = FEC_RS_MEASUREMENT_PERIOD;
6258         prescale = FEC_RS_MEASUREMENT_PRESCALE;
6259
6260         bit_errors_mant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M;
6261         bit_errors_exp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M)
6262             >> FEC_RS_NR_BIT_ERRORS_EXP__B;
6263
6264         *cnt = period * prescale * 207 * ((bit_errors_exp > 2) ? 1 : 8);
6265
6266         if (((bit_errors_mant << bit_errors_exp) >> 3) > 68700)
6267                 *ber = (*cnt) * 26570;
6268         else {
6269                 if (period * prescale == 0) {
6270                         pr_err("error: period and/or prescale is zero!\n");
6271                         return -EIO;
6272                 }
6273                 *ber = bit_errors_mant << ((bit_errors_exp > 2) ?
6274                         (bit_errors_exp - 3) : bit_errors_exp);
6275         }
6276
6277         return 0;
6278 rw_error:
6279         return rc;
6280 }
6281
6282 /**
6283 * \fn static short get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber)
6284 * \brief Get the values of ber in VSB mode
6285 * \return Error code
6286 */
6287 static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr,
6288                                    u32 *ber, u32 *cnt)
6289 {
6290         u16 data = 0;
6291         int rc;
6292
6293         rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0);
6294         if (rc != 0) {
6295                 pr_err("error %d\n", rc);
6296                 return -EIO;
6297         }
6298         *ber = data;
6299         *cnt = VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT;
6300
6301         return 0;
6302 }
6303
6304 /**
6305 * \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
6306 * \brief Get the values of MER
6307 * \return Error code
6308 */
6309 static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
6310 {
6311         int rc;
6312         u16 data_hi = 0;
6313
6314         rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0);
6315         if (rc != 0) {
6316                 pr_err("error %d\n", rc);
6317                 goto rw_error;
6318         }
6319         *mer =
6320             (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52));
6321
6322         return 0;
6323 rw_error:
6324         return rc;
6325 }
6326
6327
6328 /*============================================================================*/
6329 /*==                     END 8VSB DATAPATH FUNCTIONS                        ==*/
6330 /*============================================================================*/
6331
6332 /*============================================================================*/
6333 /*============================================================================*/
6334 /*==                       QAM DATAPATH FUNCTIONS                           ==*/
6335 /*============================================================================*/
6336 /*============================================================================*/
6337
6338 /**
6339 * \fn int power_down_qam ()
6340 * \brief Powr down QAM related blocks.
6341 * \param demod instance of demodulator.
6342 * \param channel pointer to channel data.
6343 * \return int.
6344 */
6345 static int power_down_qam(struct drx_demod_instance *demod, bool primary)
6346 {
6347         struct drxjscu_cmd cmd_scu = { /* command      */ 0,
6348                 /* parameter_len */ 0,
6349                 /* result_len    */ 0,
6350                 /* *parameter   */ NULL,
6351                 /* *result      */ NULL
6352         };
6353         int rc;
6354         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6355         struct drx_cfg_mpeg_output cfg_mpeg_output;
6356         struct drx_common_attr *common_attr = demod->my_common_attr;
6357         u16 cmd_result = 0;
6358
6359         /*
6360            STOP demodulator
6361            resets IQM, QAM and FEC HW blocks
6362          */
6363         /* stop all comm_exec */
6364         rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
6365         if (rc != 0) {
6366                 pr_err("error %d\n", rc);
6367                 goto rw_error;
6368         }
6369         rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
6370         if (rc != 0) {
6371                 pr_err("error %d\n", rc);
6372                 goto rw_error;
6373         }
6374
6375         cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
6376             SCU_RAM_COMMAND_CMD_DEMOD_STOP;
6377         cmd_scu.parameter_len = 0;
6378         cmd_scu.result_len = 1;
6379         cmd_scu.parameter = NULL;
6380         cmd_scu.result = &cmd_result;
6381         rc = scu_command(dev_addr, &cmd_scu);
6382         if (rc != 0) {
6383                 pr_err("error %d\n", rc);
6384                 goto rw_error;
6385         }
6386
6387         if (primary) {
6388                 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
6389                 if (rc != 0) {
6390                         pr_err("error %d\n", rc);
6391                         goto rw_error;
6392                 }
6393                 rc = set_iqm_af(demod, false);
6394                 if (rc != 0) {
6395                         pr_err("error %d\n", rc);
6396                         goto rw_error;
6397                 }
6398         } else {
6399                 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
6400                 if (rc != 0) {
6401                         pr_err("error %d\n", rc);
6402                         goto rw_error;
6403                 }
6404                 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
6405                 if (rc != 0) {
6406                         pr_err("error %d\n", rc);
6407                         goto rw_error;
6408                 }
6409                 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
6410                 if (rc != 0) {
6411                         pr_err("error %d\n", rc);
6412                         goto rw_error;
6413                 }
6414                 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
6415                 if (rc != 0) {
6416                         pr_err("error %d\n", rc);
6417                         goto rw_error;
6418                 }
6419                 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
6420                 if (rc != 0) {
6421                         pr_err("error %d\n", rc);
6422                         goto rw_error;
6423                 }
6424         }
6425
6426         memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
6427         cfg_mpeg_output.enable_mpeg_output = false;
6428
6429         rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6430         if (rc != 0) {
6431                 pr_err("error %d\n", rc);
6432                 goto rw_error;
6433         }
6434
6435         return 0;
6436 rw_error:
6437         return rc;
6438 }
6439
6440 /*============================================================================*/
6441
6442 /**
6443 * \fn int set_qam_measurement ()
6444 * \brief Setup of the QAM Measuremnt intervals for signal quality
6445 * \param demod instance of demod.
6446 * \param constellation current constellation.
6447 * \return int.
6448 *
6449 *  NOTE:
6450 *  Take into account that for certain settings the errorcounters can overflow.
6451 *  The implementation does not check this.
6452 *
6453 *  TODO: overriding the ext_attr->fec_bits_desired by constellation dependent
6454 *  constants to get a measurement period of approx. 1 sec. Remove fec_bits_desired
6455 *  field ?
6456 *
6457 */
6458 #ifndef DRXJ_VSB_ONLY
6459 static int
6460 set_qam_measurement(struct drx_demod_instance *demod,
6461                     enum drx_modulation constellation, u32 symbol_rate)
6462 {
6463         struct i2c_device_addr *dev_addr = NULL;        /* device address for I2C writes */
6464         struct drxj_data *ext_attr = NULL;      /* Global data container for DRXJ specif data */
6465         int rc;
6466         u32 fec_bits_desired = 0;       /* BER accounting period */
6467         u16 fec_rs_plen = 0;    /* defines RS BER measurement period */
6468         u16 fec_rs_prescale = 0;        /* ReedSolomon Measurement Prescale */
6469         u32 fec_rs_period = 0;  /* Value for corresponding I2C register */
6470         u32 fec_rs_bit_cnt = 0; /* Actual precise amount of bits */
6471         u32 fec_oc_snc_fail_period = 0; /* Value for corresponding I2C register */
6472         u32 qam_vd_period = 0;  /* Value for corresponding I2C register */
6473         u32 qam_vd_bit_cnt = 0; /* Actual precise amount of bits */
6474         u16 fec_vd_plen = 0;    /* no of trellis symbols: VD SER measur period */
6475         u16 qam_vd_prescale = 0;        /* Viterbi Measurement Prescale */
6476
6477         dev_addr = demod->my_i2c_dev_addr;
6478         ext_attr = (struct drxj_data *) demod->my_ext_attr;
6479
6480         fec_bits_desired = ext_attr->fec_bits_desired;
6481         fec_rs_prescale = ext_attr->fec_rs_prescale;
6482
6483         switch (constellation) {
6484         case DRX_CONSTELLATION_QAM16:
6485                 fec_bits_desired = 4 * symbol_rate;
6486                 break;
6487         case DRX_CONSTELLATION_QAM32:
6488                 fec_bits_desired = 5 * symbol_rate;
6489                 break;
6490         case DRX_CONSTELLATION_QAM64:
6491                 fec_bits_desired = 6 * symbol_rate;
6492                 break;
6493         case DRX_CONSTELLATION_QAM128:
6494                 fec_bits_desired = 7 * symbol_rate;
6495                 break;
6496         case DRX_CONSTELLATION_QAM256:
6497                 fec_bits_desired = 8 * symbol_rate;
6498                 break;
6499         default:
6500                 return -EINVAL;
6501         }
6502
6503         /* Parameters for Reed-Solomon Decoder */
6504         /* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */
6505         /* rs_bit_cnt   = fecrs_period*fecrs_prescale*plen                  */
6506         /*     result is within 32 bit arithmetic ->                        */
6507         /*     no need for mult or frac functions                           */
6508
6509         /* TODO: use constant instead of calculation and remove the fec_rs_plen in ext_attr */
6510         switch (ext_attr->standard) {
6511         case DRX_STANDARD_ITU_A:
6512         case DRX_STANDARD_ITU_C:
6513                 fec_rs_plen = 204 * 8;
6514                 break;
6515         case DRX_STANDARD_ITU_B:
6516                 fec_rs_plen = 128 * 7;
6517                 break;
6518         default:
6519                 return -EINVAL;
6520         }
6521
6522         ext_attr->fec_rs_plen = fec_rs_plen;    /* for getSigQual */
6523         fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen; /* temp storage   */
6524         if (fec_rs_bit_cnt == 0) {
6525                 pr_err("error: fec_rs_bit_cnt is zero!\n");
6526                 return -EIO;
6527         }
6528         fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1;  /* ceil */
6529         if (ext_attr->standard != DRX_STANDARD_ITU_B)
6530                 fec_oc_snc_fail_period = fec_rs_period;
6531
6532         /* limit to max 16 bit value (I2C register width) if needed */
6533         if (fec_rs_period > 0xFFFF)
6534                 fec_rs_period = 0xFFFF;
6535
6536         /* write corresponding registers */
6537         switch (ext_attr->standard) {
6538         case DRX_STANDARD_ITU_A:
6539         case DRX_STANDARD_ITU_C:
6540                 break;
6541         case DRX_STANDARD_ITU_B:
6542                 switch (constellation) {
6543                 case DRX_CONSTELLATION_QAM64:
6544                         fec_rs_period = 31581;
6545                         fec_oc_snc_fail_period = 17932;
6546                         break;
6547                 case DRX_CONSTELLATION_QAM256:
6548                         fec_rs_period = 45446;
6549                         fec_oc_snc_fail_period = 25805;
6550                         break;
6551                 default:
6552                         return -EINVAL;
6553                 }
6554                 break;
6555         default:
6556                 return -EINVAL;
6557         }
6558
6559         rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0);
6560         if (rc != 0) {
6561                 pr_err("error %d\n", rc);
6562                 goto rw_error;
6563         }
6564         rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0);
6565         if (rc != 0) {
6566                 pr_err("error %d\n", rc);
6567                 goto rw_error;
6568         }
6569         rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0);
6570         if (rc != 0) {
6571                 pr_err("error %d\n", rc);
6572                 goto rw_error;
6573         }
6574         ext_attr->fec_rs_period = (u16) fec_rs_period;
6575         ext_attr->fec_rs_prescale = fec_rs_prescale;
6576         rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6577         if (rc != 0) {
6578                 pr_err("error %d\n", rc);
6579                 goto rw_error;
6580         }
6581         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6582         if (rc != 0) {
6583                 pr_err("error %d\n", rc);
6584                 goto rw_error;
6585         }
6586         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6587         if (rc != 0) {
6588                 pr_err("error %d\n", rc);
6589                 goto rw_error;
6590         }
6591
6592         if (ext_attr->standard == DRX_STANDARD_ITU_B) {
6593                 /* Parameters for Viterbi Decoder */
6594                 /* qamvd_period = (int)ceil(FEC_BITS_DESIRED/                      */
6595                 /*                    (qamvd_prescale*plen*(qam_constellation+1))) */
6596                 /* vd_bit_cnt   = qamvd_period*qamvd_prescale*plen                 */
6597                 /*     result is within 32 bit arithmetic ->                       */
6598                 /*     no need for mult or frac functions                          */
6599
6600                 /* a(8 bit) * b(8 bit) = 16 bit result => mult32 not needed */
6601                 fec_vd_plen = ext_attr->fec_vd_plen;
6602                 qam_vd_prescale = ext_attr->qam_vd_prescale;
6603                 qam_vd_bit_cnt = qam_vd_prescale * fec_vd_plen; /* temp storage */
6604
6605                 switch (constellation) {
6606                 case DRX_CONSTELLATION_QAM64:
6607                         /* a(16 bit) * b(4 bit) = 20 bit result => mult32 not needed */
6608                         qam_vd_period =
6609                             qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM64 + 1)
6610                             * (QAM_TOP_CONSTELLATION_QAM64 + 1);
6611                         break;
6612                 case DRX_CONSTELLATION_QAM256:
6613                         /* a(16 bit) * b(5 bit) = 21 bit result => mult32 not needed */
6614                         qam_vd_period =
6615                             qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM256 + 1)
6616                             * (QAM_TOP_CONSTELLATION_QAM256 + 1);
6617                         break;
6618                 default:
6619                         return -EINVAL;
6620                 }
6621                 if (qam_vd_period == 0) {
6622                         pr_err("error: qam_vd_period is zero!\n");
6623                         return -EIO;
6624                 }
6625                 qam_vd_period = fec_bits_desired / qam_vd_period;
6626                 /* limit to max 16 bit value (I2C register width) if needed */
6627                 if (qam_vd_period > 0xFFFF)
6628                         qam_vd_period = 0xFFFF;
6629
6630                 /* a(16 bit) * b(16 bit) = 32 bit result => mult32 not needed */
6631                 qam_vd_bit_cnt *= qam_vd_period;
6632
6633                 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0);
6634                 if (rc != 0) {
6635                         pr_err("error %d\n", rc);
6636                         goto rw_error;
6637                 }
6638                 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0);
6639                 if (rc != 0) {
6640                         pr_err("error %d\n", rc);
6641                         goto rw_error;
6642                 }
6643                 ext_attr->qam_vd_period = (u16) qam_vd_period;
6644                 ext_attr->qam_vd_prescale = qam_vd_prescale;
6645         }
6646
6647         return 0;
6648 rw_error:
6649         return rc;
6650 }
6651
6652 /*============================================================================*/
6653
6654 /**
6655 * \fn int set_qam16 ()
6656 * \brief QAM16 specific setup
6657 * \param demod instance of demod.
6658 * \return int.
6659 */
6660 static int set_qam16(struct drx_demod_instance *demod)
6661 {
6662         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6663         int rc;
6664         const u8 qam_dq_qual_fun[] = {
6665                 DRXJ_16TO8(2),  /* fun0  */
6666                 DRXJ_16TO8(2),  /* fun1  */
6667                 DRXJ_16TO8(2),  /* fun2  */
6668                 DRXJ_16TO8(2),  /* fun3  */
6669                 DRXJ_16TO8(3),  /* fun4  */
6670                 DRXJ_16TO8(3),  /* fun5  */
6671         };
6672         const u8 qam_eq_cma_rad[] = {
6673                 DRXJ_16TO8(13517),      /* RAD0  */
6674                 DRXJ_16TO8(13517),      /* RAD1  */
6675                 DRXJ_16TO8(13517),      /* RAD2  */
6676                 DRXJ_16TO8(13517),      /* RAD3  */
6677                 DRXJ_16TO8(13517),      /* RAD4  */
6678                 DRXJ_16TO8(13517),      /* RAD5  */
6679         };
6680
6681         rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6682         if (rc != 0) {
6683                 pr_err("error %d\n", rc);
6684                 goto rw_error;
6685         }
6686         rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6687         if (rc != 0) {
6688                 pr_err("error %d\n", rc);
6689                 goto rw_error;
6690         }
6691
6692         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0);
6693         if (rc != 0) {
6694                 pr_err("error %d\n", rc);
6695                 goto rw_error;
6696         }
6697         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6698         if (rc != 0) {
6699                 pr_err("error %d\n", rc);
6700                 goto rw_error;
6701         }
6702         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0);
6703         if (rc != 0) {
6704                 pr_err("error %d\n", rc);
6705                 goto rw_error;
6706         }
6707         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0);
6708         if (rc != 0) {
6709                 pr_err("error %d\n", rc);
6710                 goto rw_error;
6711         }
6712         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0);
6713         if (rc != 0) {
6714                 pr_err("error %d\n", rc);
6715                 goto rw_error;
6716         }
6717         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0);
6718         if (rc != 0) {
6719                 pr_err("error %d\n", rc);
6720                 goto rw_error;
6721         }
6722
6723         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6724         if (rc != 0) {
6725                 pr_err("error %d\n", rc);
6726                 goto rw_error;
6727         }
6728         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6729         if (rc != 0) {
6730                 pr_err("error %d\n", rc);
6731                 goto rw_error;
6732         }
6733         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6734         if (rc != 0) {
6735                 pr_err("error %d\n", rc);
6736                 goto rw_error;
6737         }
6738
6739         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0);
6740         if (rc != 0) {
6741                 pr_err("error %d\n", rc);
6742                 goto rw_error;
6743         }
6744         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0);
6745         if (rc != 0) {
6746                 pr_err("error %d\n", rc);
6747                 goto rw_error;
6748         }
6749         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0);
6750         if (rc != 0) {
6751                 pr_err("error %d\n", rc);
6752                 goto rw_error;
6753         }
6754         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0);
6755         if (rc != 0) {
6756                 pr_err("error %d\n", rc);
6757                 goto rw_error;
6758         }
6759         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0);
6760         if (rc != 0) {
6761                 pr_err("error %d\n", rc);
6762                 goto rw_error;
6763         }
6764         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0);
6765         if (rc != 0) {
6766                 pr_err("error %d\n", rc);
6767                 goto rw_error;
6768         }
6769         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0);
6770         if (rc != 0) {
6771                 pr_err("error %d\n", rc);
6772                 goto rw_error;
6773         }
6774
6775         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
6776         if (rc != 0) {
6777                 pr_err("error %d\n", rc);
6778                 goto rw_error;
6779         }
6780         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
6781         if (rc != 0) {
6782                 pr_err("error %d\n", rc);
6783                 goto rw_error;
6784         }
6785         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
6786         if (rc != 0) {
6787                 pr_err("error %d\n", rc);
6788                 goto rw_error;
6789         }
6790         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
6791         if (rc != 0) {
6792                 pr_err("error %d\n", rc);
6793                 goto rw_error;
6794         }
6795         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
6796         if (rc != 0) {
6797                 pr_err("error %d\n", rc);
6798                 goto rw_error;
6799         }
6800         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
6801         if (rc != 0) {
6802                 pr_err("error %d\n", rc);
6803                 goto rw_error;
6804         }
6805         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
6806         if (rc != 0) {
6807                 pr_err("error %d\n", rc);
6808                 goto rw_error;
6809         }
6810         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
6811         if (rc != 0) {
6812                 pr_err("error %d\n", rc);
6813                 goto rw_error;
6814         }
6815         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
6816         if (rc != 0) {
6817                 pr_err("error %d\n", rc);
6818                 goto rw_error;
6819         }
6820         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
6821         if (rc != 0) {
6822                 pr_err("error %d\n", rc);
6823                 goto rw_error;
6824         }
6825         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
6826         if (rc != 0) {
6827                 pr_err("error %d\n", rc);
6828                 goto rw_error;
6829         }
6830         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
6831         if (rc != 0) {
6832                 pr_err("error %d\n", rc);
6833                 goto rw_error;
6834         }
6835         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
6836         if (rc != 0) {
6837                 pr_err("error %d\n", rc);
6838                 goto rw_error;
6839         }
6840         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
6841         if (rc != 0) {
6842                 pr_err("error %d\n", rc);
6843                 goto rw_error;
6844         }
6845         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
6846         if (rc != 0) {
6847                 pr_err("error %d\n", rc);
6848                 goto rw_error;
6849         }
6850         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
6851         if (rc != 0) {
6852                 pr_err("error %d\n", rc);
6853                 goto rw_error;
6854         }
6855         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0);
6856         if (rc != 0) {
6857                 pr_err("error %d\n", rc);
6858                 goto rw_error;
6859         }
6860         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
6861         if (rc != 0) {
6862                 pr_err("error %d\n", rc);
6863                 goto rw_error;
6864         }
6865         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
6866         if (rc != 0) {
6867                 pr_err("error %d\n", rc);
6868                 goto rw_error;
6869         }
6870         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
6871         if (rc != 0) {
6872                 pr_err("error %d\n", rc);
6873                 goto rw_error;
6874         }
6875
6876         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0);
6877         if (rc != 0) {
6878                 pr_err("error %d\n", rc);
6879                 goto rw_error;
6880         }
6881
6882         return 0;
6883 rw_error:
6884         return rc;
6885 }
6886
6887 /*============================================================================*/
6888
6889 /**
6890 * \fn int set_qam32 ()
6891 * \brief QAM32 specific setup
6892 * \param demod instance of demod.
6893 * \return int.
6894 */
6895 static int set_qam32(struct drx_demod_instance *demod)
6896 {
6897         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6898         int rc;
6899         const u8 qam_dq_qual_fun[] = {
6900                 DRXJ_16TO8(3),  /* fun0  */
6901                 DRXJ_16TO8(3),  /* fun1  */
6902                 DRXJ_16TO8(3),  /* fun2  */
6903                 DRXJ_16TO8(3),  /* fun3  */
6904                 DRXJ_16TO8(4),  /* fun4  */
6905                 DRXJ_16TO8(4),  /* fun5  */
6906         };
6907         const u8 qam_eq_cma_rad[] = {
6908                 DRXJ_16TO8(6707),       /* RAD0  */
6909                 DRXJ_16TO8(6707),       /* RAD1  */
6910                 DRXJ_16TO8(6707),       /* RAD2  */
6911                 DRXJ_16TO8(6707),       /* RAD3  */
6912                 DRXJ_16TO8(6707),       /* RAD4  */
6913                 DRXJ_16TO8(6707),       /* RAD5  */
6914         };
6915
6916         rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6917         if (rc != 0) {
6918                 pr_err("error %d\n", rc);
6919                 goto rw_error;
6920         }
6921         rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6922         if (rc != 0) {
6923                 pr_err("error %d\n", rc);
6924                 goto rw_error;
6925         }
6926
6927         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0);
6928         if (rc != 0) {
6929                 pr_err("error %d\n", rc);
6930                 goto rw_error;
6931         }
6932         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6933         if (rc != 0) {
6934                 pr_err("error %d\n", rc);
6935                 goto rw_error;
6936         }
6937         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
6938         if (rc != 0) {
6939                 pr_err("error %d\n", rc);
6940                 goto rw_error;
6941         }
6942         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0);
6943         if (rc != 0) {
6944                 pr_err("error %d\n", rc);
6945                 goto rw_error;
6946         }
6947         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
6948         if (rc != 0) {
6949                 pr_err("error %d\n", rc);
6950                 goto rw_error;
6951         }
6952         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
6953         if (rc != 0) {
6954                 pr_err("error %d\n", rc);
6955                 goto rw_error;
6956         }
6957
6958         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6959         if (rc != 0) {
6960                 pr_err("error %d\n", rc);
6961                 goto rw_error;
6962         }
6963         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6964         if (rc != 0) {
6965                 pr_err("error %d\n", rc);
6966                 goto rw_error;
6967         }
6968         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6969         if (rc != 0) {
6970                 pr_err("error %d\n", rc);
6971                 goto rw_error;
6972         }
6973
6974         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
6975         if (rc != 0) {
6976                 pr_err("error %d\n", rc);
6977                 goto rw_error;
6978         }
6979         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0);
6980         if (rc != 0) {
6981                 pr_err("error %d\n", rc);
6982                 goto rw_error;
6983         }
6984         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0);
6985         if (rc != 0) {
6986                 pr_err("error %d\n", rc);
6987                 goto rw_error;
6988         }
6989         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0);
6990         if (rc != 0) {
6991                 pr_err("error %d\n", rc);
6992                 goto rw_error;
6993         }
6994         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0);
6995         if (rc != 0) {
6996                 pr_err("error %d\n", rc);
6997                 goto rw_error;
6998         }
6999         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0);
7000         if (rc != 0) {
7001                 pr_err("error %d\n", rc);
7002                 goto rw_error;
7003         }
7004         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0);
7005         if (rc != 0) {
7006                 pr_err("error %d\n", rc);
7007                 goto rw_error;
7008         }
7009
7010         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7011         if (rc != 0) {
7012                 pr_err("error %d\n", rc);
7013                 goto rw_error;
7014         }
7015         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7016         if (rc != 0) {
7017                 pr_err("error %d\n", rc);
7018                 goto rw_error;
7019         }
7020         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7021         if (rc != 0) {
7022                 pr_err("error %d\n", rc);
7023                 goto rw_error;
7024         }
7025         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
7026         if (rc != 0) {
7027                 pr_err("error %d\n", rc);
7028                 goto rw_error;
7029         }
7030         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7031         if (rc != 0) {
7032                 pr_err("error %d\n", rc);
7033                 goto rw_error;
7034         }
7035         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7036         if (rc != 0) {
7037                 pr_err("error %d\n", rc);
7038                 goto rw_error;
7039         }
7040         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
7041         if (rc != 0) {
7042                 pr_err("error %d\n", rc);
7043                 goto rw_error;
7044         }
7045         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
7046         if (rc != 0) {
7047                 pr_err("error %d\n", rc);
7048                 goto rw_error;
7049         }
7050         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7051         if (rc != 0) {
7052                 pr_err("error %d\n", rc);
7053                 goto rw_error;
7054         }
7055         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7056         if (rc != 0) {
7057                 pr_err("error %d\n", rc);
7058                 goto rw_error;
7059         }
7060         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7061         if (rc != 0) {
7062                 pr_err("error %d\n", rc);
7063                 goto rw_error;
7064         }
7065         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7066         if (rc != 0) {
7067                 pr_err("error %d\n", rc);
7068                 goto rw_error;
7069         }
7070         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7071         if (rc != 0) {
7072                 pr_err("error %d\n", rc);
7073                 goto rw_error;
7074         }
7075         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7076         if (rc != 0) {
7077                 pr_err("error %d\n", rc);
7078                 goto rw_error;
7079         }
7080         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7081         if (rc != 0) {
7082                 pr_err("error %d\n", rc);
7083                 goto rw_error;
7084         }
7085         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7086         if (rc != 0) {
7087                 pr_err("error %d\n", rc);
7088                 goto rw_error;
7089         }
7090         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0);
7091         if (rc != 0) {
7092                 pr_err("error %d\n", rc);
7093                 goto rw_error;
7094         }
7095         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7096         if (rc != 0) {
7097                 pr_err("error %d\n", rc);
7098                 goto rw_error;
7099         }
7100         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7101         if (rc != 0) {
7102                 pr_err("error %d\n", rc);
7103                 goto rw_error;
7104         }
7105         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0);
7106         if (rc != 0) {
7107                 pr_err("error %d\n", rc);
7108                 goto rw_error;
7109         }
7110
7111         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0);
7112         if (rc != 0) {
7113                 pr_err("error %d\n", rc);
7114                 goto rw_error;
7115         }
7116
7117         return 0;
7118 rw_error:
7119         return rc;
7120 }
7121
7122 /*============================================================================*/
7123
7124 /**
7125 * \fn int set_qam64 ()
7126 * \brief QAM64 specific setup
7127 * \param demod instance of demod.
7128 * \return int.
7129 */
7130 static int set_qam64(struct drx_demod_instance *demod)
7131 {
7132         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7133         int rc;
7134         const u8 qam_dq_qual_fun[] = {  /* this is hw reset value. no necessary to re-write */
7135                 DRXJ_16TO8(4),  /* fun0  */
7136                 DRXJ_16TO8(4),  /* fun1  */
7137                 DRXJ_16TO8(4),  /* fun2  */
7138                 DRXJ_16TO8(4),  /* fun3  */
7139                 DRXJ_16TO8(6),  /* fun4  */
7140                 DRXJ_16TO8(6),  /* fun5  */
7141         };
7142         const u8 qam_eq_cma_rad[] = {
7143                 DRXJ_16TO8(13336),      /* RAD0  */
7144                 DRXJ_16TO8(12618),      /* RAD1  */
7145                 DRXJ_16TO8(11988),      /* RAD2  */
7146                 DRXJ_16TO8(13809),      /* RAD3  */
7147                 DRXJ_16TO8(13809),      /* RAD4  */
7148                 DRXJ_16TO8(15609),      /* RAD5  */
7149         };
7150
7151         rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7152         if (rc != 0) {
7153                 pr_err("error %d\n", rc);
7154                 goto rw_error;
7155         }
7156         rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7157         if (rc != 0) {
7158                 pr_err("error %d\n", rc);
7159                 goto rw_error;
7160         }
7161
7162         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0);
7163         if (rc != 0) {
7164                 pr_err("error %d\n", rc);
7165                 goto rw_error;
7166         }
7167         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7168         if (rc != 0) {
7169                 pr_err("error %d\n", rc);
7170                 goto rw_error;
7171         }
7172         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7173         if (rc != 0) {
7174                 pr_err("error %d\n", rc);
7175                 goto rw_error;
7176         }
7177         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0);
7178         if (rc != 0) {
7179                 pr_err("error %d\n", rc);
7180                 goto rw_error;
7181         }
7182         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7183         if (rc != 0) {
7184                 pr_err("error %d\n", rc);
7185                 goto rw_error;
7186         }
7187         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0);
7188         if (rc != 0) {
7189                 pr_err("error %d\n", rc);
7190                 goto rw_error;
7191         }
7192
7193         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7194         if (rc != 0) {
7195                 pr_err("error %d\n", rc);
7196                 goto rw_error;
7197         }
7198         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7199         if (rc != 0) {
7200                 pr_err("error %d\n", rc);
7201                 goto rw_error;
7202         }
7203         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7204         if (rc != 0) {
7205                 pr_err("error %d\n", rc);
7206                 goto rw_error;
7207         }
7208
7209         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
7210         if (rc != 0) {
7211                 pr_err("error %d\n", rc);
7212                 goto rw_error;
7213         }
7214         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0);
7215         if (rc != 0) {
7216                 pr_err("error %d\n", rc);
7217                 goto rw_error;
7218         }
7219         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0);
7220         if (rc != 0) {
7221                 pr_err("error %d\n", rc);
7222                 goto rw_error;
7223         }
7224         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0);
7225         if (rc != 0) {
7226                 pr_err("error %d\n", rc);
7227                 goto rw_error;
7228         }
7229         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0);
7230         if (rc != 0) {
7231                 pr_err("error %d\n", rc);
7232                 goto rw_error;
7233         }
7234         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0);
7235         if (rc != 0) {
7236                 pr_err("error %d\n", rc);
7237                 goto rw_error;
7238         }
7239         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0);
7240         if (rc != 0) {
7241                 pr_err("error %d\n", rc);
7242                 goto rw_error;
7243         }
7244
7245         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7246         if (rc != 0) {
7247                 pr_err("error %d\n", rc);
7248                 goto rw_error;
7249         }
7250         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7251         if (rc != 0) {
7252                 pr_err("error %d\n", rc);
7253                 goto rw_error;
7254         }
7255         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7256         if (rc != 0) {
7257                 pr_err("error %d\n", rc);
7258                 goto rw_error;
7259         }
7260         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0);
7261         if (rc != 0) {
7262                 pr_err("error %d\n", rc);
7263                 goto rw_error;
7264         }
7265         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7266         if (rc != 0) {
7267                 pr_err("error %d\n", rc);
7268                 goto rw_error;
7269         }
7270         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7271         if (rc != 0) {
7272                 pr_err("error %d\n", rc);
7273                 goto rw_error;
7274         }
7275         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0);
7276         if (rc != 0) {
7277                 pr_err("error %d\n", rc);
7278                 goto rw_error;
7279         }
7280         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7281         if (rc != 0) {
7282                 pr_err("error %d\n", rc);
7283                 goto rw_error;
7284         }
7285         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7286         if (rc != 0) {
7287                 pr_err("error %d\n", rc);
7288                 goto rw_error;
7289         }
7290         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7291         if (rc != 0) {
7292                 pr_err("error %d\n", rc);
7293                 goto rw_error;
7294         }
7295         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7296         if (rc != 0) {
7297                 pr_err("error %d\n", rc);
7298                 goto rw_error;
7299         }
7300         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7301         if (rc != 0) {
7302                 pr_err("error %d\n", rc);
7303                 goto rw_error;
7304         }
7305         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7306         if (rc != 0) {
7307                 pr_err("error %d\n", rc);
7308                 goto rw_error;
7309         }
7310         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7311         if (rc != 0) {
7312                 pr_err("error %d\n", rc);
7313                 goto rw_error;
7314         }
7315         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7316         if (rc != 0) {
7317                 pr_err("error %d\n", rc);
7318                 goto rw_error;
7319         }
7320         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7321         if (rc != 0) {
7322                 pr_err("error %d\n", rc);
7323                 goto rw_error;
7324         }
7325         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0);
7326         if (rc != 0) {
7327                 pr_err("error %d\n", rc);
7328                 goto rw_error;
7329         }
7330         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7331         if (rc != 0) {
7332                 pr_err("error %d\n", rc);
7333                 goto rw_error;
7334         }
7335         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7336         if (rc != 0) {
7337                 pr_err("error %d\n", rc);
7338                 goto rw_error;
7339         }
7340         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
7341         if (rc != 0) {
7342                 pr_err("error %d\n", rc);
7343                 goto rw_error;
7344         }
7345
7346         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0);
7347         if (rc != 0) {
7348                 pr_err("error %d\n", rc);
7349                 goto rw_error;
7350         }
7351
7352         return 0;
7353 rw_error:
7354         return rc;
7355 }
7356
7357 /*============================================================================*/
7358
7359 /**
7360 * \fn int set_qam128 ()
7361 * \brief QAM128 specific setup
7362 * \param demod: instance of demod.
7363 * \return int.
7364 */
7365 static int set_qam128(struct drx_demod_instance *demod)
7366 {
7367         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7368         int rc;
7369         const u8 qam_dq_qual_fun[] = {
7370                 DRXJ_16TO8(6),  /* fun0  */
7371                 DRXJ_16TO8(6),  /* fun1  */
7372                 DRXJ_16TO8(6),  /* fun2  */
7373                 DRXJ_16TO8(6),  /* fun3  */
7374                 DRXJ_16TO8(9),  /* fun4  */
7375                 DRXJ_16TO8(9),  /* fun5  */
7376         };
7377         const u8 qam_eq_cma_rad[] = {
7378                 DRXJ_16TO8(6164),       /* RAD0  */
7379                 DRXJ_16TO8(6598),       /* RAD1  */
7380                 DRXJ_16TO8(6394),       /* RAD2  */
7381                 DRXJ_16TO8(6409),       /* RAD3  */
7382                 DRXJ_16TO8(6656),       /* RAD4  */
7383                 DRXJ_16TO8(7238),       /* RAD5  */
7384         };
7385
7386         rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7387         if (rc != 0) {
7388                 pr_err("error %d\n", rc);
7389                 goto rw_error;
7390         }
7391         rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7392         if (rc != 0) {
7393                 pr_err("error %d\n", rc);
7394                 goto rw_error;
7395         }
7396
7397         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7398         if (rc != 0) {
7399                 pr_err("error %d\n", rc);
7400                 goto rw_error;
7401         }
7402         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7403         if (rc != 0) {
7404                 pr_err("error %d\n", rc);
7405                 goto rw_error;
7406         }
7407         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7408         if (rc != 0) {
7409                 pr_err("error %d\n", rc);
7410                 goto rw_error;
7411         }
7412         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0);
7413         if (rc != 0) {
7414                 pr_err("error %d\n", rc);
7415                 goto rw_error;
7416         }
7417         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7418         if (rc != 0) {
7419                 pr_err("error %d\n", rc);
7420                 goto rw_error;
7421         }
7422         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
7423         if (rc != 0) {
7424                 pr_err("error %d\n", rc);
7425                 goto rw_error;
7426         }
7427
7428         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7429         if (rc != 0) {
7430                 pr_err("error %d\n", rc);
7431                 goto rw_error;
7432         }
7433         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7434         if (rc != 0) {
7435                 pr_err("error %d\n", rc);
7436                 goto rw_error;
7437         }
7438         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7439         if (rc != 0) {
7440                 pr_err("error %d\n", rc);
7441                 goto rw_error;
7442         }
7443
7444         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7445         if (rc != 0) {
7446                 pr_err("error %d\n", rc);
7447                 goto rw_error;
7448         }
7449         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0);
7450         if (rc != 0) {
7451                 pr_err("error %d\n", rc);
7452                 goto rw_error;
7453         }
7454         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0);
7455         if (rc != 0) {
7456                 pr_err("error %d\n", rc);
7457                 goto rw_error;
7458         }
7459         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0);
7460         if (rc != 0) {
7461                 pr_err("error %d\n", rc);
7462                 goto rw_error;
7463         }
7464         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0);
7465         if (rc != 0) {
7466                 pr_err("error %d\n", rc);
7467                 goto rw_error;
7468         }
7469         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0);
7470         if (rc != 0) {
7471                 pr_err("error %d\n", rc);
7472                 goto rw_error;
7473         }
7474         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0);
7475         if (rc != 0) {
7476                 pr_err("error %d\n", rc);
7477                 goto rw_error;
7478         }
7479
7480         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7481         if (rc != 0) {
7482                 pr_err("error %d\n", rc);
7483                 goto rw_error;
7484         }
7485         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7486         if (rc != 0) {
7487                 pr_err("error %d\n", rc);
7488                 goto rw_error;
7489         }
7490         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7491         if (rc != 0) {
7492                 pr_err("error %d\n", rc);
7493                 goto rw_error;
7494         }
7495         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0);
7496         if (rc != 0) {
7497                 pr_err("error %d\n", rc);
7498                 goto rw_error;
7499         }
7500         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7501         if (rc != 0) {
7502                 pr_err("error %d\n", rc);
7503                 goto rw_error;
7504         }
7505         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7506         if (rc != 0) {
7507                 pr_err("error %d\n", rc);
7508                 goto rw_error;
7509         }
7510         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0);
7511         if (rc != 0) {
7512                 pr_err("error %d\n", rc);
7513                 goto rw_error;
7514         }
7515         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7516         if (rc != 0) {
7517                 pr_err("error %d\n", rc);
7518                 goto rw_error;
7519         }
7520         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7521         if (rc != 0) {
7522                 pr_err("error %d\n", rc);
7523                 goto rw_error;
7524         }
7525         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7526         if (rc != 0) {
7527                 pr_err("error %d\n", rc);
7528                 goto rw_error;
7529         }
7530         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7531         if (rc != 0) {
7532                 pr_err("error %d\n", rc);
7533                 goto rw_error;
7534         }
7535         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7536         if (rc != 0) {
7537                 pr_err("error %d\n", rc);
7538                 goto rw_error;
7539         }
7540         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7541         if (rc != 0) {
7542                 pr_err("error %d\n", rc);
7543                 goto rw_error;
7544         }
7545         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7546         if (rc != 0) {
7547                 pr_err("error %d\n", rc);
7548                 goto rw_error;
7549         }
7550         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7551         if (rc != 0) {
7552                 pr_err("error %d\n", rc);
7553                 goto rw_error;
7554         }
7555         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7556         if (rc != 0) {
7557                 pr_err("error %d\n", rc);
7558                 goto rw_error;
7559         }
7560         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0);
7561         if (rc != 0) {
7562                 pr_err("error %d\n", rc);
7563                 goto rw_error;
7564         }
7565         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7566         if (rc != 0) {
7567                 pr_err("error %d\n", rc);
7568                 goto rw_error;
7569         }
7570         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7571         if (rc != 0) {
7572                 pr_err("error %d\n", rc);
7573                 goto rw_error;
7574         }
7575         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7576         if (rc != 0) {
7577                 pr_err("error %d\n", rc);
7578                 goto rw_error;
7579         }
7580
7581         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0);
7582         if (rc != 0) {
7583                 pr_err("error %d\n", rc);
7584                 goto rw_error;
7585         }
7586
7587         return 0;
7588 rw_error:
7589         return rc;
7590 }
7591
7592 /*============================================================================*/
7593
7594 /**
7595 * \fn int set_qam256 ()
7596 * \brief QAM256 specific setup
7597 * \param demod: instance of demod.
7598 * \return int.
7599 */
7600 static int set_qam256(struct drx_demod_instance *demod)
7601 {
7602         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7603         int rc;
7604         const u8 qam_dq_qual_fun[] = {
7605                 DRXJ_16TO8(8),  /* fun0  */
7606                 DRXJ_16TO8(8),  /* fun1  */
7607                 DRXJ_16TO8(8),  /* fun2  */
7608                 DRXJ_16TO8(8),  /* fun3  */
7609                 DRXJ_16TO8(12), /* fun4  */
7610                 DRXJ_16TO8(12), /* fun5  */
7611         };
7612         const u8 qam_eq_cma_rad[] = {
7613                 DRXJ_16TO8(12345),      /* RAD0  */
7614                 DRXJ_16TO8(12345),      /* RAD1  */
7615                 DRXJ_16TO8(13626),      /* RAD2  */
7616                 DRXJ_16TO8(12931),      /* RAD3  */
7617                 DRXJ_16TO8(14719),      /* RAD4  */
7618                 DRXJ_16TO8(15356),      /* RAD5  */
7619         };
7620
7621         rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7622         if (rc != 0) {
7623                 pr_err("error %d\n", rc);
7624                 goto rw_error;
7625         }
7626         rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7627         if (rc != 0) {
7628                 pr_err("error %d\n", rc);
7629                 goto rw_error;
7630         }
7631
7632         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7633         if (rc != 0) {
7634                 pr_err("error %d\n", rc);
7635                 goto rw_error;
7636         }
7637         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7638         if (rc != 0) {
7639                 pr_err("error %d\n", rc);
7640                 goto rw_error;
7641         }
7642         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7643         if (rc != 0) {
7644                 pr_err("error %d\n", rc);
7645                 goto rw_error;
7646         }
7647         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0);
7648         if (rc != 0) {
7649                 pr_err("error %d\n", rc);
7650                 goto rw_error;
7651         }
7652         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7653         if (rc != 0) {
7654                 pr_err("error %d\n", rc);
7655                 goto rw_error;
7656         }
7657         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0);
7658         if (rc != 0) {
7659                 pr_err("error %d\n", rc);
7660                 goto rw_error;
7661         }
7662
7663         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7664         if (rc != 0) {
7665                 pr_err("error %d\n", rc);
7666                 goto rw_error;
7667         }
7668         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0);
7669         if (rc != 0) {
7670                 pr_err("error %d\n", rc);
7671                 goto rw_error;
7672         }
7673         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7674         if (rc != 0) {
7675                 pr_err("error %d\n", rc);
7676                 goto rw_error;
7677         }
7678
7679         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7680         if (rc != 0) {
7681                 pr_err("error %d\n", rc);
7682                 goto rw_error;
7683         }
7684         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0);
7685         if (rc != 0) {
7686                 pr_err("error %d\n", rc);
7687                 goto rw_error;
7688         }
7689         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0);
7690         if (rc != 0) {
7691                 pr_err("error %d\n", rc);
7692                 goto rw_error;
7693         }
7694         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0);
7695         if (rc != 0) {
7696                 pr_err("error %d\n", rc);
7697                 goto rw_error;
7698         }
7699         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0);
7700         if (rc != 0) {
7701                 pr_err("error %d\n", rc);
7702                 goto rw_error;
7703         }
7704         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0);
7705         if (rc != 0) {
7706                 pr_err("error %d\n", rc);
7707                 goto rw_error;
7708         }
7709         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0);
7710         if (rc != 0) {
7711                 pr_err("error %d\n", rc);
7712                 goto rw_error;
7713         }
7714
7715         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7716         if (rc != 0) {
7717                 pr_err("error %d\n", rc);
7718                 goto rw_error;
7719         }
7720         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7721         if (rc != 0) {
7722                 pr_err("error %d\n", rc);
7723                 goto rw_error;
7724         }
7725         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7726         if (rc != 0) {
7727                 pr_err("error %d\n", rc);
7728                 goto rw_error;
7729         }
7730         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0);
7731         if (rc != 0) {
7732                 pr_err("error %d\n", rc);
7733                 goto rw_error;
7734         }
7735         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7736         if (rc != 0) {
7737                 pr_err("error %d\n", rc);
7738                 goto rw_error;
7739         }
7740         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7741         if (rc != 0) {
7742                 pr_err("error %d\n", rc);
7743                 goto rw_error;
7744         }
7745         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0);
7746         if (rc != 0) {
7747                 pr_err("error %d\n", rc);
7748                 goto rw_error;
7749         }
7750         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7751         if (rc != 0) {
7752                 pr_err("error %d\n", rc);
7753                 goto rw_error;
7754         }
7755         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7756         if (rc != 0) {
7757                 pr_err("error %d\n", rc);
7758                 goto rw_error;
7759         }
7760         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7761         if (rc != 0) {
7762                 pr_err("error %d\n", rc);
7763                 goto rw_error;
7764         }
7765         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7766         if (rc != 0) {
7767                 pr_err("error %d\n", rc);
7768                 goto rw_error;
7769         }
7770         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7771         if (rc != 0) {
7772                 pr_err("error %d\n", rc);
7773                 goto rw_error;
7774         }
7775         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7776         if (rc != 0) {
7777                 pr_err("error %d\n", rc);
7778                 goto rw_error;
7779         }
7780         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7781         if (rc != 0) {
7782                 pr_err("error %d\n", rc);
7783                 goto rw_error;
7784         }
7785         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7786         if (rc != 0) {
7787                 pr_err("error %d\n", rc);
7788                 goto rw_error;
7789         }
7790         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7791         if (rc != 0) {
7792                 pr_err("error %d\n", rc);
7793                 goto rw_error;
7794         }
7795         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0);
7796         if (rc != 0) {
7797                 pr_err("error %d\n", rc);
7798                 goto rw_error;
7799         }
7800         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7801         if (rc != 0) {
7802                 pr_err("error %d\n", rc);
7803                 goto rw_error;
7804         }
7805         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7806         if (rc != 0) {
7807                 pr_err("error %d\n", rc);
7808                 goto rw_error;
7809         }
7810         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7811         if (rc != 0) {
7812                 pr_err("error %d\n", rc);
7813                 goto rw_error;
7814         }
7815
7816         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0);
7817         if (rc != 0) {
7818                 pr_err("error %d\n", rc);
7819                 goto rw_error;
7820         }
7821
7822         return 0;
7823 rw_error:
7824         return rc;
7825 }
7826
7827 /*============================================================================*/
7828 #define QAM_SET_OP_ALL 0x1
7829 #define QAM_SET_OP_CONSTELLATION 0x2
7830 #define QAM_SET_OP_SPECTRUM 0X4
7831
7832 /**
7833 * \fn int set_qam ()
7834 * \brief Set QAM demod.
7835 * \param demod:   instance of demod.
7836 * \param channel: pointer to channel data.
7837 * \return int.
7838 */
7839 static int
7840 set_qam(struct drx_demod_instance *demod,
7841         struct drx_channel *channel, s32 tuner_freq_offset, u32 op)
7842 {
7843         struct i2c_device_addr *dev_addr = NULL;
7844         struct drxj_data *ext_attr = NULL;
7845         struct drx_common_attr *common_attr = NULL;
7846         int rc;
7847         u32 adc_frequency = 0;
7848         u32 iqm_rc_rate = 0;
7849         u16 cmd_result = 0;
7850         u16 lc_symbol_freq = 0;
7851         u16 iqm_rc_stretch = 0;
7852         u16 set_env_parameters = 0;
7853         u16 set_param_parameters[2] = { 0 };
7854         struct drxjscu_cmd cmd_scu = { /* command      */ 0,
7855                 /* parameter_len */ 0,
7856                 /* result_len    */ 0,
7857                 /* parameter    */ NULL,
7858                 /* result       */ NULL
7859         };
7860         const u8 qam_a_taps[] = {
7861                 DRXJ_16TO8(-1), /* re0  */
7862                 DRXJ_16TO8(1),  /* re1  */
7863                 DRXJ_16TO8(1),  /* re2  */
7864                 DRXJ_16TO8(-1), /* re3  */
7865                 DRXJ_16TO8(-1), /* re4  */
7866                 DRXJ_16TO8(2),  /* re5  */
7867                 DRXJ_16TO8(1),  /* re6  */
7868                 DRXJ_16TO8(-2), /* re7  */
7869                 DRXJ_16TO8(0),  /* re8  */
7870                 DRXJ_16TO8(3),  /* re9  */
7871                 DRXJ_16TO8(-1), /* re10 */
7872                 DRXJ_16TO8(-3), /* re11 */
7873                 DRXJ_16TO8(4),  /* re12 */
7874                 DRXJ_16TO8(1),  /* re13 */
7875                 DRXJ_16TO8(-8), /* re14 */
7876                 DRXJ_16TO8(4),  /* re15 */
7877                 DRXJ_16TO8(13), /* re16 */
7878                 DRXJ_16TO8(-13),        /* re17 */
7879                 DRXJ_16TO8(-19),        /* re18 */
7880                 DRXJ_16TO8(28), /* re19 */
7881                 DRXJ_16TO8(25), /* re20 */
7882                 DRXJ_16TO8(-53),        /* re21 */
7883                 DRXJ_16TO8(-31),        /* re22 */
7884                 DRXJ_16TO8(96), /* re23 */
7885                 DRXJ_16TO8(37), /* re24 */
7886                 DRXJ_16TO8(-190),       /* re25 */
7887                 DRXJ_16TO8(-40),        /* re26 */
7888                 DRXJ_16TO8(619) /* re27 */
7889         };
7890         const u8 qam_b64_taps[] = {
7891                 DRXJ_16TO8(0),  /* re0  */
7892                 DRXJ_16TO8(-2), /* re1  */
7893                 DRXJ_16TO8(1),  /* re2  */
7894                 DRXJ_16TO8(2),  /* re3  */
7895                 DRXJ_16TO8(-2), /* re4  */
7896                 DRXJ_16TO8(0),  /* re5  */
7897                 DRXJ_16TO8(4),  /* re6  */
7898                 DRXJ_16TO8(-2), /* re7  */
7899                 DRXJ_16TO8(-4), /* re8  */
7900                 DRXJ_16TO8(4),  /* re9  */
7901                 DRXJ_16TO8(3),  /* re10 */
7902                 DRXJ_16TO8(-6), /* re11 */
7903                 DRXJ_16TO8(0),  /* re12 */
7904                 DRXJ_16TO8(6),  /* re13 */
7905                 DRXJ_16TO8(-5), /* re14 */
7906                 DRXJ_16TO8(-3), /* re15 */
7907                 DRXJ_16TO8(11), /* re16 */
7908                 DRXJ_16TO8(-4), /* re17 */
7909                 DRXJ_16TO8(-19),        /* re18 */
7910                 DRXJ_16TO8(19), /* re19 */
7911                 DRXJ_16TO8(28), /* re20 */
7912                 DRXJ_16TO8(-45),        /* re21 */
7913                 DRXJ_16TO8(-36),        /* re22 */
7914                 DRXJ_16TO8(90), /* re23 */
7915                 DRXJ_16TO8(42), /* re24 */
7916                 DRXJ_16TO8(-185),       /* re25 */
7917                 DRXJ_16TO8(-46),        /* re26 */
7918                 DRXJ_16TO8(614) /* re27 */
7919         };
7920         const u8 qam_b256_taps[] = {
7921                 DRXJ_16TO8(-2), /* re0  */
7922                 DRXJ_16TO8(4),  /* re1  */
7923                 DRXJ_16TO8(1),  /* re2  */
7924                 DRXJ_16TO8(-4), /* re3  */
7925                 DRXJ_16TO8(0),  /* re4  */
7926                 DRXJ_16TO8(4),  /* re5  */
7927                 DRXJ_16TO8(-2), /* re6  */
7928                 DRXJ_16TO8(-4), /* re7  */
7929                 DRXJ_16TO8(5),  /* re8  */
7930                 DRXJ_16TO8(2),  /* re9  */
7931                 DRXJ_16TO8(-8), /* re10 */
7932                 DRXJ_16TO8(2),  /* re11 */
7933                 DRXJ_16TO8(11), /* re12 */
7934                 DRXJ_16TO8(-8), /* re13 */
7935                 DRXJ_16TO8(-15),        /* re14 */
7936                 DRXJ_16TO8(16), /* re15 */
7937                 DRXJ_16TO8(19), /* re16 */
7938                 DRXJ_16TO8(-27),        /* re17 */
7939                 DRXJ_16TO8(-22),        /* re18 */
7940                 DRXJ_16TO8(44), /* re19 */
7941                 DRXJ_16TO8(26), /* re20 */
7942                 DRXJ_16TO8(-69),        /* re21 */
7943                 DRXJ_16TO8(-28),        /* re22 */
7944                 DRXJ_16TO8(110),        /* re23 */
7945                 DRXJ_16TO8(31), /* re24 */
7946                 DRXJ_16TO8(-201),       /* re25 */
7947                 DRXJ_16TO8(-32),        /* re26 */
7948                 DRXJ_16TO8(628) /* re27 */
7949         };
7950         const u8 qam_c_taps[] = {
7951                 DRXJ_16TO8(-3), /* re0  */
7952                 DRXJ_16TO8(3),  /* re1  */
7953                 DRXJ_16TO8(2),  /* re2  */
7954                 DRXJ_16TO8(-4), /* re3  */
7955                 DRXJ_16TO8(0),  /* re4  */
7956                 DRXJ_16TO8(4),  /* re5  */
7957                 DRXJ_16TO8(-1), /* re6  */
7958                 DRXJ_16TO8(-4), /* re7  */
7959                 DRXJ_16TO8(3),  /* re8  */
7960                 DRXJ_16TO8(3),  /* re9  */
7961                 DRXJ_16TO8(-5), /* re10 */
7962                 DRXJ_16TO8(0),  /* re11 */
7963                 DRXJ_16TO8(9),  /* re12 */
7964                 DRXJ_16TO8(-4), /* re13 */
7965                 DRXJ_16TO8(-12),        /* re14 */
7966                 DRXJ_16TO8(10), /* re15 */
7967                 DRXJ_16TO8(16), /* re16 */
7968                 DRXJ_16TO8(-21),        /* re17 */
7969                 DRXJ_16TO8(-20),        /* re18 */
7970                 DRXJ_16TO8(37), /* re19 */
7971                 DRXJ_16TO8(25), /* re20 */
7972                 DRXJ_16TO8(-62),        /* re21 */
7973                 DRXJ_16TO8(-28),        /* re22 */
7974                 DRXJ_16TO8(105),        /* re23 */
7975                 DRXJ_16TO8(31), /* re24 */
7976                 DRXJ_16TO8(-197),       /* re25 */
7977                 DRXJ_16TO8(-33),        /* re26 */
7978                 DRXJ_16TO8(626) /* re27 */
7979         };
7980
7981         dev_addr = demod->my_i2c_dev_addr;
7982         ext_attr = (struct drxj_data *) demod->my_ext_attr;
7983         common_attr = (struct drx_common_attr *) demod->my_common_attr;
7984
7985         if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
7986                 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
7987                         switch (channel->constellation) {
7988                         case DRX_CONSTELLATION_QAM256:
7989                                 iqm_rc_rate = 0x00AE3562;
7990                                 lc_symbol_freq =
7991                                     QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256;
7992                                 channel->symbolrate = 5360537;
7993                                 iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_256;
7994                                 break;
7995                         case DRX_CONSTELLATION_QAM64:
7996                                 iqm_rc_rate = 0x00C05A0E;
7997                                 lc_symbol_freq = 409;
7998                                 channel->symbolrate = 5056941;
7999                                 iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_64;
8000                                 break;
8001                         default:
8002                                 return -EINVAL;
8003                         }
8004                 } else {
8005                         adc_frequency = (common_attr->sys_clock_freq * 1000) / 3;
8006                         if (channel->symbolrate == 0) {
8007                                 pr_err("error: channel symbolrate is zero!\n");
8008                                 return -EIO;
8009                         }
8010                         iqm_rc_rate =
8011                             (adc_frequency / channel->symbolrate) * (1 << 21) +
8012                             (frac28
8013                              ((adc_frequency % channel->symbolrate),
8014                               channel->symbolrate) >> 7) - (1 << 23);
8015                         lc_symbol_freq =
8016                             (u16) (frac28
8017                                      (channel->symbolrate +
8018                                       (adc_frequency >> 13),
8019                                       adc_frequency) >> 16);
8020                         if (lc_symbol_freq > 511)
8021                                 lc_symbol_freq = 511;
8022
8023                         iqm_rc_stretch = 21;
8024                 }
8025
8026                 if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8027                         set_env_parameters = QAM_TOP_ANNEX_A;   /* annex             */
8028                         set_param_parameters[0] = channel->constellation;       /* constellation     */
8029                         set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17;   /* interleave mode   */
8030                 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8031                         set_env_parameters = QAM_TOP_ANNEX_B;   /* annex             */
8032                         set_param_parameters[0] = channel->constellation;       /* constellation     */
8033                         set_param_parameters[1] = channel->interleavemode;      /* interleave mode   */
8034                 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8035                         set_env_parameters = QAM_TOP_ANNEX_C;   /* annex             */
8036                         set_param_parameters[0] = channel->constellation;       /* constellation     */
8037                         set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17;   /* interleave mode   */
8038                 } else {
8039                         return -EINVAL;
8040                 }
8041         }
8042
8043         if (op & QAM_SET_OP_ALL) {
8044                 /*
8045                    STEP 1: reset demodulator
8046                    resets IQM, QAM and FEC HW blocks
8047                    resets SCU variables
8048                  */
8049                 /* stop all comm_exec */
8050                 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
8051                 if (rc != 0) {
8052                         pr_err("error %d\n", rc);
8053                         goto rw_error;
8054                 }
8055                 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
8056                 if (rc != 0) {
8057                         pr_err("error %d\n", rc);
8058                         goto rw_error;
8059                 }
8060                 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
8061                 if (rc != 0) {
8062                         pr_err("error %d\n", rc);
8063                         goto rw_error;
8064                 }
8065                 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
8066                 if (rc != 0) {
8067                         pr_err("error %d\n", rc);
8068                         goto rw_error;
8069                 }
8070                 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
8071                 if (rc != 0) {
8072                         pr_err("error %d\n", rc);
8073                         goto rw_error;
8074                 }
8075                 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
8076                 if (rc != 0) {
8077                         pr_err("error %d\n", rc);
8078                         goto rw_error;
8079                 }
8080                 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
8081                 if (rc != 0) {
8082                         pr_err("error %d\n", rc);
8083                         goto rw_error;
8084                 }
8085
8086                 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8087                     SCU_RAM_COMMAND_CMD_DEMOD_RESET;
8088                 cmd_scu.parameter_len = 0;
8089                 cmd_scu.result_len = 1;
8090                 cmd_scu.parameter = NULL;
8091                 cmd_scu.result = &cmd_result;
8092                 rc = scu_command(dev_addr, &cmd_scu);
8093                 if (rc != 0) {
8094                         pr_err("error %d\n", rc);
8095                         goto rw_error;
8096                 }
8097         }
8098
8099         if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8100                 /*
8101                    STEP 2: configure demodulator
8102                    -set env
8103                    -set params (resets IQM,QAM,FEC HW; initializes some SCU variables )
8104                  */
8105                 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8106                     SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
8107                 cmd_scu.parameter_len = 1;
8108                 cmd_scu.result_len = 1;
8109                 cmd_scu.parameter = &set_env_parameters;
8110                 cmd_scu.result = &cmd_result;
8111                 rc = scu_command(dev_addr, &cmd_scu);
8112                 if (rc != 0) {
8113                         pr_err("error %d\n", rc);
8114                         goto rw_error;
8115                 }
8116
8117                 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8118                     SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
8119                 cmd_scu.parameter_len = 2;
8120                 cmd_scu.result_len = 1;
8121                 cmd_scu.parameter = set_param_parameters;
8122                 cmd_scu.result = &cmd_result;
8123                 rc = scu_command(dev_addr, &cmd_scu);
8124                 if (rc != 0) {
8125                         pr_err("error %d\n", rc);
8126                         goto rw_error;
8127                 }
8128                 /* set symbol rate */
8129                 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0);
8130                 if (rc != 0) {
8131                         pr_err("error %d\n", rc);
8132                         goto rw_error;
8133                 }
8134                 ext_attr->iqm_rc_rate_ofs = iqm_rc_rate;
8135                 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate);
8136                 if (rc != 0) {
8137                         pr_err("error %d\n", rc);
8138                         goto rw_error;
8139                 }
8140         }
8141         /* STEP 3: enable the system in a mode where the ADC provides valid signal
8142            setup constellation independent registers */
8143         /* from qam_cmd.py script (qam_driver_b) */
8144         /* TODO: remove re-writes of HW reset values */
8145         if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) {
8146                 rc = set_frequency(demod, channel, tuner_freq_offset);
8147                 if (rc != 0) {
8148                         pr_err("error %d\n", rc);
8149                         goto rw_error;
8150                 }
8151         }
8152
8153         if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8154
8155                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0);
8156                 if (rc != 0) {
8157                         pr_err("error %d\n", rc);
8158                         goto rw_error;
8159                 }
8160                 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0);
8161                 if (rc != 0) {
8162                         pr_err("error %d\n", rc);
8163                         goto rw_error;
8164                 }
8165         }
8166
8167         if (op & QAM_SET_OP_ALL) {
8168                 if (!ext_attr->has_lna) {
8169                         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
8170                         if (rc != 0) {
8171                                 pr_err("error %d\n", rc);
8172                                 goto rw_error;
8173                         }
8174                 }
8175                 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
8176                 if (rc != 0) {
8177                         pr_err("error %d\n", rc);
8178                         goto rw_error;
8179                 }
8180                 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
8181                 if (rc != 0) {
8182                         pr_err("error %d\n", rc);
8183                         goto rw_error;
8184                 }
8185                 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0);
8186                 if (rc != 0) {
8187                         pr_err("error %d\n", rc);
8188                         goto rw_error;
8189                 }
8190
8191                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0);
8192                 if (rc != 0) {
8193                         pr_err("error %d\n", rc);
8194                         goto rw_error;
8195                 }       /* scu temporary shut down agc */
8196
8197                 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0);
8198                 if (rc != 0) {
8199                         pr_err("error %d\n", rc);
8200                         goto rw_error;
8201                 }
8202                 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
8203                 if (rc != 0) {
8204                         pr_err("error %d\n", rc);
8205                         goto rw_error;
8206                 }
8207                 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0);
8208                 if (rc != 0) {
8209                         pr_err("error %d\n", rc);
8210                         goto rw_error;
8211                 }
8212                 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
8213                 if (rc != 0) {
8214                         pr_err("error %d\n", rc);
8215                         goto rw_error;
8216                 }
8217                 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0);
8218                 if (rc != 0) {
8219                         pr_err("error %d\n", rc);
8220                         goto rw_error;
8221                 }
8222                 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0);
8223                 if (rc != 0) {
8224                         pr_err("error %d\n", rc);
8225                         goto rw_error;
8226                 }
8227                 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0);
8228                 if (rc != 0) {
8229                         pr_err("error %d\n", rc);
8230                         goto rw_error;
8231                 }
8232
8233                 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
8234                 if (rc != 0) {
8235                         pr_err("error %d\n", rc);
8236                         goto rw_error;
8237                 }
8238                 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0);
8239                 if (rc != 0) {
8240                         pr_err("error %d\n", rc);
8241                         goto rw_error;
8242                 }       /*! reset default val ! */
8243
8244                 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0);
8245                 if (rc != 0) {
8246                         pr_err("error %d\n", rc);
8247                         goto rw_error;
8248                 }       /*! reset default val ! */
8249                 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8250                         rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0);
8251                         if (rc != 0) {
8252                                 pr_err("error %d\n", rc);
8253                                 goto rw_error;
8254                         }       /*! reset default val ! */
8255                         rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0);
8256                         if (rc != 0) {
8257                                 pr_err("error %d\n", rc);
8258                                 goto rw_error;
8259                         }       /*! reset default val ! */
8260                         rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8261                         if (rc != 0) {
8262                                 pr_err("error %d\n", rc);
8263                                 goto rw_error;
8264                         }       /*! reset default val ! */
8265                 } else {
8266                         switch (channel->constellation) {
8267                         case DRX_CONSTELLATION_QAM16:
8268                         case DRX_CONSTELLATION_QAM64:
8269                         case DRX_CONSTELLATION_QAM256:
8270                                 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8271                                 if (rc != 0) {
8272                                         pr_err("error %d\n", rc);
8273                                         goto rw_error;
8274                                 }
8275                                 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0);
8276                                 if (rc != 0) {
8277                                         pr_err("error %d\n", rc);
8278                                         goto rw_error;
8279                                 }
8280                                 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8281                                 if (rc != 0) {
8282                                         pr_err("error %d\n", rc);
8283                                         goto rw_error;
8284                                 }       /*! reset default val ! */
8285                                 break;
8286                         case DRX_CONSTELLATION_QAM32:
8287                         case DRX_CONSTELLATION_QAM128:
8288                                 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8289                                 if (rc != 0) {
8290                                         pr_err("error %d\n", rc);
8291                                         goto rw_error;
8292                                 }
8293                                 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0);
8294                                 if (rc != 0) {
8295                                         pr_err("error %d\n", rc);
8296                                         goto rw_error;
8297                                 }
8298                                 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0);
8299                                 if (rc != 0) {
8300                                         pr_err("error %d\n", rc);
8301                                         goto rw_error;
8302                                 }
8303                                 break;
8304                         default:
8305                                 return -EIO;
8306                         }       /* switch */
8307                 }
8308
8309                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0);
8310                 if (rc != 0) {
8311                         pr_err("error %d\n", rc);
8312                         goto rw_error;
8313                 }       /*! reset default val ! */
8314                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0);
8315                 if (rc != 0) {
8316                         pr_err("error %d\n", rc);
8317                         goto rw_error;
8318                 }
8319                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0);
8320                 if (rc != 0) {
8321                         pr_err("error %d\n", rc);
8322                         goto rw_error;
8323                 }
8324                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0);
8325                 if (rc != 0) {
8326                         pr_err("error %d\n", rc);
8327                         goto rw_error;
8328                 }
8329                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0);
8330                 if (rc != 0) {
8331                         pr_err("error %d\n", rc);
8332                         goto rw_error;
8333                 }
8334                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0);
8335                 if (rc != 0) {
8336                         pr_err("error %d\n", rc);
8337                         goto rw_error;
8338                 }
8339                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0);
8340                 if (rc != 0) {
8341                         pr_err("error %d\n", rc);
8342                         goto rw_error;
8343                 }
8344                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0);
8345                 if (rc != 0) {
8346                         pr_err("error %d\n", rc);
8347                         goto rw_error;
8348                 }
8349                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0);
8350                 if (rc != 0) {
8351                         pr_err("error %d\n", rc);
8352                         goto rw_error;
8353                 }
8354                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0);
8355                 if (rc != 0) {
8356                         pr_err("error %d\n", rc);
8357                         goto rw_error;
8358                 }
8359                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0);
8360                 if (rc != 0) {
8361                         pr_err("error %d\n", rc);
8362                         goto rw_error;
8363                 }
8364                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0);
8365                 if (rc != 0) {
8366                         pr_err("error %d\n", rc);
8367                         goto rw_error;
8368                 }
8369                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0);
8370                 if (rc != 0) {
8371                         pr_err("error %d\n", rc);
8372                         goto rw_error;
8373                 }
8374                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0);
8375                 if (rc != 0) {
8376                         pr_err("error %d\n", rc);
8377                         goto rw_error;
8378                 }
8379                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0);
8380                 if (rc != 0) {
8381                         pr_err("error %d\n", rc);
8382                         goto rw_error;
8383                 }
8384                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0);
8385                 if (rc != 0) {
8386                         pr_err("error %d\n", rc);
8387                         goto rw_error;
8388                 }
8389                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0);
8390                 if (rc != 0) {
8391                         pr_err("error %d\n", rc);
8392                         goto rw_error;
8393                 }
8394                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0);
8395                 if (rc != 0) {
8396                         pr_err("error %d\n", rc);
8397                         goto rw_error;
8398                 }
8399                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0);
8400                 if (rc != 0) {
8401                         pr_err("error %d\n", rc);
8402                         goto rw_error;
8403                 }
8404                 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0);
8405                 if (rc != 0) {
8406                         pr_err("error %d\n", rc);
8407                         goto rw_error;
8408                 }
8409
8410                 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0);
8411                 if (rc != 0) {
8412                         pr_err("error %d\n", rc);
8413                         goto rw_error;
8414                 }
8415                 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0);
8416                 if (rc != 0) {
8417                         pr_err("error %d\n", rc);
8418                         goto rw_error;
8419                 }
8420                 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0);
8421                 if (rc != 0) {
8422                         pr_err("error %d\n", rc);
8423                         goto rw_error;
8424                 }
8425                 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0);
8426                 if (rc != 0) {
8427                         pr_err("error %d\n", rc);
8428                         goto rw_error;
8429                 }
8430                 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
8431                 if (rc != 0) {
8432                         pr_err("error %d\n", rc);
8433                         goto rw_error;
8434                 }
8435
8436                 /* No more resets of the IQM, current standard correctly set =>
8437                    now AGCs can be configured. */
8438                 /* turn on IQMAF. It has to be in front of setAgc**() */
8439                 rc = set_iqm_af(demod, true);
8440                 if (rc != 0) {
8441                         pr_err("error %d\n", rc);
8442                         goto rw_error;
8443                 }
8444                 rc = adc_synchronization(demod);
8445                 if (rc != 0) {
8446                         pr_err("error %d\n", rc);
8447                         goto rw_error;
8448                 }
8449
8450                 rc = init_agc(demod);
8451                 if (rc != 0) {
8452                         pr_err("error %d\n", rc);
8453                         goto rw_error;
8454                 }
8455                 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false);
8456                 if (rc != 0) {
8457                         pr_err("error %d\n", rc);
8458                         goto rw_error;
8459                 }
8460                 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false);
8461                 if (rc != 0) {
8462                         pr_err("error %d\n", rc);
8463                         goto rw_error;
8464                 }
8465                 {
8466                         /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
8467                            of only the gain */
8468                         struct drxj_cfg_afe_gain qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 };
8469
8470                         qam_pga_cfg.gain = ext_attr->qam_pga_cfg;
8471                         rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg);
8472                         if (rc != 0) {
8473                                 pr_err("error %d\n", rc);
8474                                 goto rw_error;
8475                         }
8476                 }
8477                 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg));
8478                 if (rc != 0) {
8479                         pr_err("error %d\n", rc);
8480                         goto rw_error;
8481                 }
8482         }
8483
8484         if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8485                 if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8486                         rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8487                         if (rc != 0) {
8488                                 pr_err("error %d\n", rc);
8489                                 goto rw_error;
8490                         }
8491                         rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8492                         if (rc != 0) {
8493                                 pr_err("error %d\n", rc);
8494                                 goto rw_error;
8495                         }
8496                 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8497                         switch (channel->constellation) {
8498                         case DRX_CONSTELLATION_QAM64:
8499                                 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8500                                 if (rc != 0) {
8501                                         pr_err("error %d\n", rc);
8502                                         goto rw_error;
8503                                 }
8504                                 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8505                                 if (rc != 0) {
8506                                         pr_err("error %d\n", rc);
8507                                         goto rw_error;
8508                                 }
8509                                 break;
8510                         case DRX_CONSTELLATION_QAM256:
8511                                 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8512                                 if (rc != 0) {
8513                                         pr_err("error %d\n", rc);
8514                                         goto rw_error;
8515                                 }
8516                                 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8517                                 if (rc != 0) {
8518                                         pr_err("error %d\n", rc);
8519                                         goto rw_error;
8520                                 }
8521                                 break;
8522                         default:
8523                                 return -EIO;
8524                         }
8525                 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8526                         rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8527                         if (rc != 0) {
8528                                 pr_err("error %d\n", rc);
8529                                 goto rw_error;
8530                         }
8531                         rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8532                         if (rc != 0) {
8533                                 pr_err("error %d\n", rc);
8534                                 goto rw_error;
8535                         }
8536                 }
8537
8538                 /* SETP 4: constellation specific setup */
8539                 switch (channel->constellation) {
8540                 case DRX_CONSTELLATION_QAM16:
8541                         rc = set_qam16(demod);
8542                         if (rc != 0) {
8543                                 pr_err("error %d\n", rc);
8544                                 goto rw_error;
8545                         }
8546                         break;
8547                 case DRX_CONSTELLATION_QAM32:
8548                         rc = set_qam32(demod);
8549                         if (rc != 0) {
8550                                 pr_err("error %d\n", rc);
8551                                 goto rw_error;
8552                         }
8553                         break;
8554                 case DRX_CONSTELLATION_QAM64:
8555                         rc = set_qam64(demod);
8556                         if (rc != 0) {
8557                                 pr_err("error %d\n", rc);
8558                                 goto rw_error;
8559                         }
8560                         break;
8561                 case DRX_CONSTELLATION_QAM128:
8562                         rc = set_qam128(demod);
8563                         if (rc != 0) {
8564                                 pr_err("error %d\n", rc);
8565                                 goto rw_error;
8566                         }
8567                         break;
8568                 case DRX_CONSTELLATION_QAM256:
8569                         rc = set_qam256(demod);
8570                         if (rc != 0) {
8571                                 pr_err("error %d\n", rc);
8572                                 goto rw_error;
8573                         }
8574                         break;
8575                 default:
8576                         return -EIO;
8577                 }               /* switch */
8578         }
8579
8580         if ((op & QAM_SET_OP_ALL)) {
8581                 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
8582                 if (rc != 0) {
8583                         pr_err("error %d\n", rc);
8584                         goto rw_error;
8585                 }
8586
8587                 /* Mpeg output has to be in front of FEC active */
8588                 rc = set_mpegtei_handling(demod);
8589                 if (rc != 0) {
8590                         pr_err("error %d\n", rc);
8591                         goto rw_error;
8592                 }
8593                 rc = bit_reverse_mpeg_output(demod);
8594                 if (rc != 0) {
8595                         pr_err("error %d\n", rc);
8596                         goto rw_error;
8597                 }
8598                 rc = set_mpeg_start_width(demod);
8599                 if (rc != 0) {
8600                         pr_err("error %d\n", rc);
8601                         goto rw_error;
8602                 }
8603                 {
8604                         /* TODO: move to set_standard after hardware reset value problem is solved */
8605                         /* Configure initial MPEG output */
8606                         struct drx_cfg_mpeg_output cfg_mpeg_output;
8607
8608                         memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
8609                         cfg_mpeg_output.enable_mpeg_output = true;
8610
8611                         rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
8612                         if (rc != 0) {
8613                                 pr_err("error %d\n", rc);
8614                                 goto rw_error;
8615                         }
8616                 }
8617         }
8618
8619         if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8620
8621                 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
8622                 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8623                     SCU_RAM_COMMAND_CMD_DEMOD_START;
8624                 cmd_scu.parameter_len = 0;
8625                 cmd_scu.result_len = 1;
8626                 cmd_scu.parameter = NULL;
8627                 cmd_scu.result = &cmd_result;
8628                 rc = scu_command(dev_addr, &cmd_scu);
8629                 if (rc != 0) {
8630                         pr_err("error %d\n", rc);
8631                         goto rw_error;
8632                 }
8633         }
8634
8635         rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
8636         if (rc != 0) {
8637                 pr_err("error %d\n", rc);
8638                 goto rw_error;
8639         }
8640         rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0);
8641         if (rc != 0) {
8642                 pr_err("error %d\n", rc);
8643                 goto rw_error;
8644         }
8645         rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
8646         if (rc != 0) {
8647                 pr_err("error %d\n", rc);
8648                 goto rw_error;
8649         }
8650
8651         return 0;
8652 rw_error:
8653         return rc;
8654 }
8655
8656 /*============================================================================*/
8657 static int ctrl_get_qam_sig_quality(struct drx_demod_instance *demod);
8658
8659 static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel)
8660 {
8661         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
8662         struct drxj_data *ext_attr = demod->my_ext_attr;
8663         int rc;
8664         u32 iqm_fs_rate_ofs = 0;
8665         u32 iqm_fs_rate_lo = 0;
8666         u16 qam_ctl_ena = 0;
8667         u16 data = 0;
8668         u16 equ_mode = 0;
8669         u16 fsm_state = 0;
8670         int i = 0;
8671         int ofsofs = 0;
8672
8673         /* Silence the controlling of lc, equ, and the acquisition state machine */
8674         rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);
8675         if (rc != 0) {
8676                 pr_err("error %d\n", rc);
8677                 goto rw_error;
8678         }
8679         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0);
8680         if (rc != 0) {
8681                 pr_err("error %d\n", rc);
8682                 goto rw_error;
8683         }
8684
8685         /* freeze the frequency control loop */
8686         rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0);
8687         if (rc != 0) {
8688                 pr_err("error %d\n", rc);
8689                 goto rw_error;
8690         }
8691         rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0);
8692         if (rc != 0) {
8693                 pr_err("error %d\n", rc);
8694                 goto rw_error;
8695         }
8696
8697         rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0);
8698         if (rc != 0) {
8699                 pr_err("error %d\n", rc);
8700                 goto rw_error;
8701         }
8702         rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0);
8703         if (rc != 0) {
8704                 pr_err("error %d\n", rc);
8705                 goto rw_error;
8706         }
8707         ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs;
8708         iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
8709         iqm_fs_rate_ofs -= 2 * ofsofs;
8710
8711         /* freeze dq/fq updating */
8712         rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8713         if (rc != 0) {
8714                 pr_err("error %d\n", rc);
8715                 goto rw_error;
8716         }
8717         data = (data & 0xfff9);
8718         rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8719         if (rc != 0) {
8720                 pr_err("error %d\n", rc);
8721                 goto rw_error;
8722         }
8723         rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8724         if (rc != 0) {
8725                 pr_err("error %d\n", rc);
8726                 goto rw_error;
8727         }
8728
8729         /* lc_cp / _ci / _ca */
8730         rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0);
8731         if (rc != 0) {
8732                 pr_err("error %d\n", rc);
8733                 goto rw_error;
8734         }
8735         rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0);
8736         if (rc != 0) {
8737                 pr_err("error %d\n", rc);
8738                 goto rw_error;
8739         }
8740         rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0);
8741         if (rc != 0) {
8742                 pr_err("error %d\n", rc);
8743                 goto rw_error;
8744         }
8745
8746         /* flip the spec */
8747         rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
8748         if (rc != 0) {
8749                 pr_err("error %d\n", rc);
8750                 goto rw_error;
8751         }
8752         ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
8753         ext_attr->pos_image = (ext_attr->pos_image) ? false : true;
8754
8755         /* freeze dq/fq updating */
8756         rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8757         if (rc != 0) {
8758                 pr_err("error %d\n", rc);
8759                 goto rw_error;
8760         }
8761         equ_mode = data;
8762         data = (data & 0xfff9);
8763         rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8764         if (rc != 0) {
8765                 pr_err("error %d\n", rc);
8766                 goto rw_error;
8767         }
8768         rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8769         if (rc != 0) {
8770                 pr_err("error %d\n", rc);
8771                 goto rw_error;
8772         }
8773
8774         for (i = 0; i < 28; i++) {
8775                 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8776                 if (rc != 0) {
8777                         pr_err("error %d\n", rc);
8778                         goto rw_error;
8779                 }
8780                 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8781                 if (rc != 0) {
8782                         pr_err("error %d\n", rc);
8783                         goto rw_error;
8784                 }
8785         }
8786
8787         for (i = 0; i < 24; i++) {
8788                 rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8789                 if (rc != 0) {
8790                         pr_err("error %d\n", rc);
8791                         goto rw_error;
8792                 }
8793                 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8794                 if (rc != 0) {
8795                         pr_err("error %d\n", rc);
8796                         goto rw_error;
8797                 }
8798         }
8799
8800         data = equ_mode;
8801         rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8802         if (rc != 0) {
8803                 pr_err("error %d\n", rc);
8804                 goto rw_error;
8805         }
8806         rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8807         if (rc != 0) {
8808                 pr_err("error %d\n", rc);
8809                 goto rw_error;
8810         }
8811
8812         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0);
8813         if (rc != 0) {
8814                 pr_err("error %d\n", rc);
8815                 goto rw_error;
8816         }
8817
8818         i = 0;
8819         while ((fsm_state != 4) && (i++ < 100)) {
8820                 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0);
8821                 if (rc != 0) {
8822                         pr_err("error %d\n", rc);
8823                         goto rw_error;
8824                 }
8825         }
8826         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0);
8827         if (rc != 0) {
8828                 pr_err("error %d\n", rc);
8829                 goto rw_error;
8830         }
8831
8832         return 0;
8833 rw_error:
8834         return rc;
8835
8836 }
8837
8838 #define  NO_LOCK        0x0
8839 #define  DEMOD_LOCKED   0x1
8840 #define  SYNC_FLIPPED   0x2
8841 #define  SPEC_MIRRORED  0x4
8842 /**
8843 * \fn int qam64auto ()
8844 * \brief auto do sync pattern switching and mirroring.
8845 * \param demod:   instance of demod.
8846 * \param channel: pointer to channel data.
8847 * \param tuner_freq_offset: tuner frequency offset.
8848 * \param lock_status: pointer to lock status.
8849 * \return int.
8850 */
8851 static int
8852 qam64auto(struct drx_demod_instance *demod,
8853           struct drx_channel *channel,
8854           s32 tuner_freq_offset, enum drx_lock_status *lock_status)
8855 {
8856         struct drxj_data *ext_attr = demod->my_ext_attr;
8857         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
8858         struct drx39xxj_state *state = dev_addr->user_data;
8859         struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
8860         int rc;
8861         u32 lck_state = NO_LOCK;
8862         u32 start_time = 0;
8863         u32 d_locked_time = 0;
8864         u32 timeout_ofs = 0;
8865         u16 data = 0;
8866
8867         /* external attributes for storing aquired channel constellation */
8868         *lock_status = DRX_NOT_LOCKED;
8869         start_time = jiffies_to_msecs(jiffies);
8870         lck_state = NO_LOCK;
8871         do {
8872                 rc = ctrl_lock_status(demod, lock_status);
8873                 if (rc != 0) {
8874                         pr_err("error %d\n", rc);
8875                         goto rw_error;
8876                 }
8877
8878                 switch (lck_state) {
8879                 case NO_LOCK:
8880                         if (*lock_status == DRXJ_DEMOD_LOCK) {
8881                                 rc = ctrl_get_qam_sig_quality(demod);
8882                                 if (rc != 0) {
8883                                         pr_err("error %d\n", rc);
8884                                         goto rw_error;
8885                                 }
8886                                 if (p->cnr.stat[0].svalue > 20800) {
8887                                         lck_state = DEMOD_LOCKED;
8888                                         /* some delay to see if fec_lock possible TODO find the right value */
8889                                         timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME;        /* see something, waiting longer */
8890                                         d_locked_time = jiffies_to_msecs(jiffies);
8891                                 }
8892                         }
8893                         break;
8894                 case DEMOD_LOCKED:
8895                         if ((*lock_status == DRXJ_DEMOD_LOCK) &&        /* still demod_lock in 150ms */
8896                             ((jiffies_to_msecs(jiffies) - d_locked_time) >
8897                              DRXJ_QAM_FEC_LOCK_WAITTIME)) {
8898                                 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8899                                 if (rc != 0) {
8900                                         pr_err("error %d\n", rc);
8901                                         goto rw_error;
8902                                 }
8903                                 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8904                                 if (rc != 0) {
8905                                         pr_err("error %d\n", rc);
8906                                         goto rw_error;
8907                                 }
8908                                 lck_state = SYNC_FLIPPED;
8909                                 msleep(10);
8910                         }
8911                         break;
8912                 case SYNC_FLIPPED:
8913                         if (*lock_status == DRXJ_DEMOD_LOCK) {
8914                                 if (channel->mirror == DRX_MIRROR_AUTO) {
8915                                         /* flip sync pattern back */
8916                                         rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8917                                         if (rc != 0) {
8918                                                 pr_err("error %d\n", rc);
8919                                                 goto rw_error;
8920                                         }
8921                                         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0);
8922                                         if (rc != 0) {
8923                                                 pr_err("error %d\n", rc);
8924                                                 goto rw_error;
8925                                         }
8926                                         /* flip spectrum */
8927                                         ext_attr->mirror = DRX_MIRROR_YES;
8928                                         rc = qam_flip_spec(demod, channel);
8929                                         if (rc != 0) {
8930                                                 pr_err("error %d\n", rc);
8931                                                 goto rw_error;
8932                                         }
8933                                         lck_state = SPEC_MIRRORED;
8934                                         /* reset timer TODO: still need 500ms? */
8935                                         start_time = d_locked_time =
8936                                             jiffies_to_msecs(jiffies);
8937                                         timeout_ofs = 0;
8938                                 } else {        /* no need to wait lock */
8939
8940                                         start_time =
8941                                             jiffies_to_msecs(jiffies) -
8942                                             DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
8943                                 }
8944                         }
8945                         break;
8946                 case SPEC_MIRRORED:
8947                         if ((*lock_status == DRXJ_DEMOD_LOCK) &&        /* still demod_lock in 150ms */
8948                             ((jiffies_to_msecs(jiffies) - d_locked_time) >
8949                              DRXJ_QAM_FEC_LOCK_WAITTIME)) {
8950                                 rc = ctrl_get_qam_sig_quality(demod);
8951                                 if (rc != 0) {
8952                                         pr_err("error %d\n", rc);
8953                                         goto rw_error;
8954                                 }
8955                                 if (p->cnr.stat[0].svalue > 20800) {
8956                                         rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8957                                         if (rc != 0) {
8958                                                 pr_err("error %d\n", rc);
8959                                                 goto rw_error;
8960                                         }
8961                                         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8962                                         if (rc != 0) {
8963                                                 pr_err("error %d\n", rc);
8964                                                 goto rw_error;
8965                                         }
8966                                         /* no need to wait lock */
8967                                         start_time =
8968                                             jiffies_to_msecs(jiffies) -
8969                                             DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
8970                                 }
8971                         }
8972                         break;
8973                 default:
8974                         break;
8975                 }
8976                 msleep(10);
8977         } while
8978             ((*lock_status != DRX_LOCKED) &&
8979              (*lock_status != DRX_NEVER_LOCK) &&
8980              ((jiffies_to_msecs(jiffies) - start_time) <
8981               (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))
8982             );
8983         /* Returning control to apllication ... */
8984
8985         return 0;
8986 rw_error:
8987         return rc;
8988 }
8989
8990 /**
8991 * \fn int qam256auto ()
8992 * \brief auto do sync pattern switching and mirroring.
8993 * \param demod:   instance of demod.
8994 * \param channel: pointer to channel data.
8995 * \param tuner_freq_offset: tuner frequency offset.
8996 * \param lock_status: pointer to lock status.
8997 * \return int.
8998 */
8999 static int
9000 qam256auto(struct drx_demod_instance *demod,
9001            struct drx_channel *channel,
9002            s32 tuner_freq_offset, enum drx_lock_status *lock_status)
9003 {
9004         struct drxj_data *ext_attr = demod->my_ext_attr;
9005         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9006         struct drx39xxj_state *state = dev_addr->user_data;
9007         struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
9008         int rc;
9009         u32 lck_state = NO_LOCK;
9010         u32 start_time = 0;
9011         u32 d_locked_time = 0;
9012         u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME;
9013
9014         /* external attributes for storing aquired channel constellation */
9015         *lock_status = DRX_NOT_LOCKED;
9016         start_time = jiffies_to_msecs(jiffies);
9017         lck_state = NO_LOCK;
9018         do {
9019                 rc = ctrl_lock_status(demod, lock_status);
9020                 if (rc != 0) {
9021                         pr_err("error %d\n", rc);
9022                         goto rw_error;
9023                 }
9024                 switch (lck_state) {
9025                 case NO_LOCK:
9026                         if (*lock_status == DRXJ_DEMOD_LOCK) {
9027                                 rc = ctrl_get_qam_sig_quality(demod);
9028                                 if (rc != 0) {
9029                                         pr_err("error %d\n", rc);
9030                                         goto rw_error;
9031                                 }
9032                                 if (p->cnr.stat[0].svalue > 26800) {
9033                                         lck_state = DEMOD_LOCKED;
9034                                         timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME;        /* see something, wait longer */
9035                                         d_locked_time = jiffies_to_msecs(jiffies);
9036                                 }
9037                         }
9038                         break;
9039                 case DEMOD_LOCKED:
9040                         if (*lock_status == DRXJ_DEMOD_LOCK) {
9041                                 if ((channel->mirror == DRX_MIRROR_AUTO) &&
9042                                     ((jiffies_to_msecs(jiffies) - d_locked_time) >
9043                                      DRXJ_QAM_FEC_LOCK_WAITTIME)) {
9044                                         ext_attr->mirror = DRX_MIRROR_YES;
9045                                         rc = qam_flip_spec(demod, channel);
9046                                         if (rc != 0) {
9047                                                 pr_err("error %d\n", rc);
9048                                                 goto rw_error;
9049                                         }
9050                                         lck_state = SPEC_MIRRORED;
9051                                         /* reset timer TODO: still need 300ms? */
9052                                         start_time = jiffies_to_msecs(jiffies);
9053                                         timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2;
9054                                 }
9055                         }
9056                         break;
9057                 case SPEC_MIRRORED:
9058                         break;
9059                 default:
9060                         break;
9061                 }
9062                 msleep(10);
9063         } while
9064             ((*lock_status < DRX_LOCKED) &&
9065              (*lock_status != DRX_NEVER_LOCK) &&
9066              ((jiffies_to_msecs(jiffies) - start_time) <
9067               (DRXJ_QAM_MAX_WAITTIME + timeout_ofs)));
9068
9069         return 0;
9070 rw_error:
9071         return rc;
9072 }
9073
9074 /**
9075 * \fn int set_qam_channel ()
9076 * \brief Set QAM channel according to the requested constellation.
9077 * \param demod:   instance of demod.
9078 * \param channel: pointer to channel data.
9079 * \return int.
9080 */
9081 static int
9082 set_qam_channel(struct drx_demod_instance *demod,
9083                struct drx_channel *channel, s32 tuner_freq_offset)
9084 {
9085         struct drxj_data *ext_attr = NULL;
9086         int rc;
9087         enum drx_lock_status lock_status = DRX_NOT_LOCKED;
9088         bool auto_flag = false;
9089
9090         /* external attributes for storing aquired channel constellation */
9091         ext_attr = (struct drxj_data *) demod->my_ext_attr;
9092
9093         /* set QAM channel constellation */
9094         switch (channel->constellation) {
9095         case DRX_CONSTELLATION_QAM16:
9096         case DRX_CONSTELLATION_QAM32:
9097         case DRX_CONSTELLATION_QAM128:
9098                 return -EINVAL;
9099         case DRX_CONSTELLATION_QAM64:
9100         case DRX_CONSTELLATION_QAM256:
9101                 if (ext_attr->standard != DRX_STANDARD_ITU_B)
9102                         return -EINVAL;
9103
9104                 ext_attr->constellation = channel->constellation;
9105                 if (channel->mirror == DRX_MIRROR_AUTO)
9106                         ext_attr->mirror = DRX_MIRROR_NO;
9107                 else
9108                         ext_attr->mirror = channel->mirror;
9109
9110                 rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL);
9111                 if (rc != 0) {
9112                         pr_err("error %d\n", rc);
9113                         goto rw_error;
9114                 }
9115
9116                 if (channel->constellation == DRX_CONSTELLATION_QAM64)
9117                         rc = qam64auto(demod, channel, tuner_freq_offset,
9118                                        &lock_status);
9119                 else
9120                         rc = qam256auto(demod, channel, tuner_freq_offset,
9121                                         &lock_status);
9122                 if (rc != 0) {
9123                         pr_err("error %d\n", rc);
9124                         goto rw_error;
9125                 }
9126                 break;
9127         case DRX_CONSTELLATION_AUTO:    /* for channel scan */
9128                 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9129                         u16 qam_ctl_ena = 0;
9130
9131                         auto_flag = true;
9132
9133                         /* try to lock default QAM constellation: QAM256 */
9134                         channel->constellation = DRX_CONSTELLATION_QAM256;
9135                         ext_attr->constellation = DRX_CONSTELLATION_QAM256;
9136                         if (channel->mirror == DRX_MIRROR_AUTO)
9137                                 ext_attr->mirror = DRX_MIRROR_NO;
9138                         else
9139                                 ext_attr->mirror = channel->mirror;
9140                         rc = set_qam(demod, channel, tuner_freq_offset,
9141                                      QAM_SET_OP_ALL);
9142                         if (rc != 0) {
9143                                 pr_err("error %d\n", rc);
9144                                 goto rw_error;
9145                         }
9146                         rc = qam256auto(demod, channel, tuner_freq_offset,
9147                                         &lock_status);
9148                         if (rc != 0) {
9149                                 pr_err("error %d\n", rc);
9150                                 goto rw_error;
9151                         }
9152
9153                         if (lock_status >= DRX_LOCKED) {
9154                                 channel->constellation = DRX_CONSTELLATION_AUTO;
9155                                 break;
9156                         }
9157
9158                         /* QAM254 not locked. Try QAM64 constellation */
9159                         channel->constellation = DRX_CONSTELLATION_QAM64;
9160                         ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9161                         if (channel->mirror == DRX_MIRROR_AUTO)
9162                                 ext_attr->mirror = DRX_MIRROR_NO;
9163                         else
9164                                 ext_attr->mirror = channel->mirror;
9165
9166                         rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9167                                                      SCU_RAM_QAM_CTL_ENA__A,
9168                                                      &qam_ctl_ena, 0);
9169                         if (rc != 0) {
9170                                 pr_err("error %d\n", rc);
9171                                 goto rw_error;
9172                         }
9173                         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9174                                                       SCU_RAM_QAM_CTL_ENA__A,
9175                                                       qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
9176                         if (rc != 0) {
9177                                 pr_err("error %d\n", rc);
9178                                 goto rw_error;
9179                         }
9180                         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9181                                                       SCU_RAM_QAM_FSM_STATE_TGT__A,
9182                                                       0x2, 0);
9183                         if (rc != 0) {
9184                                 pr_err("error %d\n", rc);
9185                                 goto rw_error;
9186                         }       /* force to rate hunting */
9187
9188                         rc = set_qam(demod, channel, tuner_freq_offset,
9189                                      QAM_SET_OP_CONSTELLATION);
9190                         if (rc != 0) {
9191                                 pr_err("error %d\n", rc);
9192                                 goto rw_error;
9193                         }
9194                         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9195                                                       SCU_RAM_QAM_CTL_ENA__A,
9196                                                       qam_ctl_ena, 0);
9197                         if (rc != 0) {
9198                                 pr_err("error %d\n", rc);
9199                                 goto rw_error;
9200                         }
9201
9202                         rc = qam64auto(demod, channel, tuner_freq_offset,
9203                                        &lock_status);
9204                         if (rc != 0) {
9205                                 pr_err("error %d\n", rc);
9206                                 goto rw_error;
9207                         }
9208
9209                         channel->constellation = DRX_CONSTELLATION_AUTO;
9210                 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
9211                         u16 qam_ctl_ena = 0;
9212
9213                         channel->constellation = DRX_CONSTELLATION_QAM64;
9214                         ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9215                         auto_flag = true;
9216
9217                         if (channel->mirror == DRX_MIRROR_AUTO)
9218                                 ext_attr->mirror = DRX_MIRROR_NO;
9219                         else
9220                                 ext_attr->mirror = channel->mirror;
9221                         rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9222                                                      SCU_RAM_QAM_CTL_ENA__A,
9223                                                      &qam_ctl_ena, 0);
9224                         if (rc != 0) {
9225                                 pr_err("error %d\n", rc);
9226                                 goto rw_error;
9227                         }
9228                         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9229                                                       SCU_RAM_QAM_CTL_ENA__A,
9230                                                       qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
9231                         if (rc != 0) {
9232                                 pr_err("error %d\n", rc);
9233                                 goto rw_error;
9234                         }
9235                         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9236                                                       SCU_RAM_QAM_FSM_STATE_TGT__A,
9237                                                       0x2, 0);
9238                         if (rc != 0) {
9239                                 pr_err("error %d\n", rc);
9240                                 goto rw_error;
9241                         }       /* force to rate hunting */
9242
9243                         rc = set_qam(demod, channel, tuner_freq_offset,
9244                                      QAM_SET_OP_CONSTELLATION);
9245                         if (rc != 0) {
9246                                 pr_err("error %d\n", rc);
9247                                 goto rw_error;
9248                         }
9249                         rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9250                                                       SCU_RAM_QAM_CTL_ENA__A,
9251                                                       qam_ctl_ena, 0);
9252                         if (rc != 0) {
9253                                 pr_err("error %d\n", rc);
9254                                 goto rw_error;
9255                         }
9256                         rc = qam64auto(demod, channel, tuner_freq_offset,
9257                                        &lock_status);
9258                         if (rc != 0) {
9259                                 pr_err("error %d\n", rc);
9260                                 goto rw_error;
9261                         }
9262                         channel->constellation = DRX_CONSTELLATION_AUTO;
9263                 } else {
9264                         return -EINVAL;
9265                 }
9266                 break;
9267         default:
9268                 return -EINVAL;
9269         }
9270
9271         return 0;
9272 rw_error:
9273         /* restore starting value */
9274         if (auto_flag)
9275                 channel->constellation = DRX_CONSTELLATION_AUTO;
9276         return rc;
9277 }
9278
9279 /*============================================================================*/
9280
9281 /**
9282 * \fn static short get_qamrs_err_count(struct i2c_device_addr *dev_addr)
9283 * \brief Get RS error count in QAM mode (used for post RS BER calculation)
9284 * \return Error code
9285 *
9286 * precondition: measurement period & measurement prescale must be set
9287 *
9288 */
9289 static int
9290 get_qamrs_err_count(struct i2c_device_addr *dev_addr,
9291                     struct drxjrs_errors *rs_errors)
9292 {
9293         int rc;
9294         u16 nr_bit_errors = 0,
9295             nr_symbol_errors = 0,
9296             nr_packet_errors = 0, nr_failures = 0, nr_snc_par_fail_count = 0;
9297
9298         /* check arguments */
9299         if (dev_addr == NULL)
9300                 return -EINVAL;
9301
9302         /* all reported errors are received in the  */
9303         /* most recently finished measurment period */
9304         /*   no of pre RS bit errors */
9305         rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0);
9306         if (rc != 0) {
9307                 pr_err("error %d\n", rc);
9308                 goto rw_error;
9309         }
9310         /*   no of symbol errors      */
9311         rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0);
9312         if (rc != 0) {
9313                 pr_err("error %d\n", rc);
9314                 goto rw_error;
9315         }
9316         /*   no of packet errors      */
9317         rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0);
9318         if (rc != 0) {
9319                 pr_err("error %d\n", rc);
9320                 goto rw_error;
9321         }
9322         /*   no of failures to decode */
9323         rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0);
9324         if (rc != 0) {
9325                 pr_err("error %d\n", rc);
9326                 goto rw_error;
9327         }
9328         /*   no of post RS bit erros  */
9329         rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0);
9330         if (rc != 0) {
9331                 pr_err("error %d\n", rc);
9332                 goto rw_error;
9333         }
9334         /* TODO: NOTE */
9335         /* These register values are fetched in non-atomic fashion           */
9336         /* It is possible that the read values contain unrelated information */
9337
9338         rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M;
9339         rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M;
9340         rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M;
9341         rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M;
9342         rs_errors->nr_snc_par_fail_count =
9343             nr_snc_par_fail_count & FEC_OC_SNC_FAIL_COUNT__M;
9344
9345         return 0;
9346 rw_error:
9347         return rc;
9348 }
9349
9350 /*============================================================================*/
9351
9352 /**
9353  * \fn int get_sig_strength()
9354  * \brief Retrieve signal strength for VSB and QAM.
9355  * \param demod Pointer to demod instance
9356  * \param u16-t Pointer to signal strength data; range 0, .. , 100.
9357  * \return int.
9358  * \retval 0 sig_strength contains valid data.
9359  * \retval -EINVAL sig_strength is NULL.
9360  * \retval -EIO Erroneous data, sig_strength contains invalid data.
9361  */
9362 #define DRXJ_AGC_TOP    0x2800
9363 #define DRXJ_AGC_SNS    0x1600
9364 #define DRXJ_RFAGC_MAX  0x3fff
9365 #define DRXJ_RFAGC_MIN  0x800
9366
9367 static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength)
9368 {
9369         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9370         int rc;
9371         u16 rf_gain = 0;
9372         u16 if_gain = 0;
9373         u16 if_agc_sns = 0;
9374         u16 if_agc_top = 0;
9375         u16 rf_agc_max = 0;
9376         u16 rf_agc_min = 0;
9377
9378         rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0);
9379         if (rc != 0) {
9380                 pr_err("error %d\n", rc);
9381                 goto rw_error;
9382         }
9383         if_gain &= IQM_AF_AGC_IF__M;
9384         rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0);
9385         if (rc != 0) {
9386                 pr_err("error %d\n", rc);
9387                 goto rw_error;
9388         }
9389         rf_gain &= IQM_AF_AGC_RF__M;
9390
9391         if_agc_sns = DRXJ_AGC_SNS;
9392         if_agc_top = DRXJ_AGC_TOP;
9393         rf_agc_max = DRXJ_RFAGC_MAX;
9394         rf_agc_min = DRXJ_RFAGC_MIN;
9395
9396         if (if_gain > if_agc_top) {
9397                 if (rf_gain > rf_agc_max)
9398                         *sig_strength = 100;
9399                 else if (rf_gain > rf_agc_min) {
9400                         if (rf_agc_max == rf_agc_min) {
9401                                 pr_err("error: rf_agc_max == rf_agc_min\n");
9402                                 return -EIO;
9403                         }
9404                         *sig_strength =
9405                         75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max -
9406                                                                 rf_agc_min);
9407                 } else
9408                         *sig_strength = 75;
9409         } else if (if_gain > if_agc_sns) {
9410                 if (if_agc_top == if_agc_sns) {
9411                         pr_err("error: if_agc_top == if_agc_sns\n");
9412                         return -EIO;
9413                 }
9414                 *sig_strength =
9415                 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns);
9416         } else {
9417                 if (!if_agc_sns) {
9418                         pr_err("error: if_agc_sns is zero!\n");
9419                         return -EIO;
9420                 }
9421                 *sig_strength = (20 * if_gain / if_agc_sns);
9422         }
9423
9424         if (*sig_strength <= 7)
9425                 *sig_strength = 0;
9426
9427         return 0;
9428 rw_error:
9429         return rc;
9430 }
9431
9432 /**
9433 * \fn int ctrl_get_qam_sig_quality()
9434 * \brief Retreive QAM signal quality from device.
9435 * \param devmod Pointer to demodulator instance.
9436 * \param sig_quality Pointer to signal quality data.
9437 * \return int.
9438 * \retval 0 sig_quality contains valid data.
9439 * \retval -EINVAL sig_quality is NULL.
9440 * \retval -EIO Erroneous data, sig_quality contains invalid data.
9441
9442 *  Pre-condition: Device must be started and in lock.
9443 */
9444 static int
9445 ctrl_get_qam_sig_quality(struct drx_demod_instance *demod)
9446 {
9447         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9448         struct drxj_data *ext_attr = demod->my_ext_attr;
9449         struct drx39xxj_state *state = dev_addr->user_data;
9450         struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
9451         struct drxjrs_errors measuredrs_errors = { 0, 0, 0, 0, 0 };
9452         enum drx_modulation constellation = ext_attr->constellation;
9453         int rc;
9454
9455         u32 pre_bit_err_rs = 0; /* pre RedSolomon Bit Error Rate */
9456         u32 post_bit_err_rs = 0;        /* post RedSolomon Bit Error Rate */
9457         u32 pkt_errs = 0;       /* no of packet errors in RS */
9458         u16 qam_sl_err_power = 0;       /* accumulated error between raw and sliced symbols */
9459         u16 qsym_err_vd = 0;    /* quadrature symbol errors in QAM_VD */
9460         u16 fec_oc_period = 0;  /* SNC sync failure measurement period */
9461         u16 fec_rs_prescale = 0;        /* ReedSolomon Measurement Prescale */
9462         u16 fec_rs_period = 0;  /* Value for corresponding I2C register */
9463         /* calculation constants */
9464         u32 rs_bit_cnt = 0;     /* RedSolomon Bit Count */
9465         u32 qam_sl_sig_power = 0;       /* used for MER, depends of QAM constellation */
9466         /* intermediate results */
9467         u32 e = 0;              /* exponent value used for QAM BER/SER */
9468         u32 m = 0;              /* mantisa value used for QAM BER/SER */
9469         u32 ber_cnt = 0;        /* BER count */
9470         /* signal quality info */
9471         u32 qam_sl_mer = 0;     /* QAM MER */
9472         u32 qam_pre_rs_ber = 0; /* Pre RedSolomon BER */
9473         u32 qam_post_rs_ber = 0;        /* Post RedSolomon BER */
9474         u32 qam_vd_ser = 0;     /* ViterbiDecoder SER */
9475         u16 qam_vd_prescale = 0;        /* Viterbi Measurement Prescale */
9476         u16 qam_vd_period = 0;  /* Viterbi Measurement period */
9477         u32 vd_bit_cnt = 0;     /* ViterbiDecoder Bit Count */
9478
9479         p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9480
9481         /* read the physical registers */
9482         /*   Get the RS error data */
9483         rc = get_qamrs_err_count(dev_addr, &measuredrs_errors);
9484         if (rc != 0) {
9485                 pr_err("error %d\n", rc);
9486                 goto rw_error;
9487         }
9488         /* get the register value needed for MER */
9489         rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0);
9490         if (rc != 0) {
9491                 pr_err("error %d\n", rc);
9492                 goto rw_error;
9493         }
9494         /* get the register value needed for post RS BER */
9495         rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0);
9496         if (rc != 0) {
9497                 pr_err("error %d\n", rc);
9498                 goto rw_error;
9499         }
9500
9501         /* get constants needed for signal quality calculation */
9502         fec_rs_period = ext_attr->fec_rs_period;
9503         fec_rs_prescale = ext_attr->fec_rs_prescale;
9504         rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen;
9505         qam_vd_period = ext_attr->qam_vd_period;
9506         qam_vd_prescale = ext_attr->qam_vd_prescale;
9507         vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen;
9508
9509         /* DRXJ_QAM_SL_SIG_POWER_QAMxxx  * 4     */
9510         switch (constellation) {
9511         case DRX_CONSTELLATION_QAM16:
9512                 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2;
9513                 break;
9514         case DRX_CONSTELLATION_QAM32:
9515                 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2;
9516                 break;
9517         case DRX_CONSTELLATION_QAM64:
9518                 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2;
9519                 break;
9520         case DRX_CONSTELLATION_QAM128:
9521                 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2;
9522                 break;
9523         case DRX_CONSTELLATION_QAM256:
9524                 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2;
9525                 break;
9526         default:
9527                 return -EIO;
9528         }
9529
9530         /* ------------------------------ */
9531         /* MER Calculation                */
9532         /* ------------------------------ */
9533         /* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */
9534
9535         /* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */
9536         if (qam_sl_err_power == 0)
9537                 qam_sl_mer = 0;
9538         else
9539                 qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power);
9540
9541         /* ----------------------------------------- */
9542         /* Pre Viterbi Symbol Error Rate Calculation */
9543         /* ----------------------------------------- */
9544         /* pre viterbi SER is good if it is bellow 0.025 */
9545
9546         /* get the register value */
9547         /*   no of quadrature symbol errors */
9548         rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0);
9549         if (rc != 0) {
9550                 pr_err("error %d\n", rc);
9551                 goto rw_error;
9552         }
9553         /* Extract the Exponent and the Mantisa  */
9554         /* of number of quadrature symbol errors */
9555         e = (qsym_err_vd & QAM_VD_NR_QSYM_ERRORS_EXP__M) >>
9556             QAM_VD_NR_QSYM_ERRORS_EXP__B;
9557         m = (qsym_err_vd & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >>
9558             QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B;
9559
9560         if ((m << e) >> 3 > 549752)
9561                 qam_vd_ser = 500000 * vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
9562         else
9563                 qam_vd_ser = m << ((e > 2) ? (e - 3) : e);
9564
9565         /* --------------------------------------- */
9566         /* pre and post RedSolomon BER Calculation */
9567         /* --------------------------------------- */
9568         /* pre RS BER is good if it is below 3.5e-4 */
9569
9570         /* get the register values */
9571         pre_bit_err_rs = (u32) measuredrs_errors.nr_bit_errors;
9572         pkt_errs = post_bit_err_rs = (u32) measuredrs_errors.nr_snc_par_fail_count;
9573
9574         /* Extract the Exponent and the Mantisa of the */
9575         /* pre Reed-Solomon bit error count            */
9576         e = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_EXP__M) >>
9577             FEC_RS_NR_BIT_ERRORS_EXP__B;
9578         m = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M) >>
9579             FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B;
9580
9581         ber_cnt = m << e;
9582
9583         /*qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); */
9584         if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0)
9585                 qam_pre_rs_ber = 500000 * rs_bit_cnt >> e;
9586         else
9587                 qam_pre_rs_ber = ber_cnt;
9588
9589         /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) /  */
9590         /*               (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A)  */
9591         /*
9592            => c = (1000000*100*11.17)/1504 =
9593            post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) /
9594            (100 * FEC_OC_SNC_FAIL_PERIOD__A)
9595            *100 and /100 is for more precision.
9596            => (20 bits * 12 bits) /(16 bits * 7 bits)  => safe in 32 bits computation
9597
9598            Precision errors still possible.
9599          */
9600         e = post_bit_err_rs * 742686;
9601         m = fec_oc_period * 100;
9602         if (fec_oc_period == 0)
9603                 qam_post_rs_ber = 0xFFFFFFFF;
9604         else
9605                 qam_post_rs_ber = e / m;
9606
9607         /* fill signal quality data structure */
9608         p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
9609         p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
9610         p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
9611         p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
9612         p->block_error.stat[0].scale = FE_SCALE_COUNTER;
9613         p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
9614
9615         p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100;
9616         if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9617                 p->pre_bit_error.stat[0].uvalue += qam_vd_ser;
9618                 p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
9619         } else {
9620                 p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber;
9621                 p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
9622         }
9623
9624         p->post_bit_error.stat[0].uvalue += qam_post_rs_ber;
9625         p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
9626
9627         p->block_error.stat[0].uvalue += pkt_errs;
9628
9629 #ifdef DRXJ_SIGNAL_ACCUM_ERR
9630         rc = get_acc_pkt_err(demod, &sig_quality->packet_error);
9631         if (rc != 0) {
9632                 pr_err("error %d\n", rc);
9633                 goto rw_error;
9634         }
9635 #endif
9636
9637         return 0;
9638 rw_error:
9639         p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9640         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9641         p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9642         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9643         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9644         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9645
9646         return rc;
9647 }
9648
9649 #endif /* #ifndef DRXJ_VSB_ONLY */
9650
9651 /*============================================================================*/
9652 /*==                     END QAM DATAPATH FUNCTIONS                         ==*/
9653 /*============================================================================*/
9654
9655 /*============================================================================*/
9656 /*============================================================================*/
9657 /*==                       ATV DATAPATH FUNCTIONS                           ==*/
9658 /*============================================================================*/
9659 /*============================================================================*/
9660
9661 /*
9662    Implementation notes.
9663
9664    NTSC/FM AGCs
9665
9666       Four AGCs are used for NTSC:
9667       (1) RF (used to attenuate the input signal in case of to much power)
9668       (2) IF (used to attenuate the input signal in case of to much power)
9669       (3) Video AGC (used to amplify the output signal in case input to low)
9670       (4) SIF AGC (used to amplify the output signal in case input to low)
9671
9672       Video AGC is coupled to RF and IF. SIF AGC is not coupled. It is assumed
9673       that the coupling between Video AGC and the RF and IF AGCs also works in
9674       favor of the SIF AGC.
9675
9676       Three AGCs are used for FM:
9677       (1) RF (used to attenuate the input signal in case of to much power)
9678       (2) IF (used to attenuate the input signal in case of to much power)
9679       (3) SIF AGC (used to amplify the output signal in case input to low)
9680
9681       The SIF AGC is now coupled to the RF/IF AGCs.
9682       The SIF AGC is needed for both SIF ouput and the internal SIF signal to
9683       the AUD block.
9684
9685       RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of
9686       the ATV block. The AGC control algorithms are all implemented in
9687       microcode.
9688
9689    ATV SETTINGS
9690
9691       (Shadow settings will not be used for now, they will be implemented
9692        later on because of the schedule)
9693
9694       Several HW/SCU "settings" can be used for ATV. The standard selection
9695       will reset most of these settings. To avoid that the end user apllication
9696       has to perform these settings each time the ATV or FM standards is
9697       selected the driver will shadow these settings. This enables the end user
9698       to perform the settings only once after a drx_open(). The driver must
9699       write the shadow settings to HW/SCU incase:
9700          ( setstandard FM/ATV) ||
9701          ( settings have changed && FM/ATV standard is active)
9702       The shadow settings will be stored in the device specific data container.
9703       A set of flags will be defined to flag changes in shadow settings.
9704       A routine will be implemented to write all changed shadow settings to
9705       HW/SCU.
9706
9707       The "settings" will consist of: AGC settings, filter settings etc.
9708
9709       Disadvantage of use of shadow settings:
9710       Direct changes in HW/SCU registers will not be reflected in the
9711       shadow settings and these changes will be overwritten during a next
9712       update. This can happen during evaluation. This will not be a problem
9713       for normal customer usage.
9714 */
9715 /* -------------------------------------------------------------------------- */
9716
9717 /**
9718 * \fn int power_down_atv ()
9719 * \brief Power down ATV.
9720 * \param demod instance of demodulator
9721 * \param standard either NTSC or FM (sub strandard for ATV )
9722 * \return int.
9723 *
9724 *  Stops and thus resets ATV and IQM block
9725 *  SIF and CVBS ADC are powered down
9726 *  Calls audio power down
9727 */
9728 static int
9729 power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary)
9730 {
9731         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9732         struct drxjscu_cmd cmd_scu = { /* command      */ 0,
9733                 /* parameter_len */ 0,
9734                 /* result_len    */ 0,
9735                 /* *parameter   */ NULL,
9736                 /* *result      */ NULL
9737         };
9738         int rc;
9739         u16 cmd_result = 0;
9740
9741         /* ATV NTSC */
9742
9743         /* Stop ATV SCU (will reset ATV and IQM hardware */
9744         cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV |
9745             SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9746         cmd_scu.parameter_len = 0;
9747         cmd_scu.result_len = 1;
9748         cmd_scu.parameter = NULL;
9749         cmd_scu.result = &cmd_result;
9750         rc = scu_command(dev_addr, &cmd_scu);
9751         if (rc != 0) {
9752                 pr_err("error %d\n", rc);
9753                 goto rw_error;
9754         }
9755         /* Disable ATV outputs (ATV reset enables CVBS, undo this) */
9756         rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0);
9757         if (rc != 0) {
9758                 pr_err("error %d\n", rc);
9759                 goto rw_error;
9760         }
9761
9762         rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0);
9763         if (rc != 0) {
9764                 pr_err("error %d\n", rc);
9765                 goto rw_error;
9766         }
9767         if (primary) {
9768                 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
9769                 if (rc != 0) {
9770                         pr_err("error %d\n", rc);
9771                         goto rw_error;
9772                 }
9773                 rc = set_iqm_af(demod, false);
9774                 if (rc != 0) {
9775                         pr_err("error %d\n", rc);
9776                         goto rw_error;
9777                 }
9778         } else {
9779                 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
9780                 if (rc != 0) {
9781                         pr_err("error %d\n", rc);
9782                         goto rw_error;
9783                 }
9784                 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
9785                 if (rc != 0) {
9786                         pr_err("error %d\n", rc);
9787                         goto rw_error;
9788                 }
9789                 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
9790                 if (rc != 0) {
9791                         pr_err("error %d\n", rc);
9792                         goto rw_error;
9793                 }
9794                 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
9795                 if (rc != 0) {
9796                         pr_err("error %d\n", rc);
9797                         goto rw_error;
9798                 }
9799                 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
9800                 if (rc != 0) {
9801                         pr_err("error %d\n", rc);
9802                         goto rw_error;
9803                 }
9804         }
9805         rc = power_down_aud(demod);
9806         if (rc != 0) {
9807                 pr_err("error %d\n", rc);
9808                 goto rw_error;
9809         }
9810
9811         return 0;
9812 rw_error:
9813         return rc;
9814 }
9815
9816 /*============================================================================*/
9817
9818 /**
9819 * \brief Power up AUD.
9820 * \param demod instance of demodulator
9821 * \return int.
9822 *
9823 */
9824 static int power_down_aud(struct drx_demod_instance *demod)
9825 {
9826         struct i2c_device_addr *dev_addr = NULL;
9827         struct drxj_data *ext_attr = NULL;
9828         int rc;
9829
9830         dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr;
9831         ext_attr = (struct drxj_data *) demod->my_ext_attr;
9832
9833         rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0);
9834         if (rc != 0) {
9835                 pr_err("error %d\n", rc);
9836                 goto rw_error;
9837         }
9838
9839         ext_attr->aud_data.audio_is_active = false;
9840
9841         return 0;
9842 rw_error:
9843         return rc;
9844 }
9845
9846 /**
9847 * \fn int set_orx_nsu_aox()
9848 * \brief Configure OrxNsuAox for OOB
9849 * \param demod instance of demodulator.
9850 * \param active
9851 * \return int.
9852 */
9853 static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active)
9854 {
9855         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9856         int rc;
9857         u16 data = 0;
9858
9859         /* Configure NSU_AOX */
9860         rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0);
9861         if (rc != 0) {
9862                 pr_err("error %d\n", rc);
9863                 goto rw_error;
9864         }
9865         if (!active)
9866                 data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON));
9867         else
9868                 data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON);
9869         rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0);
9870         if (rc != 0) {
9871                 pr_err("error %d\n", rc);
9872                 goto rw_error;
9873         }
9874
9875         return 0;
9876 rw_error:
9877         return rc;
9878 }
9879
9880 /**
9881 * \fn int ctrl_set_oob()
9882 * \brief Set OOB channel to be used.
9883 * \param demod instance of demodulator
9884 * \param oob_param OOB parameters for channel setting.
9885 * \frequency should be in KHz
9886 * \return int.
9887 *
9888 * Accepts  only. Returns error otherwise.
9889 * Demapper value is written after scu_command START
9890 * because START command causes COMM_EXEC transition
9891 * from 0 to 1 which causes all registers to be
9892 * overwritten with initial value
9893 *
9894 */
9895
9896 /* Nyquist filter impulse response */
9897 #define IMPULSE_COSINE_ALPHA_0_3    {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */
9898 #define IMPULSE_COSINE_ALPHA_0_5    { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145}   /*sqrt raised-cosine filter with alpha=0.5 */
9899 #define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16,  0, 34, 77, 114, 128}     /*full raised-cosine filter with alpha=0.5 (receiver only) */
9900
9901 /* Coefficients for the nyquist fitler (total: 27 taps) */
9902 #define NYQFILTERLEN 27
9903
9904 static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param)
9905 {
9906         int rc;
9907         s32 freq = 0;   /* KHz */
9908         struct i2c_device_addr *dev_addr = NULL;
9909         struct drxj_data *ext_attr = NULL;
9910         u16 i = 0;
9911         bool mirror_freq_spect_oob = false;
9912         u16 trk_filter_value = 0;
9913         struct drxjscu_cmd scu_cmd;
9914         u16 set_param_parameters[3];
9915         u16 cmd_result[2] = { 0, 0 };
9916         s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = {
9917                 IMPULSE_COSINE_ALPHA_0_3,       /* Target Mode 0 */
9918                 IMPULSE_COSINE_ALPHA_0_3,       /* Target Mode 1 */
9919                 IMPULSE_COSINE_ALPHA_0_5,       /* Target Mode 2 */
9920                 IMPULSE_COSINE_ALPHA_RO_0_5     /* Target Mode 3 */
9921         };
9922         u8 mode_val[4] = { 2, 2, 0, 1 };
9923         u8 pfi_coeffs[4][6] = {
9924                 {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)},   /* TARGET_MODE = 0:     PFI_A = -23/32; PFI_B = -54/32;  PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */
9925                 {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)},     /* TARGET_MODE = 1:     PFI_A = -16/32; PFI_B = -40/32;  PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */
9926                 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)},     /* TARGET_MODE = 2, 3:  PFI_A = -20/32; PFI_B = -49/32;  PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
9927                 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}      /* TARGET_MODE = 2, 3:  PFI_A = -20/32; PFI_B = -49/32;  PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
9928         };
9929         u16 mode_index;
9930
9931         dev_addr = demod->my_i2c_dev_addr;
9932         ext_attr = (struct drxj_data *) demod->my_ext_attr;
9933         mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob;
9934
9935         /* Check parameters */
9936         if (oob_param == NULL) {
9937                 /* power off oob module  */
9938                 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
9939                     | SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9940                 scu_cmd.parameter_len = 0;
9941                 scu_cmd.result_len = 1;
9942                 scu_cmd.result = cmd_result;
9943                 rc = scu_command(dev_addr, &scu_cmd);
9944                 if (rc != 0) {
9945                         pr_err("error %d\n", rc);
9946                         goto rw_error;
9947                 }
9948                 rc = set_orx_nsu_aox(demod, false);
9949                 if (rc != 0) {
9950                         pr_err("error %d\n", rc);
9951                         goto rw_error;
9952                 }
9953                 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
9954                 if (rc != 0) {
9955                         pr_err("error %d\n", rc);
9956                         goto rw_error;
9957                 }
9958
9959                 ext_attr->oob_power_on = false;
9960                 return 0;
9961         }
9962
9963         freq = oob_param->frequency;
9964         if ((freq < 70000) || (freq > 130000))
9965                 return -EIO;
9966         freq = (freq - 50000) / 50;
9967
9968         {
9969                 u16 index = 0;
9970                 u16 remainder = 0;
9971                 u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg;
9972
9973                 index = (u16) ((freq - 400) / 200);
9974                 remainder = (u16) ((freq - 400) % 200);
9975                 trk_filter_value =
9976                     trk_filtercfg[index] - (trk_filtercfg[index] -
9977                                            trk_filtercfg[index +
9978                                                         1]) / 10 * remainder /
9979                     20;
9980         }
9981
9982    /*********/
9983         /* Stop  */
9984    /*********/
9985         rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
9986         if (rc != 0) {
9987                 pr_err("error %d\n", rc);
9988                 goto rw_error;
9989         }
9990         scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
9991             | SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9992         scu_cmd.parameter_len = 0;
9993         scu_cmd.result_len = 1;
9994         scu_cmd.result = cmd_result;
9995         rc = scu_command(dev_addr, &scu_cmd);
9996         if (rc != 0) {
9997                 pr_err("error %d\n", rc);
9998                 goto rw_error;
9999         }
10000    /*********/
10001         /* Reset */
10002    /*********/
10003         scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10004             | SCU_RAM_COMMAND_CMD_DEMOD_RESET;
10005         scu_cmd.parameter_len = 0;
10006         scu_cmd.result_len = 1;
10007         scu_cmd.result = cmd_result;
10008         rc = scu_command(dev_addr, &scu_cmd);
10009         if (rc != 0) {
10010                 pr_err("error %d\n", rc);
10011                 goto rw_error;
10012         }
10013    /***********/
10014         /* SET_ENV */
10015    /***********/
10016         /* set frequency, spectrum inversion and data rate */
10017         scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10018             | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
10019         scu_cmd.parameter_len = 3;
10020         /* 1-data rate;2-frequency */
10021         switch (oob_param->standard) {
10022         case DRX_OOB_MODE_A:
10023                 if (
10024                            /* signal is transmitted inverted */
10025                            ((oob_param->spectrum_inverted == true) &&
10026                             /* and tuner is not mirroring the signal */
10027                             (!mirror_freq_spect_oob)) |
10028                            /* or */
10029                            /* signal is transmitted noninverted */
10030                            ((oob_param->spectrum_inverted == false) &&
10031                             /* and tuner is mirroring the signal */
10032                             (mirror_freq_spect_oob))
10033                     )
10034                         set_param_parameters[0] =
10035                             SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC;
10036                 else
10037                         set_param_parameters[0] =
10038                             SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC;
10039                 break;
10040         case DRX_OOB_MODE_B_GRADE_A:
10041                 if (
10042                            /* signal is transmitted inverted */
10043                            ((oob_param->spectrum_inverted == true) &&
10044                             /* and tuner is not mirroring the signal */
10045                             (!mirror_freq_spect_oob)) |
10046                            /* or */
10047                            /* signal is transmitted noninverted */
10048                            ((oob_param->spectrum_inverted == false) &&
10049                             /* and tuner is mirroring the signal */
10050                             (mirror_freq_spect_oob))
10051                     )
10052                         set_param_parameters[0] =
10053                             SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC;
10054                 else
10055                         set_param_parameters[0] =
10056                             SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC;
10057                 break;
10058         case DRX_OOB_MODE_B_GRADE_B:
10059         default:
10060                 if (
10061                            /* signal is transmitted inverted */
10062                            ((oob_param->spectrum_inverted == true) &&
10063                             /* and tuner is not mirroring the signal */
10064                             (!mirror_freq_spect_oob)) |
10065                            /* or */
10066                            /* signal is transmitted noninverted */
10067                            ((oob_param->spectrum_inverted == false) &&
10068                             /* and tuner is mirroring the signal */
10069                             (mirror_freq_spect_oob))
10070                     )
10071                         set_param_parameters[0] =
10072                             SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC;
10073                 else
10074                         set_param_parameters[0] =
10075                             SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC;
10076                 break;
10077         }
10078         set_param_parameters[1] = (u16) (freq & 0xFFFF);
10079         set_param_parameters[2] = trk_filter_value;
10080         scu_cmd.parameter = set_param_parameters;
10081         scu_cmd.result_len = 1;
10082         scu_cmd.result = cmd_result;
10083         mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6];
10084         rc = scu_command(dev_addr, &scu_cmd);
10085         if (rc != 0) {
10086                 pr_err("error %d\n", rc);
10087                 goto rw_error;
10088         }
10089
10090         rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
10091         if (rc != 0) {
10092                 pr_err("error %d\n", rc);
10093                 goto rw_error;
10094         }       /*  Write magic word to enable pdr reg write  */
10095         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0);
10096         if (rc != 0) {
10097                 pr_err("error %d\n", rc);
10098                 goto rw_error;
10099         }
10100         rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0);
10101         if (rc != 0) {
10102                 pr_err("error %d\n", rc);
10103                 goto rw_error;
10104         }
10105         rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
10106         if (rc != 0) {
10107                 pr_err("error %d\n", rc);
10108                 goto rw_error;
10109         }       /*  Write magic word to disable pdr reg write */
10110
10111         rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0);
10112         if (rc != 0) {
10113                 pr_err("error %d\n", rc);
10114                 goto rw_error;
10115         }
10116         rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0);
10117         if (rc != 0) {
10118                 pr_err("error %d\n", rc);
10119                 goto rw_error;
10120         }
10121         rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0);
10122         if (rc != 0) {
10123                 pr_err("error %d\n", rc);
10124                 goto rw_error;
10125         }
10126
10127         /* ddc */
10128         rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0);
10129         if (rc != 0) {
10130                 pr_err("error %d\n", rc);
10131                 goto rw_error;
10132         }
10133
10134         /* nsu */
10135         rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);
10136         if (rc != 0) {
10137                 pr_err("error %d\n", rc);
10138                 goto rw_error;
10139         }
10140
10141         /* initialization for target mode */
10142         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0);
10143         if (rc != 0) {
10144                 pr_err("error %d\n", rc);
10145                 goto rw_error;
10146         }
10147         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0);
10148         if (rc != 0) {
10149                 pr_err("error %d\n", rc);
10150                 goto rw_error;
10151         }
10152
10153         /* Reset bits for timing and freq. recovery */
10154         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0);
10155         if (rc != 0) {
10156                 pr_err("error %d\n", rc);
10157                 goto rw_error;
10158         }
10159         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0);
10160         if (rc != 0) {
10161                 pr_err("error %d\n", rc);
10162                 goto rw_error;
10163         }
10164         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0);
10165         if (rc != 0) {
10166                 pr_err("error %d\n", rc);
10167                 goto rw_error;
10168         }
10169         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0);
10170         if (rc != 0) {
10171                 pr_err("error %d\n", rc);
10172                 goto rw_error;
10173         }
10174
10175         /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */
10176         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0);
10177         if (rc != 0) {
10178                 pr_err("error %d\n", rc);
10179                 goto rw_error;
10180         }
10181         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0);
10182         if (rc != 0) {
10183                 pr_err("error %d\n", rc);
10184                 goto rw_error;
10185         }
10186         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0);
10187         if (rc != 0) {
10188                 pr_err("error %d\n", rc);
10189                 goto rw_error;
10190         }
10191         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0);
10192         if (rc != 0) {
10193                 pr_err("error %d\n", rc);
10194                 goto rw_error;
10195         }
10196         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0);
10197         if (rc != 0) {
10198                 pr_err("error %d\n", rc);
10199                 goto rw_error;
10200         }
10201
10202         /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */
10203         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0);
10204         if (rc != 0) {
10205                 pr_err("error %d\n", rc);
10206                 goto rw_error;
10207         }
10208         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0);
10209         if (rc != 0) {
10210                 pr_err("error %d\n", rc);
10211                 goto rw_error;
10212         }
10213         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0);
10214         if (rc != 0) {
10215                 pr_err("error %d\n", rc);
10216                 goto rw_error;
10217         }
10218         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0);
10219         if (rc != 0) {
10220                 pr_err("error %d\n", rc);
10221                 goto rw_error;
10222         }
10223         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0);
10224         if (rc != 0) {
10225                 pr_err("error %d\n", rc);
10226                 goto rw_error;
10227         }
10228
10229         /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */
10230         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0);
10231         if (rc != 0) {
10232                 pr_err("error %d\n", rc);
10233                 goto rw_error;
10234         }
10235         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0);
10236         if (rc != 0) {
10237                 pr_err("error %d\n", rc);
10238                 goto rw_error;
10239         }
10240         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0);
10241         if (rc != 0) {
10242                 pr_err("error %d\n", rc);
10243                 goto rw_error;
10244         }
10245         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0);
10246         if (rc != 0) {
10247                 pr_err("error %d\n", rc);
10248                 goto rw_error;
10249         }
10250         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0);
10251         if (rc != 0) {
10252                 pr_err("error %d\n", rc);
10253                 goto rw_error;
10254         }
10255
10256         /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */
10257         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0);
10258         if (rc != 0) {
10259                 pr_err("error %d\n", rc);
10260                 goto rw_error;
10261         }
10262         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0);
10263         if (rc != 0) {
10264                 pr_err("error %d\n", rc);
10265                 goto rw_error;
10266         }
10267         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0);
10268         if (rc != 0) {
10269                 pr_err("error %d\n", rc);
10270                 goto rw_error;
10271         }
10272         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0);
10273         if (rc != 0) {
10274                 pr_err("error %d\n", rc);
10275                 goto rw_error;
10276         }
10277         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0);
10278         if (rc != 0) {
10279                 pr_err("error %d\n", rc);
10280                 goto rw_error;
10281         }
10282
10283         /* TIM_LOCK = {300,      -2048, 8, -8, 0, 1<<4}; */
10284         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0);
10285         if (rc != 0) {
10286                 pr_err("error %d\n", rc);
10287                 goto rw_error;
10288         }
10289         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0);
10290         if (rc != 0) {
10291                 pr_err("error %d\n", rc);
10292                 goto rw_error;
10293         }
10294         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0);
10295         if (rc != 0) {
10296                 pr_err("error %d\n", rc);
10297                 goto rw_error;
10298         }
10299         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0);
10300         if (rc != 0) {
10301                 pr_err("error %d\n", rc);
10302                 goto rw_error;
10303         }
10304         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0);
10305         if (rc != 0) {
10306                 pr_err("error %d\n", rc);
10307                 goto rw_error;
10308         }
10309
10310         /* EQU_LOCK = {20,      -2048, 8, -8, 0, 1<<5}; */
10311         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0);
10312         if (rc != 0) {
10313                 pr_err("error %d\n", rc);
10314                 goto rw_error;
10315         }
10316         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0);
10317         if (rc != 0) {
10318                 pr_err("error %d\n", rc);
10319                 goto rw_error;
10320         }
10321         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0);
10322         if (rc != 0) {
10323                 pr_err("error %d\n", rc);
10324                 goto rw_error;
10325         }
10326         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0);
10327         if (rc != 0) {
10328                 pr_err("error %d\n", rc);
10329                 goto rw_error;
10330         }
10331         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0);
10332         if (rc != 0) {
10333                 pr_err("error %d\n", rc);
10334                 goto rw_error;
10335         }
10336
10337         /* PRE-Filter coefficients (PFI) */
10338         rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0);
10339         if (rc != 0) {
10340                 pr_err("error %d\n", rc);
10341                 goto rw_error;
10342         }
10343         rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0);
10344         if (rc != 0) {
10345                 pr_err("error %d\n", rc);
10346                 goto rw_error;
10347         }
10348
10349         /* NYQUIST-Filter coefficients (NYQ) */
10350         for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) {
10351                 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0);
10352                 if (rc != 0) {
10353                         pr_err("error %d\n", rc);
10354                         goto rw_error;
10355                 }
10356                 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0);
10357                 if (rc != 0) {
10358                         pr_err("error %d\n", rc);
10359                         goto rw_error;
10360                 }
10361         }
10362         rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0);
10363         if (rc != 0) {
10364                 pr_err("error %d\n", rc);
10365                 goto rw_error;
10366         }
10367         rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0);
10368         if (rc != 0) {
10369                 pr_err("error %d\n", rc);
10370                 goto rw_error;
10371         }
10372         /*********/
10373         /* Start */
10374         /*********/
10375         scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10376             | SCU_RAM_COMMAND_CMD_DEMOD_START;
10377         scu_cmd.parameter_len = 0;
10378         scu_cmd.result_len = 1;
10379         scu_cmd.result = cmd_result;
10380         rc = scu_command(dev_addr, &scu_cmd);
10381         if (rc != 0) {
10382                 pr_err("error %d\n", rc);
10383                 goto rw_error;
10384         }
10385
10386         rc = set_orx_nsu_aox(demod, true);
10387         if (rc != 0) {
10388                 pr_err("error %d\n", rc);
10389                 goto rw_error;
10390         }
10391         rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);
10392         if (rc != 0) {
10393                 pr_err("error %d\n", rc);
10394                 goto rw_error;
10395         }
10396
10397         ext_attr->oob_power_on = true;
10398
10399         return 0;
10400 rw_error:
10401         return rc;
10402 }
10403
10404 /*============================================================================*/
10405 /*==                     END OOB DATAPATH FUNCTIONS                         ==*/
10406 /*============================================================================*/
10407
10408 /*=============================================================================
10409   ===== MC command related functions ==========================================
10410   ===========================================================================*/
10411
10412 /*=============================================================================
10413   ===== ctrl_set_channel() ==========================================================
10414   ===========================================================================*/
10415 /**
10416 * \fn int ctrl_set_channel()
10417 * \brief Select a new transmission channel.
10418 * \param demod instance of demod.
10419 * \param channel Pointer to channel data.
10420 * \return int.
10421 *
10422 * In case the tuner module is not used and in case of NTSC/FM the pogrammer
10423 * must tune the tuner to the centre frequency of the NTSC/FM channel.
10424 *
10425 */
10426 static int
10427 ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel)
10428 {
10429         int rc;
10430         s32 tuner_freq_offset = 0;
10431         struct drxj_data *ext_attr = NULL;
10432         struct i2c_device_addr *dev_addr = NULL;
10433         enum drx_standard standard = DRX_STANDARD_UNKNOWN;
10434 #ifndef DRXJ_VSB_ONLY
10435         u32 min_symbol_rate = 0;
10436         u32 max_symbol_rate = 0;
10437         int bandwidth_temp = 0;
10438         int bandwidth = 0;
10439 #endif
10440    /*== check arguments ======================================================*/
10441         if ((demod == NULL) || (channel == NULL))
10442                 return -EINVAL;
10443
10444         dev_addr = demod->my_i2c_dev_addr;
10445         ext_attr = (struct drxj_data *) demod->my_ext_attr;
10446         standard = ext_attr->standard;
10447
10448         /* check valid standards */
10449         switch (standard) {
10450         case DRX_STANDARD_8VSB:
10451 #ifndef DRXJ_VSB_ONLY
10452         case DRX_STANDARD_ITU_A:
10453         case DRX_STANDARD_ITU_B:
10454         case DRX_STANDARD_ITU_C:
10455 #endif /* DRXJ_VSB_ONLY */
10456                 break;
10457         case DRX_STANDARD_UNKNOWN:
10458         default:
10459                 return -EINVAL;
10460         }
10461
10462         /* check bandwidth QAM annex B, NTSC and 8VSB */
10463         if ((standard == DRX_STANDARD_ITU_B) ||
10464             (standard == DRX_STANDARD_8VSB) ||
10465             (standard == DRX_STANDARD_NTSC)) {
10466                 switch (channel->bandwidth) {
10467                 case DRX_BANDWIDTH_6MHZ:
10468                 case DRX_BANDWIDTH_UNKNOWN:     /* fall through */
10469                         channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10470                         break;
10471                 case DRX_BANDWIDTH_8MHZ:        /* fall through */
10472                 case DRX_BANDWIDTH_7MHZ:        /* fall through */
10473                 default:
10474                         return -EINVAL;
10475                 }
10476         }
10477
10478         /* For QAM annex A and annex C:
10479            -check symbolrate and constellation
10480            -derive bandwidth from symbolrate (input bandwidth is ignored)
10481          */
10482 #ifndef DRXJ_VSB_ONLY
10483         if ((standard == DRX_STANDARD_ITU_A) ||
10484             (standard == DRX_STANDARD_ITU_C)) {
10485                 struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW };
10486                 int bw_rolloff_factor = 0;
10487
10488                 bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113;
10489                 min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN;
10490                 max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX;
10491                 /* config SMA_TX pin to SAW switch mode */
10492                 rc = ctrl_set_uio_cfg(demod, &uio_cfg);
10493                 if (rc != 0) {
10494                         pr_err("error %d\n", rc);
10495                         goto rw_error;
10496                 }
10497
10498                 if (channel->symbolrate < min_symbol_rate ||
10499                     channel->symbolrate > max_symbol_rate) {
10500                         return -EINVAL;
10501                 }
10502
10503                 switch (channel->constellation) {
10504                 case DRX_CONSTELLATION_QAM16:   /* fall through */
10505                 case DRX_CONSTELLATION_QAM32:   /* fall through */
10506                 case DRX_CONSTELLATION_QAM64:   /* fall through */
10507                 case DRX_CONSTELLATION_QAM128:  /* fall through */
10508                 case DRX_CONSTELLATION_QAM256:
10509                         bandwidth_temp = channel->symbolrate * bw_rolloff_factor;
10510                         bandwidth = bandwidth_temp / 100;
10511
10512                         if ((bandwidth_temp % 100) >= 50)
10513                                 bandwidth++;
10514
10515                         if (bandwidth <= 6100000) {
10516                                 channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10517                         } else if ((bandwidth > 6100000)
10518                                    && (bandwidth <= 7100000)) {
10519                                 channel->bandwidth = DRX_BANDWIDTH_7MHZ;
10520                         } else if (bandwidth > 7100000) {
10521                                 channel->bandwidth = DRX_BANDWIDTH_8MHZ;
10522                         }
10523                         break;
10524                 default:
10525                         return -EINVAL;
10526                 }
10527         }
10528
10529         /* For QAM annex B:
10530            -check constellation
10531          */
10532         if (standard == DRX_STANDARD_ITU_B) {
10533                 switch (channel->constellation) {
10534                 case DRX_CONSTELLATION_AUTO:
10535                 case DRX_CONSTELLATION_QAM256:
10536                 case DRX_CONSTELLATION_QAM64:
10537                         break;
10538                 default:
10539                         return -EINVAL;
10540                 }
10541
10542                 switch (channel->interleavemode) {
10543                 case DRX_INTERLEAVEMODE_I128_J1:
10544                 case DRX_INTERLEAVEMODE_I128_J1_V2:
10545                 case DRX_INTERLEAVEMODE_I128_J2:
10546                 case DRX_INTERLEAVEMODE_I64_J2:
10547                 case DRX_INTERLEAVEMODE_I128_J3:
10548                 case DRX_INTERLEAVEMODE_I32_J4:
10549                 case DRX_INTERLEAVEMODE_I128_J4:
10550                 case DRX_INTERLEAVEMODE_I16_J8:
10551                 case DRX_INTERLEAVEMODE_I128_J5:
10552                 case DRX_INTERLEAVEMODE_I8_J16:
10553                 case DRX_INTERLEAVEMODE_I128_J6:
10554                 case DRX_INTERLEAVEMODE_I128_J7:
10555                 case DRX_INTERLEAVEMODE_I128_J8:
10556                 case DRX_INTERLEAVEMODE_I12_J17:
10557                 case DRX_INTERLEAVEMODE_I5_J4:
10558                 case DRX_INTERLEAVEMODE_B52_M240:
10559                 case DRX_INTERLEAVEMODE_B52_M720:
10560                 case DRX_INTERLEAVEMODE_UNKNOWN:
10561                 case DRX_INTERLEAVEMODE_AUTO:
10562                         break;
10563                 default:
10564                         return -EINVAL;
10565                 }
10566         }
10567
10568         if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) {
10569                 /* SAW SW, user UIO is used for switchable SAW */
10570                 struct drxuio_data uio1 = { DRX_UIO1, false };
10571
10572                 switch (channel->bandwidth) {
10573                 case DRX_BANDWIDTH_8MHZ:
10574                         uio1.value = true;
10575                         break;
10576                 case DRX_BANDWIDTH_7MHZ:
10577                         uio1.value = false;
10578                         break;
10579                 case DRX_BANDWIDTH_6MHZ:
10580                         uio1.value = false;
10581                         break;
10582                 case DRX_BANDWIDTH_UNKNOWN:
10583                 default:
10584                         return -EINVAL;
10585                 }
10586
10587                 rc = ctrl_uio_write(demod, &uio1);
10588                 if (rc != 0) {
10589                         pr_err("error %d\n", rc);
10590                         goto rw_error;
10591                 }
10592         }
10593 #endif /* DRXJ_VSB_ONLY */
10594         rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
10595         if (rc != 0) {
10596                 pr_err("error %d\n", rc);
10597                 goto rw_error;
10598         }
10599
10600         tuner_freq_offset = 0;
10601
10602    /*== Setup demod for specific standard ====================================*/
10603         switch (standard) {
10604         case DRX_STANDARD_8VSB:
10605                 if (channel->mirror == DRX_MIRROR_AUTO)
10606                         ext_attr->mirror = DRX_MIRROR_NO;
10607                 else
10608                         ext_attr->mirror = channel->mirror;
10609                 rc = set_vsb(demod);
10610                 if (rc != 0) {
10611                         pr_err("error %d\n", rc);
10612                         goto rw_error;
10613                 }
10614                 rc = set_frequency(demod, channel, tuner_freq_offset);
10615                 if (rc != 0) {
10616                         pr_err("error %d\n", rc);
10617                         goto rw_error;
10618                 }
10619                 break;
10620 #ifndef DRXJ_VSB_ONLY
10621         case DRX_STANDARD_ITU_A:        /* fallthrough */
10622         case DRX_STANDARD_ITU_B:        /* fallthrough */
10623         case DRX_STANDARD_ITU_C:
10624                 rc = set_qam_channel(demod, channel, tuner_freq_offset);
10625                 if (rc != 0) {
10626                         pr_err("error %d\n", rc);
10627                         goto rw_error;
10628                 }
10629                 break;
10630 #endif
10631         case DRX_STANDARD_UNKNOWN:
10632         default:
10633                 return -EIO;
10634         }
10635
10636         /* flag the packet error counter reset */
10637         ext_attr->reset_pkt_err_acc = true;
10638
10639         return 0;
10640 rw_error:
10641         return rc;
10642 }
10643
10644 /*=============================================================================
10645   ===== SigQuality() ==========================================================
10646   ===========================================================================*/
10647
10648 /**
10649 * \fn int ctrl_sig_quality()
10650 * \brief Retreive signal quality form device.
10651 * \param devmod Pointer to demodulator instance.
10652 * \param sig_quality Pointer to signal quality data.
10653 * \return int.
10654 * \retval 0 sig_quality contains valid data.
10655 * \retval -EINVAL sig_quality is NULL.
10656 * \retval -EIO Erroneous data, sig_quality contains invalid data.
10657
10658 */
10659 static int
10660 ctrl_sig_quality(struct drx_demod_instance *demod,
10661                  enum drx_lock_status lock_status)
10662 {
10663         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
10664         struct drxj_data *ext_attr = demod->my_ext_attr;
10665         struct drx39xxj_state *state = dev_addr->user_data;
10666         struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
10667         enum drx_standard standard = ext_attr->standard;
10668         int rc;
10669         u32 ber, cnt, err, pkt;
10670         u16 mer, strength = 0;
10671
10672         rc = get_sig_strength(demod, &strength);
10673         if (rc < 0) {
10674                 pr_err("error getting signal strength %d\n", rc);
10675                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10676         } else {
10677                 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
10678                 p->strength.stat[0].uvalue = 65535UL *  strength/ 100;
10679         }
10680
10681         switch (standard) {
10682         case DRX_STANDARD_8VSB:
10683 #ifdef DRXJ_SIGNAL_ACCUM_ERR
10684                 rc = get_acc_pkt_err(demod, &pkt);
10685                 if (rc != 0) {
10686                         pr_err("error %d\n", rc);
10687                         goto rw_error;
10688                 }
10689 #endif
10690                 if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) {
10691                         p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10692                         p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10693                         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10694                         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10695                         p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10696                         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10697                         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10698                 } else {
10699                         rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt);
10700                         if (rc != 0) {
10701                                 pr_err("error %d getting UCB\n", rc);
10702                                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10703                         } else {
10704                                 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
10705                                 p->block_error.stat[0].uvalue += err;
10706                                 p->block_count.stat[0].scale = FE_SCALE_COUNTER;
10707                                 p->block_count.stat[0].uvalue += pkt;
10708                         }
10709
10710                         /* PostViterbi is compute in steps of 10^(-6) */
10711                         rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt);
10712                         if (rc != 0) {
10713                                 pr_err("error %d getting pre-ber\n", rc);
10714                                 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10715                         } else {
10716                                 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
10717                                 p->pre_bit_error.stat[0].uvalue += ber;
10718                                 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
10719                                 p->pre_bit_count.stat[0].uvalue += cnt;
10720                         }
10721
10722                         rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt);
10723                         if (rc != 0) {
10724                                 pr_err("error %d getting post-ber\n", rc);
10725                                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10726                         } else {
10727                                 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
10728                                 p->post_bit_error.stat[0].uvalue += ber;
10729                                 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
10730                                 p->post_bit_count.stat[0].uvalue += cnt;
10731                         }
10732                         rc = get_vsbmer(dev_addr, &mer);
10733                         if (rc != 0) {
10734                                 pr_err("error %d getting MER\n", rc);
10735                                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10736                         } else {
10737                                 p->cnr.stat[0].svalue = mer * 100;
10738                                 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
10739                         }
10740                 }
10741                 break;
10742 #ifndef DRXJ_VSB_ONLY
10743         case DRX_STANDARD_ITU_A:
10744         case DRX_STANDARD_ITU_B:
10745         case DRX_STANDARD_ITU_C:
10746                 rc = ctrl_get_qam_sig_quality(demod);
10747                 if (rc != 0) {
10748                         pr_err("error %d\n", rc);
10749                         goto rw_error;
10750                 }
10751                 break;
10752 #endif
10753         default:
10754                 return -EIO;
10755         }
10756
10757         return 0;
10758 rw_error:
10759         return rc;
10760 }
10761
10762 /*============================================================================*/
10763
10764 /**
10765 * \fn int ctrl_lock_status()
10766 * \brief Retreive lock status .
10767 * \param dev_addr Pointer to demodulator device address.
10768 * \param lock_stat Pointer to lock status structure.
10769 * \return int.
10770 *
10771 */
10772 static int
10773 ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat)
10774 {
10775         enum drx_standard standard = DRX_STANDARD_UNKNOWN;
10776         struct drxj_data *ext_attr = NULL;
10777         struct i2c_device_addr *dev_addr = NULL;
10778         struct drxjscu_cmd cmd_scu = { /* command      */ 0,
10779                 /* parameter_len */ 0,
10780                 /* result_len    */ 0,
10781                 /* *parameter   */ NULL,
10782                 /* *result      */ NULL
10783         };
10784         int rc;
10785         u16 cmd_result[2] = { 0, 0 };
10786         u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED;
10787
10788         /* check arguments */
10789         if ((demod == NULL) || (lock_stat == NULL))
10790                 return -EINVAL;
10791
10792         dev_addr = demod->my_i2c_dev_addr;
10793         ext_attr = (struct drxj_data *) demod->my_ext_attr;
10794         standard = ext_attr->standard;
10795
10796         *lock_stat = DRX_NOT_LOCKED;
10797
10798         /* define the SCU command code */
10799         switch (standard) {
10800         case DRX_STANDARD_8VSB:
10801                 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
10802                     SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
10803                 demod_lock |= 0x6;
10804                 break;
10805 #ifndef DRXJ_VSB_ONLY
10806         case DRX_STANDARD_ITU_A:
10807         case DRX_STANDARD_ITU_B:
10808         case DRX_STANDARD_ITU_C:
10809                 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
10810                     SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
10811                 break;
10812 #endif
10813         case DRX_STANDARD_UNKNOWN:      /* fallthrough */
10814         default:
10815                 return -EIO;
10816         }
10817
10818         /* define the SCU command paramters and execute the command */
10819         cmd_scu.parameter_len = 0;
10820         cmd_scu.result_len = 2;
10821         cmd_scu.parameter = NULL;
10822         cmd_scu.result = cmd_result;
10823         rc = scu_command(dev_addr, &cmd_scu);
10824         if (rc != 0) {
10825                 pr_err("error %d\n", rc);
10826                 goto rw_error;
10827         }
10828
10829         /* set the lock status */
10830         if (cmd_scu.result[1] < demod_lock) {
10831                 /* 0x0000 NOT LOCKED */
10832                 *lock_stat = DRX_NOT_LOCKED;
10833         } else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) {
10834                 *lock_stat = DRXJ_DEMOD_LOCK;
10835         } else if (cmd_scu.result[1] <
10836                    SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) {
10837                 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
10838                 *lock_stat = DRX_LOCKED;
10839         } else {
10840                 /* 0xC000 NEVER LOCKED */
10841                 /* (system will never be able to lock to the signal) */
10842                 *lock_stat = DRX_NEVER_LOCK;
10843         }
10844
10845         return 0;
10846 rw_error:
10847         return rc;
10848 }
10849
10850 /*============================================================================*/
10851
10852 /**
10853 * \fn int ctrl_set_standard()
10854 * \brief Set modulation standard to be used.
10855 * \param standard Modulation standard.
10856 * \return int.
10857 *
10858 * Setup stuff for the desired demodulation standard.
10859 * Disable and power down the previous selected demodulation standard
10860 *
10861 */
10862 static int
10863 ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard)
10864 {
10865         struct drxj_data *ext_attr = NULL;
10866         int rc;
10867         enum drx_standard prev_standard;
10868
10869         /* check arguments */
10870         if ((standard == NULL) || (demod == NULL))
10871                 return -EINVAL;
10872
10873         ext_attr = (struct drxj_data *) demod->my_ext_attr;
10874         prev_standard = ext_attr->standard;
10875
10876         /*
10877            Stop and power down previous standard
10878          */
10879         switch (prev_standard) {
10880 #ifndef DRXJ_VSB_ONLY
10881         case DRX_STANDARD_ITU_A:        /* fallthrough */
10882         case DRX_STANDARD_ITU_B:        /* fallthrough */
10883         case DRX_STANDARD_ITU_C:
10884                 rc = power_down_qam(demod, false);
10885                 if (rc != 0) {
10886                         pr_err("error %d\n", rc);
10887                         goto rw_error;
10888                 }
10889                 break;
10890 #endif
10891         case DRX_STANDARD_8VSB:
10892                 rc = power_down_vsb(demod, false);
10893                 if (rc != 0) {
10894                         pr_err("error %d\n", rc);
10895                         goto rw_error;
10896                 }
10897                 break;
10898         case DRX_STANDARD_UNKNOWN:
10899                 /* Do nothing */
10900                 break;
10901         case DRX_STANDARD_AUTO: /* fallthrough */
10902         default:
10903                 return -EINVAL;
10904         }
10905
10906         /*
10907            Initialize channel independent registers
10908            Power up new standard
10909          */
10910         ext_attr->standard = *standard;
10911
10912         switch (*standard) {
10913 #ifndef DRXJ_VSB_ONLY
10914         case DRX_STANDARD_ITU_A:        /* fallthrough */
10915         case DRX_STANDARD_ITU_B:        /* fallthrough */
10916         case DRX_STANDARD_ITU_C:
10917                 do {
10918                         u16 dummy;
10919                         rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0);
10920                         if (rc != 0) {
10921                                 pr_err("error %d\n", rc);
10922                                 goto rw_error;
10923                         }
10924                 } while (0);
10925                 break;
10926 #endif
10927         case DRX_STANDARD_8VSB:
10928                 rc = set_vsb_leak_n_gain(demod);
10929                 if (rc != 0) {
10930                         pr_err("error %d\n", rc);
10931                         goto rw_error;
10932                 }
10933                 break;
10934         default:
10935                 ext_attr->standard = DRX_STANDARD_UNKNOWN;
10936                 return -EINVAL;
10937                 break;
10938         }
10939
10940         return 0;
10941 rw_error:
10942         /* Don't know what the standard is now ... try again */
10943         ext_attr->standard = DRX_STANDARD_UNKNOWN;
10944         return rc;
10945 }
10946
10947 /*============================================================================*/
10948
10949 static void drxj_reset_mode(struct drxj_data *ext_attr)
10950 {
10951         /* Initialize default AFE configuartion for QAM */
10952         if (ext_attr->has_lna) {
10953                 /* IF AGC off, PGA active */
10954 #ifndef DRXJ_VSB_ONLY
10955                 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10956                 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10957                 ext_attr->qam_pga_cfg = 140 + (11 * 13);
10958 #endif
10959                 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10960                 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10961                 ext_attr->vsb_pga_cfg = 140 + (11 * 13);
10962         } else {
10963                 /* IF AGC on, PGA not active */
10964 #ifndef DRXJ_VSB_ONLY
10965                 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10966                 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10967                 ext_attr->qam_if_agc_cfg.min_output_level = 0;
10968                 ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF;
10969                 ext_attr->qam_if_agc_cfg.speed = 3;
10970                 ext_attr->qam_if_agc_cfg.top = 1297;
10971                 ext_attr->qam_pga_cfg = 140;
10972 #endif
10973                 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10974                 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10975                 ext_attr->vsb_if_agc_cfg.min_output_level = 0;
10976                 ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF;
10977                 ext_attr->vsb_if_agc_cfg.speed = 3;
10978                 ext_attr->vsb_if_agc_cfg.top = 1024;
10979                 ext_attr->vsb_pga_cfg = 140;
10980         }
10981         /* TODO: remove min_output_level and max_output_level for both QAM and VSB after */
10982         /* mc has not used them */
10983 #ifndef DRXJ_VSB_ONLY
10984         ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B;
10985         ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10986         ext_attr->qam_rf_agc_cfg.min_output_level = 0;
10987         ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF;
10988         ext_attr->qam_rf_agc_cfg.speed = 3;
10989         ext_attr->qam_rf_agc_cfg.top = 9500;
10990         ext_attr->qam_rf_agc_cfg.cut_off_current = 4000;
10991         ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B;
10992         ext_attr->qam_pre_saw_cfg.reference = 0x07;
10993         ext_attr->qam_pre_saw_cfg.use_pre_saw = true;
10994 #endif
10995         /* Initialize default AFE configuartion for VSB */
10996         ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB;
10997         ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10998         ext_attr->vsb_rf_agc_cfg.min_output_level = 0;
10999         ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF;
11000         ext_attr->vsb_rf_agc_cfg.speed = 3;
11001         ext_attr->vsb_rf_agc_cfg.top = 9500;
11002         ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000;
11003         ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB;
11004         ext_attr->vsb_pre_saw_cfg.reference = 0x07;
11005         ext_attr->vsb_pre_saw_cfg.use_pre_saw = true;
11006 }
11007
11008 /**
11009 * \fn int ctrl_power_mode()
11010 * \brief Set the power mode of the device to the specified power mode
11011 * \param demod Pointer to demodulator instance.
11012 * \param mode  Pointer to new power mode.
11013 * \return int.
11014 * \retval 0          Success
11015 * \retval -EIO       I2C error or other failure
11016 * \retval -EINVAL Invalid mode argument.
11017 *
11018 *
11019 */
11020 static int
11021 ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode)
11022 {
11023         struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
11024         struct drxj_data *ext_attr = (struct drxj_data *) NULL;
11025         struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL;
11026         int rc;
11027         u16 sio_cc_pwd_mode = 0;
11028
11029         common_attr = (struct drx_common_attr *) demod->my_common_attr;
11030         ext_attr = (struct drxj_data *) demod->my_ext_attr;
11031         dev_addr = demod->my_i2c_dev_addr;
11032
11033         /* Check arguments */
11034         if (mode == NULL)
11035                 return -EINVAL;
11036
11037         /* If already in requested power mode, do nothing */
11038         if (common_attr->current_power_mode == *mode)
11039                 return 0;
11040
11041         switch (*mode) {
11042         case DRX_POWER_UP:
11043         case DRXJ_POWER_DOWN_MAIN_PATH:
11044                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
11045                 break;
11046         case DRXJ_POWER_DOWN_CORE:
11047                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
11048                 break;
11049         case DRXJ_POWER_DOWN_PLL:
11050                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
11051                 break;
11052         case DRX_POWER_DOWN:
11053                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
11054                 break;
11055         default:
11056                 /* Unknow sleep mode */
11057                 return -EINVAL;
11058                 break;
11059         }
11060
11061         /* Check if device needs to be powered up */
11062         if ((common_attr->current_power_mode != DRX_POWER_UP)) {
11063                 rc = power_up_device(demod);
11064                 if (rc != 0) {
11065                         pr_err("error %d\n", rc);
11066                         goto rw_error;
11067                 }
11068         }
11069
11070         if ((*mode == DRX_POWER_UP)) {
11071                 /* Restore analog & pin configuartion */
11072
11073                 /* Initialize default AFE configuartion for VSB */
11074                 drxj_reset_mode(ext_attr);
11075         } else {
11076                 /* Power down to requested mode */
11077                 /* Backup some register settings */
11078                 /* Set pins with possible pull-ups connected to them in input mode */
11079                 /* Analog power down */
11080                 /* ADC power down */
11081                 /* Power down device */
11082                 /* stop all comm_exec */
11083                 /*
11084                    Stop and power down previous standard
11085                  */
11086
11087                 switch (ext_attr->standard) {
11088                 case DRX_STANDARD_ITU_A:
11089                 case DRX_STANDARD_ITU_B:
11090                 case DRX_STANDARD_ITU_C:
11091                         rc = power_down_qam(demod, true);
11092                         if (rc != 0) {
11093                                 pr_err("error %d\n", rc);
11094                                 goto rw_error;
11095                         }
11096                         break;
11097                 case DRX_STANDARD_8VSB:
11098                         rc = power_down_vsb(demod, true);
11099                         if (rc != 0) {
11100                                 pr_err("error %d\n", rc);
11101                                 goto rw_error;
11102                         }
11103                         break;
11104                 case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */
11105                 case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */
11106                 case DRX_STANDARD_PAL_SECAM_I:  /* fallthrough */
11107                 case DRX_STANDARD_PAL_SECAM_L:  /* fallthrough */
11108                 case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */
11109                 case DRX_STANDARD_NTSC: /* fallthrough */
11110                 case DRX_STANDARD_FM:
11111                         rc = power_down_atv(demod, ext_attr->standard, true);
11112                         if (rc != 0) {
11113                                 pr_err("error %d\n", rc);
11114                                 goto rw_error;
11115                         }
11116                         break;
11117                 case DRX_STANDARD_UNKNOWN:
11118                         /* Do nothing */
11119                         break;
11120                 case DRX_STANDARD_AUTO: /* fallthrough */
11121                 default:
11122                         return -EIO;
11123                 }
11124                 ext_attr->standard = DRX_STANDARD_UNKNOWN;
11125         }
11126
11127         if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) {
11128                 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0);
11129                 if (rc != 0) {
11130                         pr_err("error %d\n", rc);
11131                         goto rw_error;
11132                 }
11133                 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11134                 if (rc != 0) {
11135                         pr_err("error %d\n", rc);
11136                         goto rw_error;
11137                 }
11138
11139                 if ((*mode != DRX_POWER_UP)) {
11140                         /* Initialize HI, wakeup key especially before put IC to sleep */
11141                         rc = init_hi(demod);
11142                         if (rc != 0) {
11143                                 pr_err("error %d\n", rc);
11144                                 goto rw_error;
11145                         }
11146
11147                         ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
11148                         rc = hi_cfg_command(demod);
11149                         if (rc != 0) {
11150                                 pr_err("error %d\n", rc);
11151                                 goto rw_error;
11152                         }
11153                 }
11154         }
11155
11156         common_attr->current_power_mode = *mode;
11157
11158         return 0;
11159 rw_error:
11160         return rc;
11161 }
11162
11163 /*============================================================================*/
11164 /*== CTRL Set/Get Config related functions ===================================*/
11165 /*============================================================================*/
11166
11167 /**
11168 * \fn int ctrl_set_cfg_pre_saw()
11169 * \brief Set Pre-saw reference.
11170 * \param demod demod instance
11171 * \param u16 *
11172 * \return int.
11173 *
11174 * Check arguments
11175 * Dispatch handling to standard specific function.
11176 *
11177 */
11178 static int
11179 ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw)
11180 {
11181         struct i2c_device_addr *dev_addr = NULL;
11182         struct drxj_data *ext_attr = NULL;
11183         int rc;
11184
11185         dev_addr = demod->my_i2c_dev_addr;
11186         ext_attr = (struct drxj_data *) demod->my_ext_attr;
11187
11188         /* check arguments */
11189         if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M)
11190             ) {
11191                 return -EINVAL;
11192         }
11193
11194         /* Only if standard is currently active */
11195         if ((ext_attr->standard == pre_saw->standard) ||
11196             (DRXJ_ISQAMSTD(ext_attr->standard) &&
11197              DRXJ_ISQAMSTD(pre_saw->standard)) ||
11198             (DRXJ_ISATVSTD(ext_attr->standard) &&
11199              DRXJ_ISATVSTD(pre_saw->standard))) {
11200                 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0);
11201                 if (rc != 0) {
11202                         pr_err("error %d\n", rc);
11203                         goto rw_error;
11204                 }
11205         }
11206
11207         /* Store pre-saw settings */
11208         switch (pre_saw->standard) {
11209         case DRX_STANDARD_8VSB:
11210                 ext_attr->vsb_pre_saw_cfg = *pre_saw;
11211                 break;
11212 #ifndef DRXJ_VSB_ONLY
11213         case DRX_STANDARD_ITU_A:        /* fallthrough */
11214         case DRX_STANDARD_ITU_B:        /* fallthrough */
11215         case DRX_STANDARD_ITU_C:
11216                 ext_attr->qam_pre_saw_cfg = *pre_saw;
11217                 break;
11218 #endif
11219         default:
11220                 return -EINVAL;
11221         }
11222
11223         return 0;
11224 rw_error:
11225         return rc;
11226 }
11227
11228 /*============================================================================*/
11229
11230 /**
11231 * \fn int ctrl_set_cfg_afe_gain()
11232 * \brief Set AFE Gain.
11233 * \param demod demod instance
11234 * \param u16 *
11235 * \return int.
11236 *
11237 * Check arguments
11238 * Dispatch handling to standard specific function.
11239 *
11240 */
11241 static int
11242 ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain)
11243 {
11244         struct i2c_device_addr *dev_addr = NULL;
11245         struct drxj_data *ext_attr = NULL;
11246         int rc;
11247         u8 gain = 0;
11248
11249         /* check arguments */
11250         if (afe_gain == NULL)
11251                 return -EINVAL;
11252
11253         dev_addr = demod->my_i2c_dev_addr;
11254         ext_attr = (struct drxj_data *) demod->my_ext_attr;
11255
11256         switch (afe_gain->standard) {
11257         case DRX_STANDARD_8VSB: /* fallthrough */
11258 #ifndef DRXJ_VSB_ONLY
11259         case DRX_STANDARD_ITU_A:        /* fallthrough */
11260         case DRX_STANDARD_ITU_B:        /* fallthrough */
11261         case DRX_STANDARD_ITU_C:
11262 #endif
11263                 /* Do nothing */
11264                 break;
11265         default:
11266                 return -EINVAL;
11267         }
11268
11269         /* TODO PGA gain is also written by microcode (at least by QAM and VSB)
11270            So I (PJ) think interface requires choice between auto, user mode */
11271
11272         if (afe_gain->gain >= 329)
11273                 gain = 15;
11274         else if (afe_gain->gain <= 147)
11275                 gain = 0;
11276         else
11277                 gain = (afe_gain->gain - 140 + 6) / 13;
11278
11279         /* Only if standard is currently active */
11280         if (ext_attr->standard == afe_gain->standard) {
11281                         rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0);
11282                         if (rc != 0) {
11283                                 pr_err("error %d\n", rc);
11284                                 goto rw_error;
11285                         }
11286                 }
11287
11288         /* Store AFE Gain settings */
11289         switch (afe_gain->standard) {
11290         case DRX_STANDARD_8VSB:
11291                 ext_attr->vsb_pga_cfg = gain * 13 + 140;
11292                 break;
11293 #ifndef DRXJ_VSB_ONLY
11294         case DRX_STANDARD_ITU_A:        /* fallthrough */
11295         case DRX_STANDARD_ITU_B:        /* fallthrough */
11296         case DRX_STANDARD_ITU_C:
11297                 ext_attr->qam_pga_cfg = gain * 13 + 140;
11298                 break;
11299 #endif
11300         default:
11301                 return -EIO;
11302         }
11303
11304         return 0;
11305 rw_error:
11306         return rc;
11307 }
11308
11309 /*============================================================================*/
11310
11311
11312 /*=============================================================================
11313 ===== EXPORTED FUNCTIONS ====================================================*/
11314
11315 static int drx_ctrl_u_code(struct drx_demod_instance *demod,
11316                        struct drxu_code_info *mc_info,
11317                        enum drxu_code_action action);
11318 static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state);
11319
11320 /**
11321 * \fn drxj_open()
11322 * \brief Open the demod instance, configure device, configure drxdriver
11323 * \return Status_t Return status.
11324 *
11325 * drxj_open() can be called with a NULL ucode image => no ucode upload.
11326 * This means that drxj_open() must NOT contain SCU commands or, in general,
11327 * rely on SCU or AUD ucode to be present.
11328 *
11329 */
11330
11331 static int drxj_open(struct drx_demod_instance *demod)
11332 {
11333         struct i2c_device_addr *dev_addr = NULL;
11334         struct drxj_data *ext_attr = NULL;
11335         struct drx_common_attr *common_attr = NULL;
11336         u32 driver_version = 0;
11337         struct drxu_code_info ucode_info;
11338         struct drx_cfg_mpeg_output cfg_mpeg_output;
11339         int rc;
11340         enum drx_power_mode power_mode = DRX_POWER_UP;
11341
11342         if ((demod == NULL) ||
11343             (demod->my_common_attr == NULL) ||
11344             (demod->my_ext_attr == NULL) ||
11345             (demod->my_i2c_dev_addr == NULL) ||
11346             (demod->my_common_attr->is_opened)) {
11347                 return -EINVAL;
11348         }
11349
11350         /* Check arguments */
11351         if (demod->my_ext_attr == NULL)
11352                 return -EINVAL;
11353
11354         dev_addr = demod->my_i2c_dev_addr;
11355         ext_attr = (struct drxj_data *) demod->my_ext_attr;
11356         common_attr = (struct drx_common_attr *) demod->my_common_attr;
11357
11358         rc = ctrl_power_mode(demod, &power_mode);
11359         if (rc != 0) {
11360                 pr_err("error %d\n", rc);
11361                 goto rw_error;
11362         }
11363         if (power_mode != DRX_POWER_UP) {
11364                 rc = -EINVAL;
11365                 pr_err("failed to powerup device\n");
11366                 goto rw_error;
11367         }
11368
11369         /* has to be in front of setIqmAf and setOrxNsuAox */
11370         rc = get_device_capabilities(demod);
11371         if (rc != 0) {
11372                 pr_err("error %d\n", rc);
11373                 goto rw_error;
11374         }
11375
11376         /*
11377          * Soft reset of sys- and osc-clockdomain
11378          *
11379          * HACK: On windows, it writes a 0x07 here, instead of just 0x03.
11380          * As we didn't load the firmware here yet, we should do the same.
11381          * Btw, this is coherent with DRX-K, where we send reset codes
11382          * for modulation (OFTM, in DRX-k), SYS and OSC clock domains.
11383          */
11384         rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0);
11385         if (rc != 0) {
11386                 pr_err("error %d\n", rc);
11387                 goto rw_error;
11388         }
11389         rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11390         if (rc != 0) {
11391                 pr_err("error %d\n", rc);
11392                 goto rw_error;
11393         }
11394         msleep(1);
11395
11396         /* TODO first make sure that everything keeps working before enabling this */
11397         /* PowerDownAnalogBlocks() */
11398         rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0);
11399         if (rc != 0) {
11400                 pr_err("error %d\n", rc);
11401                 goto rw_error;
11402         }
11403
11404         rc = set_iqm_af(demod, false);
11405         if (rc != 0) {
11406                 pr_err("error %d\n", rc);
11407                 goto rw_error;
11408         }
11409         rc = set_orx_nsu_aox(demod, false);
11410         if (rc != 0) {
11411                 pr_err("error %d\n", rc);
11412                 goto rw_error;
11413         }
11414
11415         rc = init_hi(demod);
11416         if (rc != 0) {
11417                 pr_err("error %d\n", rc);
11418                 goto rw_error;
11419         }
11420
11421         /* disable mpegoutput pins */
11422         memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
11423         cfg_mpeg_output.enable_mpeg_output = false;
11424
11425         rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
11426         if (rc != 0) {
11427                 pr_err("error %d\n", rc);
11428                 goto rw_error;
11429         }
11430         /* Stop AUD Inform SetAudio it will need to do all setting */
11431         rc = power_down_aud(demod);
11432         if (rc != 0) {
11433                 pr_err("error %d\n", rc);
11434                 goto rw_error;
11435         }
11436         /* Stop SCU */
11437         rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0);
11438         if (rc != 0) {
11439                 pr_err("error %d\n", rc);
11440                 goto rw_error;
11441         }
11442
11443         /* Upload microcode */
11444         if (common_attr->microcode_file != NULL) {
11445                 /* Dirty trick to use common ucode upload & verify,
11446                    pretend device is already open */
11447                 common_attr->is_opened = true;
11448                 ucode_info.mc_file = common_attr->microcode_file;
11449
11450                 if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) {
11451                         pr_err("Should powerup before loading the firmware.");
11452                         return -EINVAL;
11453                 }
11454
11455                 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD);
11456                 if (rc != 0) {
11457                         pr_err("error %d while uploading the firmware\n", rc);
11458                         goto rw_error;
11459                 }
11460                 if (common_attr->verify_microcode == true) {
11461                         rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY);
11462                         if (rc != 0) {
11463                                 pr_err("error %d while verifying the firmware\n",
11464                                        rc);
11465                                 goto rw_error;
11466                         }
11467                 }
11468                 common_attr->is_opened = false;
11469         }
11470
11471         /* Run SCU for a little while to initialize microcode version numbers */
11472         rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11473         if (rc != 0) {
11474                 pr_err("error %d\n", rc);
11475                 goto rw_error;
11476         }
11477
11478         /* Initialize scan timeout */
11479         common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT;
11480         common_attr->scan_desired_lock = DRX_LOCKED;
11481
11482         drxj_reset_mode(ext_attr);
11483         ext_attr->standard = DRX_STANDARD_UNKNOWN;
11484
11485         rc = smart_ant_init(demod);
11486         if (rc != 0) {
11487                 pr_err("error %d\n", rc);
11488                 goto rw_error;
11489         }
11490
11491         /* Stamp driver version number in SCU data RAM in BCD code
11492            Done to enable field application engineers to retreive drxdriver version
11493            via I2C from SCU RAM
11494          */
11495         driver_version = (VERSION_MAJOR / 100) % 10;
11496         driver_version <<= 4;
11497         driver_version += (VERSION_MAJOR / 10) % 10;
11498         driver_version <<= 4;
11499         driver_version += (VERSION_MAJOR % 10);
11500         driver_version <<= 4;
11501         driver_version += (VERSION_MINOR % 10);
11502         driver_version <<= 4;
11503         driver_version += (VERSION_PATCH / 1000) % 10;
11504         driver_version <<= 4;
11505         driver_version += (VERSION_PATCH / 100) % 10;
11506         driver_version <<= 4;
11507         driver_version += (VERSION_PATCH / 10) % 10;
11508         driver_version <<= 4;
11509         driver_version += (VERSION_PATCH % 10);
11510         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0);
11511         if (rc != 0) {
11512                 pr_err("error %d\n", rc);
11513                 goto rw_error;
11514         }
11515         rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0);
11516         if (rc != 0) {
11517                 pr_err("error %d\n", rc);
11518                 goto rw_error;
11519         }
11520
11521         rc = ctrl_set_oob(demod, NULL);
11522         if (rc != 0) {
11523                 pr_err("error %d\n", rc);
11524                 goto rw_error;
11525         }
11526
11527         /* refresh the audio data structure with default */
11528         ext_attr->aud_data = drxj_default_aud_data_g;
11529
11530         demod->my_common_attr->is_opened = true;
11531         drxj_set_lna_state(demod, false);
11532         return 0;
11533 rw_error:
11534         common_attr->is_opened = false;
11535         return rc;
11536 }
11537
11538 /*============================================================================*/
11539 /**
11540 * \fn drxj_close()
11541 * \brief Close the demod instance, power down the device
11542 * \return Status_t Return status.
11543 *
11544 */
11545 static int drxj_close(struct drx_demod_instance *demod)
11546 {
11547         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
11548         int rc;
11549         enum drx_power_mode power_mode = DRX_POWER_UP;
11550
11551         if ((demod->my_common_attr == NULL) ||
11552             (demod->my_ext_attr == NULL) ||
11553             (demod->my_i2c_dev_addr == NULL) ||
11554             (!demod->my_common_attr->is_opened)) {
11555                 return -EINVAL;
11556         }
11557
11558         /* power up */
11559         rc = ctrl_power_mode(demod, &power_mode);
11560         if (rc != 0) {
11561                 pr_err("error %d\n", rc);
11562                 goto rw_error;
11563         }
11564
11565         rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11566         if (rc != 0) {
11567                 pr_err("error %d\n", rc);
11568                 goto rw_error;
11569         }
11570         power_mode = DRX_POWER_DOWN;
11571         rc = ctrl_power_mode(demod, &power_mode);
11572         if (rc != 0) {
11573                 pr_err("error %d\n", rc);
11574                 goto rw_error;
11575         }
11576
11577         DRX_ATTR_ISOPENED(demod) = false;
11578
11579         return 0;
11580 rw_error:
11581         DRX_ATTR_ISOPENED(demod) = false;
11582
11583         return rc;
11584 }
11585
11586 /*
11587  * Microcode related functions
11588  */
11589
11590 /**
11591  * drx_u_code_compute_crc       - Compute CRC of block of microcode data.
11592  * @block_data: Pointer to microcode data.
11593  * @nr_words:   Size of microcode block (number of 16 bits words).
11594  *
11595  * returns The computed CRC residue.
11596  */
11597 static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words)
11598 {
11599         u16 i = 0;
11600         u16 j = 0;
11601         u32 crc_word = 0;
11602         u32 carry = 0;
11603
11604         while (i < nr_words) {
11605                 crc_word |= (u32)be16_to_cpu(*(__be16 *)(block_data));
11606                 for (j = 0; j < 16; j++) {
11607                         crc_word <<= 1;
11608                         if (carry != 0)
11609                                 crc_word ^= 0x80050000UL;
11610                         carry = crc_word & 0x80000000UL;
11611                 }
11612                 i++;
11613                 block_data += (sizeof(u16));
11614         }
11615         return (u16)(crc_word >> 16);
11616 }
11617
11618 /**
11619  * drx_check_firmware - checks if the loaded firmware is valid
11620  *
11621  * @demod:      demod structure
11622  * @mc_data:    pointer to the start of the firmware
11623  * @size:       firmware size
11624  */
11625 static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data,
11626                           unsigned size)
11627 {
11628         struct drxu_code_block_hdr block_hdr;
11629         int i;
11630         unsigned count = 2 * sizeof(u16);
11631         u32 mc_dev_type, mc_version, mc_base_version;
11632         u16 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data + sizeof(u16)));
11633
11634         /*
11635          * Scan microcode blocks first for version info
11636          * and firmware check
11637          */
11638
11639         /* Clear version block */
11640         DRX_ATTR_MCRECORD(demod).aux_type = 0;
11641         DRX_ATTR_MCRECORD(demod).mc_dev_type = 0;
11642         DRX_ATTR_MCRECORD(demod).mc_version = 0;
11643         DRX_ATTR_MCRECORD(demod).mc_base_version = 0;
11644
11645         for (i = 0; i < mc_nr_of_blks; i++) {
11646                 if (count + 3 * sizeof(u16) + sizeof(u32) > size)
11647                         goto eof;
11648
11649                 /* Process block header */
11650                 block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data + count));
11651                 count += sizeof(u32);
11652                 block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data + count));
11653                 count += sizeof(u16);
11654                 block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data + count));
11655                 count += sizeof(u16);
11656                 block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data + count));
11657                 count += sizeof(u16);
11658
11659                 pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
11660                         count, block_hdr.addr, block_hdr.size, block_hdr.flags,
11661                         block_hdr.CRC);
11662
11663                 if (block_hdr.flags & 0x8) {
11664                         u8 *auxblk = ((void *)mc_data) + block_hdr.addr;
11665                         u16 auxtype;
11666
11667                         if (block_hdr.addr + sizeof(u16) > size)
11668                                 goto eof;
11669
11670                         auxtype = be16_to_cpu(*(__be16 *)(auxblk));
11671
11672                         /* Aux block. Check type */
11673                         if (DRX_ISMCVERTYPE(auxtype)) {
11674                                 if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size)
11675                                         goto eof;
11676
11677                                 auxblk += sizeof(u16);
11678                                 mc_dev_type = be32_to_cpu(*(__be32 *)(auxblk));
11679                                 auxblk += sizeof(u32);
11680                                 mc_version = be32_to_cpu(*(__be32 *)(auxblk));
11681                                 auxblk += sizeof(u32);
11682                                 mc_base_version = be32_to_cpu(*(__be32 *)(auxblk));
11683
11684                                 DRX_ATTR_MCRECORD(demod).aux_type = auxtype;
11685                                 DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type;
11686                                 DRX_ATTR_MCRECORD(demod).mc_version = mc_version;
11687                                 DRX_ATTR_MCRECORD(demod).mc_base_version = mc_base_version;
11688
11689                                 pr_info("Firmware dev %x, ver %x, base ver %x\n",
11690                                         mc_dev_type, mc_version, mc_base_version);
11691
11692                         }
11693                 } else if (count + block_hdr.size * sizeof(u16) > size)
11694                         goto eof;
11695
11696                 count += block_hdr.size * sizeof(u16);
11697         }
11698         return 0;
11699 eof:
11700         pr_err("Firmware is truncated at pos %u/%u\n", count, size);
11701         return -EINVAL;
11702 }
11703
11704 /**
11705  * drx_ctrl_u_code - Handle microcode upload or verify.
11706  * @dev_addr: Address of device.
11707  * @mc_info:  Pointer to information about microcode data.
11708  * @action:  Either UCODE_UPLOAD or UCODE_VERIFY
11709  *
11710  * This function returns:
11711  *      0:
11712  *              - In case of UCODE_UPLOAD: code is successfully uploaded.
11713  *               - In case of UCODE_VERIFY: image on device is equal to
11714  *                image provided to this control function.
11715  *      -EIO:
11716  *              - In case of UCODE_UPLOAD: I2C error.
11717  *              - In case of UCODE_VERIFY: I2C error or image on device
11718  *                is not equal to image provided to this control function.
11719  *      -EINVAL:
11720  *              - Invalid arguments.
11721  *              - Provided image is corrupt
11722  */
11723 static int drx_ctrl_u_code(struct drx_demod_instance *demod,
11724                        struct drxu_code_info *mc_info,
11725                        enum drxu_code_action action)
11726 {
11727         struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
11728         int rc;
11729         u16 i = 0;
11730         u16 mc_nr_of_blks = 0;
11731         u16 mc_magic_word = 0;
11732         const u8 *mc_data_init = NULL;
11733         u8 *mc_data = NULL;
11734         unsigned size;
11735         char *mc_file;
11736
11737         /* Check arguments */
11738         if (!mc_info || !mc_info->mc_file)
11739                 return -EINVAL;
11740
11741         mc_file = mc_info->mc_file;
11742
11743         if (!demod->firmware) {
11744                 const struct firmware *fw = NULL;
11745
11746                 rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent);
11747                 if (rc < 0) {
11748                         pr_err("Couldn't read firmware %s\n", mc_file);
11749                         return rc;
11750                 }
11751                 demod->firmware = fw;
11752
11753                 if (demod->firmware->size < 2 * sizeof(u16)) {
11754                         rc = -EINVAL;
11755                         pr_err("Firmware is too short!\n");
11756                         goto release;
11757                 }
11758
11759                 pr_info("Firmware %s, size %zu\n",
11760                         mc_file, demod->firmware->size);
11761         }
11762
11763         mc_data_init = demod->firmware->data;
11764         size = demod->firmware->size;
11765
11766         mc_data = (void *)mc_data_init;
11767         /* Check data */
11768         mc_magic_word = be16_to_cpu(*(__be16 *)(mc_data));
11769         mc_data += sizeof(u16);
11770         mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data));
11771         mc_data += sizeof(u16);
11772
11773         if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) {
11774                 rc = -EINVAL;
11775                 pr_err("Firmware magic word doesn't match\n");
11776                 goto release;
11777         }
11778
11779         if (action == UCODE_UPLOAD) {
11780                 rc = drx_check_firmware(demod, (u8 *)mc_data_init, size);
11781                 if (rc)
11782                         goto release;
11783                 pr_info("Uploading firmware %s\n", mc_file);
11784         } else {
11785                 pr_info("Verifying if firmware upload was ok.\n");
11786         }
11787
11788         /* Process microcode blocks */
11789         for (i = 0; i < mc_nr_of_blks; i++) {
11790                 struct drxu_code_block_hdr block_hdr;
11791                 u16 mc_block_nr_bytes = 0;
11792
11793                 /* Process block header */
11794                 block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data));
11795                 mc_data += sizeof(u32);
11796                 block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data));
11797                 mc_data += sizeof(u16);
11798                 block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data));
11799                 mc_data += sizeof(u16);
11800                 block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data));
11801                 mc_data += sizeof(u16);
11802
11803                 pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
11804                         (unsigned)(mc_data - mc_data_init), block_hdr.addr,
11805                          block_hdr.size, block_hdr.flags, block_hdr.CRC);
11806
11807                 /* Check block header on:
11808                    - data larger than 64Kb
11809                    - if CRC enabled check CRC
11810                  */
11811                 if ((block_hdr.size > 0x7FFF) ||
11812                     (((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) &&
11813                      (block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size)))
11814                     ) {
11815                         /* Wrong data ! */
11816                         rc = -EINVAL;
11817                         pr_err("firmware CRC is wrong\n");
11818                         goto release;
11819                 }
11820
11821                 if (!block_hdr.size)
11822                         continue;
11823
11824                 mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16));
11825
11826                 /* Perform the desired action */
11827                 switch (action) {
11828                 case UCODE_UPLOAD:      /* Upload microcode */
11829                         if (drxdap_fasi_write_block(dev_addr,
11830                                                         block_hdr.addr,
11831                                                         mc_block_nr_bytes,
11832                                                         mc_data, 0x0000)) {
11833                                 rc = -EIO;
11834                                 pr_err("error writing firmware at pos %u\n",
11835                                        (unsigned)(mc_data - mc_data_init));
11836                                 goto release;
11837                         }
11838                         break;
11839                 case UCODE_VERIFY: {    /* Verify uploaded microcode */
11840                         int result = 0;
11841                         u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE];
11842                         u32 bytes_to_comp = 0;
11843                         u32 bytes_left = mc_block_nr_bytes;
11844                         u32 curr_addr = block_hdr.addr;
11845                         u8 *curr_ptr = mc_data;
11846
11847                         while (bytes_left != 0) {
11848                                 if (bytes_left > DRX_UCODE_MAX_BUF_SIZE)
11849                                         bytes_to_comp = DRX_UCODE_MAX_BUF_SIZE;
11850                                 else
11851                                         bytes_to_comp = bytes_left;
11852
11853                                 if (drxdap_fasi_read_block(dev_addr,
11854                                                     curr_addr,
11855                                                     (u16)bytes_to_comp,
11856                                                     (u8 *)mc_data_buffer,
11857                                                     0x0000)) {
11858                                         pr_err("error reading firmware at pos %u\n",
11859                                                (unsigned)(mc_data - mc_data_init));
11860                                         return -EIO;
11861                                 }
11862
11863                                 result = memcmp(curr_ptr, mc_data_buffer,
11864                                                 bytes_to_comp);
11865
11866                                 if (result) {
11867                                         pr_err("error verifying firmware at pos %u\n",
11868                                                (unsigned)(mc_data - mc_data_init));
11869                                         return -EIO;
11870                                 }
11871
11872                                 curr_addr += ((dr_xaddr_t)(bytes_to_comp / 2));
11873                                 curr_ptr =&(curr_ptr[bytes_to_comp]);
11874                                 bytes_left -=((u32) bytes_to_comp);
11875                         }
11876                         break;
11877                 }
11878                 default:
11879                         return -EINVAL;
11880                         break;
11881
11882                 }
11883                 mc_data += mc_block_nr_bytes;
11884         }
11885
11886         return 0;
11887
11888 release:
11889         release_firmware(demod->firmware);
11890         demod->firmware = NULL;
11891
11892         return rc;
11893 }
11894
11895 /* caller is expeced to check if lna is supported before enabling */
11896 static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state)
11897 {
11898         struct drxuio_cfg uio_cfg;
11899         struct drxuio_data uio_data;
11900         int result;
11901
11902         uio_cfg.uio = DRX_UIO1;
11903         uio_cfg.mode = DRX_UIO_MODE_READWRITE;
11904         /* Configure user-I/O #3: enable read/write */
11905         result = ctrl_set_uio_cfg(demod, &uio_cfg);
11906         if (result) {
11907                 pr_err("Failed to setup LNA GPIO!\n");
11908                 return result;
11909         }
11910
11911         uio_data.uio = DRX_UIO1;
11912         uio_data.value = state;
11913         result = ctrl_uio_write(demod, &uio_data);
11914         if (result != 0) {
11915                 pr_err("Failed to %sable LNA!\n",
11916                        state ? "en" : "dis");
11917                 return result;
11918         }
11919         return 0;
11920 }
11921
11922 /*
11923  * The Linux DVB Driver for Micronas DRX39xx family (drx3933j)
11924  *
11925  * Written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
11926  */
11927
11928 static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable)
11929 {
11930         struct drx39xxj_state *state = fe->demodulator_priv;
11931         struct drx_demod_instance *demod = state->demod;
11932         int result;
11933         enum drx_power_mode power_mode;
11934
11935         if (enable)
11936                 power_mode = DRX_POWER_UP;
11937         else
11938                 power_mode = DRX_POWER_DOWN;
11939
11940         result = ctrl_power_mode(demod, &power_mode);
11941         if (result != 0) {
11942                 pr_err("Power state change failed\n");
11943                 return 0;
11944         }
11945
11946         return 0;
11947 }
11948
11949 static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status)
11950 {
11951         struct drx39xxj_state *state = fe->demodulator_priv;
11952         struct drx_demod_instance *demod = state->demod;
11953         int result;
11954         enum drx_lock_status lock_status;
11955
11956         *status = 0;
11957
11958         result = ctrl_lock_status(demod, &lock_status);
11959         if (result != 0) {
11960                 pr_err("drx39xxj: could not get lock status!\n");
11961                 *status = 0;
11962         }
11963
11964         switch (lock_status) {
11965         case DRX_NEVER_LOCK:
11966                 *status = 0;
11967                 pr_err("drx says NEVER_LOCK\n");
11968                 break;
11969         case DRX_NOT_LOCKED:
11970                 *status = 0;
11971                 break;
11972         case DRX_LOCK_STATE_1:
11973         case DRX_LOCK_STATE_2:
11974         case DRX_LOCK_STATE_3:
11975         case DRX_LOCK_STATE_4:
11976         case DRX_LOCK_STATE_5:
11977         case DRX_LOCK_STATE_6:
11978         case DRX_LOCK_STATE_7:
11979         case DRX_LOCK_STATE_8:
11980         case DRX_LOCK_STATE_9:
11981                 *status = FE_HAS_SIGNAL
11982                     | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
11983                 break;
11984         case DRX_LOCKED:
11985                 *status = FE_HAS_SIGNAL
11986                     | FE_HAS_CARRIER
11987                     | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
11988                 break;
11989         default:
11990                 pr_err("Lock state unknown %d\n", lock_status);
11991         }
11992         ctrl_sig_quality(demod, lock_status);
11993
11994         return 0;
11995 }
11996
11997 static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber)
11998 {
11999         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12000
12001         if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12002                 *ber = 0;
12003                 return 0;
12004         }
12005
12006         if (!p->pre_bit_count.stat[0].uvalue) {
12007                 if (!p->pre_bit_error.stat[0].uvalue)
12008                         *ber = 0;
12009                 else
12010                         *ber = 1000000;
12011         } else {
12012                 *ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue,
12013                                      p->pre_bit_count.stat[0].uvalue);
12014         }
12015         return 0;
12016 }
12017
12018 static int drx39xxj_read_signal_strength(struct dvb_frontend *fe,
12019                                          u16 *strength)
12020 {
12021         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12022
12023         if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12024                 *strength = 0;
12025                 return 0;
12026         }
12027
12028         *strength = p->strength.stat[0].uvalue;
12029         return 0;
12030 }
12031
12032 static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr)
12033 {
12034         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12035         u64 tmp64;
12036
12037         if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12038                 *snr = 0;
12039                 return 0;
12040         }
12041
12042         tmp64 = p->cnr.stat[0].svalue;
12043         do_div(tmp64, 10);
12044         *snr = tmp64;
12045         return 0;
12046 }
12047
12048 static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucb)
12049 {
12050         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12051
12052         if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12053                 *ucb = 0;
12054                 return 0;
12055         }
12056
12057         *ucb = p->block_error.stat[0].uvalue;
12058         return 0;
12059 }
12060
12061 static int drx39xxj_set_frontend(struct dvb_frontend *fe)
12062 {
12063 #ifdef DJH_DEBUG
12064         int i;
12065 #endif
12066         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12067         struct drx39xxj_state *state = fe->demodulator_priv;
12068         struct drx_demod_instance *demod = state->demod;
12069         enum drx_standard standard = DRX_STANDARD_8VSB;
12070         struct drx_channel channel;
12071         int result;
12072         static const struct drx_channel def_channel = {
12073                 /* frequency      */ 0,
12074                 /* bandwidth      */ DRX_BANDWIDTH_6MHZ,
12075                 /* mirror         */ DRX_MIRROR_NO,
12076                 /* constellation  */ DRX_CONSTELLATION_AUTO,
12077                 /* hierarchy      */ DRX_HIERARCHY_UNKNOWN,
12078                 /* priority       */ DRX_PRIORITY_UNKNOWN,
12079                 /* coderate       */ DRX_CODERATE_UNKNOWN,
12080                 /* guard          */ DRX_GUARD_UNKNOWN,
12081                 /* fftmode        */ DRX_FFTMODE_UNKNOWN,
12082                 /* classification */ DRX_CLASSIFICATION_AUTO,
12083                 /* symbolrate     */ 5057000,
12084                 /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN,
12085                 /* ldpc           */ DRX_LDPC_UNKNOWN,
12086                 /* carrier        */ DRX_CARRIER_UNKNOWN,
12087                 /* frame mode     */ DRX_FRAMEMODE_UNKNOWN
12088         };
12089         u32 constellation = DRX_CONSTELLATION_AUTO;
12090
12091         /* Bring the demod out of sleep */
12092         drx39xxj_set_powerstate(fe, 1);
12093
12094         if (fe->ops.tuner_ops.set_params) {
12095                 u32 int_freq;
12096
12097                 if (fe->ops.i2c_gate_ctrl)
12098                         fe->ops.i2c_gate_ctrl(fe, 1);
12099
12100                 /* Set tuner to desired frequency and standard */
12101                 fe->ops.tuner_ops.set_params(fe);
12102
12103                 /* Use the tuner's IF */
12104                 if (fe->ops.tuner_ops.get_if_frequency) {
12105                         fe->ops.tuner_ops.get_if_frequency(fe, &int_freq);
12106                         demod->my_common_attr->intermediate_freq = int_freq / 1000;
12107                 }
12108
12109                 if (fe->ops.i2c_gate_ctrl)
12110                         fe->ops.i2c_gate_ctrl(fe, 0);
12111         }
12112
12113         switch (p->delivery_system) {
12114         case SYS_ATSC:
12115                 standard = DRX_STANDARD_8VSB;
12116                 break;
12117         case SYS_DVBC_ANNEX_B:
12118                 standard = DRX_STANDARD_ITU_B;
12119
12120                 switch (p->modulation) {
12121                 case QAM_64:
12122                         constellation = DRX_CONSTELLATION_QAM64;
12123                         break;
12124                 case QAM_256:
12125                         constellation = DRX_CONSTELLATION_QAM256;
12126                         break;
12127                 default:
12128                         constellation = DRX_CONSTELLATION_AUTO;
12129                         break;
12130                 }
12131                 break;
12132         default:
12133                 return -EINVAL;
12134         }
12135         /* Set the standard (will be powered up if necessary */
12136         result = ctrl_set_standard(demod, &standard);
12137         if (result != 0) {
12138                 pr_err("Failed to set standard! result=%02x\n",
12139                         result);
12140                 return -EINVAL;
12141         }
12142
12143         /* set channel parameters */
12144         channel = def_channel;
12145         channel.frequency = p->frequency / 1000;
12146         channel.bandwidth = DRX_BANDWIDTH_6MHZ;
12147         channel.constellation = constellation;
12148
12149         /* program channel */
12150         result = ctrl_set_channel(demod, &channel);
12151         if (result != 0) {
12152                 pr_err("Failed to set channel!\n");
12153                 return -EINVAL;
12154         }
12155         /* Just for giggles, let's shut off the LNA again.... */
12156         drxj_set_lna_state(demod, false);
12157
12158         /* After set_frontend, except for strength, stats aren't available */
12159         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
12160
12161         return 0;
12162 }
12163
12164 static int drx39xxj_sleep(struct dvb_frontend *fe)
12165 {
12166         /* power-down the demodulator */
12167         return drx39xxj_set_powerstate(fe, 0);
12168 }
12169
12170 static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
12171 {
12172         struct drx39xxj_state *state = fe->demodulator_priv;
12173         struct drx_demod_instance *demod = state->demod;
12174         bool i2c_gate_state;
12175         int result;
12176
12177 #ifdef DJH_DEBUG
12178         pr_debug("i2c gate call: enable=%d state=%d\n", enable,
12179                state->i2c_gate_open);
12180 #endif
12181
12182         if (enable)
12183                 i2c_gate_state = true;
12184         else
12185                 i2c_gate_state = false;
12186
12187         if (state->i2c_gate_open == enable) {
12188                 /* We're already in the desired state */
12189                 return 0;
12190         }
12191
12192         result = ctrl_i2c_bridge(demod, &i2c_gate_state);
12193         if (result != 0) {
12194                 pr_err("drx39xxj: could not open i2c gate [%d]\n",
12195                        result);
12196                 dump_stack();
12197         } else {
12198                 state->i2c_gate_open = enable;
12199         }
12200         return 0;
12201 }
12202
12203 static int drx39xxj_init(struct dvb_frontend *fe)
12204 {
12205         struct drx39xxj_state *state = fe->demodulator_priv;
12206         struct drx_demod_instance *demod = state->demod;
12207         int rc = 0;
12208
12209         if (fe->exit == DVB_FE_DEVICE_RESUME) {
12210                 /* so drxj_open() does what it needs to do */
12211                 demod->my_common_attr->is_opened = false;
12212                 rc = drxj_open(demod);
12213                 if (rc != 0)
12214                         pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc);
12215         } else
12216                 drx39xxj_set_powerstate(fe, 1);
12217
12218         return rc;
12219 }
12220
12221 static int drx39xxj_set_lna(struct dvb_frontend *fe)
12222 {
12223         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
12224         struct drx39xxj_state *state = fe->demodulator_priv;
12225         struct drx_demod_instance *demod = state->demod;
12226         struct drxj_data *ext_attr = demod->my_ext_attr;
12227
12228         if (c->lna) {
12229                 if (!ext_attr->has_lna) {
12230                         pr_err("LNA is not supported on this device!\n");
12231                         return -EINVAL;
12232
12233                 }
12234         }
12235
12236         return drxj_set_lna_state(demod, c->lna);
12237 }
12238
12239 static int drx39xxj_get_tune_settings(struct dvb_frontend *fe,
12240                                       struct dvb_frontend_tune_settings *tune)
12241 {
12242         tune->min_delay_ms = 1000;
12243         return 0;
12244 }
12245
12246 static void drx39xxj_release(struct dvb_frontend *fe)
12247 {
12248         struct drx39xxj_state *state = fe->demodulator_priv;
12249         struct drx_demod_instance *demod = state->demod;
12250
12251         /* if device is removed don't access it */
12252         if (fe->exit != DVB_FE_DEVICE_REMOVED)
12253                 drxj_close(demod);
12254
12255         kfree(demod->my_ext_attr);
12256         kfree(demod->my_common_attr);
12257         kfree(demod->my_i2c_dev_addr);
12258         release_firmware(demod->firmware);
12259         kfree(demod);
12260         kfree(state);
12261 }
12262
12263 static struct dvb_frontend_ops drx39xxj_ops;
12264
12265 struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
12266 {
12267         struct drx39xxj_state *state = NULL;
12268         struct i2c_device_addr *demod_addr = NULL;
12269         struct drx_common_attr *demod_comm_attr = NULL;
12270         struct drxj_data *demod_ext_attr = NULL;
12271         struct drx_demod_instance *demod = NULL;
12272         struct dtv_frontend_properties *p;
12273         int result;
12274
12275         /* allocate memory for the internal state */
12276         state = kzalloc(sizeof(struct drx39xxj_state), GFP_KERNEL);
12277         if (state == NULL)
12278                 goto error;
12279
12280         demod = kmalloc(sizeof(struct drx_demod_instance), GFP_KERNEL);
12281         if (demod == NULL)
12282                 goto error;
12283
12284         demod_addr = kmemdup(&drxj_default_addr_g,
12285                              sizeof(struct i2c_device_addr), GFP_KERNEL);
12286         if (demod_addr == NULL)
12287                 goto error;
12288
12289         demod_comm_attr = kmemdup(&drxj_default_comm_attr_g,
12290                                   sizeof(struct drx_common_attr), GFP_KERNEL);
12291         if (demod_comm_attr == NULL)
12292                 goto error;
12293
12294         demod_ext_attr = kmemdup(&drxj_data_g, sizeof(struct drxj_data),
12295                                  GFP_KERNEL);
12296         if (demod_ext_attr == NULL)
12297                 goto error;
12298
12299         /* setup the state */
12300         state->i2c = i2c;
12301         state->demod = demod;
12302
12303         /* setup the demod data */
12304         memcpy(demod, &drxj_default_demod_g, sizeof(struct drx_demod_instance));
12305
12306         demod->my_i2c_dev_addr = demod_addr;
12307         demod->my_common_attr = demod_comm_attr;
12308         demod->my_i2c_dev_addr->user_data = state;
12309         demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE;
12310         demod->my_common_attr->verify_microcode = true;
12311         demod->my_common_attr->intermediate_freq = 5000;
12312         demod->my_common_attr->current_power_mode = DRX_POWER_DOWN;
12313         demod->my_ext_attr = demod_ext_attr;
12314         ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE;
12315         demod->i2c = i2c;
12316
12317         result = drxj_open(demod);
12318         if (result != 0) {
12319                 pr_err("DRX open failed!  Aborting\n");
12320                 goto error;
12321         }
12322
12323         /* create dvb_frontend */
12324         memcpy(&state->frontend.ops, &drx39xxj_ops,
12325                sizeof(struct dvb_frontend_ops));
12326
12327         state->frontend.demodulator_priv = state;
12328
12329         /* Initialize stats - needed for DVBv5 stats to work */
12330         p = &state->frontend.dtv_property_cache;
12331         p->strength.len = 1;
12332         p->pre_bit_count.len = 1;
12333         p->pre_bit_error.len = 1;
12334         p->post_bit_count.len = 1;
12335         p->post_bit_error.len = 1;
12336         p->block_count.len = 1;
12337         p->block_error.len = 1;
12338         p->cnr.len = 1;
12339
12340         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
12341         p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12342         p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12343         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12344         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12345         p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12346         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12347         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12348
12349         return &state->frontend;
12350
12351 error:
12352         kfree(demod_ext_attr);
12353         kfree(demod_comm_attr);
12354         kfree(demod_addr);
12355         kfree(demod);
12356         kfree(state);
12357
12358         return NULL;
12359 }
12360 EXPORT_SYMBOL(drx39xxj_attach);
12361
12362 static struct dvb_frontend_ops drx39xxj_ops = {
12363         .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
12364         .info = {
12365                  .name = "Micronas DRX39xxj family Frontend",
12366                  .frequency_stepsize = 62500,
12367                  .frequency_min = 51000000,
12368                  .frequency_max = 858000000,
12369                  .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
12370         },
12371
12372         .init = drx39xxj_init,
12373         .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl,
12374         .sleep = drx39xxj_sleep,
12375         .set_frontend = drx39xxj_set_frontend,
12376         .get_tune_settings = drx39xxj_get_tune_settings,
12377         .read_status = drx39xxj_read_status,
12378         .read_ber = drx39xxj_read_ber,
12379         .read_signal_strength = drx39xxj_read_signal_strength,
12380         .read_snr = drx39xxj_read_snr,
12381         .read_ucblocks = drx39xxj_read_ucblocks,
12382         .release = drx39xxj_release,
12383         .set_lna = drx39xxj_set_lna,
12384 };
12385
12386 MODULE_DESCRIPTION("Micronas DRX39xxj Frontend");
12387 MODULE_AUTHOR("Devin Heitmueller");
12388 MODULE_LICENSE("GPL");
12389 MODULE_FIRMWARE(DRX39XX_MAIN_FIRMWARE);