kernel/drivers/infiniband/hw/ocrdma/ocrdma_sli.h

   1 /* This file is part of the Emulex RoCE Device Driver for
   2  * RoCE (RDMA over Converged Ethernet) adapters.
   3  * Copyright (C) 2012-2015 Emulex. All rights reserved.
   4  * EMULEX and SLI are trademarks of Emulex.
   5  * www.emulex.com
   6  *
   7  * This software is available to you under a choice of one of two licenses.
   8  * You may choose to be licensed under the terms of the GNU General Public
   9  * License (GPL) Version 2, available from the file COPYING in the main
  10  * directory of this source tree, or the BSD license below:
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  *
  16  * - Redistributions of source code must retain the above copyright notice,
  17  *   this list of conditions and the following disclaimer.
  18  *
  19  * - Redistributions in binary form must reproduce the above copyright
  20  *   notice, this list of conditions and the following disclaimer in
  21  *   the documentation and/or other materials provided with the distribution.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  24  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  32  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  33  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  *
  35  * Contact Information:
  36  * linux-drivers@emulex.com
  37  *
  38  * Emulex
  39  * 3333 Susan Street
  40  * Costa Mesa, CA 92626
  41  */
  42
  43 #ifndef __OCRDMA_SLI_H__
  44 #define __OCRDMA_SLI_H__
  45
  46 enum {
  47         OCRDMA_ASIC_GEN_SKH_R = 0x04,
  48         OCRDMA_ASIC_GEN_LANCER = 0x0B
  49 };
  50
  51 enum {
  52         OCRDMA_ASIC_REV_A0 = 0x00,
  53         OCRDMA_ASIC_REV_B0 = 0x10,
  54         OCRDMA_ASIC_REV_C0 = 0x20
  55 };
  56
  57 #define OCRDMA_SUBSYS_ROCE 10
  58 enum {
  59         OCRDMA_CMD_QUERY_CONFIG = 1,
  60         OCRDMA_CMD_ALLOC_PD = 2,
  61         OCRDMA_CMD_DEALLOC_PD = 3,
  62
  63         OCRDMA_CMD_CREATE_AH_TBL = 4,
  64         OCRDMA_CMD_DELETE_AH_TBL = 5,
  65
  66         OCRDMA_CMD_CREATE_QP = 6,
  67         OCRDMA_CMD_QUERY_QP = 7,
  68         OCRDMA_CMD_MODIFY_QP = 8 ,
  69         OCRDMA_CMD_DELETE_QP = 9,
  70
  71         OCRDMA_CMD_RSVD1 = 10,
  72         OCRDMA_CMD_ALLOC_LKEY = 11,
  73         OCRDMA_CMD_DEALLOC_LKEY = 12,
  74         OCRDMA_CMD_REGISTER_NSMR = 13,
  75         OCRDMA_CMD_REREGISTER_NSMR = 14,
  76         OCRDMA_CMD_REGISTER_NSMR_CONT = 15,
  77         OCRDMA_CMD_QUERY_NSMR = 16,
  78         OCRDMA_CMD_ALLOC_MW = 17,
  79         OCRDMA_CMD_QUERY_MW = 18,
  80
  81         OCRDMA_CMD_CREATE_SRQ = 19,
  82         OCRDMA_CMD_QUERY_SRQ = 20,
  83         OCRDMA_CMD_MODIFY_SRQ = 21,
  84         OCRDMA_CMD_DELETE_SRQ = 22,
  85
  86         OCRDMA_CMD_ATTACH_MCAST = 23,
  87         OCRDMA_CMD_DETACH_MCAST = 24,
  88
  89         OCRDMA_CMD_CREATE_RBQ = 25,
  90         OCRDMA_CMD_DESTROY_RBQ = 26,
  91
  92         OCRDMA_CMD_GET_RDMA_STATS = 27,
  93         OCRDMA_CMD_ALLOC_PD_RANGE = 28,
  94         OCRDMA_CMD_DEALLOC_PD_RANGE = 29,
  95
  96         OCRDMA_CMD_MAX
  97 };
  98
  99 #define OCRDMA_SUBSYS_COMMON 1
 100 enum {
 101         OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1 = 5,
 102         OCRDMA_CMD_CREATE_CQ            = 12,
 103         OCRDMA_CMD_CREATE_EQ            = 13,
 104         OCRDMA_CMD_CREATE_MQ            = 21,
 105         OCRDMA_CMD_GET_CTRL_ATTRIBUTES  = 32,
 106         OCRDMA_CMD_GET_FW_VER           = 35,
 107         OCRDMA_CMD_MODIFY_EQ_DELAY      = 41,
 108         OCRDMA_CMD_DELETE_MQ            = 53,
 109         OCRDMA_CMD_DELETE_CQ            = 54,
 110         OCRDMA_CMD_DELETE_EQ            = 55,
 111         OCRDMA_CMD_GET_FW_CONFIG        = 58,
 112         OCRDMA_CMD_CREATE_MQ_EXT        = 90,
 113         OCRDMA_CMD_PHY_DETAILS          = 102
 114 };
 115
 116 enum {
 117         QTYPE_EQ        = 1,
 118         QTYPE_CQ        = 2,
 119         QTYPE_MCCQ      = 3
 120 };
 121
 122 #define OCRDMA_MAX_SGID         16
 123
 124 #define OCRDMA_MAX_QP    2048
 125 #define OCRDMA_MAX_CQ    2048
 126 #define OCRDMA_MAX_STAG 16384
 127
 128 enum {
 129         OCRDMA_DB_RQ_OFFSET             = 0xE0,
 130         OCRDMA_DB_GEN2_RQ_OFFSET        = 0x100,
 131         OCRDMA_DB_SQ_OFFSET             = 0x60,
 132         OCRDMA_DB_GEN2_SQ_OFFSET        = 0x1C0,
 133         OCRDMA_DB_SRQ_OFFSET            = OCRDMA_DB_RQ_OFFSET,
 134         OCRDMA_DB_GEN2_SRQ_OFFSET       = OCRDMA_DB_GEN2_RQ_OFFSET,
 135         OCRDMA_DB_CQ_OFFSET             = 0x120,
 136         OCRDMA_DB_EQ_OFFSET             = OCRDMA_DB_CQ_OFFSET,
 137         OCRDMA_DB_MQ_OFFSET             = 0x140,
 138
 139         OCRDMA_DB_SQ_SHIFT              = 16,
 140         OCRDMA_DB_RQ_SHIFT              = 24
 141 };
 142
 143 #define OCRDMA_ROUDP_FLAGS_SHIFT        0x03
 144
 145 #define OCRDMA_DB_CQ_RING_ID_MASK       0x3FF   /* bits 0 - 9 */
 146 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK  0x0C00   /* bits 10-11 of qid at 12-11 */
 147 /* qid #2 msbits at 12-11 */
 148 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT  0x1
 149 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT   16      /* bits 16 - 28 */
 150 /* Rearm bit */
 151 #define OCRDMA_DB_CQ_REARM_SHIFT        29      /* bit 29 */
 152 /* solicited bit */
 153 #define OCRDMA_DB_CQ_SOLICIT_SHIFT      31      /* bit 31 */
 154
 155 #define OCRDMA_EQ_ID_MASK               0x1FF   /* bits 0 - 8 */
 156 #define OCRDMA_EQ_ID_EXT_MASK           0x3e00  /* bits 9-13 */
 157 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT     2       /* qid bits 9-13 at 11-15 */
 158
 159 /* Clear the interrupt for this eq */
 160 #define OCRDMA_EQ_CLR_SHIFT             9       /* bit 9 */
 161 /* Must be 1 */
 162 #define OCRDMA_EQ_TYPE_SHIFT            10      /* bit 10 */
 163 /* Number of event entries processed */
 164 #define OCRDMA_NUM_EQE_SHIFT            16      /* bits 16 - 28 */
 165 /* Rearm bit */
 166 #define OCRDMA_REARM_SHIFT              29      /* bit 29 */
 167
 168 #define OCRDMA_MQ_ID_MASK               0x7FF   /* bits 0 - 10 */
 169 /* Number of entries posted */
 170 #define OCRDMA_MQ_NUM_MQE_SHIFT 16      /* bits 16 - 29 */
 171
 172 #define OCRDMA_MIN_HPAGE_SIZE   4096
 173
 174 #define OCRDMA_MIN_Q_PAGE_SIZE  4096
 175 #define OCRDMA_MAX_Q_PAGES      8
 176
 177 #define OCRDMA_SLI_ASIC_ID_OFFSET       0x9C
 178 #define OCRDMA_SLI_ASIC_REV_MASK        0x000000FF
 179 #define OCRDMA_SLI_ASIC_GEN_NUM_MASK    0x0000FF00
 180 #define OCRDMA_SLI_ASIC_GEN_NUM_SHIFT   0x08
 181 /*
 182 # 0: 4K Bytes
 183 # 1: 8K Bytes
 184 # 2: 16K Bytes
 185 # 3: 32K Bytes
 186 # 4: 64K Bytes
 187 # 5: 128K Bytes
 188 # 6: 256K Bytes
 189 # 7: 512K Bytes
 190 */
 191 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT      8
 192 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)
 193
 194 #define MAX_OCRDMA_QP_PAGES             8
 195 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)
 196
 197 #define OCRDMA_CREATE_CQ_MAX_PAGES      4
 198 #define OCRDMA_DPP_CQE_SIZE             4
 199
 200 #define OCRDMA_GEN2_MAX_CQE 1024
 201 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096
 202 #define OCRDMA_GEN2_WQE_SIZE 256
 203 #define OCRDMA_MAX_CQE  4095
 204 #define OCRDMA_CQ_PAGE_SIZE 16384
 205 #define OCRDMA_WQE_SIZE 128
 206 #define OCRDMA_WQE_STRIDE 8
 207 #define OCRDMA_WQE_ALIGN_BYTES 16
 208
 209 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES
 210
 211 enum {
 212         OCRDMA_MCH_OPCODE_SHIFT = 0,
 213         OCRDMA_MCH_OPCODE_MASK  = 0xFF,
 214         OCRDMA_MCH_SUBSYS_SHIFT = 8,
 215         OCRDMA_MCH_SUBSYS_MASK  = 0xFF00
 216 };
 217
 218 /* mailbox cmd header */
 219 struct ocrdma_mbx_hdr {
 220         u32 subsys_op;
 221         u32 timeout;            /* in seconds */
 222         u32 cmd_len;
 223         u32 rsvd_version;
 224 };
 225
 226 enum {
 227         OCRDMA_MBX_RSP_OPCODE_SHIFT     = 0,
 228         OCRDMA_MBX_RSP_OPCODE_MASK      = 0xFF,
 229         OCRDMA_MBX_RSP_SUBSYS_SHIFT     = 8,
 230         OCRDMA_MBX_RSP_SUBSYS_MASK      = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT,
 231
 232         OCRDMA_MBX_RSP_STATUS_SHIFT     = 0,
 233         OCRDMA_MBX_RSP_STATUS_MASK      = 0xFF,
 234         OCRDMA_MBX_RSP_ASTATUS_SHIFT    = 8,
 235         OCRDMA_MBX_RSP_ASTATUS_MASK     = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT
 236 };
 237
 238 /* mailbox cmd response */
 239 struct ocrdma_mbx_rsp {
 240         u32 subsys_op;
 241         u32 status;
 242         u32 rsp_len;
 243         u32 add_rsp_len;
 244 };
 245
 246 enum {
 247         OCRDMA_MQE_EMBEDDED     = 1,
 248         OCRDMA_MQE_NONEMBEDDED  = 0
 249 };
 250
 251 struct ocrdma_mqe_sge {
 252         u32 pa_lo;
 253         u32 pa_hi;
 254         u32 len;
 255 };
 256
 257 enum {
 258         OCRDMA_MQE_HDR_EMB_SHIFT        = 0,
 259         OCRDMA_MQE_HDR_EMB_MASK         = BIT(0),
 260         OCRDMA_MQE_HDR_SGE_CNT_SHIFT    = 3,
 261         OCRDMA_MQE_HDR_SGE_CNT_MASK     = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,
 262         OCRDMA_MQE_HDR_SPECIAL_SHIFT    = 24,
 263         OCRDMA_MQE_HDR_SPECIAL_MASK     = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT
 264 };
 265
 266 struct ocrdma_mqe_hdr {
 267         u32 spcl_sge_cnt_emb;
 268         u32 pyld_len;
 269         u32 tag_lo;
 270         u32 tag_hi;
 271         u32 rsvd3;
 272 };
 273
 274 struct ocrdma_mqe_emb_cmd {
 275         struct ocrdma_mbx_hdr mch;
 276         u8 pyld[220];
 277 };
 278
 279 struct ocrdma_mqe {
 280         struct ocrdma_mqe_hdr hdr;
 281         union {
 282                 struct ocrdma_mqe_emb_cmd emb_req;
 283                 struct {
 284                         struct ocrdma_mqe_sge sge[19];
 285                 } nonemb_req;
 286                 u8 cmd[236];
 287                 struct ocrdma_mbx_rsp rsp;
 288         } u;
 289 };
 290
 291 #define OCRDMA_EQ_LEN       4096
 292 #define OCRDMA_MQ_CQ_LEN    256
 293 #define OCRDMA_MQ_LEN       128
 294
 295 #define PAGE_SHIFT_4K           12
 296 #define PAGE_SIZE_4K            (1 << PAGE_SHIFT_4K)
 297
 298 /* Returns number of pages spanned by the data starting at the given addr */
 299 #define PAGES_4K_SPANNED(_address, size) \
 300         ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) +     \
 301                         (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
 302
 303 struct ocrdma_delete_q_req {
 304         struct ocrdma_mbx_hdr req;
 305         u32 id;
 306 };
 307
 308 struct ocrdma_pa {
 309         u32 lo;
 310         u32 hi;
 311 };
 312
 313 #define MAX_OCRDMA_EQ_PAGES     8
 314 struct ocrdma_create_eq_req {
 315         struct ocrdma_mbx_hdr req;
 316         u32 num_pages;
 317         u32 valid;
 318         u32 cnt;
 319         u32 delay;
 320         u32 rsvd;
 321         struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES];
 322 };
 323
 324 enum {
 325         OCRDMA_CREATE_EQ_VALID  = BIT(29),
 326         OCRDMA_CREATE_EQ_CNT_SHIFT      = 26,
 327         OCRDMA_CREATE_CQ_DELAY_SHIFT    = 13,
 328 };
 329
 330 struct ocrdma_create_eq_rsp {
 331         struct ocrdma_mbx_rsp rsp;
 332         u32 vector_eqid;
 333 };
 334
 335 #define OCRDMA_EQ_MINOR_OTHER   0x1
 336
 337 struct ocrmda_set_eqd {
 338         u32 eq_id;
 339         u32 phase;
 340         u32 delay_multiplier;
 341 };
 342
 343 struct ocrdma_modify_eqd_cmd {
 344         struct ocrdma_mbx_hdr req;
 345         u32 num_eq;
 346         struct ocrmda_set_eqd set_eqd[8];
 347 } __packed;
 348
 349 struct ocrdma_modify_eqd_req {
 350         struct ocrdma_mqe_hdr hdr;
 351         struct ocrdma_modify_eqd_cmd cmd;
 352 };
 353
 354
 355 struct ocrdma_modify_eq_delay_rsp {
 356         struct ocrdma_mbx_rsp hdr;
 357         u32 rsvd0;
 358 } __packed;
 359
 360 enum {
 361         OCRDMA_MCQE_STATUS_SHIFT        = 0,
 362         OCRDMA_MCQE_STATUS_MASK         = 0xFFFF,
 363         OCRDMA_MCQE_ESTATUS_SHIFT       = 16,
 364         OCRDMA_MCQE_ESTATUS_MASK        = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,
 365         OCRDMA_MCQE_CONS_SHIFT          = 27,
 366         OCRDMA_MCQE_CONS_MASK           = BIT(27),
 367         OCRDMA_MCQE_CMPL_SHIFT          = 28,
 368         OCRDMA_MCQE_CMPL_MASK           = BIT(28),
 369         OCRDMA_MCQE_AE_SHIFT            = 30,
 370         OCRDMA_MCQE_AE_MASK             = BIT(30),
 371         OCRDMA_MCQE_VALID_SHIFT         = 31,
 372         OCRDMA_MCQE_VALID_MASK          = BIT(31)
 373 };
 374
 375 struct ocrdma_mcqe {
 376         u32 status;
 377         u32 tag_lo;
 378         u32 tag_hi;
 379         u32 valid_ae_cmpl_cons;
 380 };
 381
 382 enum {
 383         OCRDMA_AE_MCQE_QPVALID          = BIT(31),
 384         OCRDMA_AE_MCQE_QPID_MASK        = 0xFFFF,
 385
 386         OCRDMA_AE_MCQE_CQVALID          = BIT(31),
 387         OCRDMA_AE_MCQE_CQID_MASK        = 0xFFFF,
 388         OCRDMA_AE_MCQE_VALID            = BIT(31),
 389         OCRDMA_AE_MCQE_AE               = BIT(30),
 390         OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,
 391         OCRDMA_AE_MCQE_EVENT_TYPE_MASK  =
 392                                         0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT,
 393         OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8,
 394         OCRDMA_AE_MCQE_EVENT_CODE_MASK  =
 395                                         0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
 396 };
 397 struct ocrdma_ae_mcqe {
 398         u32 qpvalid_qpid;
 399         u32 cqvalid_cqid;
 400         u32 evt_tag;
 401         u32 valid_ae_event;
 402 };
 403
 404 enum {
 405         OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT = 0,
 406         OCRDMA_AE_PVID_MCQE_ENABLED_MASK  = 0xFF,
 407         OCRDMA_AE_PVID_MCQE_TAG_SHIFT = 16,
 408         OCRDMA_AE_PVID_MCQE_TAG_MASK = 0xFFFF << OCRDMA_AE_PVID_MCQE_TAG_SHIFT
 409 };
 410
 411 struct ocrdma_ae_pvid_mcqe {
 412         u32 tag_enabled;
 413         u32 event_tag;
 414         u32 rsvd1;
 415         u32 rsvd2;
 416 };
 417
 418 enum {
 419         OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT         = 16,
 420         OCRDMA_AE_MPA_MCQE_REQ_ID_MASK          = 0xFFFF <<
 421                                         OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT,
 422
 423         OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT     = 8,
 424         OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK      = 0xFF <<
 425                                         OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT,
 426         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT     = 16,
 427         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK      = 0xFF <<
 428                                         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
 429         OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT       = 30,
 430         OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK        = BIT(30),
 431         OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT    = 31,
 432         OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK     = BIT(31)
 433 };
 434
 435 struct ocrdma_ae_mpa_mcqe {
 436         u32 req_id;
 437         u32 w1;
 438         u32 w2;
 439         u32 valid_ae_event;
 440 };
 441
 442 enum {
 443         OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT    = 0,
 444         OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK     = 0xFFFF,
 445         OCRDMA_AE_QP_MCQE_QP_ID_SHIFT           = 16,
 446         OCRDMA_AE_QP_MCQE_QP_ID_MASK            = 0xFFFF <<
 447                                                 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT,
 448
 449         OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT      = 8,
 450         OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK       = 0xFF <<
 451                                 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT,
 452         OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT      = 16,
 453         OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK       = 0xFF <<
 454                                 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
 455         OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT        = 30,
 456         OCRDMA_AE_QP_MCQE_EVENT_AE_MASK         = BIT(30),
 457         OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT     = 31,
 458         OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK      = BIT(31)
 459 };
 460
 461 struct ocrdma_ae_qp_mcqe {
 462         u32 qp_id_state;
 463         u32 w1;
 464         u32 w2;
 465         u32 valid_ae_event;
 466 };
 467
 468 enum ocrdma_async_event_code {
 469         OCRDMA_ASYNC_LINK_EVE_CODE      = 0x01,
 470         OCRDMA_ASYNC_GRP5_EVE_CODE      = 0x05,
 471         OCRDMA_ASYNC_RDMA_EVE_CODE      = 0x14
 472 };
 473
 474 enum ocrdma_async_grp5_events {
 475         OCRDMA_ASYNC_EVENT_QOS_VALUE    = 0x01,
 476         OCRDMA_ASYNC_EVENT_COS_VALUE    = 0x02,
 477         OCRDMA_ASYNC_EVENT_PVID_STATE   = 0x03
 478 };
 479
 480 enum OCRDMA_ASYNC_EVENT_TYPE {
 481         OCRDMA_CQ_ERROR                 = 0x00,
 482         OCRDMA_CQ_OVERRUN_ERROR         = 0x01,
 483         OCRDMA_CQ_QPCAT_ERROR           = 0x02,
 484         OCRDMA_QP_ACCESS_ERROR          = 0x03,
 485         OCRDMA_QP_COMM_EST_EVENT        = 0x04,
 486         OCRDMA_SQ_DRAINED_EVENT         = 0x05,
 487         OCRDMA_DEVICE_FATAL_EVENT       = 0x08,
 488         OCRDMA_SRQCAT_ERROR             = 0x0E,
 489         OCRDMA_SRQ_LIMIT_EVENT          = 0x0F,
 490         OCRDMA_QP_LAST_WQE_EVENT        = 0x10,
 491
 492         OCRDMA_MAX_ASYNC_ERRORS
 493 };
 494
 495 struct ocrdma_ae_lnkst_mcqe {
 496         u32 speed_state_ptn;
 497         u32 qos_reason_falut;
 498         u32 evt_tag;
 499         u32 valid_ae_event;
 500 };
 501
 502 enum {
 503         OCRDMA_AE_LSC_PORT_NUM_MASK     = 0x3F,
 504         OCRDMA_AE_LSC_PT_SHIFT          = 0x06,
 505         OCRDMA_AE_LSC_PT_MASK           = (0x03 <<
 506                         OCRDMA_AE_LSC_PT_SHIFT),
 507         OCRDMA_AE_LSC_LS_SHIFT          = 0x08,
 508         OCRDMA_AE_LSC_LS_MASK           = (0xFF <<
 509                         OCRDMA_AE_LSC_LS_SHIFT),
 510         OCRDMA_AE_LSC_LD_SHIFT          = 0x10,
 511         OCRDMA_AE_LSC_LD_MASK           = (0xFF <<
 512                         OCRDMA_AE_LSC_LD_SHIFT),
 513         OCRDMA_AE_LSC_PPS_SHIFT         = 0x18,
 514         OCRDMA_AE_LSC_PPS_MASK          = (0xFF <<
 515                         OCRDMA_AE_LSC_PPS_SHIFT),
 516         OCRDMA_AE_LSC_PPF_MASK          = 0xFF,
 517         OCRDMA_AE_LSC_ER_SHIFT          = 0x08,
 518         OCRDMA_AE_LSC_ER_MASK           = (0xFF <<
 519                         OCRDMA_AE_LSC_ER_SHIFT),
 520         OCRDMA_AE_LSC_QOS_SHIFT         = 0x10,
 521         OCRDMA_AE_LSC_QOS_MASK          = (0xFFFF <<
 522                         OCRDMA_AE_LSC_QOS_SHIFT)
 523 };
 524
 525 enum {
 526         OCRDMA_AE_LSC_PLINK_DOWN        = 0x00,
 527         OCRDMA_AE_LSC_PLINK_UP          = 0x01,
 528         OCRDMA_AE_LSC_LLINK_DOWN        = 0x02,
 529         OCRDMA_AE_LSC_LLINK_MASK        = 0x02,
 530         OCRDMA_AE_LSC_LLINK_UP          = 0x03
 531 };
 532
 533 /* mailbox command request and responses */
 534 enum {
 535         OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT          = 2,
 536         OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK           = BIT(2),
 537         OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT        = 3,
 538         OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK         = BIT(3),
 539         OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT               = 8,
 540         OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK                = 0xFFFFFF <<
 541                                 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,
 542
 543         OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT               = 16,
 544         OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK                = 0xFFFF <<
 545                                         OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT,
 546         OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT         = 8,
 547         OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK          = 0xFF <<
 548                                 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT,
 549
 550         OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT         = 0,
 551         OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK          = 0xFFFF,
 552         OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT        = 16,
 553         OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK         = 0xFFFF <<
 554                                 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT,
 555
 556         OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT       = 0,
 557         OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK        = 0xFFFF,
 558         OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT       = 16,
 559         OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK        = 0xFFFF <<
 560                                 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT,
 561
 562         OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET        = 24,
 563         OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK          = 0xFF <<
 564                                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET,
 565         OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET        = 16,
 566         OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK          = 0xFF <<
 567                                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET,
 568         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET        = 0,
 569         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK          = 0xFFFF <<
 570                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET,
 571
 572         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET             = 16,
 573         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK               = 0xFFFF <<
 574                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET,
 575         OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET        = 0,
 576         OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK          = 0xFFFF <<
 577                                 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET,
 578
 579         OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET         = 16,
 580         OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK           = 0xFFFF <<
 581                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET,
 582         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET     = 0,
 583         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK       = 0xFFFF <<
 584                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET,
 585
 586         OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET         = 0,
 587         OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK           = 0xFFFF <<
 588                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET,
 589
 590         OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET     = 16,
 591         OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK       = 0xFFFF <<
 592                                 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,
 593         OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET     = 0,
 594         OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK       = 0xFFFF <<
 595                                 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET,
 596
 597         OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET              = 16,
 598         OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK                = 0xFFFF <<
 599                                 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET,
 600         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET     = 0,
 601         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK       = 0xFFFF <<
 602                                 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET,
 603
 604         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET         = 16,
 605         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK           = 0xFFFF <<
 606                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET,
 607         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET         = 0,
 608         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK           = 0xFFFF <<
 609                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET,
 610 };
 611
 612 struct ocrdma_mbx_query_config {
 613         struct ocrdma_mqe_hdr hdr;
 614         struct ocrdma_mbx_rsp rsp;
 615         u32 qp_srq_cq_ird_ord;
 616         u32 max_pd_ca_ack_delay;
 617         u32 max_write_send_sge;
 618         u32 max_ird_ord_per_qp;
 619         u32 max_shared_ird_ord;
 620         u32 max_mr;
 621         u32 max_mr_size_hi;
 622         u32 max_mr_size_lo;
 623         u32 max_num_mr_pbl;
 624         u32 max_mw;
 625         u32 max_fmr;
 626         u32 max_pages_per_frmr;
 627         u32 max_mcast_group;
 628         u32 max_mcast_qp_attach;
 629         u32 max_total_mcast_qp_attach;
 630         u32 wqe_rqe_stride_max_dpp_cqs;
 631         u32 max_srq_rpir_qps;
 632         u32 max_dpp_pds_credits;
 633         u32 max_dpp_credits_pds_per_pd;
 634         u32 max_wqes_rqes_per_q;
 635         u32 max_cq_cqes_per_cq;
 636         u32 max_srq_rqe_sge;
 637 };
 638
 639 struct ocrdma_fw_ver_rsp {
 640         struct ocrdma_mqe_hdr hdr;
 641         struct ocrdma_mbx_rsp rsp;
 642
 643         u8 running_ver[32];
 644 };
 645
 646 struct ocrdma_fw_conf_rsp {
 647         struct ocrdma_mqe_hdr hdr;
 648         struct ocrdma_mbx_rsp rsp;
 649
 650         u32 config_num;
 651         u32 asic_revision;
 652         u32 phy_port;
 653         u32 fn_mode;
 654         struct {
 655                 u32 mode;
 656                 u32 nic_wqid_base;
 657                 u32 nic_wq_tot;
 658                 u32 prot_wqid_base;
 659                 u32 prot_wq_tot;
 660                 u32 prot_rqid_base;
 661                 u32 prot_rqid_tot;
 662                 u32 rsvd[6];
 663         } ulp[2];
 664         u32 fn_capabilities;
 665         u32 rsvd1;
 666         u32 rsvd2;
 667         u32 base_eqid;
 668         u32 max_eq;
 669
 670 };
 671
 672 enum {
 673         OCRDMA_FN_MODE_RDMA     = 0x4
 674 };
 675
 676 enum {
 677         OCRDMA_IF_TYPE_MASK             = 0xFFFF0000,
 678         OCRDMA_IF_TYPE_SHIFT            = 0x10,
 679         OCRDMA_PHY_TYPE_MASK            = 0x0000FFFF,
 680         OCRDMA_FUTURE_DETAILS_MASK      = 0xFFFF0000,
 681         OCRDMA_FUTURE_DETAILS_SHIFT     = 0x10,
 682         OCRDMA_EX_PHY_DETAILS_MASK      = 0x0000FFFF,
 683         OCRDMA_FSPEED_SUPP_MASK         = 0xFFFF0000,
 684         OCRDMA_FSPEED_SUPP_SHIFT        = 0x10,
 685         OCRDMA_ASPEED_SUPP_MASK         = 0x0000FFFF
 686 };
 687
 688 struct ocrdma_get_phy_info_rsp {
 689         struct ocrdma_mqe_hdr hdr;
 690         struct ocrdma_mbx_rsp rsp;
 691
 692         u32 ityp_ptyp;
 693         u32 misc_params;
 694         u32 ftrdtl_exphydtl;
 695         u32 fspeed_aspeed;
 696         u32 future_use[2];
 697 };
 698
 699 enum {
 700         OCRDMA_PHY_SPEED_ZERO = 0x0,
 701         OCRDMA_PHY_SPEED_10MBPS = 0x1,
 702         OCRDMA_PHY_SPEED_100MBPS = 0x2,
 703         OCRDMA_PHY_SPEED_1GBPS = 0x4,
 704         OCRDMA_PHY_SPEED_10GBPS = 0x8,
 705         OCRDMA_PHY_SPEED_40GBPS = 0x20
 706 };
 707
 708 enum {
 709         OCRDMA_PORT_NUM_MASK    = 0x3F,
 710         OCRDMA_PT_MASK          = 0xC0,
 711         OCRDMA_PT_SHIFT         = 0x6,
 712         OCRDMA_LINK_DUP_MASK    = 0x0000FF00,
 713         OCRDMA_LINK_DUP_SHIFT   = 0x8,
 714         OCRDMA_PHY_PS_MASK      = 0x00FF0000,
 715         OCRDMA_PHY_PS_SHIFT     = 0x10,
 716         OCRDMA_PHY_PFLT_MASK    = 0xFF000000,
 717         OCRDMA_PHY_PFLT_SHIFT   = 0x18,
 718         OCRDMA_QOS_LNKSP_MASK   = 0xFFFF0000,
 719         OCRDMA_QOS_LNKSP_SHIFT  = 0x10,
 720         OCRDMA_LINK_ST_MASK     = 0x01,
 721         OCRDMA_PLFC_MASK        = 0x00000400,
 722         OCRDMA_PLFC_SHIFT       = 0x8,
 723         OCRDMA_PLRFC_MASK       = 0x00000200,
 724         OCRDMA_PLRFC_SHIFT      = 0x8,
 725         OCRDMA_PLTFC_MASK       = 0x00000100,
 726         OCRDMA_PLTFC_SHIFT      = 0x8
 727 };
 728
 729 struct ocrdma_get_link_speed_rsp {
 730         struct ocrdma_mqe_hdr hdr;
 731         struct ocrdma_mbx_rsp rsp;
 732
 733         u32 pflt_pps_ld_pnum;
 734         u32 qos_lsp;
 735         u32 res_lnk_st;
 736 };
 737
 738 enum {
 739         OCRDMA_PHYS_LINK_SPEED_ZERO = 0x0,
 740         OCRDMA_PHYS_LINK_SPEED_10MBPS = 0x1,
 741         OCRDMA_PHYS_LINK_SPEED_100MBPS = 0x2,
 742         OCRDMA_PHYS_LINK_SPEED_1GBPS = 0x3,
 743         OCRDMA_PHYS_LINK_SPEED_10GBPS = 0x4,
 744         OCRDMA_PHYS_LINK_SPEED_20GBPS = 0x5,
 745         OCRDMA_PHYS_LINK_SPEED_25GBPS = 0x6,
 746         OCRDMA_PHYS_LINK_SPEED_40GBPS = 0x7,
 747         OCRDMA_PHYS_LINK_SPEED_100GBPS = 0x8
 748 };
 749
 750 enum {
 751         OCRDMA_CREATE_CQ_VER2                   = 2,
 752         OCRDMA_CREATE_CQ_VER3                   = 3,
 753
 754         OCRDMA_CREATE_CQ_PAGE_CNT_MASK          = 0xFFFF,
 755         OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT        = 16,
 756         OCRDMA_CREATE_CQ_PAGE_SIZE_MASK         = 0xFF,
 757
 758         OCRDMA_CREATE_CQ_COALESCWM_SHIFT        = 12,
 759         OCRDMA_CREATE_CQ_COALESCWM_MASK         = BIT(13) | BIT(12),
 760         OCRDMA_CREATE_CQ_FLAGS_NODELAY          = BIT(14),
 761         OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID       = BIT(15),
 762
 763         OCRDMA_CREATE_CQ_EQ_ID_MASK             = 0xFFFF,
 764         OCRDMA_CREATE_CQ_CQE_COUNT_MASK         = 0xFFFF
 765 };
 766
 767 enum {
 768         OCRDMA_CREATE_CQ_VER0                   = 0,
 769         OCRDMA_CREATE_CQ_DPP                    = 1,
 770         OCRDMA_CREATE_CQ_TYPE_SHIFT             = 24,
 771         OCRDMA_CREATE_CQ_EQID_SHIFT             = 22,
 772
 773         OCRDMA_CREATE_CQ_CNT_SHIFT              = 27,
 774         OCRDMA_CREATE_CQ_FLAGS_VALID            = BIT(29),
 775         OCRDMA_CREATE_CQ_FLAGS_EVENTABLE        = BIT(31),
 776         OCRDMA_CREATE_CQ_DEF_FLAGS              = OCRDMA_CREATE_CQ_FLAGS_VALID |
 777                                         OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
 778                                         OCRDMA_CREATE_CQ_FLAGS_NODELAY
 779 };
 780
 781 struct ocrdma_create_cq_cmd {
 782         struct ocrdma_mbx_hdr req;
 783         u32 pgsz_pgcnt;
 784         u32 ev_cnt_flags;
 785         u32 eqn;
 786         u32 pdid_cqecnt;
 787         u32 rsvd6;
 788         struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES];
 789 };
 790
 791 struct ocrdma_create_cq {
 792         struct ocrdma_mqe_hdr hdr;
 793         struct ocrdma_create_cq_cmd cmd;
 794 };
 795
 796 enum {
 797         OCRDMA_CREATE_CQ_CMD_PDID_SHIFT = 0x10
 798 };
 799
 800 enum {
 801         OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF
 802 };
 803
 804 struct ocrdma_create_cq_cmd_rsp {
 805         struct ocrdma_mbx_rsp rsp;
 806         u32 cq_id;
 807 };
 808
 809 struct ocrdma_create_cq_rsp {
 810         struct ocrdma_mqe_hdr hdr;
 811         struct ocrdma_create_cq_cmd_rsp rsp;
 812 };
 813
 814 enum {
 815         OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT         = 22,
 816         OCRDMA_CREATE_MQ_CQ_ID_SHIFT            = 16,
 817         OCRDMA_CREATE_MQ_RING_SIZE_SHIFT        = 16,
 818         OCRDMA_CREATE_MQ_VALID                  = BIT(31),
 819         OCRDMA_CREATE_MQ_ASYNC_CQ_VALID         = BIT(0)
 820 };
 821
 822 struct ocrdma_create_mq_req {
 823         struct ocrdma_mbx_hdr req;
 824         u32 cqid_pages;
 825         u32 async_event_bitmap;
 826         u32 async_cqid_ringsize;
 827         u32 valid;
 828         u32 async_cqid_valid;
 829         u32 rsvd;
 830         struct ocrdma_pa pa[8];
 831 };
 832
 833 struct ocrdma_create_mq_rsp {
 834         struct ocrdma_mbx_rsp rsp;
 835         u32 id;
 836 };
 837
 838 enum {
 839         OCRDMA_DESTROY_CQ_QID_SHIFT                     = 0,
 840         OCRDMA_DESTROY_CQ_QID_MASK                      = 0xFFFF,
 841         OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT        = 16,
 842         OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK         = 0xFFFF <<
 843                                 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
 844 };
 845
 846 struct ocrdma_destroy_cq {
 847         struct ocrdma_mqe_hdr hdr;
 848         struct ocrdma_mbx_hdr req;
 849
 850         u32 bypass_flush_qid;
 851 };
 852
 853 struct ocrdma_destroy_cq_rsp {
 854         struct ocrdma_mqe_hdr hdr;
 855         struct ocrdma_mbx_rsp rsp;
 856 };
 857
 858 enum {
 859         OCRDMA_QPT_GSI  = 1,
 860         OCRDMA_QPT_RC   = 2,
 861         OCRDMA_QPT_UD   = 4,
 862 };
 863
 864 enum {
 865         OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT        = 0,
 866         OCRDMA_CREATE_QP_REQ_PD_ID_MASK         = 0xFFFF,
 867         OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,
 868         OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19,
 869         OCRDMA_CREATE_QP_REQ_QPT_SHIFT          = 29,
 870         OCRDMA_CREATE_QP_REQ_QPT_MASK           = BIT(31) | BIT(30) | BIT(29),
 871
 872         OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT      = 0,
 873         OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK       = 0xFFFF,
 874         OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT      = 16,
 875         OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK       = 0xFFFF <<
 876                                         OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT,
 877
 878         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT        = 0,
 879         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK         = 0xFFFF,
 880         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT         = 16,
 881         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK          = 0xFFFF <<
 882                                         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,
 883
 884         OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT               = 0,
 885         OCRDMA_CREATE_QP_REQ_FMR_EN_MASK                = BIT(0),
 886         OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT          = 1,
 887         OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK           = BIT(1),
 888         OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT          = 2,
 889         OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK           = BIT(2),
 890         OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT             = 3,
 891         OCRDMA_CREATE_QP_REQ_INB_WREN_MASK              = BIT(3),
 892         OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT             = 4,
 893         OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK              = BIT(4),
 894         OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT              = 5,
 895         OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK               = BIT(5),
 896         OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT          = 6,
 897         OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK           = BIT(6),
 898         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT           = 7,
 899         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK            = BIT(7),
 900         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT        = 8,
 901         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK         = BIT(8),
 902         OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT         = 16,
 903         OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK          = 0xFFFF <<
 904                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,
 905
 906         OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT              = 0,
 907         OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK               = 0xFFFF,
 908         OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT              = 16,
 909         OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK               = 0xFFFF <<
 910                                 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT,
 911
 912         OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT         = 0,
 913         OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK          = 0xFFFF,
 914         OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT         = 16,
 915         OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK          = 0xFFFF <<
 916                                 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT,
 917
 918         OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT             = 0,
 919         OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK              = 0xFFFF,
 920         OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT             = 16,
 921         OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK              = 0xFFFF <<
 922                                 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT,
 923
 924         OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT              = 0,
 925         OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK               = 0xFFFF,
 926         OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT              = 16,
 927         OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK               = 0xFFFF <<
 928                                 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT,
 929
 930         OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT            = 0,
 931         OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK             = 0xFFFF,
 932         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT           = 16,
 933         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK            = 0xFFFF <<
 934                                 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
 935 };
 936
 937 enum {
 938         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT   = 16,
 939         OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT     = 1
 940 };
 941
 942 #define MAX_OCRDMA_IRD_PAGES 4
 943
 944 enum ocrdma_qp_flags {
 945         OCRDMA_QP_MW_BIND       = 1,
 946         OCRDMA_QP_LKEY0         = (1 << 1),
 947         OCRDMA_QP_FAST_REG      = (1 << 2),
 948         OCRDMA_QP_INB_RD        = (1 << 6),
 949         OCRDMA_QP_INB_WR        = (1 << 7),
 950 };
 951
 952 enum ocrdma_qp_state {
 953         OCRDMA_QPS_RST          = 0,
 954         OCRDMA_QPS_INIT         = 1,
 955         OCRDMA_QPS_RTR          = 2,
 956         OCRDMA_QPS_RTS          = 3,
 957         OCRDMA_QPS_SQE          = 4,
 958         OCRDMA_QPS_SQ_DRAINING  = 5,
 959         OCRDMA_QPS_ERR          = 6,
 960         OCRDMA_QPS_SQD          = 7
 961 };
 962
 963 struct ocrdma_create_qp_req {
 964         struct ocrdma_mqe_hdr hdr;
 965         struct ocrdma_mbx_hdr req;
 966
 967         u32 type_pgsz_pdn;
 968         u32 max_wqe_rqe;
 969         u32 max_sge_send_write;
 970         u32 max_sge_recv_flags;
 971         u32 max_ord_ird;
 972         u32 num_wq_rq_pages;
 973         u32 wqe_rqe_size;
 974         u32 wq_rq_cqid;
 975         struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES];
 976         struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES];
 977         u32 dpp_credits_cqid;
 978         u32 rpir_lkey;
 979         struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES];
 980 };
 981
 982 enum {
 983         OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT                = 0,
 984         OCRDMA_CREATE_QP_RSP_QP_ID_MASK                 = 0xFFFF,
 985
 986         OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT              = 0,
 987         OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK               = 0xFFFF,
 988         OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT              = 16,
 989         OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK               = 0xFFFF <<
 990                                 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT,
 991
 992         OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT        = 0,
 993         OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK         = 0xFFFF,
 994         OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT         = 16,
 995         OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK          = 0xFFFF <<
 996                                 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT,
 997
 998         OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT         = 16,
 999         OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK          = 0xFFFF <<
1000                                 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT,
1001
1002         OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT              = 0,
1003         OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK               = 0xFFFF,
1004         OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT              = 16,
1005         OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK               = 0xFFFF <<
1006                                 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT,
1007
1008         OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT                = 0,
1009         OCRDMA_CREATE_QP_RSP_RQ_ID_MASK                 = 0xFFFF,
1010         OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT                = 16,
1011         OCRDMA_CREATE_QP_RSP_SQ_ID_MASK                 = 0xFFFF <<
1012                                 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,
1013
1014         OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK           = BIT(0),
1015         OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT      = 1,
1016         OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK       = 0x7FFF <<
1017                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
1018         OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT          = 16,
1019         OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK           = 0xFFFF <<
1020                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT,
1021 };
1022
1023 struct ocrdma_create_qp_rsp {
1024         struct ocrdma_mqe_hdr hdr;
1025         struct ocrdma_mbx_rsp rsp;
1026
1027         u32 qp_id;
1028         u32 max_wqe_rqe;
1029         u32 max_sge_send_write;
1030         u32 max_sge_recv;
1031         u32 max_ord_ird;
1032         u32 sq_rq_id;
1033         u32 dpp_response;
1034 };
1035
1036 struct ocrdma_destroy_qp {
1037         struct ocrdma_mqe_hdr hdr;
1038         struct ocrdma_mbx_hdr req;
1039         u32 qp_id;
1040 };
1041
1042 struct ocrdma_destroy_qp_rsp {
1043         struct ocrdma_mqe_hdr hdr;
1044         struct ocrdma_mbx_rsp rsp;
1045 };
1046
1047 enum {
1048         OCRDMA_MODIFY_QP_ID_SHIFT       = 0,
1049         OCRDMA_MODIFY_QP_ID_MASK        = 0xFFFF,
1050
1051         OCRDMA_QP_PARA_QPS_VALID        = BIT(0),
1052         OCRDMA_QP_PARA_SQD_ASYNC_VALID  = BIT(1),
1053         OCRDMA_QP_PARA_PKEY_VALID       = BIT(2),
1054         OCRDMA_QP_PARA_QKEY_VALID       = BIT(3),
1055         OCRDMA_QP_PARA_PMTU_VALID       = BIT(4),
1056         OCRDMA_QP_PARA_ACK_TO_VALID     = BIT(5),
1057         OCRDMA_QP_PARA_RETRY_CNT_VALID  = BIT(6),
1058         OCRDMA_QP_PARA_RRC_VALID        = BIT(7),
1059         OCRDMA_QP_PARA_RQPSN_VALID      = BIT(8),
1060         OCRDMA_QP_PARA_MAX_IRD_VALID    = BIT(9),
1061         OCRDMA_QP_PARA_MAX_ORD_VALID    = BIT(10),
1062         OCRDMA_QP_PARA_RNT_VALID        = BIT(11),
1063         OCRDMA_QP_PARA_SQPSN_VALID      = BIT(12),
1064         OCRDMA_QP_PARA_DST_QPN_VALID    = BIT(13),
1065         OCRDMA_QP_PARA_MAX_WQE_VALID    = BIT(14),
1066         OCRDMA_QP_PARA_MAX_RQE_VALID    = BIT(15),
1067         OCRDMA_QP_PARA_SGE_SEND_VALID   = BIT(16),
1068         OCRDMA_QP_PARA_SGE_RECV_VALID   = BIT(17),
1069         OCRDMA_QP_PARA_SGE_WR_VALID     = BIT(18),
1070         OCRDMA_QP_PARA_INB_RDEN_VALID   = BIT(19),
1071         OCRDMA_QP_PARA_INB_WREN_VALID   = BIT(20),
1072         OCRDMA_QP_PARA_FLOW_LBL_VALID   = BIT(21),
1073         OCRDMA_QP_PARA_BIND_EN_VALID    = BIT(22),
1074         OCRDMA_QP_PARA_ZLKEY_EN_VALID   = BIT(23),
1075         OCRDMA_QP_PARA_FMR_EN_VALID     = BIT(24),
1076         OCRDMA_QP_PARA_INBAT_EN_VALID   = BIT(25),
1077         OCRDMA_QP_PARA_VLAN_EN_VALID    = BIT(26),
1078
1079         OCRDMA_MODIFY_QP_FLAGS_RD       = BIT(0),
1080         OCRDMA_MODIFY_QP_FLAGS_WR       = BIT(1),
1081         OCRDMA_MODIFY_QP_FLAGS_SEND     = BIT(2),
1082         OCRDMA_MODIFY_QP_FLAGS_ATOMIC   = BIT(3)
1083 };
1084
1085 enum {
1086         OCRDMA_QP_PARAMS_SRQ_ID_SHIFT           = 0,
1087         OCRDMA_QP_PARAMS_SRQ_ID_MASK            = 0xFFFF,
1088
1089         OCRDMA_QP_PARAMS_MAX_RQE_SHIFT          = 0,
1090         OCRDMA_QP_PARAMS_MAX_RQE_MASK           = 0xFFFF,
1091         OCRDMA_QP_PARAMS_MAX_WQE_SHIFT          = 16,
1092         OCRDMA_QP_PARAMS_MAX_WQE_MASK           = 0xFFFF <<
1093             OCRDMA_QP_PARAMS_MAX_WQE_SHIFT,
1094
1095         OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT    = 0,
1096         OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK     = 0xFFFF,
1097         OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT     = 16,
1098         OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK      = 0xFFFF <<
1099                                         OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,
1100
1101         OCRDMA_QP_PARAMS_FLAGS_FMR_EN           = BIT(0),
1102         OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN        = BIT(1),
1103         OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN       = BIT(2),
1104         OCRDMA_QP_PARAMS_FLAGS_INBWR_EN         = BIT(3),
1105         OCRDMA_QP_PARAMS_FLAGS_INBRD_EN         = BIT(4),
1106         OCRDMA_QP_PARAMS_STATE_SHIFT            = 5,
1107         OCRDMA_QP_PARAMS_STATE_MASK             = BIT(5) | BIT(6) | BIT(7),
1108         OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC        = BIT(8),
1109         OCRDMA_QP_PARAMS_FLAGS_INB_ATEN         = BIT(9),
1110         OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT     = 16,
1111         OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK      = 0xFFFF <<
1112                                         OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,
1113
1114         OCRDMA_QP_PARAMS_MAX_IRD_SHIFT          = 0,
1115         OCRDMA_QP_PARAMS_MAX_IRD_MASK           = 0xFFFF,
1116         OCRDMA_QP_PARAMS_MAX_ORD_SHIFT          = 16,
1117         OCRDMA_QP_PARAMS_MAX_ORD_MASK           = 0xFFFF <<
1118                                         OCRDMA_QP_PARAMS_MAX_ORD_SHIFT,
1119
1120         OCRDMA_QP_PARAMS_RQ_CQID_SHIFT          = 0,
1121         OCRDMA_QP_PARAMS_RQ_CQID_MASK           = 0xFFFF,
1122         OCRDMA_QP_PARAMS_WQ_CQID_SHIFT          = 16,
1123         OCRDMA_QP_PARAMS_WQ_CQID_MASK           = 0xFFFF <<
1124                                         OCRDMA_QP_PARAMS_WQ_CQID_SHIFT,
1125
1126         OCRDMA_QP_PARAMS_RQ_PSN_SHIFT           = 0,
1127         OCRDMA_QP_PARAMS_RQ_PSN_MASK            = 0xFFFFFF,
1128         OCRDMA_QP_PARAMS_HOP_LMT_SHIFT          = 24,
1129         OCRDMA_QP_PARAMS_HOP_LMT_MASK           = 0xFF <<
1130                                         OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
1131
1132         OCRDMA_QP_PARAMS_SQ_PSN_SHIFT           = 0,
1133         OCRDMA_QP_PARAMS_SQ_PSN_MASK            = 0xFFFFFF,
1134         OCRDMA_QP_PARAMS_TCLASS_SHIFT           = 24,
1135         OCRDMA_QP_PARAMS_TCLASS_MASK            = 0xFF <<
1136                                         OCRDMA_QP_PARAMS_TCLASS_SHIFT,
1137
1138         OCRDMA_QP_PARAMS_DEST_QPN_SHIFT         = 0,
1139         OCRDMA_QP_PARAMS_DEST_QPN_MASK          = 0xFFFFFF,
1140         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT    = 24,
1141         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK     = 0x7 <<
1142                                         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT,
1143         OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT      = 27,
1144         OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK       = 0x1F <<
1145                                         OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT,
1146
1147         OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT       = 0,
1148         OCRDMA_QP_PARAMS_PKEY_INDEX_MASK        = 0xFFFF,
1149         OCRDMA_QP_PARAMS_PATH_MTU_SHIFT         = 18,
1150         OCRDMA_QP_PARAMS_PATH_MTU_MASK          = 0x3FFF <<
1151                                         OCRDMA_QP_PARAMS_PATH_MTU_SHIFT,
1152
1153         OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT       = 0,
1154         OCRDMA_QP_PARAMS_FLOW_LABEL_MASK        = 0xFFFFF,
1155         OCRDMA_QP_PARAMS_SL_SHIFT               = 20,
1156         OCRDMA_QP_PARAMS_SL_MASK                = 0xF <<
1157                                         OCRDMA_QP_PARAMS_SL_SHIFT,
1158         OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT        = 24,
1159         OCRDMA_QP_PARAMS_RETRY_CNT_MASK         = 0x7 <<
1160                                         OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT,
1161         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT    = 27,
1162         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK     = 0x1F <<
1163                                         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT,
1164
1165         OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT    = 0,
1166         OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK     = 0xFFFF,
1167         OCRDMA_QP_PARAMS_VLAN_SHIFT             = 16,
1168         OCRDMA_QP_PARAMS_VLAN_MASK              = 0xFFFF <<
1169                                         OCRDMA_QP_PARAMS_VLAN_SHIFT
1170 };
1171
1172 struct ocrdma_qp_params {
1173         u32 id;
1174         u32 max_wqe_rqe;
1175         u32 max_sge_send_write;
1176         u32 max_sge_recv_flags;
1177         u32 max_ord_ird;
1178         u32 wq_rq_cqid;
1179         u32 hop_lmt_rq_psn;
1180         u32 tclass_sq_psn;
1181         u32 ack_to_rnr_rtc_dest_qpn;
1182         u32 path_mtu_pkey_indx;
1183         u32 rnt_rc_sl_fl;
1184         u8 sgid[16];
1185         u8 dgid[16];
1186         u32 dmac_b0_to_b3;
1187         u32 vlan_dmac_b4_to_b5;
1188         u32 qkey;
1189 };
1190
1191
1192 struct ocrdma_modify_qp {
1193         struct ocrdma_mqe_hdr hdr;
1194         struct ocrdma_mbx_hdr req;
1195
1196         struct ocrdma_qp_params params;
1197         u32 flags;
1198         u32 rdma_flags;
1199         u32 num_outstanding_atomic_rd;
1200 };
1201
1202 enum {
1203         OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT      = 0,
1204         OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK       = 0xFFFF,
1205         OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT      = 16,
1206         OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK       = 0xFFFF <<
1207                                         OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT,
1208
1209         OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT      = 0,
1210         OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK       = 0xFFFF,
1211         OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT      = 16,
1212         OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK       = 0xFFFF <<
1213                                         OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
1214 };
1215
1216 struct ocrdma_modify_qp_rsp {
1217         struct ocrdma_mqe_hdr hdr;
1218         struct ocrdma_mbx_rsp rsp;
1219
1220         u32 max_wqe_rqe;
1221         u32 max_ord_ird;
1222 };
1223
1224 struct ocrdma_query_qp {
1225         struct ocrdma_mqe_hdr hdr;
1226         struct ocrdma_mbx_hdr req;
1227
1228 #define OCRDMA_QUERY_UP_QP_ID_SHIFT     0
1229 #define OCRDMA_QUERY_UP_QP_ID_MASK      0xFFFFFF
1230         u32 qp_id;
1231 };
1232
1233 struct ocrdma_query_qp_rsp {
1234         struct ocrdma_mqe_hdr hdr;
1235         struct ocrdma_mbx_rsp rsp;
1236         struct ocrdma_qp_params params;
1237         u32 dpp_credits_cqid;
1238         u32 rbq_id;
1239 };
1240
1241 enum {
1242         OCRDMA_CREATE_SRQ_PD_ID_SHIFT           = 0,
1243         OCRDMA_CREATE_SRQ_PD_ID_MASK            = 0xFFFF,
1244         OCRDMA_CREATE_SRQ_PG_SZ_SHIFT           = 16,
1245         OCRDMA_CREATE_SRQ_PG_SZ_MASK            = 0x3 <<
1246                                         OCRDMA_CREATE_SRQ_PG_SZ_SHIFT,
1247
1248         OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT         = 0,
1249         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT    = 16,
1250         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK     = 0xFFFF <<
1251                                         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT,
1252
1253         OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT        = 0,
1254         OCRDMA_CREATE_SRQ_RQE_SIZE_MASK         = 0xFFFF,
1255         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT    = 16,
1256         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK     = 0xFFFF <<
1257                                         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
1258 };
1259
1260 struct ocrdma_create_srq {
1261         struct ocrdma_mqe_hdr hdr;
1262         struct ocrdma_mbx_hdr req;
1263
1264         u32 pgsz_pdid;
1265         u32 max_sge_rqe;
1266         u32 pages_rqe_sz;
1267         struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES];
1268 };
1269
1270 enum {
1271         OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT                      = 0,
1272         OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK                       = 0xFFFFFF,
1273
1274         OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT           = 0,
1275         OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK            = 0xFFFF,
1276         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT      = 16,
1277         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK       = 0xFFFF <<
1278                         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
1279 };
1280
1281 struct ocrdma_create_srq_rsp {
1282         struct ocrdma_mqe_hdr hdr;
1283         struct ocrdma_mbx_rsp rsp;
1284
1285         u32 id;
1286         u32 max_sge_rqe_allocated;
1287 };
1288
1289 enum {
1290         OCRDMA_MODIFY_SRQ_ID_SHIFT      = 0,
1291         OCRDMA_MODIFY_SRQ_ID_MASK       = 0xFFFFFF,
1292
1293         OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0,
1294         OCRDMA_MODIFY_SRQ_MAX_RQE_MASK  = 0xFFFF,
1295         OCRDMA_MODIFY_SRQ_LIMIT_SHIFT   = 16,
1296         OCRDMA_MODIFY_SRQ__LIMIT_MASK   = 0xFFFF <<
1297                                         OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
1298 };
1299
1300 struct ocrdma_modify_srq {
1301         struct ocrdma_mqe_hdr hdr;
1302         struct ocrdma_mbx_rsp rep;
1303
1304         u32 id;
1305         u32 limit_max_rqe;
1306 };
1307
1308 enum {
1309         OCRDMA_QUERY_SRQ_ID_SHIFT       = 0,
1310         OCRDMA_QUERY_SRQ_ID_MASK        = 0xFFFFFF
1311 };
1312
1313 struct ocrdma_query_srq {
1314         struct ocrdma_mqe_hdr hdr;
1315         struct ocrdma_mbx_rsp req;
1316
1317         u32 id;
1318 };
1319
1320 enum {
1321         OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT        = 0,
1322         OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK         = 0xFFFF,
1323         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT      = 16,
1324         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK       = 0xFFFF <<
1325                                         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT,
1326
1327         OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0,
1328         OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK  = 0xFFFF,
1329         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT    = 16,
1330         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK     = 0xFFFF <<
1331                                         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
1332 };
1333
1334 struct ocrdma_query_srq_rsp {
1335         struct ocrdma_mqe_hdr hdr;
1336         struct ocrdma_mbx_rsp req;
1337
1338         u32 max_rqe_pdid;
1339         u32 srq_lmt_max_sge;
1340 };
1341
1342 enum {
1343         OCRDMA_DESTROY_SRQ_ID_SHIFT     = 0,
1344         OCRDMA_DESTROY_SRQ_ID_MASK      = 0xFFFFFF
1345 };
1346
1347 struct ocrdma_destroy_srq {
1348         struct ocrdma_mqe_hdr hdr;
1349         struct ocrdma_mbx_rsp req;
1350
1351         u32 id;
1352 };
1353
1354 enum {
1355         OCRDMA_ALLOC_PD_ENABLE_DPP      = BIT(16),
1356         OCRDMA_DPP_PAGE_SIZE            = 4096
1357 };
1358
1359 struct ocrdma_alloc_pd {
1360         struct ocrdma_mqe_hdr hdr;
1361         struct ocrdma_mbx_hdr req;
1362         u32 enable_dpp_rsvd;
1363 };
1364
1365 enum {
1366         OCRDMA_ALLOC_PD_RSP_DPP                 = BIT(16),
1367         OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT      = 20,
1368         OCRDMA_ALLOC_PD_RSP_PDID_MASK           = 0xFFFF,
1369 };
1370
1371 struct ocrdma_alloc_pd_rsp {
1372         struct ocrdma_mqe_hdr hdr;
1373         struct ocrdma_mbx_rsp rsp;
1374         u32 dpp_page_pdid;
1375 };
1376
1377 struct ocrdma_dealloc_pd {
1378         struct ocrdma_mqe_hdr hdr;
1379         struct ocrdma_mbx_hdr req;
1380         u32 id;
1381 };
1382
1383 struct ocrdma_dealloc_pd_rsp {
1384         struct ocrdma_mqe_hdr hdr;
1385         struct ocrdma_mbx_rsp rsp;
1386 };
1387
1388 struct ocrdma_alloc_pd_range {
1389         struct ocrdma_mqe_hdr hdr;
1390         struct ocrdma_mbx_hdr req;
1391         u32 enable_dpp_rsvd;
1392         u32 pd_count;
1393 };
1394
1395 struct ocrdma_alloc_pd_range_rsp {
1396         struct ocrdma_mqe_hdr hdr;
1397         struct ocrdma_mbx_rsp rsp;
1398         u32 dpp_page_pdid;
1399         u32 pd_count;
1400 };
1401
1402 enum {
1403         OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK = 0xFFFF,
1404 };
1405
1406 struct ocrdma_dealloc_pd_range {
1407         struct ocrdma_mqe_hdr hdr;
1408         struct ocrdma_mbx_hdr req;
1409         u32 start_pd_id;
1410         u32 pd_count;
1411 };
1412
1413 struct ocrdma_dealloc_pd_range_rsp {
1414         struct ocrdma_mqe_hdr hdr;
1415         struct ocrdma_mbx_hdr req;
1416         u32 rsvd;
1417 };
1418
1419 enum {
1420         OCRDMA_ADDR_CHECK_ENABLE        = 1,
1421         OCRDMA_ADDR_CHECK_DISABLE       = 0
1422 };
1423
1424 enum {
1425         OCRDMA_ALLOC_LKEY_PD_ID_SHIFT           = 0,
1426         OCRDMA_ALLOC_LKEY_PD_ID_MASK            = 0xFFFF,
1427
1428         OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT      = 0,
1429         OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK       = BIT(0),
1430         OCRDMA_ALLOC_LKEY_FMR_SHIFT             = 1,
1431         OCRDMA_ALLOC_LKEY_FMR_MASK              = BIT(1),
1432         OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT      = 2,
1433         OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK       = BIT(2),
1434         OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT       = 3,
1435         OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK        = BIT(3),
1436         OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT       = 4,
1437         OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK        = BIT(4),
1438         OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT        = 5,
1439         OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK         = BIT(5),
1440         OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK    = BIT(6),
1441         OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT   = 6,
1442         OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT        = 16,
1443         OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK         = 0xFFFF <<
1444                                                 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
1445 };
1446
1447 struct ocrdma_alloc_lkey {
1448         struct ocrdma_mqe_hdr hdr;
1449         struct ocrdma_mbx_hdr req;
1450
1451         u32 pdid;
1452         u32 pbl_sz_flags;
1453 };
1454
1455 struct ocrdma_alloc_lkey_rsp {
1456         struct ocrdma_mqe_hdr hdr;
1457         struct ocrdma_mbx_rsp rsp;
1458
1459         u32 lrkey;
1460         u32 num_pbl_rsvd;
1461 };
1462
1463 struct ocrdma_dealloc_lkey {
1464         struct ocrdma_mqe_hdr hdr;
1465         struct ocrdma_mbx_hdr req;
1466
1467         u32 lkey;
1468         u32 rsvd_frmr;
1469 };
1470
1471 struct ocrdma_dealloc_lkey_rsp {
1472         struct ocrdma_mqe_hdr hdr;
1473         struct ocrdma_mbx_rsp rsp;
1474 };
1475
1476 #define MAX_OCRDMA_NSMR_PBL    (u32)22
1477 #define MAX_OCRDMA_PBL_SIZE     65536
1478 #define MAX_OCRDMA_PBL_PER_LKEY 32767
1479
1480 enum {
1481         OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT       = 0,
1482         OCRDMA_REG_NSMR_LRKEY_INDEX_MASK        = 0xFFFFFF,
1483         OCRDMA_REG_NSMR_LRKEY_SHIFT             = 24,
1484         OCRDMA_REG_NSMR_LRKEY_MASK              = 0xFF <<
1485                                         OCRDMA_REG_NSMR_LRKEY_SHIFT,
1486
1487         OCRDMA_REG_NSMR_PD_ID_SHIFT             = 0,
1488         OCRDMA_REG_NSMR_PD_ID_MASK              = 0xFFFF,
1489         OCRDMA_REG_NSMR_NUM_PBL_SHIFT           = 16,
1490         OCRDMA_REG_NSMR_NUM_PBL_MASK            = 0xFFFF <<
1491                                         OCRDMA_REG_NSMR_NUM_PBL_SHIFT,
1492
1493         OCRDMA_REG_NSMR_PBE_SIZE_SHIFT          = 0,
1494         OCRDMA_REG_NSMR_PBE_SIZE_MASK           = 0xFFFF,
1495         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT        = 16,
1496         OCRDMA_REG_NSMR_HPAGE_SIZE_MASK         = 0xFF <<
1497                                         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
1498         OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT       = 24,
1499         OCRDMA_REG_NSMR_BIND_MEMWIN_MASK        = BIT(24),
1500         OCRDMA_REG_NSMR_ZB_SHIFT                = 25,
1501         OCRDMA_REG_NSMR_ZB_SHIFT_MASK           = BIT(25),
1502         OCRDMA_REG_NSMR_REMOTE_INV_SHIFT        = 26,
1503         OCRDMA_REG_NSMR_REMOTE_INV_MASK         = BIT(26),
1504         OCRDMA_REG_NSMR_REMOTE_WR_SHIFT         = 27,
1505         OCRDMA_REG_NSMR_REMOTE_WR_MASK          = BIT(27),
1506         OCRDMA_REG_NSMR_REMOTE_RD_SHIFT         = 28,
1507         OCRDMA_REG_NSMR_REMOTE_RD_MASK          = BIT(28),
1508         OCRDMA_REG_NSMR_LOCAL_WR_SHIFT          = 29,
1509         OCRDMA_REG_NSMR_LOCAL_WR_MASK           = BIT(29),
1510         OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT     = 30,
1511         OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK      = BIT(30),
1512         OCRDMA_REG_NSMR_LAST_SHIFT              = 31,
1513         OCRDMA_REG_NSMR_LAST_MASK               = BIT(31)
1514 };
1515
1516 struct ocrdma_reg_nsmr {
1517         struct ocrdma_mqe_hdr hdr;
1518         struct ocrdma_mbx_hdr cmd;
1519
1520         u32 fr_mr;
1521         u32 num_pbl_pdid;
1522         u32 flags_hpage_pbe_sz;
1523         u32 totlen_low;
1524         u32 totlen_high;
1525         u32 fbo_low;
1526         u32 fbo_high;
1527         u32 va_loaddr;
1528         u32 va_hiaddr;
1529         struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1530 };
1531
1532 enum {
1533         OCRDMA_REG_NSMR_CONT_PBL_SHIFT          = 0,
1534         OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK     = 0xFFFF,
1535         OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT      = 16,
1536         OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK       = 0xFFFF <<
1537                                         OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,
1538
1539         OCRDMA_REG_NSMR_CONT_LAST_SHIFT         = 31,
1540         OCRDMA_REG_NSMR_CONT_LAST_MASK          = BIT(31)
1541 };
1542
1543 struct ocrdma_reg_nsmr_cont {
1544         struct ocrdma_mqe_hdr hdr;
1545         struct ocrdma_mbx_hdr cmd;
1546
1547         u32 lrkey;
1548         u32 num_pbl_offset;
1549         u32 last;
1550
1551         struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1552 };
1553
1554 struct ocrdma_pbe {
1555         u32 pa_hi;
1556         u32 pa_lo;
1557 };
1558
1559 enum {
1560         OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT       = 16,
1561         OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK        = 0xFFFF0000
1562 };
1563 struct ocrdma_reg_nsmr_rsp {
1564         struct ocrdma_mqe_hdr hdr;
1565         struct ocrdma_mbx_rsp rsp;
1566
1567         u32 lrkey;
1568         u32 num_pbl;
1569 };
1570
1571 enum {
1572         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT      = 0,
1573         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK       = 0xFFFFFF,
1574         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT            = 24,
1575         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK             = 0xFF <<
1576                                         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT,
1577
1578         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT          = 16,
1579         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK           = 0xFFFF <<
1580                                         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
1581 };
1582
1583 struct ocrdma_reg_nsmr_cont_rsp {
1584         struct ocrdma_mqe_hdr hdr;
1585         struct ocrdma_mbx_rsp rsp;
1586
1587         u32 lrkey_key_index;
1588         u32 num_pbl;
1589 };
1590
1591 enum {
1592         OCRDMA_ALLOC_MW_PD_ID_SHIFT     = 0,
1593         OCRDMA_ALLOC_MW_PD_ID_MASK      = 0xFFFF
1594 };
1595
1596 struct ocrdma_alloc_mw {
1597         struct ocrdma_mqe_hdr hdr;
1598         struct ocrdma_mbx_hdr req;
1599
1600         u32 pdid;
1601 };
1602
1603 enum {
1604         OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT   = 0,
1605         OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK    = 0xFFFFFF
1606 };
1607
1608 struct ocrdma_alloc_mw_rsp {
1609         struct ocrdma_mqe_hdr hdr;
1610         struct ocrdma_mbx_rsp rsp;
1611
1612         u32 lrkey_index;
1613 };
1614
1615 struct ocrdma_attach_mcast {
1616         struct ocrdma_mqe_hdr hdr;
1617         struct ocrdma_mbx_hdr req;
1618         u32 qp_id;
1619         u8 mgid[16];
1620         u32 mac_b0_to_b3;
1621         u32 vlan_mac_b4_to_b5;
1622 };
1623
1624 struct ocrdma_attach_mcast_rsp {
1625         struct ocrdma_mqe_hdr hdr;
1626         struct ocrdma_mbx_rsp rsp;
1627 };
1628
1629 struct ocrdma_detach_mcast {
1630         struct ocrdma_mqe_hdr hdr;
1631         struct ocrdma_mbx_hdr req;
1632         u32 qp_id;
1633         u8 mgid[16];
1634         u32 mac_b0_to_b3;
1635         u32 vlan_mac_b4_to_b5;
1636 };
1637
1638 struct ocrdma_detach_mcast_rsp {
1639         struct ocrdma_mqe_hdr hdr;
1640         struct ocrdma_mbx_rsp rsp;
1641 };
1642
1643 enum {
1644         OCRDMA_CREATE_AH_NUM_PAGES_SHIFT        = 19,
1645         OCRDMA_CREATE_AH_NUM_PAGES_MASK         = 0xF <<
1646                                         OCRDMA_CREATE_AH_NUM_PAGES_SHIFT,
1647
1648         OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT        = 16,
1649         OCRDMA_CREATE_AH_PAGE_SIZE_MASK         = 0x7 <<
1650                                         OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT,
1651
1652         OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT       = 23,
1653         OCRDMA_CREATE_AH_ENTRY_SIZE_MASK        = 0x1FF <<
1654                                         OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT,
1655 };
1656
1657 #define OCRDMA_AH_TBL_PAGES 8
1658
1659 struct ocrdma_create_ah_tbl {
1660         struct ocrdma_mqe_hdr hdr;
1661         struct ocrdma_mbx_hdr req;
1662
1663         u32 ah_conf;
1664         struct ocrdma_pa tbl_addr[8];
1665 };
1666
1667 struct ocrdma_create_ah_tbl_rsp {
1668         struct ocrdma_mqe_hdr hdr;
1669         struct ocrdma_mbx_rsp rsp;
1670         u32 ahid;
1671 };
1672
1673 struct ocrdma_delete_ah_tbl {
1674         struct ocrdma_mqe_hdr hdr;
1675         struct ocrdma_mbx_hdr req;
1676         u32 ahid;
1677 };
1678
1679 struct ocrdma_delete_ah_tbl_rsp {
1680         struct ocrdma_mqe_hdr hdr;
1681         struct ocrdma_mbx_rsp rsp;
1682 };
1683
1684 enum {
1685         OCRDMA_EQE_VALID_SHIFT          = 0,
1686         OCRDMA_EQE_VALID_MASK           = BIT(0),
1687         OCRDMA_EQE_MAJOR_CODE_MASK      = 0x0E,
1688         OCRDMA_EQE_MAJOR_CODE_SHIFT     = 0x01,
1689         OCRDMA_EQE_FOR_CQE_MASK         = 0xFFFE,
1690         OCRDMA_EQE_RESOURCE_ID_SHIFT    = 16,
1691         OCRDMA_EQE_RESOURCE_ID_MASK     = 0xFFFF <<
1692                                 OCRDMA_EQE_RESOURCE_ID_SHIFT,
1693 };
1694
1695 enum major_code {
1696         OCRDMA_MAJOR_CODE_COMPLETION    = 0x00,
1697         OCRDMA_MAJOR_CODE_SENTINAL      = 0x01
1698 };
1699
1700 struct ocrdma_eqe {
1701         u32 id_valid;
1702 };
1703
1704 enum OCRDMA_CQE_STATUS {
1705         OCRDMA_CQE_SUCCESS = 0,
1706         OCRDMA_CQE_LOC_LEN_ERR,
1707         OCRDMA_CQE_LOC_QP_OP_ERR,
1708         OCRDMA_CQE_LOC_EEC_OP_ERR,
1709         OCRDMA_CQE_LOC_PROT_ERR,
1710         OCRDMA_CQE_WR_FLUSH_ERR,
1711         OCRDMA_CQE_MW_BIND_ERR,
1712         OCRDMA_CQE_BAD_RESP_ERR,
1713         OCRDMA_CQE_LOC_ACCESS_ERR,
1714         OCRDMA_CQE_REM_INV_REQ_ERR,
1715         OCRDMA_CQE_REM_ACCESS_ERR,
1716         OCRDMA_CQE_REM_OP_ERR,
1717         OCRDMA_CQE_RETRY_EXC_ERR,
1718         OCRDMA_CQE_RNR_RETRY_EXC_ERR,
1719         OCRDMA_CQE_LOC_RDD_VIOL_ERR,
1720         OCRDMA_CQE_REM_INV_RD_REQ_ERR,
1721         OCRDMA_CQE_REM_ABORT_ERR,
1722         OCRDMA_CQE_INV_EECN_ERR,
1723         OCRDMA_CQE_INV_EEC_STATE_ERR,
1724         OCRDMA_CQE_FATAL_ERR,
1725         OCRDMA_CQE_RESP_TIMEOUT_ERR,
1726         OCRDMA_CQE_GENERAL_ERR,
1727
1728         OCRDMA_MAX_CQE_ERR
1729 };
1730
1731 enum {
1732         /* w0 */
1733         OCRDMA_CQE_WQEIDX_SHIFT         = 0,
1734         OCRDMA_CQE_WQEIDX_MASK          = 0xFFFF,
1735
1736         /* w1 */
1737         OCRDMA_CQE_UD_XFER_LEN_SHIFT    = 16,
1738         OCRDMA_CQE_PKEY_SHIFT           = 0,
1739         OCRDMA_CQE_PKEY_MASK            = 0xFFFF,
1740
1741         /* w2 */
1742         OCRDMA_CQE_QPN_SHIFT            = 0,
1743         OCRDMA_CQE_QPN_MASK             = 0x0000FFFF,
1744
1745         OCRDMA_CQE_BUFTAG_SHIFT         = 16,
1746         OCRDMA_CQE_BUFTAG_MASK          = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT,
1747
1748         /* w3 */
1749         OCRDMA_CQE_UD_STATUS_SHIFT      = 24,
1750         OCRDMA_CQE_UD_STATUS_MASK       = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,
1751         OCRDMA_CQE_STATUS_SHIFT         = 16,
1752         OCRDMA_CQE_STATUS_MASK          = 0xFF << OCRDMA_CQE_STATUS_SHIFT,
1753         OCRDMA_CQE_VALID                = BIT(31),
1754         OCRDMA_CQE_INVALIDATE           = BIT(30),
1755         OCRDMA_CQE_QTYPE                = BIT(29),
1756         OCRDMA_CQE_IMM                  = BIT(28),
1757         OCRDMA_CQE_WRITE_IMM            = BIT(27),
1758         OCRDMA_CQE_QTYPE_SQ             = 0,
1759         OCRDMA_CQE_QTYPE_RQ             = 1,
1760         OCRDMA_CQE_SRCQP_MASK           = 0xFFFFFF
1761 };
1762
1763 struct ocrdma_cqe {
1764         union {
1765                 /* w0 to w2 */
1766                 struct {
1767                         u32 wqeidx;
1768                         u32 bytes_xfered;
1769                         u32 qpn;
1770                 } wq;
1771                 struct {
1772                         u32 lkey_immdt;
1773                         u32 rxlen;
1774                         u32 buftag_qpn;
1775                 } rq;
1776                 struct {
1777                         u32 lkey_immdt;
1778                         u32 rxlen_pkey;
1779                         u32 buftag_qpn;
1780                 } ud;
1781                 struct {
1782                         u32 word_0;
1783                         u32 word_1;
1784                         u32 qpn;
1785                 } cmn;
1786         };
1787         u32 flags_status_srcqpn;        /* w3 */
1788 };
1789
1790 struct ocrdma_sge {
1791         u32 addr_hi;
1792         u32 addr_lo;
1793         u32 lrkey;
1794         u32 len;
1795 };
1796
1797 enum {
1798         OCRDMA_FLAG_SIG         = 0x1,
1799         OCRDMA_FLAG_INV         = 0x2,
1800         OCRDMA_FLAG_FENCE_L     = 0x4,
1801         OCRDMA_FLAG_FENCE_R     = 0x8,
1802         OCRDMA_FLAG_SOLICIT     = 0x10,
1803         OCRDMA_FLAG_IMM         = 0x20,
1804         OCRDMA_FLAG_AH_VLAN_PR  = 0x40,
1805
1806         /* Stag flags */
1807         OCRDMA_LKEY_FLAG_LOCAL_WR       = 0x1,
1808         OCRDMA_LKEY_FLAG_REMOTE_RD      = 0x2,
1809         OCRDMA_LKEY_FLAG_REMOTE_WR      = 0x4,
1810         OCRDMA_LKEY_FLAG_VATO           = 0x8,
1811 };
1812
1813 enum OCRDMA_WQE_OPCODE {
1814         OCRDMA_WRITE            = 0x06,
1815         OCRDMA_READ             = 0x0C,
1816         OCRDMA_RESV0            = 0x02,
1817         OCRDMA_SEND             = 0x00,
1818         OCRDMA_CMP_SWP          = 0x14,
1819         OCRDMA_BIND_MW          = 0x10,
1820         OCRDMA_FR_MR            = 0x11,
1821         OCRDMA_RESV1            = 0x0A,
1822         OCRDMA_LKEY_INV         = 0x15,
1823         OCRDMA_FETCH_ADD        = 0x13,
1824         OCRDMA_POST_RQ          = 0x12
1825 };
1826
1827 enum {
1828         OCRDMA_TYPE_INLINE      = 0x0,
1829         OCRDMA_TYPE_LKEY        = 0x1,
1830 };
1831
1832 enum {
1833         OCRDMA_WQE_OPCODE_SHIFT         = 0,
1834         OCRDMA_WQE_OPCODE_MASK          = 0x0000001F,
1835         OCRDMA_WQE_FLAGS_SHIFT          = 5,
1836         OCRDMA_WQE_TYPE_SHIFT           = 16,
1837         OCRDMA_WQE_TYPE_MASK            = 0x00030000,
1838         OCRDMA_WQE_SIZE_SHIFT           = 18,
1839         OCRDMA_WQE_SIZE_MASK            = 0xFF,
1840         OCRDMA_WQE_NXT_WQE_SIZE_SHIFT   = 25,
1841
1842         OCRDMA_WQE_LKEY_FLAGS_SHIFT     = 0,
1843         OCRDMA_WQE_LKEY_FLAGS_MASK      = 0xF
1844 };
1845
1846 /* header WQE for all the SQ and RQ operations */
1847 struct ocrdma_hdr_wqe {
1848         u32 cw;
1849         union {
1850                 u32 rsvd_tag;
1851                 u32 rsvd_lkey_flags;
1852         };
1853         union {
1854                 u32 immdt;
1855                 u32 lkey;
1856         };
1857         u32 total_len;
1858 };
1859
1860 struct ocrdma_ewqe_ud_hdr {
1861         u32 rsvd_dest_qpn;
1862         u32 qkey;
1863         u32 rsvd_ahid;
1864         u32 rsvd;
1865 };
1866
1867 /* extended wqe followed by hdr_wqe for Fast Memory register */
1868 struct ocrdma_ewqe_fr {
1869         u32 va_hi;
1870         u32 va_lo;
1871         u32 fbo_hi;
1872         u32 fbo_lo;
1873         u32 size_sge;
1874         u32 num_sges;
1875         u32 rsvd;
1876         u32 rsvd2;
1877 };
1878
1879 struct ocrdma_eth_basic {
1880         u8 dmac[6];
1881         u8 smac[6];
1882         __be16 eth_type;
1883 } __packed;
1884
1885 struct ocrdma_eth_vlan {
1886         u8 dmac[6];
1887         u8 smac[6];
1888         __be16 eth_type;
1889         __be16 vlan_tag;
1890 #define OCRDMA_ROCE_ETH_TYPE 0x8915
1891         __be16 roce_eth_type;
1892 } __packed;
1893
1894 struct ocrdma_grh {
1895         __be32  tclass_flow;
1896         __be32  pdid_hoplimit;
1897         u8      sgid[16];
1898         u8      dgid[16];
1899         u16     rsvd;
1900 } __packed;
1901
1902 #define OCRDMA_AV_VALID         BIT(7)
1903 #define OCRDMA_AV_VLAN_VALID    BIT(1)
1904
1905 struct ocrdma_av {
1906         struct ocrdma_eth_vlan eth_hdr;
1907         struct ocrdma_grh grh;
1908         u32 valid;
1909 } __packed;
1910
1911 struct ocrdma_rsrc_stats {
1912         u32 dpp_pds;
1913         u32 non_dpp_pds;
1914         u32 rc_dpp_qps;
1915         u32 uc_dpp_qps;
1916         u32 ud_dpp_qps;
1917         u32 rc_non_dpp_qps;
1918         u32 rsvd;
1919         u32 uc_non_dpp_qps;
1920         u32 ud_non_dpp_qps;
1921         u32 rsvd1;
1922         u32 srqs;
1923         u32 rbqs;
1924         u32 r64K_nsmr;
1925         u32 r64K_to_2M_nsmr;
1926         u32 r2M_to_44M_nsmr;
1927         u32 r44M_to_1G_nsmr;
1928         u32 r1G_to_4G_nsmr;
1929         u32 nsmr_count_4G_to_32G;
1930         u32 r32G_to_64G_nsmr;
1931         u32 r64G_to_128G_nsmr;
1932         u32 r128G_to_higher_nsmr;
1933         u32 embedded_nsmr;
1934         u32 frmr;
1935         u32 prefetch_qps;
1936         u32 ondemand_qps;
1937         u32 phy_mr;
1938         u32 mw;
1939         u32 rsvd2[7];
1940 };
1941
1942 struct ocrdma_db_err_stats {
1943         u32 sq_doorbell_errors;
1944         u32 cq_doorbell_errors;
1945         u32 rq_srq_doorbell_errors;
1946         u32 cq_overflow_errors;
1947         u32 rsvd[4];
1948 };
1949
1950 struct ocrdma_wqe_stats {
1951         u32 large_send_rc_wqes_lo;
1952         u32 large_send_rc_wqes_hi;
1953         u32 large_write_rc_wqes_lo;
1954         u32 large_write_rc_wqes_hi;
1955         u32 rsvd[4];
1956         u32 read_wqes_lo;
1957         u32 read_wqes_hi;
1958         u32 frmr_wqes_lo;
1959         u32 frmr_wqes_hi;
1960         u32 mw_bind_wqes_lo;
1961         u32 mw_bind_wqes_hi;
1962         u32 invalidate_wqes_lo;
1963         u32 invalidate_wqes_hi;
1964         u32 rsvd1[2];
1965         u32 dpp_wqe_drops;
1966         u32 rsvd2[5];
1967 };
1968
1969 struct ocrdma_tx_stats {
1970         u32 send_pkts_lo;
1971         u32 send_pkts_hi;
1972         u32 write_pkts_lo;
1973         u32 write_pkts_hi;
1974         u32 read_pkts_lo;
1975         u32 read_pkts_hi;
1976         u32 read_rsp_pkts_lo;
1977         u32 read_rsp_pkts_hi;
1978         u32 ack_pkts_lo;
1979         u32 ack_pkts_hi;
1980         u32 send_bytes_lo;
1981         u32 send_bytes_hi;
1982         u32 write_bytes_lo;
1983         u32 write_bytes_hi;
1984         u32 read_req_bytes_lo;
1985         u32 read_req_bytes_hi;
1986         u32 read_rsp_bytes_lo;
1987         u32 read_rsp_bytes_hi;
1988         u32 ack_timeouts;
1989         u32 rsvd[5];
1990 };
1991
1992
1993 struct ocrdma_tx_qp_err_stats {
1994         u32 local_length_errors;
1995         u32 local_protection_errors;
1996         u32 local_qp_operation_errors;
1997         u32 retry_count_exceeded_errors;
1998         u32 rnr_retry_count_exceeded_errors;
1999         u32 rsvd[3];
2000 };
2001
2002 struct ocrdma_rx_stats {
2003         u32 roce_frame_bytes_lo;
2004         u32 roce_frame_bytes_hi;
2005         u32 roce_frame_icrc_drops;
2006         u32 roce_frame_payload_len_drops;
2007         u32 ud_drops;
2008         u32 qp1_drops;
2009         u32 psn_error_request_packets;
2010         u32 psn_error_resp_packets;
2011         u32 rnr_nak_timeouts;
2012         u32 rnr_nak_receives;
2013         u32 roce_frame_rxmt_drops;
2014         u32 nak_count_psn_sequence_errors;
2015         u32 rc_drop_count_lookup_errors;
2016         u32 rq_rnr_naks;
2017         u32 srq_rnr_naks;
2018         u32 roce_frames_lo;
2019         u32 roce_frames_hi;
2020         u32 rsvd;
2021 };
2022
2023 struct ocrdma_rx_qp_err_stats {
2024         u32 nak_invalid_requst_errors;
2025         u32 nak_remote_operation_errors;
2026         u32 nak_count_remote_access_errors;
2027         u32 local_length_errors;
2028         u32 local_protection_errors;
2029         u32 local_qp_operation_errors;
2030         u32 rsvd[2];
2031 };
2032
2033 struct ocrdma_tx_dbg_stats {
2034         u32 data[100];
2035 };
2036
2037 struct ocrdma_rx_dbg_stats {
2038         u32 data[200];
2039 };
2040
2041 struct ocrdma_rdma_stats_req {
2042         struct ocrdma_mbx_hdr hdr;
2043         u8 reset_stats;
2044         u8 rsvd[3];
2045 } __packed;
2046
2047 struct ocrdma_rdma_stats_resp {
2048         struct ocrdma_mbx_hdr hdr;
2049         struct ocrdma_rsrc_stats act_rsrc_stats;
2050         struct ocrdma_rsrc_stats th_rsrc_stats;
2051         struct ocrdma_db_err_stats      db_err_stats;
2052         struct ocrdma_wqe_stats         wqe_stats;
2053         struct ocrdma_tx_stats          tx_stats;
2054         struct ocrdma_tx_qp_err_stats   tx_qp_err_stats;
2055         struct ocrdma_rx_stats          rx_stats;
2056         struct ocrdma_rx_qp_err_stats   rx_qp_err_stats;
2057         struct ocrdma_tx_dbg_stats      tx_dbg_stats;
2058         struct ocrdma_rx_dbg_stats      rx_dbg_stats;
2059 } __packed;
2060
2061 enum {
2062         OCRDMA_HBA_ATTRB_EPROM_VER_LO_MASK      = 0xFF,
2063         OCRDMA_HBA_ATTRB_EPROM_VER_HI_MASK      = 0xFF00,
2064         OCRDMA_HBA_ATTRB_EPROM_VER_HI_SHIFT     = 0x08,
2065         OCRDMA_HBA_ATTRB_CDBLEN_MASK            = 0xFFFF,
2066         OCRDMA_HBA_ATTRB_ASIC_REV_MASK          = 0xFF0000,
2067         OCRDMA_HBA_ATTRB_ASIC_REV_SHIFT         = 0x10,
2068         OCRDMA_HBA_ATTRB_GUID0_MASK             = 0xFF000000,
2069         OCRDMA_HBA_ATTRB_GUID0_SHIFT            = 0x18,
2070         OCRDMA_HBA_ATTRB_GUID13_MASK            = 0xFF,
2071         OCRDMA_HBA_ATTRB_GUID14_MASK            = 0xFF00,
2072         OCRDMA_HBA_ATTRB_GUID14_SHIFT           = 0x08,
2073         OCRDMA_HBA_ATTRB_GUID15_MASK            = 0xFF0000,
2074         OCRDMA_HBA_ATTRB_GUID15_SHIFT           = 0x10,
2075         OCRDMA_HBA_ATTRB_PCNT_MASK              = 0xFF000000,
2076         OCRDMA_HBA_ATTRB_PCNT_SHIFT             = 0x18,
2077         OCRDMA_HBA_ATTRB_LDTOUT_MASK            = 0xFFFF,
2078         OCRDMA_HBA_ATTRB_ISCSI_VER_MASK         = 0xFF0000,
2079         OCRDMA_HBA_ATTRB_ISCSI_VER_SHIFT        = 0x10,
2080         OCRDMA_HBA_ATTRB_MFUNC_DEV_MASK         = 0xFF000000,
2081         OCRDMA_HBA_ATTRB_MFUNC_DEV_SHIFT        = 0x18,
2082         OCRDMA_HBA_ATTRB_CV_MASK                = 0xFF,
2083         OCRDMA_HBA_ATTRB_HBA_ST_MASK            = 0xFF00,
2084         OCRDMA_HBA_ATTRB_HBA_ST_SHIFT           = 0x08,
2085         OCRDMA_HBA_ATTRB_MAX_DOMS_MASK          = 0xFF0000,
2086         OCRDMA_HBA_ATTRB_MAX_DOMS_SHIFT         = 0x10,
2087         OCRDMA_HBA_ATTRB_PTNUM_MASK             = 0x3F000000,
2088         OCRDMA_HBA_ATTRB_PTNUM_SHIFT            = 0x18,
2089         OCRDMA_HBA_ATTRB_PT_MASK                = 0xC0000000,
2090         OCRDMA_HBA_ATTRB_PT_SHIFT               = 0x1E,
2091         OCRDMA_HBA_ATTRB_ISCSI_FET_MASK         = 0xFF,
2092         OCRDMA_HBA_ATTRB_ASIC_GEN_MASK          = 0xFF00,
2093         OCRDMA_HBA_ATTRB_ASIC_GEN_SHIFT         = 0x08,
2094         OCRDMA_HBA_ATTRB_PCI_VID_MASK           = 0xFFFF,
2095         OCRDMA_HBA_ATTRB_PCI_DID_MASK           = 0xFFFF0000,
2096         OCRDMA_HBA_ATTRB_PCI_DID_SHIFT          = 0x10,
2097         OCRDMA_HBA_ATTRB_PCI_SVID_MASK          = 0xFFFF,
2098         OCRDMA_HBA_ATTRB_PCI_SSID_MASK          = 0xFFFF0000,
2099         OCRDMA_HBA_ATTRB_PCI_SSID_SHIFT         = 0x10,
2100         OCRDMA_HBA_ATTRB_PCI_BUSNUM_MASK        = 0xFF,
2101         OCRDMA_HBA_ATTRB_PCI_DEVNUM_MASK        = 0xFF00,
2102         OCRDMA_HBA_ATTRB_PCI_DEVNUM_SHIFT       = 0x08,
2103         OCRDMA_HBA_ATTRB_PCI_FUNCNUM_MASK       = 0xFF0000,
2104         OCRDMA_HBA_ATTRB_PCI_FUNCNUM_SHIFT      = 0x10,
2105         OCRDMA_HBA_ATTRB_IF_TYPE_MASK           = 0xFF000000,
2106         OCRDMA_HBA_ATTRB_IF_TYPE_SHIFT          = 0x18,
2107         OCRDMA_HBA_ATTRB_NETFIL_MASK            =0xFF
2108 };
2109
2110 struct mgmt_hba_attribs {
2111         u8 flashrom_version_string[32];
2112         u8 manufacturer_name[32];
2113         u32 supported_modes;
2114         u32 rsvd_eprom_verhi_verlo;
2115         u32 mbx_ds_ver;
2116         u32 epfw_ds_ver;
2117         u8 ncsi_ver_string[12];
2118         u32 default_extended_timeout;
2119         u8 controller_model_number[32];
2120         u8 controller_description[64];
2121         u8 controller_serial_number[32];
2122         u8 ip_version_string[32];
2123         u8 firmware_version_string[32];
2124         u8 bios_version_string[32];
2125         u8 redboot_version_string[32];
2126         u8 driver_version_string[32];
2127         u8 fw_on_flash_version_string[32];
2128         u32 functionalities_supported;
2129         u32 guid0_asicrev_cdblen;
2130         u8 generational_guid[12];
2131         u32 portcnt_guid15;
2132         u32 mfuncdev_iscsi_ldtout;
2133         u32 ptpnum_maxdoms_hbast_cv;
2134         u32 firmware_post_status;
2135         u32 hba_mtu[8];
2136         u32 res_asicgen_iscsi_feaures;
2137         u32 rsvd1[3];
2138 };
2139
2140 struct mgmt_controller_attrib {
2141         struct mgmt_hba_attribs hba_attribs;
2142         u32 pci_did_vid;
2143         u32 pci_ssid_svid;
2144         u32 ityp_fnum_devnum_bnum;
2145         u32 uid_hi;
2146         u32 uid_lo;
2147         u32 res_nnetfil;
2148         u32 rsvd0[4];
2149 };
2150
2151 struct ocrdma_get_ctrl_attribs_rsp {
2152         struct ocrdma_mbx_hdr hdr;
2153         struct mgmt_controller_attrib ctrl_attribs;
2154 };
2155
2156 #define OCRDMA_SUBSYS_DCBX 0x10
2157
2158 enum OCRDMA_DCBX_OPCODE {
2159         OCRDMA_CMD_GET_DCBX_CONFIG = 0x01
2160 };
2161
2162 enum OCRDMA_DCBX_PARAM_TYPE {
2163         OCRDMA_PARAMETER_TYPE_ADMIN     = 0x00,
2164         OCRDMA_PARAMETER_TYPE_OPER      = 0x01,
2165         OCRDMA_PARAMETER_TYPE_PEER      = 0x02
2166 };
2167
2168 enum OCRDMA_DCBX_APP_PROTO {
2169         OCRDMA_APP_PROTO_ROCE   = 0x8915
2170 };
2171
2172 enum OCRDMA_DCBX_PROTO {
2173         OCRDMA_PROTO_SELECT_L2  = 0x00,
2174         OCRDMA_PROTO_SELECT_L4  = 0x01
2175 };
2176
2177 enum OCRDMA_DCBX_APP_PARAM {
2178         OCRDMA_APP_PARAM_APP_PROTO_MASK = 0xFFFF,
2179         OCRDMA_APP_PARAM_PROTO_SEL_MASK = 0xFF,
2180         OCRDMA_APP_PARAM_PROTO_SEL_SHIFT = 0x10,
2181         OCRDMA_APP_PARAM_VALID_MASK     = 0xFF,
2182         OCRDMA_APP_PARAM_VALID_SHIFT    = 0x18
2183 };
2184
2185 enum OCRDMA_DCBX_STATE_FLAGS {
2186         OCRDMA_STATE_FLAG_ENABLED       = 0x01,
2187         OCRDMA_STATE_FLAG_ADDVERTISED   = 0x02,
2188         OCRDMA_STATE_FLAG_WILLING       = 0x04,
2189         OCRDMA_STATE_FLAG_SYNC          = 0x08,
2190         OCRDMA_STATE_FLAG_UNSUPPORTED   = 0x40000000,
2191         OCRDMA_STATE_FLAG_NEG_FAILD     = 0x80000000
2192 };
2193
2194 enum OCRDMA_TCV_AEV_OPV_ST {
2195         OCRDMA_DCBX_TC_SUPPORT_MASK     = 0xFF,
2196         OCRDMA_DCBX_TC_SUPPORT_SHIFT    = 0x18,
2197         OCRDMA_DCBX_APP_ENTRY_SHIFT     = 0x10,
2198         OCRDMA_DCBX_OP_PARAM_SHIFT      = 0x08,
2199         OCRDMA_DCBX_STATE_MASK          = 0xFF
2200 };
2201
2202 struct ocrdma_app_parameter {
2203         u32 valid_proto_app;
2204         u32 oui;
2205         u32 app_prio[2];
2206 };
2207
2208 struct ocrdma_dcbx_cfg {
2209         u32 tcv_aev_opv_st;
2210         u32 tc_state;
2211         u32 pfc_state;
2212         u32 qcn_state;
2213         u32 appl_state;
2214         u32 ll_state;
2215         u32 tc_bw[2];
2216         u32 tc_prio[8];
2217         u32 pfc_prio[2];
2218         struct ocrdma_app_parameter app_param[15];
2219 };
2220
2221 struct ocrdma_get_dcbx_cfg_req {
2222         struct ocrdma_mbx_hdr hdr;
2223         u32 param_type;
2224 } __packed;
2225
2226 struct ocrdma_get_dcbx_cfg_rsp {
2227         struct ocrdma_mbx_rsp hdr;
2228         struct ocrdma_dcbx_cfg cfg;
2229 } __packed;
2230
2231 #endif                          /* __OCRDMA_SLI_H__ */