kernel/drivers/infiniband/hw/ipath/ipath_init_chip.c

   1 /*
   2  * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/pci.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/slab.h>
  38 #include <linux/stat.h>
  39 #include <linux/vmalloc.h>
  40
  41 #include "ipath_kernel.h"
  42 #include "ipath_common.h"
  43
  44 /*
  45  * min buffers we want to have per port, after driver
  46  */
  47 #define IPATH_MIN_USER_PORT_BUFCNT 7
  48
  49 /*
  50  * Number of ports we are configured to use (to allow for more pio
  51  * buffers per port, etc.)  Zero means use chip value.
  52  */
  53 static ushort ipath_cfgports;
  54
  55 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
  56 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
  57
  58 /*
  59  * Number of buffers reserved for driver (verbs and layered drivers.)
  60  * Initialized based on number of PIO buffers if not set via module interface.
  61  * The problem with this is that it's global, but we'll use different
  62  * numbers for different chip types.
  63  */
  64 static ushort ipath_kpiobufs;
  65
  66 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
  67
  68 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
  69                   &ipath_kpiobufs, S_IWUSR | S_IRUGO);
  70 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
  71
  72 /**
  73  * create_port0_egr - allocate the eager TID buffers
  74  * @dd: the infinipath device
  75  *
  76  * This code is now quite different for user and kernel, because
  77  * the kernel uses skb's, for the accelerated network performance.
  78  * This is the kernel (port0) version.
  79  *
  80  * Allocate the eager TID buffers and program them into infinipath.
  81  * We use the network layer alloc_skb() allocator to allocate the
  82  * memory, and either use the buffers as is for things like verbs
  83  * packets, or pass the buffers up to the ipath layered driver and
  84  * thence the network layer, replacing them as we do so (see
  85  * ipath_rcv_layer()).
  86  */
  87 static int create_port0_egr(struct ipath_devdata *dd)
  88 {
  89         unsigned e, egrcnt;
  90         struct ipath_skbinfo *skbinfo;
  91         int ret;
  92
  93         egrcnt = dd->ipath_p0_rcvegrcnt;
  94
  95         skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt);
  96         if (skbinfo == NULL) {
  97                 ipath_dev_err(dd, "allocation error for eager TID "
  98                               "skb array\n");
  99                 ret = -ENOMEM;
 100                 goto bail;
 101         }
 102         for (e = 0; e < egrcnt; e++) {
 103                 /*
 104                  * This is a bit tricky in that we allocate extra
 105                  * space for 2 bytes of the 14 byte ethernet header.
 106                  * These two bytes are passed in the ipath header so
 107                  * the rest of the data is word aligned.  We allocate
 108                  * 4 bytes so that the data buffer stays word aligned.
 109                  * See ipath_kreceive() for more details.
 110                  */
 111                 skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL);
 112                 if (!skbinfo[e].skb) {
 113                         ipath_dev_err(dd, "SKB allocation error for "
 114                                       "eager TID %u\n", e);
 115                         while (e != 0)
 116                                 dev_kfree_skb(skbinfo[--e].skb);
 117                         vfree(skbinfo);
 118                         ret = -ENOMEM;
 119                         goto bail;
 120                 }
 121         }
 122         /*
 123          * After loop above, so we can test non-NULL to see if ready
 124          * to use at receive, etc.
 125          */
 126         dd->ipath_port0_skbinfo = skbinfo;
 127
 128         for (e = 0; e < egrcnt; e++) {
 129                 dd->ipath_port0_skbinfo[e].phys =
 130                   ipath_map_single(dd->pcidev,
 131                                    dd->ipath_port0_skbinfo[e].skb->data,
 132                                    dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE);
 133                 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
 134                                     ((char __iomem *) dd->ipath_kregbase +
 135                                      dd->ipath_rcvegrbase),
 136                                     RCVHQ_RCV_TYPE_EAGER,
 137                                     dd->ipath_port0_skbinfo[e].phys);
 138         }
 139
 140         ret = 0;
 141
 142 bail:
 143         return ret;
 144 }
 145
 146 static int bringup_link(struct ipath_devdata *dd)
 147 {
 148         u64 val, ibc;
 149         int ret = 0;
 150
 151         /* hold IBC in reset */
 152         dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
 153         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 154                          dd->ipath_control);
 155
 156         /*
 157          * set initial max size pkt IBC will send, including ICRC; it's the
 158          * PIO buffer size in dwords, less 1; also see ipath_set_mtu()
 159          */
 160         val = (dd->ipath_ibmaxlen >> 2) + 1;
 161         ibc = val << dd->ibcc_mpl_shift;
 162
 163         /* flowcontrolwatermark is in units of KBytes */
 164         ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
 165         /*
 166          * How often flowctrl sent.  More or less in usecs; balance against
 167          * watermark value, so that in theory senders always get a flow
 168          * control update in time to not let the IB link go idle.
 169          */
 170         ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
 171         /* max error tolerance */
 172         ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
 173         /* use "real" buffer space for */
 174         ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
 175         /* IB credit flow control. */
 176         ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
 177         /* initially come up waiting for TS1, without sending anything. */
 178         dd->ipath_ibcctrl = ibc;
 179         /*
 180          * Want to start out with both LINKCMD and LINKINITCMD in NOP
 181          * (0 and 0).  Don't put linkinitcmd in ipath_ibcctrl, want that
 182          * to stay a NOP. Flag that we are disabled, for the (unlikely)
 183          * case that some recovery path is trying to bring the link up
 184          * before we are ready.
 185          */
 186         ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
 187                 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
 188         dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
 189         ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
 190                    (unsigned long long) ibc);
 191         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
 192
 193         // be sure chip saw it
 194         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 195
 196         ret = dd->ipath_f_bringup_serdes(dd);
 197
 198         if (ret)
 199                 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
 200                          "not usable\n");
 201         else {
 202                 /* enable IBC */
 203                 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
 204                 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 205                                  dd->ipath_control);
 206         }
 207
 208         return ret;
 209 }
 210
 211 static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd)
 212 {
 213         struct ipath_portdata *pd = NULL;
 214
 215         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 216         if (pd) {
 217                 pd->port_dd = dd;
 218                 pd->port_cnt = 1;
 219                 /* The port 0 pkey table is used by the layer interface. */
 220                 pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY;
 221                 pd->port_seq_cnt = 1;
 222         }
 223         return pd;
 224 }
 225
 226 static int init_chip_first(struct ipath_devdata *dd)
 227 {
 228         struct ipath_portdata *pd;
 229         int ret = 0;
 230         u64 val;
 231
 232         spin_lock_init(&dd->ipath_kernel_tid_lock);
 233         spin_lock_init(&dd->ipath_user_tid_lock);
 234         spin_lock_init(&dd->ipath_sendctrl_lock);
 235         spin_lock_init(&dd->ipath_uctxt_lock);
 236         spin_lock_init(&dd->ipath_sdma_lock);
 237         spin_lock_init(&dd->ipath_gpio_lock);
 238         spin_lock_init(&dd->ipath_eep_st_lock);
 239         spin_lock_init(&dd->ipath_sdepb_lock);
 240         mutex_init(&dd->ipath_eep_lock);
 241
 242         /*
 243          * skip cfgports stuff because we are not allocating memory,
 244          * and we don't want problems if the portcnt changed due to
 245          * cfgports.  We do still check and report a difference, if
 246          * not same (should be impossible).
 247          */
 248         dd->ipath_f_config_ports(dd, ipath_cfgports);
 249         if (!ipath_cfgports)
 250                 dd->ipath_cfgports = dd->ipath_portcnt;
 251         else if (ipath_cfgports <= dd->ipath_portcnt) {
 252                 dd->ipath_cfgports = ipath_cfgports;
 253                 ipath_dbg("Configured to use %u ports out of %u in chip\n",
 254                           dd->ipath_cfgports, ipath_read_kreg32(dd,
 255                           dd->ipath_kregs->kr_portcnt));
 256         } else {
 257                 dd->ipath_cfgports = dd->ipath_portcnt;
 258                 ipath_dbg("Tried to configured to use %u ports; chip "
 259                           "only supports %u\n", ipath_cfgports,
 260                           ipath_read_kreg32(dd,
 261                                   dd->ipath_kregs->kr_portcnt));
 262         }
 263         /*
 264          * Allocate full portcnt array, rather than just cfgports, because
 265          * cleanup iterates across all possible ports.
 266          */
 267         dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt,
 268                                GFP_KERNEL);
 269
 270         if (!dd->ipath_pd) {
 271                 ipath_dev_err(dd, "Unable to allocate portdata array, "
 272                               "failing\n");
 273                 ret = -ENOMEM;
 274                 goto done;
 275         }
 276
 277         pd = create_portdata0(dd);
 278         if (!pd) {
 279                 ipath_dev_err(dd, "Unable to allocate portdata for port "
 280                               "0, failing\n");
 281                 ret = -ENOMEM;
 282                 goto done;
 283         }
 284         dd->ipath_pd[0] = pd;
 285
 286         dd->ipath_rcvtidcnt =
 287                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 288         dd->ipath_rcvtidbase =
 289                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 290         dd->ipath_rcvegrcnt =
 291                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 292         dd->ipath_rcvegrbase =
 293                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 294         dd->ipath_palign =
 295                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
 296         dd->ipath_piobufbase =
 297                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
 298         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
 299         dd->ipath_piosize2k = val & ~0U;
 300         dd->ipath_piosize4k = val >> 32;
 301         if (dd->ipath_piosize4k == 0 && ipath_mtu4096)
 302                 ipath_mtu4096 = 0; /* 4KB not supported by this chip */
 303         dd->ipath_ibmtu = ipath_mtu4096 ? 4096 : 2048;
 304         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
 305         dd->ipath_piobcnt2k = val & ~0U;
 306         dd->ipath_piobcnt4k = val >> 32;
 307         dd->ipath_pio2kbase =
 308                 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
 309                                  (dd->ipath_piobufbase & 0xffffffff));
 310         if (dd->ipath_piobcnt4k) {
 311                 dd->ipath_pio4kbase = (u32 __iomem *)
 312                         (((char __iomem *) dd->ipath_kregbase) +
 313                          (dd->ipath_piobufbase >> 32));
 314                 /*
 315                  * 4K buffers take 2 pages; we use roundup just to be
 316                  * paranoid; we calculate it once here, rather than on
 317                  * ever buf allocate
 318                  */
 319                 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
 320                                           dd->ipath_palign);
 321                 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
 322                           "(%x aligned)\n",
 323                           dd->ipath_piobcnt2k, dd->ipath_piosize2k,
 324                           dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
 325                           dd->ipath_piosize4k, dd->ipath_pio4kbase,
 326                           dd->ipath_4kalign);
 327         }
 328         else ipath_dbg("%u 2k piobufs @ %p\n",
 329                        dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
 330
 331 done:
 332         return ret;
 333 }
 334
 335 /**
 336  * init_chip_reset - re-initialize after a reset, or enable
 337  * @dd: the infinipath device
 338  *
 339  * sanity check at least some of the values after reset, and
 340  * ensure no receive or transmit (explicitly, in case reset
 341  * failed
 342  */
 343 static int init_chip_reset(struct ipath_devdata *dd)
 344 {
 345         u32 rtmp;
 346         int i;
 347         unsigned long flags;
 348
 349         /*
 350          * ensure chip does no sends or receives, tail updates, or
 351          * pioavail updates while we re-initialize
 352          */
 353         dd->ipath_rcvctrl &= ~(1ULL << dd->ipath_r_tailupd_shift);
 354         for (i = 0; i < dd->ipath_portcnt; i++) {
 355                 clear_bit(dd->ipath_r_portenable_shift + i,
 356                           &dd->ipath_rcvctrl);
 357                 clear_bit(dd->ipath_r_intravail_shift + i,
 358                           &dd->ipath_rcvctrl);
 359         }
 360         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 361                 dd->ipath_rcvctrl);
 362
 363         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 364         dd->ipath_sendctrl = 0U; /* no sdma, etc */
 365         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 366         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 367         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 368
 369         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
 370
 371         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 372         if (rtmp != dd->ipath_rcvtidcnt)
 373                 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
 374                          "reset, now %u, using original\n",
 375                          dd->ipath_rcvtidcnt, rtmp);
 376         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 377         if (rtmp != dd->ipath_rcvtidbase)
 378                 dev_info(&dd->pcidev->dev, "tidbase was %u before "
 379                          "reset, now %u, using original\n",
 380                          dd->ipath_rcvtidbase, rtmp);
 381         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 382         if (rtmp != dd->ipath_rcvegrcnt)
 383                 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
 384                          "reset, now %u, using original\n",
 385                          dd->ipath_rcvegrcnt, rtmp);
 386         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 387         if (rtmp != dd->ipath_rcvegrbase)
 388                 dev_info(&dd->pcidev->dev, "egrbase was %u before "
 389                          "reset, now %u, using original\n",
 390                          dd->ipath_rcvegrbase, rtmp);
 391
 392         return 0;
 393 }
 394
 395 static int init_pioavailregs(struct ipath_devdata *dd)
 396 {
 397         int ret;
 398
 399         dd->ipath_pioavailregs_dma = dma_alloc_coherent(
 400                 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
 401                 GFP_KERNEL);
 402         if (!dd->ipath_pioavailregs_dma) {
 403                 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
 404                               "in memory\n");
 405                 ret = -ENOMEM;
 406                 goto done;
 407         }
 408
 409         /*
 410          * we really want L2 cache aligned, but for current CPUs of
 411          * interest, they are the same.
 412          */
 413         dd->ipath_statusp = (u64 *)
 414                 ((char *)dd->ipath_pioavailregs_dma +
 415                  ((2 * L1_CACHE_BYTES +
 416                    dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
 417         /* copy the current value now that it's really allocated */
 418         *dd->ipath_statusp = dd->_ipath_status;
 419         /*
 420          * setup buffer to hold freeze msg, accessible to apps,
 421          * following statusp
 422          */
 423         dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
 424         /* and its length */
 425         dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
 426
 427         ret = 0;
 428
 429 done:
 430         return ret;
 431 }
 432
 433 /**
 434  * init_shadow_tids - allocate the shadow TID array
 435  * @dd: the infinipath device
 436  *
 437  * allocate the shadow TID array, so we can ipath_munlock previous
 438  * entries.  It may make more sense to move the pageshadow to the
 439  * port data structure, so we only allocate memory for ports actually
 440  * in use, since we at 8k per port, now.
 441  */
 442 static void init_shadow_tids(struct ipath_devdata *dd)
 443 {
 444         struct page **pages;
 445         dma_addr_t *addrs;
 446
 447         pages = vzalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 448                         sizeof(struct page *));
 449         if (!pages) {
 450                 ipath_dev_err(dd, "failed to allocate shadow page * "
 451                               "array, no expected sends!\n");
 452                 dd->ipath_pageshadow = NULL;
 453                 return;
 454         }
 455
 456         addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 457                         sizeof(dma_addr_t));
 458         if (!addrs) {
 459                 ipath_dev_err(dd, "failed to allocate shadow dma handle "
 460                               "array, no expected sends!\n");
 461                 vfree(pages);
 462                 dd->ipath_pageshadow = NULL;
 463                 return;
 464         }
 465
 466         dd->ipath_pageshadow = pages;
 467         dd->ipath_physshadow = addrs;
 468 }
 469
 470 static void enable_chip(struct ipath_devdata *dd, int reinit)
 471 {
 472         u32 val;
 473         u64 rcvmask;
 474         unsigned long flags;
 475         int i;
 476
 477         if (!reinit)
 478                 init_waitqueue_head(&ipath_state_wait);
 479
 480         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 481                          dd->ipath_rcvctrl);
 482
 483         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 484         /* Enable PIO send, and update of PIOavail regs to memory. */
 485         dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
 486                 INFINIPATH_S_PIOBUFAVAILUPD;
 487
 488         /*
 489          * Set the PIO avail update threshold to host memory
 490          * on chips that support it.
 491          */
 492         if (dd->ipath_pioupd_thresh)
 493                 dd->ipath_sendctrl |= dd->ipath_pioupd_thresh
 494                         << INFINIPATH_S_UPDTHRESH_SHIFT;
 495         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 496         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 497         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 498
 499         /*
 500          * Enable kernel ports' receive and receive interrupt.
 501          * Other ports done as user opens and inits them.
 502          */
 503         rcvmask = 1ULL;
 504         dd->ipath_rcvctrl |= (rcvmask << dd->ipath_r_portenable_shift) |
 505                 (rcvmask << dd->ipath_r_intravail_shift);
 506         if (!(dd->ipath_flags & IPATH_NODMA_RTAIL))
 507                 dd->ipath_rcvctrl |= (1ULL << dd->ipath_r_tailupd_shift);
 508
 509         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 510                          dd->ipath_rcvctrl);
 511
 512         /*
 513          * now ready for use.  this should be cleared whenever we
 514          * detect a reset, or initiate one.
 515          */
 516         dd->ipath_flags |= IPATH_INITTED;
 517
 518         /*
 519          * Init our shadow copies of head from tail values,
 520          * and write head values to match.
 521          */
 522         val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
 523         ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
 524
 525         /* Initialize so we interrupt on next packet received */
 526         ipath_write_ureg(dd, ur_rcvhdrhead,
 527                          dd->ipath_rhdrhead_intr_off |
 528                          dd->ipath_pd[0]->port_head, 0);
 529
 530         /*
 531          * by now pioavail updates to memory should have occurred, so
 532          * copy them into our working/shadow registers; this is in
 533          * case something went wrong with abort, but mostly to get the
 534          * initial values of the generation bit correct.
 535          */
 536         for (i = 0; i < dd->ipath_pioavregs; i++) {
 537                 __le64 pioavail;
 538
 539                 /*
 540                  * Chip Errata bug 6641; even and odd qwords>3 are swapped.
 541                  */
 542                 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
 543                         pioavail = dd->ipath_pioavailregs_dma[i ^ 1];
 544                 else
 545                         pioavail = dd->ipath_pioavailregs_dma[i];
 546                 /*
 547                  * don't need to worry about ipath_pioavailkernel here
 548                  * because we will call ipath_chg_pioavailkernel() later
 549                  * in initialization, to busy out buffers as needed
 550                  */
 551                 dd->ipath_pioavailshadow[i] = le64_to_cpu(pioavail);
 552         }
 553         /* can get counters, stats, etc. */
 554         dd->ipath_flags |= IPATH_PRESENT;
 555 }
 556
 557 static int init_housekeeping(struct ipath_devdata *dd, int reinit)
 558 {
 559         char boardn[40];
 560         int ret = 0;
 561
 562         /*
 563          * have to clear shadow copies of registers at init that are
 564          * not otherwise set here, or all kinds of bizarre things
 565          * happen with driver on chip reset
 566          */
 567         dd->ipath_rcvhdrsize = 0;
 568
 569         /*
 570          * Don't clear ipath_flags as 8bit mode was set before
 571          * entering this func. However, we do set the linkstate to
 572          * unknown, so we can watch for a transition.
 573          * PRESENT is set because we want register reads to work,
 574          * and the kernel infrastructure saw it in config space;
 575          * We clear it if we have failures.
 576          */
 577         dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
 578         dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
 579                              IPATH_LINKDOWN | IPATH_LINKINIT);
 580
 581         ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
 582         dd->ipath_revision =
 583                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
 584
 585         /*
 586          * set up fundamental info we need to use the chip; we assume
 587          * if the revision reg and these regs are OK, we don't need to
 588          * special case the rest
 589          */
 590         dd->ipath_sregbase =
 591                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
 592         dd->ipath_cregbase =
 593                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
 594         dd->ipath_uregbase =
 595                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
 596         ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
 597                    "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
 598                    dd->ipath_uregbase, dd->ipath_cregbase);
 599         if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
 600             || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
 601             || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
 602             || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
 603                 ipath_dev_err(dd, "Register read failures from chip, "
 604                               "giving up initialization\n");
 605                 dd->ipath_flags &= ~IPATH_PRESENT;
 606                 ret = -ENODEV;
 607                 goto done;
 608         }
 609
 610
 611         /* clear diagctrl register, in case diags were running and crashed */
 612         ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0);
 613
 614         /* clear the initial reset flag, in case first driver load */
 615         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
 616                          INFINIPATH_E_RESET);
 617
 618         ipath_cdbg(VERBOSE, "Revision %llx (PCI %x)\n",
 619                    (unsigned long long) dd->ipath_revision,
 620                    dd->ipath_pcirev);
 621
 622         if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
 623              INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
 624                 ipath_dev_err(dd, "Driver only handles version %d, "
 625                               "chip swversion is %d (%llx), failng\n",
 626                               IPATH_CHIP_SWVERSION,
 627                               (int)(dd->ipath_revision >>
 628                                     INFINIPATH_R_SOFTWARE_SHIFT) &
 629                               INFINIPATH_R_SOFTWARE_MASK,
 630                               (unsigned long long) dd->ipath_revision);
 631                 ret = -ENOSYS;
 632                 goto done;
 633         }
 634         dd->ipath_majrev = (u8) ((dd->ipath_revision >>
 635                                   INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
 636                                  INFINIPATH_R_CHIPREVMAJOR_MASK);
 637         dd->ipath_minrev = (u8) ((dd->ipath_revision >>
 638                                   INFINIPATH_R_CHIPREVMINOR_SHIFT) &
 639                                  INFINIPATH_R_CHIPREVMINOR_MASK);
 640         dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
 641                                     INFINIPATH_R_BOARDID_SHIFT) &
 642                                    INFINIPATH_R_BOARDID_MASK);
 643
 644         ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
 645
 646         snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
 647                  "ChipABI %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
 648                  "SW Compat %u\n",
 649                  IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
 650                  (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
 651                  INFINIPATH_R_ARCH_MASK,
 652                  dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
 653                  (unsigned)(dd->ipath_revision >>
 654                             INFINIPATH_R_SOFTWARE_SHIFT) &
 655                  INFINIPATH_R_SOFTWARE_MASK);
 656
 657         ipath_dbg("%s", dd->ipath_boardversion);
 658
 659         if (ret)
 660                 goto done;
 661
 662         if (reinit)
 663                 ret = init_chip_reset(dd);
 664         else
 665                 ret = init_chip_first(dd);
 666
 667 done:
 668         return ret;
 669 }
 670
 671 static void verify_interrupt(unsigned long opaque)
 672 {
 673         struct ipath_devdata *dd = (struct ipath_devdata *) opaque;
 674
 675         if (!dd)
 676                 return; /* being torn down */
 677
 678         /*
 679          * If we don't have any interrupts, let the user know and
 680          * don't bother checking again.
 681          */
 682         if (dd->ipath_int_counter == 0) {
 683                 if (!dd->ipath_f_intr_fallback(dd))
 684                         dev_err(&dd->pcidev->dev, "No interrupts detected, "
 685                                 "not usable.\n");
 686                 else /* re-arm the timer to see if fallback works */
 687                         mod_timer(&dd->ipath_intrchk_timer, jiffies + HZ/2);
 688         } else
 689                 ipath_cdbg(VERBOSE, "%u interrupts at timer check\n",
 690                         dd->ipath_int_counter);
 691 }
 692
 693 /**
 694  * ipath_init_chip - do the actual initialization sequence on the chip
 695  * @dd: the infinipath device
 696  * @reinit: reinitializing, so don't allocate new memory
 697  *
 698  * Do the actual initialization sequence on the chip.  This is done
 699  * both from the init routine called from the PCI infrastructure, and
 700  * when we reset the chip, or detect that it was reset internally,
 701  * or it's administratively re-enabled.
 702  *
 703  * Memory allocation here and in called routines is only done in
 704  * the first case (reinit == 0).  We have to be careful, because even
 705  * without memory allocation, we need to re-write all the chip registers
 706  * TIDs, etc. after the reset or enable has completed.
 707  */
 708 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
 709 {
 710         int ret = 0;
 711         u32 kpiobufs, defkbufs;
 712         u32 piobufs, uports;
 713         u64 val;
 714         struct ipath_portdata *pd;
 715         gfp_t gfp_flags = GFP_USER | __GFP_COMP;
 716
 717         ret = init_housekeeping(dd, reinit);
 718         if (ret)
 719                 goto done;
 720
 721         /*
 722          * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
 723          * but then it no longer nicely fits power of two, and since
 724          * we now use routines that backend onto __get_free_pages, the
 725          * rest would be wasted.
 726          */
 727         dd->ipath_rcvhdrcnt = max(dd->ipath_p0_rcvegrcnt, dd->ipath_rcvegrcnt);
 728         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
 729                          dd->ipath_rcvhdrcnt);
 730
 731         /*
 732          * Set up the shadow copies of the piobufavail registers,
 733          * which we compare against the chip registers for now, and
 734          * the in memory DMA'ed copies of the registers.  This has to
 735          * be done early, before we calculate lastport, etc.
 736          */
 737         piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
 738         /*
 739          * calc number of pioavail registers, and save it; we have 2
 740          * bits per buffer.
 741          */
 742         dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2)
 743                 / (sizeof(u64) * BITS_PER_BYTE / 2);
 744         uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0;
 745         if (piobufs > 144)
 746                 defkbufs = 32 + dd->ipath_pioreserved;
 747         else
 748                 defkbufs = 16 + dd->ipath_pioreserved;
 749
 750         if (ipath_kpiobufs && (ipath_kpiobufs +
 751                 (uports * IPATH_MIN_USER_PORT_BUFCNT)) > piobufs) {
 752                 int i = (int) piobufs -
 753                         (int) (uports * IPATH_MIN_USER_PORT_BUFCNT);
 754                 if (i < 1)
 755                         i = 1;
 756                 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of "
 757                          "%d for kernel leaves too few for %d user ports "
 758                          "(%d each); using %u\n", ipath_kpiobufs,
 759                          piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i);
 760                 /*
 761                  * shouldn't change ipath_kpiobufs, because could be
 762                  * different for different devices...
 763                  */
 764                 kpiobufs = i;
 765         } else if (ipath_kpiobufs)
 766                 kpiobufs = ipath_kpiobufs;
 767         else
 768                 kpiobufs = defkbufs;
 769         dd->ipath_lastport_piobuf = piobufs - kpiobufs;
 770         dd->ipath_pbufsport =
 771                 uports ? dd->ipath_lastport_piobuf / uports : 0;
 772         /* if not an even divisor, some user ports get extra buffers */
 773         dd->ipath_ports_extrabuf = dd->ipath_lastport_piobuf -
 774                 (dd->ipath_pbufsport * uports);
 775         if (dd->ipath_ports_extrabuf)
 776                 ipath_dbg("%u pbufs/port leaves some unused, add 1 buffer to "
 777                         "ports <= %u\n", dd->ipath_pbufsport,
 778                         dd->ipath_ports_extrabuf);
 779         dd->ipath_lastpioindex = 0;
 780         dd->ipath_lastpioindexl = dd->ipath_piobcnt2k;
 781         /* ipath_pioavailshadow initialized earlier */
 782         ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
 783                    "each for %u user ports\n", kpiobufs,
 784                    piobufs, dd->ipath_pbufsport, uports);
 785         ret = dd->ipath_f_early_init(dd);
 786         if (ret) {
 787                 ipath_dev_err(dd, "Early initialization failure\n");
 788                 goto done;
 789         }
 790
 791         /*
 792          * Early_init sets rcvhdrentsize and rcvhdrsize, so this must be
 793          * done after early_init.
 794          */
 795         dd->ipath_hdrqlast =
 796                 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
 797         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
 798                          dd->ipath_rcvhdrentsize);
 799         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
 800                          dd->ipath_rcvhdrsize);
 801
 802         if (!reinit) {
 803                 ret = init_pioavailregs(dd);
 804                 init_shadow_tids(dd);
 805                 if (ret)
 806                         goto done;
 807         }
 808
 809         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
 810                          dd->ipath_pioavailregs_phys);
 811
 812         /*
 813          * this is to detect s/w errors, which the h/w works around by
 814          * ignoring the low 6 bits of address, if it wasn't aligned.
 815          */
 816         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
 817         if (val != dd->ipath_pioavailregs_phys) {
 818                 ipath_dev_err(dd, "Catastrophic software error, "
 819                               "SendPIOAvailAddr written as %lx, "
 820                               "read back as %llx\n",
 821                               (unsigned long) dd->ipath_pioavailregs_phys,
 822                               (unsigned long long) val);
 823                 ret = -EINVAL;
 824                 goto done;
 825         }
 826
 827         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
 828
 829         /*
 830          * make sure we are not in freeze, and PIO send enabled, so
 831          * writes to pbc happen
 832          */
 833         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
 834         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 835                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 836         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
 837
 838         /*
 839          * before error clears, since we expect serdes pll errors during
 840          * this, the first time after reset
 841          */
 842         if (bringup_link(dd)) {
 843                 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
 844                 ret = -ENETDOWN;
 845                 goto done;
 846         }
 847
 848         /*
 849          * clear any "expected" hwerrs from reset and/or initialization
 850          * clear any that aren't enabled (at least this once), and then
 851          * set the enable mask
 852          */
 853         dd->ipath_f_init_hwerrors(dd);
 854         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 855                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 856         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 857                          dd->ipath_hwerrmask);
 858
 859         /* clear all */
 860         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
 861         /* enable errors that are masked, at least this first time. */
 862         ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
 863                          ~dd->ipath_maskederrs);
 864         dd->ipath_maskederrs = 0; /* don't re-enable ignored in timer */
 865         dd->ipath_errormask =
 866                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_errormask);
 867         /* clear any interrupts up to this point (ints still not enabled) */
 868         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
 869
 870         dd->ipath_f_tidtemplate(dd);
 871
 872         /*
 873          * Set up the port 0 (kernel) rcvhdr q and egr TIDs.  If doing
 874          * re-init, the simplest way to handle this is to free
 875          * existing, and re-allocate.
 876          * Need to re-create rest of port 0 portdata as well.
 877          */
 878         pd = dd->ipath_pd[0];
 879         if (reinit) {
 880                 struct ipath_portdata *npd;
 881
 882                 /*
 883                  * Alloc and init new ipath_portdata for port0,
 884                  * Then free old pd. Could lead to fragmentation, but also
 885                  * makes later support for hot-swap easier.
 886                  */
 887                 npd = create_portdata0(dd);
 888                 if (npd) {
 889                         ipath_free_pddata(dd, pd);
 890                         dd->ipath_pd[0] = npd;
 891                         pd = npd;
 892                 } else {
 893                         ipath_dev_err(dd, "Unable to allocate portdata"
 894                                       " for port 0, failing\n");
 895                         ret = -ENOMEM;
 896                         goto done;
 897                 }
 898         }
 899         ret = ipath_create_rcvhdrq(dd, pd);
 900         if (!ret)
 901                 ret = create_port0_egr(dd);
 902         if (ret) {
 903                 ipath_dev_err(dd, "failed to allocate kernel port's "
 904                               "rcvhdrq and/or egr bufs\n");
 905                 goto done;
 906         }
 907         else
 908                 enable_chip(dd, reinit);
 909
 910         /* after enable_chip, so pioavailshadow setup */
 911         ipath_chg_pioavailkernel(dd, 0, piobufs, 1);
 912
 913         /*
 914          * Cancel any possible active sends from early driver load.
 915          * Follows early_init because some chips have to initialize
 916          * PIO buffers in early_init to avoid false parity errors.
 917          * After enable and ipath_chg_pioavailkernel so we can safely
 918          * enable pioavail updates and PIOENABLE; packets are now
 919          * ready to go out.
 920          */
 921         ipath_cancel_sends(dd, 1);
 922
 923         if (!reinit) {
 924                 /*
 925                  * Used when we close a port, for DMA already in flight
 926                  * at close.
 927                  */
 928                 dd->ipath_dummy_hdrq = dma_alloc_coherent(
 929                         &dd->pcidev->dev, dd->ipath_pd[0]->port_rcvhdrq_size,
 930                         &dd->ipath_dummy_hdrq_phys,
 931                         gfp_flags);
 932                 if (!dd->ipath_dummy_hdrq) {
 933                         dev_info(&dd->pcidev->dev,
 934                                 "Couldn't allocate 0x%lx bytes for dummy hdrq\n",
 935                                 dd->ipath_pd[0]->port_rcvhdrq_size);
 936                         /* fallback to just 0'ing */
 937                         dd->ipath_dummy_hdrq_phys = 0UL;
 938                 }
 939         }
 940
 941         /*
 942          * cause retrigger of pending interrupts ignored during init,
 943          * even if we had errors
 944          */
 945         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
 946
 947         if (!dd->ipath_stats_timer_active) {
 948                 /*
 949                  * first init, or after an admin disable/enable
 950                  * set up stats retrieval timer, even if we had errors
 951                  * in last portion of setup
 952                  */
 953                 init_timer(&dd->ipath_stats_timer);
 954                 dd->ipath_stats_timer.function = ipath_get_faststats;
 955                 dd->ipath_stats_timer.data = (unsigned long) dd;
 956                 /* every 5 seconds; */
 957                 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
 958                 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
 959                 add_timer(&dd->ipath_stats_timer);
 960                 dd->ipath_stats_timer_active = 1;
 961         }
 962
 963         /* Set up SendDMA if chip supports it */
 964         if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
 965                 ret = setup_sdma(dd);
 966
 967         /* Set up HoL state */
 968         init_timer(&dd->ipath_hol_timer);
 969         dd->ipath_hol_timer.function = ipath_hol_event;
 970         dd->ipath_hol_timer.data = (unsigned long)dd;
 971         dd->ipath_hol_state = IPATH_HOL_UP;
 972
 973 done:
 974         if (!ret) {
 975                 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
 976                 if (!dd->ipath_f_intrsetup(dd)) {
 977                         /* now we can enable all interrupts from the chip */
 978                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
 979                                          -1LL);
 980                         /* force re-interrupt of any pending interrupts. */
 981                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
 982                                          0ULL);
 983                         /* chip is usable; mark it as initialized */
 984                         *dd->ipath_statusp |= IPATH_STATUS_INITTED;
 985
 986                         /*
 987                          * setup to verify we get an interrupt, and fallback
 988                          * to an alternate if necessary and possible
 989                          */
 990                         if (!reinit) {
 991                                 init_timer(&dd->ipath_intrchk_timer);
 992                                 dd->ipath_intrchk_timer.function =
 993                                         verify_interrupt;
 994                                 dd->ipath_intrchk_timer.data =
 995                                         (unsigned long) dd;
 996                         }
 997                         dd->ipath_intrchk_timer.expires = jiffies + HZ/2;
 998                         add_timer(&dd->ipath_intrchk_timer);
 999                 } else
1000                         ipath_dev_err(dd, "No interrupts enabled, couldn't "
1001                                       "setup interrupt address\n");
1002
1003                 if (dd->ipath_cfgports > ipath_stats.sps_nports)
1004                         /*
1005                          * sps_nports is a global, so, we set it to
1006                          * the highest number of ports of any of the
1007                          * chips we find; we never decrement it, at
1008                          * least for now.  Since this might have changed
1009                          * over disable/enable or prior to reset, always
1010                          * do the check and potentially adjust.
1011                          */
1012                         ipath_stats.sps_nports = dd->ipath_cfgports;
1013         } else
1014                 ipath_dbg("Failed (%d) to initialize chip\n", ret);
1015
1016         /* if ret is non-zero, we probably should do some cleanup
1017            here... */
1018         return ret;
1019 }
1020
1021 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
1022 {
1023         struct ipath_devdata *dd;
1024         unsigned long flags;
1025         unsigned short val;
1026         int ret;
1027
1028         ret = ipath_parse_ushort(str, &val);
1029
1030         spin_lock_irqsave(&ipath_devs_lock, flags);
1031
1032         if (ret < 0)
1033                 goto bail;
1034
1035         if (val == 0) {
1036                 ret = -EINVAL;
1037                 goto bail;
1038         }
1039
1040         list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
1041                 if (dd->ipath_kregbase)
1042                         continue;
1043                 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
1044                            (dd->ipath_cfgports *
1045                             IPATH_MIN_USER_PORT_BUFCNT)))
1046                 {
1047                         ipath_dev_err(
1048                                 dd,
1049                                 "Allocating %d PIO bufs for kernel leaves "
1050                                 "too few for %d user ports (%d each)\n",
1051                                 val, dd->ipath_cfgports - 1,
1052                                 IPATH_MIN_USER_PORT_BUFCNT);
1053                         ret = -EINVAL;
1054                         goto bail;
1055                 }
1056                 dd->ipath_lastport_piobuf =
1057                         dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
1058         }
1059
1060         ipath_kpiobufs = val;
1061         ret = 0;
1062 bail:
1063         spin_unlock_irqrestore(&ipath_devs_lock, flags);
1064
1065         return ret;
1066 }