kernel/drivers/infiniband/hw/cxgb4/qp.c

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34
  35 #include "iw_cxgb4.h"
  36
  37 static int db_delay_usecs = 1;
  38 module_param(db_delay_usecs, int, 0644);
  39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
  40
  41 static int ocqp_support = 1;
  42 module_param(ocqp_support, int, 0644);
  43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
  44
  45 int db_fc_threshold = 1000;
  46 module_param(db_fc_threshold, int, 0644);
  47 MODULE_PARM_DESC(db_fc_threshold,
  48                  "QP count/threshold that triggers"
  49                  " automatic db flow control mode (default = 1000)");
  50
  51 int db_coalescing_threshold;
  52 module_param(db_coalescing_threshold, int, 0644);
  53 MODULE_PARM_DESC(db_coalescing_threshold,
  54                  "QP count/threshold that triggers"
  55                  " disabling db coalescing (default = 0)");
  56
  57 static int max_fr_immd = T4_MAX_FR_IMMD;
  58 module_param(max_fr_immd, int, 0644);
  59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
  60
  61 static int alloc_ird(struct c4iw_dev *dev, u32 ird)
  62 {
  63         int ret = 0;
  64
  65         spin_lock_irq(&dev->lock);
  66         if (ird <= dev->avail_ird)
  67                 dev->avail_ird -= ird;
  68         else
  69                 ret = -ENOMEM;
  70         spin_unlock_irq(&dev->lock);
  71
  72         if (ret)
  73                 dev_warn(&dev->rdev.lldi.pdev->dev,
  74                          "device IRD resources exhausted\n");
  75
  76         return ret;
  77 }
  78
  79 static void free_ird(struct c4iw_dev *dev, int ird)
  80 {
  81         spin_lock_irq(&dev->lock);
  82         dev->avail_ird += ird;
  83         spin_unlock_irq(&dev->lock);
  84 }
  85
  86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
  87 {
  88         unsigned long flag;
  89         spin_lock_irqsave(&qhp->lock, flag);
  90         qhp->attr.state = state;
  91         spin_unlock_irqrestore(&qhp->lock, flag);
  92 }
  93
  94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  95 {
  96         c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
  97 }
  98
  99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 100 {
 101         dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
 102                           pci_unmap_addr(sq, mapping));
 103 }
 104
 105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 106 {
 107         if (t4_sq_onchip(sq))
 108                 dealloc_oc_sq(rdev, sq);
 109         else
 110                 dealloc_host_sq(rdev, sq);
 111 }
 112
 113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 114 {
 115         if (!ocqp_support || !ocqp_supported(&rdev->lldi))
 116                 return -ENOSYS;
 117         sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
 118         if (!sq->dma_addr)
 119                 return -ENOMEM;
 120         sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
 121                         rdev->lldi.vr->ocq.start;
 122         sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
 123                                             rdev->lldi.vr->ocq.start);
 124         sq->flags |= T4_SQ_ONCHIP;
 125         return 0;
 126 }
 127
 128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 129 {
 130         sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
 131                                        &(sq->dma_addr), GFP_KERNEL);
 132         if (!sq->queue)
 133                 return -ENOMEM;
 134         sq->phys_addr = virt_to_phys(sq->queue);
 135         pci_unmap_addr_set(sq, mapping, sq->dma_addr);
 136         return 0;
 137 }
 138
 139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
 140 {
 141         int ret = -ENOSYS;
 142         if (user)
 143                 ret = alloc_oc_sq(rdev, sq);
 144         if (ret)
 145                 ret = alloc_host_sq(rdev, sq);
 146         return ret;
 147 }
 148
 149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 150                       struct c4iw_dev_ucontext *uctx)
 151 {
 152         /*
 153          * uP clears EQ contexts when the connection exits rdma mode,
 154          * so no need to post a RESET WR for these EQs.
 155          */
 156         dma_free_coherent(&(rdev->lldi.pdev->dev),
 157                           wq->rq.memsize, wq->rq.queue,
 158                           dma_unmap_addr(&wq->rq, mapping));
 159         dealloc_sq(rdev, &wq->sq);
 160         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 161         kfree(wq->rq.sw_rq);
 162         kfree(wq->sq.sw_sq);
 163         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 164         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 165         return 0;
 166 }
 167
 168 /*
 169  * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL,
 170  * then this is a user mapping so compute the page-aligned physical address
 171  * for mapping.
 172  */
 173 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
 174                               enum cxgb4_bar2_qtype qtype,
 175                               unsigned int *pbar2_qid, u64 *pbar2_pa)
 176 {
 177         u64 bar2_qoffset;
 178         int ret;
 179
 180         ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype,
 181                                    pbar2_pa ? 1 : 0,
 182                                    &bar2_qoffset, pbar2_qid);
 183         if (ret)
 184                 return NULL;
 185
 186         if (pbar2_pa)
 187                 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK;
 188         return rdev->bar2_kva + bar2_qoffset;
 189 }
 190
 191 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 192                      struct t4_cq *rcq, struct t4_cq *scq,
 193                      struct c4iw_dev_ucontext *uctx)
 194 {
 195         int user = (uctx != &rdev->uctx);
 196         struct fw_ri_res_wr *res_wr;
 197         struct fw_ri_res *res;
 198         int wr_len;
 199         struct c4iw_wr_wait wr_wait;
 200         struct sk_buff *skb;
 201         int ret = 0;
 202         int eqsize;
 203
 204         wq->sq.qid = c4iw_get_qpid(rdev, uctx);
 205         if (!wq->sq.qid)
 206                 return -ENOMEM;
 207
 208         wq->rq.qid = c4iw_get_qpid(rdev, uctx);
 209         if (!wq->rq.qid) {
 210                 ret = -ENOMEM;
 211                 goto free_sq_qid;
 212         }
 213
 214         if (!user) {
 215                 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
 216                                  GFP_KERNEL);
 217                 if (!wq->sq.sw_sq) {
 218                         ret = -ENOMEM;
 219                         goto free_rq_qid;
 220                 }
 221
 222                 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
 223                                  GFP_KERNEL);
 224                 if (!wq->rq.sw_rq) {
 225                         ret = -ENOMEM;
 226                         goto free_sw_sq;
 227                 }
 228         }
 229
 230         /*
 231          * RQT must be a power of 2 and at least 16 deep.
 232          */
 233         wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16));
 234         wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
 235         if (!wq->rq.rqt_hwaddr) {
 236                 ret = -ENOMEM;
 237                 goto free_sw_rq;
 238         }
 239
 240         ret = alloc_sq(rdev, &wq->sq, user);
 241         if (ret)
 242                 goto free_hwaddr;
 243         memset(wq->sq.queue, 0, wq->sq.memsize);
 244         dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
 245
 246         wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
 247                                           wq->rq.memsize, &(wq->rq.dma_addr),
 248                                           GFP_KERNEL);
 249         if (!wq->rq.queue) {
 250                 ret = -ENOMEM;
 251                 goto free_sq;
 252         }
 253         PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
 254                 __func__, wq->sq.queue,
 255                 (unsigned long long)virt_to_phys(wq->sq.queue),
 256                 wq->rq.queue,
 257                 (unsigned long long)virt_to_phys(wq->rq.queue));
 258         memset(wq->rq.queue, 0, wq->rq.memsize);
 259         dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
 260
 261         wq->db = rdev->lldi.db_reg;
 262
 263         wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid, T4_BAR2_QTYPE_EGRESS,
 264                                          &wq->sq.bar2_qid,
 265                                          user ? &wq->sq.bar2_pa : NULL);
 266         wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid, T4_BAR2_QTYPE_EGRESS,
 267                                          &wq->rq.bar2_qid,
 268                                          user ? &wq->rq.bar2_pa : NULL);
 269
 270         /*
 271          * User mode must have bar2 access.
 272          */
 273         if (user && (!wq->sq.bar2_va || !wq->rq.bar2_va)) {
 274                 pr_warn(MOD "%s: sqid %u or rqid %u not in BAR2 range.\n",
 275                         pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid);
 276                 goto free_dma;
 277         }
 278
 279         wq->rdev = rdev;
 280         wq->rq.msn = 1;
 281
 282         /* build fw_ri_res_wr */
 283         wr_len = sizeof *res_wr + 2 * sizeof *res;
 284
 285         skb = alloc_skb(wr_len, GFP_KERNEL);
 286         if (!skb) {
 287                 ret = -ENOMEM;
 288                 goto free_dma;
 289         }
 290         set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
 291
 292         res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
 293         memset(res_wr, 0, wr_len);
 294         res_wr->op_nres = cpu_to_be32(
 295                         FW_WR_OP_V(FW_RI_RES_WR) |
 296                         FW_RI_RES_WR_NRES_V(2) |
 297                         FW_WR_COMPL_F);
 298         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
 299         res_wr->cookie = (uintptr_t)&wr_wait;
 300         res = res_wr->res;
 301         res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
 302         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 303
 304         /*
 305          * eqsize is the number of 64B entries plus the status page size.
 306          */
 307         eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
 308                 rdev->hw_queue.t4_eq_status_entries;
 309
 310         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 311                 FW_RI_RES_WR_HOSTFCMODE_V(0) |  /* no host cidx updates */
 312                 FW_RI_RES_WR_CPRIO_V(0) |       /* don't keep in chip cache */
 313                 FW_RI_RES_WR_PCIECHN_V(0) |     /* set by uP at ri_init time */
 314                 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) |
 315                 FW_RI_RES_WR_IQID_V(scq->cqid));
 316         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 317                 FW_RI_RES_WR_DCAEN_V(0) |
 318                 FW_RI_RES_WR_DCACPU_V(0) |
 319                 FW_RI_RES_WR_FBMIN_V(2) |
 320                 FW_RI_RES_WR_FBMAX_V(2) |
 321                 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
 322                 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
 323                 FW_RI_RES_WR_EQSIZE_V(eqsize));
 324         res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
 325         res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
 326         res++;
 327         res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
 328         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 329
 330         /*
 331          * eqsize is the number of 64B entries plus the status page size.
 332          */
 333         eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
 334                 rdev->hw_queue.t4_eq_status_entries;
 335         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 336                 FW_RI_RES_WR_HOSTFCMODE_V(0) |  /* no host cidx updates */
 337                 FW_RI_RES_WR_CPRIO_V(0) |       /* don't keep in chip cache */
 338                 FW_RI_RES_WR_PCIECHN_V(0) |     /* set by uP at ri_init time */
 339                 FW_RI_RES_WR_IQID_V(rcq->cqid));
 340         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 341                 FW_RI_RES_WR_DCAEN_V(0) |
 342                 FW_RI_RES_WR_DCACPU_V(0) |
 343                 FW_RI_RES_WR_FBMIN_V(2) |
 344                 FW_RI_RES_WR_FBMAX_V(2) |
 345                 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
 346                 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
 347                 FW_RI_RES_WR_EQSIZE_V(eqsize));
 348         res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
 349         res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
 350
 351         c4iw_init_wr_wait(&wr_wait);
 352
 353         ret = c4iw_ofld_send(rdev, skb);
 354         if (ret)
 355                 goto free_dma;
 356         ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
 357         if (ret)
 358                 goto free_dma;
 359
 360         PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n",
 361              __func__, wq->sq.qid, wq->rq.qid, wq->db,
 362              wq->sq.bar2_va, wq->rq.bar2_va);
 363
 364         return 0;
 365 free_dma:
 366         dma_free_coherent(&(rdev->lldi.pdev->dev),
 367                           wq->rq.memsize, wq->rq.queue,
 368                           dma_unmap_addr(&wq->rq, mapping));
 369 free_sq:
 370         dealloc_sq(rdev, &wq->sq);
 371 free_hwaddr:
 372         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 373 free_sw_rq:
 374         kfree(wq->rq.sw_rq);
 375 free_sw_sq:
 376         kfree(wq->sq.sw_sq);
 377 free_rq_qid:
 378         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 379 free_sq_qid:
 380         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 381         return ret;
 382 }
 383
 384 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
 385                       struct ib_send_wr *wr, int max, u32 *plenp)
 386 {
 387         u8 *dstp, *srcp;
 388         u32 plen = 0;
 389         int i;
 390         int rem, len;
 391
 392         dstp = (u8 *)immdp->data;
 393         for (i = 0; i < wr->num_sge; i++) {
 394                 if ((plen + wr->sg_list[i].length) > max)
 395                         return -EMSGSIZE;
 396                 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
 397                 plen += wr->sg_list[i].length;
 398                 rem = wr->sg_list[i].length;
 399                 while (rem) {
 400                         if (dstp == (u8 *)&sq->queue[sq->size])
 401                                 dstp = (u8 *)sq->queue;
 402                         if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
 403                                 len = rem;
 404                         else
 405                                 len = (u8 *)&sq->queue[sq->size] - dstp;
 406                         memcpy(dstp, srcp, len);
 407                         dstp += len;
 408                         srcp += len;
 409                         rem -= len;
 410                 }
 411         }
 412         len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
 413         if (len)
 414                 memset(dstp, 0, len);
 415         immdp->op = FW_RI_DATA_IMMD;
 416         immdp->r1 = 0;
 417         immdp->r2 = 0;
 418         immdp->immdlen = cpu_to_be32(plen);
 419         *plenp = plen;
 420         return 0;
 421 }
 422
 423 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
 424                       struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
 425                       int num_sge, u32 *plenp)
 426
 427 {
 428         int i;
 429         u32 plen = 0;
 430         __be64 *flitp = (__be64 *)isglp->sge;
 431
 432         for (i = 0; i < num_sge; i++) {
 433                 if ((plen + sg_list[i].length) < plen)
 434                         return -EMSGSIZE;
 435                 plen += sg_list[i].length;
 436                 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
 437                                      sg_list[i].length);
 438                 if (++flitp == queue_end)
 439                         flitp = queue_start;
 440                 *flitp = cpu_to_be64(sg_list[i].addr);
 441                 if (++flitp == queue_end)
 442                         flitp = queue_start;
 443         }
 444         *flitp = (__force __be64)0;
 445         isglp->op = FW_RI_DATA_ISGL;
 446         isglp->r1 = 0;
 447         isglp->nsge = cpu_to_be16(num_sge);
 448         isglp->r2 = 0;
 449         if (plenp)
 450                 *plenp = plen;
 451         return 0;
 452 }
 453
 454 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
 455                            struct ib_send_wr *wr, u8 *len16)
 456 {
 457         u32 plen;
 458         int size;
 459         int ret;
 460
 461         if (wr->num_sge > T4_MAX_SEND_SGE)
 462                 return -EINVAL;
 463         switch (wr->opcode) {
 464         case IB_WR_SEND:
 465                 if (wr->send_flags & IB_SEND_SOLICITED)
 466                         wqe->send.sendop_pkd = cpu_to_be32(
 467                                 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE));
 468                 else
 469                         wqe->send.sendop_pkd = cpu_to_be32(
 470                                 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND));
 471                 wqe->send.stag_inv = 0;
 472                 break;
 473         case IB_WR_SEND_WITH_INV:
 474                 if (wr->send_flags & IB_SEND_SOLICITED)
 475                         wqe->send.sendop_pkd = cpu_to_be32(
 476                                 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV));
 477                 else
 478                         wqe->send.sendop_pkd = cpu_to_be32(
 479                                 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV));
 480                 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 481                 break;
 482
 483         default:
 484                 return -EINVAL;
 485         }
 486         wqe->send.r3 = 0;
 487         wqe->send.r4 = 0;
 488
 489         plen = 0;
 490         if (wr->num_sge) {
 491                 if (wr->send_flags & IB_SEND_INLINE) {
 492                         ret = build_immd(sq, wqe->send.u.immd_src, wr,
 493                                          T4_MAX_SEND_INLINE, &plen);
 494                         if (ret)
 495                                 return ret;
 496                         size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
 497                                plen;
 498                 } else {
 499                         ret = build_isgl((__be64 *)sq->queue,
 500                                          (__be64 *)&sq->queue[sq->size],
 501                                          wqe->send.u.isgl_src,
 502                                          wr->sg_list, wr->num_sge, &plen);
 503                         if (ret)
 504                                 return ret;
 505                         size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
 506                                wr->num_sge * sizeof(struct fw_ri_sge);
 507                 }
 508         } else {
 509                 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
 510                 wqe->send.u.immd_src[0].r1 = 0;
 511                 wqe->send.u.immd_src[0].r2 = 0;
 512                 wqe->send.u.immd_src[0].immdlen = 0;
 513                 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
 514                 plen = 0;
 515         }
 516         *len16 = DIV_ROUND_UP(size, 16);
 517         wqe->send.plen = cpu_to_be32(plen);
 518         return 0;
 519 }
 520
 521 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
 522                             struct ib_send_wr *wr, u8 *len16)
 523 {
 524         u32 plen;
 525         int size;
 526         int ret;
 527
 528         if (wr->num_sge > T4_MAX_SEND_SGE)
 529                 return -EINVAL;
 530         wqe->write.r2 = 0;
 531         wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
 532         wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
 533         if (wr->num_sge) {
 534                 if (wr->send_flags & IB_SEND_INLINE) {
 535                         ret = build_immd(sq, wqe->write.u.immd_src, wr,
 536                                          T4_MAX_WRITE_INLINE, &plen);
 537                         if (ret)
 538                                 return ret;
 539                         size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
 540                                plen;
 541                 } else {
 542                         ret = build_isgl((__be64 *)sq->queue,
 543                                          (__be64 *)&sq->queue[sq->size],
 544                                          wqe->write.u.isgl_src,
 545                                          wr->sg_list, wr->num_sge, &plen);
 546                         if (ret)
 547                                 return ret;
 548                         size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
 549                                wr->num_sge * sizeof(struct fw_ri_sge);
 550                 }
 551         } else {
 552                 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
 553                 wqe->write.u.immd_src[0].r1 = 0;
 554                 wqe->write.u.immd_src[0].r2 = 0;
 555                 wqe->write.u.immd_src[0].immdlen = 0;
 556                 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
 557                 plen = 0;
 558         }
 559         *len16 = DIV_ROUND_UP(size, 16);
 560         wqe->write.plen = cpu_to_be32(plen);
 561         return 0;
 562 }
 563
 564 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
 565 {
 566         if (wr->num_sge > 1)
 567                 return -EINVAL;
 568         if (wr->num_sge) {
 569                 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey);
 570                 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr
 571                                                         >> 32));
 572                 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr);
 573                 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
 574                 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
 575                 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
 576                                                          >> 32));
 577                 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
 578         } else {
 579                 wqe->read.stag_src = cpu_to_be32(2);
 580                 wqe->read.to_src_hi = 0;
 581                 wqe->read.to_src_lo = 0;
 582                 wqe->read.stag_sink = cpu_to_be32(2);
 583                 wqe->read.plen = 0;
 584                 wqe->read.to_sink_hi = 0;
 585                 wqe->read.to_sink_lo = 0;
 586         }
 587         wqe->read.r2 = 0;
 588         wqe->read.r5 = 0;
 589         *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
 590         return 0;
 591 }
 592
 593 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
 594                            struct ib_recv_wr *wr, u8 *len16)
 595 {
 596         int ret;
 597
 598         ret = build_isgl((__be64 *)qhp->wq.rq.queue,
 599                          (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
 600                          &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
 601         if (ret)
 602                 return ret;
 603         *len16 = DIV_ROUND_UP(sizeof wqe->recv +
 604                               wr->num_sge * sizeof(struct fw_ri_sge), 16);
 605         return 0;
 606 }
 607
 608 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
 609                         struct ib_reg_wr *wr, u8 *len16, u8 t5dev)
 610 {
 611         struct c4iw_mr *mhp = to_c4iw_mr(wr->mr);
 612         struct fw_ri_immd *imdp;
 613         __be64 *p;
 614         int i;
 615         int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
 616         int rem;
 617
 618         if (mhp->mpl_len > t4_max_fr_depth(use_dsgl))
 619                 return -EINVAL;
 620
 621         wqe->fr.qpbinde_to_dcacpu = 0;
 622         wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12;
 623         wqe->fr.addr_type = FW_RI_VA_BASED_TO;
 624         wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access);
 625         wqe->fr.len_hi = 0;
 626         wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length);
 627         wqe->fr.stag = cpu_to_be32(wr->key);
 628         wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
 629         wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova &
 630                                         0xffffffff);
 631
 632         if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
 633                 struct fw_ri_dsgl *sglp;
 634
 635                 for (i = 0; i < mhp->mpl_len; i++)
 636                         mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]);
 637
 638                 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
 639                 sglp->op = FW_RI_DATA_DSGL;
 640                 sglp->r1 = 0;
 641                 sglp->nsge = cpu_to_be16(1);
 642                 sglp->addr0 = cpu_to_be64(mhp->mpl_addr);
 643                 sglp->len0 = cpu_to_be32(pbllen);
 644
 645                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
 646         } else {
 647                 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
 648                 imdp->op = FW_RI_DATA_IMMD;
 649                 imdp->r1 = 0;
 650                 imdp->r2 = 0;
 651                 imdp->immdlen = cpu_to_be32(pbllen);
 652                 p = (__be64 *)(imdp + 1);
 653                 rem = pbllen;
 654                 for (i = 0; i < mhp->mpl_len; i++) {
 655                         *p = cpu_to_be64((u64)mhp->mpl[i]);
 656                         rem -= sizeof(*p);
 657                         if (++p == (__be64 *)&sq->queue[sq->size])
 658                                 p = (__be64 *)sq->queue;
 659                 }
 660                 BUG_ON(rem < 0);
 661                 while (rem) {
 662                         *p = 0;
 663                         rem -= sizeof(*p);
 664                         if (++p == (__be64 *)&sq->queue[sq->size])
 665                                 p = (__be64 *)sq->queue;
 666                 }
 667                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
 668                                       + pbllen, 16);
 669         }
 670         return 0;
 671 }
 672
 673 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
 674                           u8 *len16)
 675 {
 676         wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 677         wqe->inv.r2 = 0;
 678         *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
 679         return 0;
 680 }
 681
 682 void c4iw_qp_add_ref(struct ib_qp *qp)
 683 {
 684         PDBG("%s ib_qp %p\n", __func__, qp);
 685         atomic_inc(&(to_c4iw_qp(qp)->refcnt));
 686 }
 687
 688 void c4iw_qp_rem_ref(struct ib_qp *qp)
 689 {
 690         PDBG("%s ib_qp %p\n", __func__, qp);
 691         if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
 692                 wake_up(&(to_c4iw_qp(qp)->wait));
 693 }
 694
 695 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
 696 {
 697         if (list_empty(entry))
 698                 list_add_tail(entry, head);
 699 }
 700
 701 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
 702 {
 703         unsigned long flags;
 704
 705         spin_lock_irqsave(&qhp->rhp->lock, flags);
 706         spin_lock(&qhp->lock);
 707         if (qhp->rhp->db_state == NORMAL)
 708                 t4_ring_sq_db(&qhp->wq, inc, NULL);
 709         else {
 710                 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
 711                 qhp->wq.sq.wq_pidx_inc += inc;
 712         }
 713         spin_unlock(&qhp->lock);
 714         spin_unlock_irqrestore(&qhp->rhp->lock, flags);
 715         return 0;
 716 }
 717
 718 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
 719 {
 720         unsigned long flags;
 721
 722         spin_lock_irqsave(&qhp->rhp->lock, flags);
 723         spin_lock(&qhp->lock);
 724         if (qhp->rhp->db_state == NORMAL)
 725                 t4_ring_rq_db(&qhp->wq, inc, NULL);
 726         else {
 727                 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
 728                 qhp->wq.rq.wq_pidx_inc += inc;
 729         }
 730         spin_unlock(&qhp->lock);
 731         spin_unlock_irqrestore(&qhp->rhp->lock, flags);
 732         return 0;
 733 }
 734
 735 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 736                    struct ib_send_wr **bad_wr)
 737 {
 738         int err = 0;
 739         u8 len16 = 0;
 740         enum fw_wr_opcodes fw_opcode = 0;
 741         enum fw_ri_wr_flags fw_flags;
 742         struct c4iw_qp *qhp;
 743         union t4_wr *wqe = NULL;
 744         u32 num_wrs;
 745         struct t4_swsqe *swsqe;
 746         unsigned long flag;
 747         u16 idx = 0;
 748
 749         qhp = to_c4iw_qp(ibqp);
 750         spin_lock_irqsave(&qhp->lock, flag);
 751         if (t4_wq_in_error(&qhp->wq)) {
 752                 spin_unlock_irqrestore(&qhp->lock, flag);
 753                 return -EINVAL;
 754         }
 755         num_wrs = t4_sq_avail(&qhp->wq);
 756         if (num_wrs == 0) {
 757                 spin_unlock_irqrestore(&qhp->lock, flag);
 758                 return -ENOMEM;
 759         }
 760         while (wr) {
 761                 if (num_wrs == 0) {
 762                         err = -ENOMEM;
 763                         *bad_wr = wr;
 764                         break;
 765                 }
 766                 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
 767                       qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
 768
 769                 fw_flags = 0;
 770                 if (wr->send_flags & IB_SEND_SOLICITED)
 771                         fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
 772                 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
 773                         fw_flags |= FW_RI_COMPLETION_FLAG;
 774                 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
 775                 switch (wr->opcode) {
 776                 case IB_WR_SEND_WITH_INV:
 777                 case IB_WR_SEND:
 778                         if (wr->send_flags & IB_SEND_FENCE)
 779                                 fw_flags |= FW_RI_READ_FENCE_FLAG;
 780                         fw_opcode = FW_RI_SEND_WR;
 781                         if (wr->opcode == IB_WR_SEND)
 782                                 swsqe->opcode = FW_RI_SEND;
 783                         else
 784                                 swsqe->opcode = FW_RI_SEND_WITH_INV;
 785                         err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
 786                         break;
 787                 case IB_WR_RDMA_WRITE:
 788                         fw_opcode = FW_RI_RDMA_WRITE_WR;
 789                         swsqe->opcode = FW_RI_RDMA_WRITE;
 790                         err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
 791                         break;
 792                 case IB_WR_RDMA_READ:
 793                 case IB_WR_RDMA_READ_WITH_INV:
 794                         fw_opcode = FW_RI_RDMA_READ_WR;
 795                         swsqe->opcode = FW_RI_READ_REQ;
 796                         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
 797                                 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
 798                         else
 799                                 fw_flags = 0;
 800                         err = build_rdma_read(wqe, wr, &len16);
 801                         if (err)
 802                                 break;
 803                         swsqe->read_len = wr->sg_list[0].length;
 804                         if (!qhp->wq.sq.oldest_read)
 805                                 qhp->wq.sq.oldest_read = swsqe;
 806                         break;
 807                 case IB_WR_REG_MR:
 808                         fw_opcode = FW_RI_FR_NSMR_WR;
 809                         swsqe->opcode = FW_RI_FAST_REGISTER;
 810                         err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr), &len16,
 811                                            is_t5(
 812                                            qhp->rhp->rdev.lldi.adapter_type) ?
 813                                            1 : 0);
 814                         break;
 815                 case IB_WR_LOCAL_INV:
 816                         if (wr->send_flags & IB_SEND_FENCE)
 817                                 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
 818                         fw_opcode = FW_RI_INV_LSTAG_WR;
 819                         swsqe->opcode = FW_RI_LOCAL_INV;
 820                         err = build_inv_stag(wqe, wr, &len16);
 821                         break;
 822                 default:
 823                         PDBG("%s post of type=%d TBD!\n", __func__,
 824                              wr->opcode);
 825                         err = -EINVAL;
 826                 }
 827                 if (err) {
 828                         *bad_wr = wr;
 829                         break;
 830                 }
 831                 swsqe->idx = qhp->wq.sq.pidx;
 832                 swsqe->complete = 0;
 833                 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
 834                                   qhp->sq_sig_all;
 835                 swsqe->flushed = 0;
 836                 swsqe->wr_id = wr->wr_id;
 837                 if (c4iw_wr_log) {
 838                         swsqe->sge_ts = cxgb4_read_sge_timestamp(
 839                                         qhp->rhp->rdev.lldi.ports[0]);
 840                         getnstimeofday(&swsqe->host_ts);
 841                 }
 842
 843                 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
 844
 845                 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
 846                      __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
 847                      swsqe->opcode, swsqe->read_len);
 848                 wr = wr->next;
 849                 num_wrs--;
 850                 t4_sq_produce(&qhp->wq, len16);
 851                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 852         }
 853         if (!qhp->rhp->rdev.status_page->db_off) {
 854                 t4_ring_sq_db(&qhp->wq, idx, wqe);
 855                 spin_unlock_irqrestore(&qhp->lock, flag);
 856         } else {
 857                 spin_unlock_irqrestore(&qhp->lock, flag);
 858                 ring_kernel_sq_db(qhp, idx);
 859         }
 860         return err;
 861 }
 862
 863 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 864                       struct ib_recv_wr **bad_wr)
 865 {
 866         int err = 0;
 867         struct c4iw_qp *qhp;
 868         union t4_recv_wr *wqe = NULL;
 869         u32 num_wrs;
 870         u8 len16 = 0;
 871         unsigned long flag;
 872         u16 idx = 0;
 873
 874         qhp = to_c4iw_qp(ibqp);
 875         spin_lock_irqsave(&qhp->lock, flag);
 876         if (t4_wq_in_error(&qhp->wq)) {
 877                 spin_unlock_irqrestore(&qhp->lock, flag);
 878                 return -EINVAL;
 879         }
 880         num_wrs = t4_rq_avail(&qhp->wq);
 881         if (num_wrs == 0) {
 882                 spin_unlock_irqrestore(&qhp->lock, flag);
 883                 return -ENOMEM;
 884         }
 885         while (wr) {
 886                 if (wr->num_sge > T4_MAX_RECV_SGE) {
 887                         err = -EINVAL;
 888                         *bad_wr = wr;
 889                         break;
 890                 }
 891                 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
 892                                            qhp->wq.rq.wq_pidx *
 893                                            T4_EQ_ENTRY_SIZE);
 894                 if (num_wrs)
 895                         err = build_rdma_recv(qhp, wqe, wr, &len16);
 896                 else
 897                         err = -ENOMEM;
 898                 if (err) {
 899                         *bad_wr = wr;
 900                         break;
 901                 }
 902
 903                 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
 904                 if (c4iw_wr_log) {
 905                         qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts =
 906                                 cxgb4_read_sge_timestamp(
 907                                                 qhp->rhp->rdev.lldi.ports[0]);
 908                         getnstimeofday(
 909                                 &qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_ts);
 910                 }
 911
 912                 wqe->recv.opcode = FW_RI_RECV_WR;
 913                 wqe->recv.r1 = 0;
 914                 wqe->recv.wrid = qhp->wq.rq.pidx;
 915                 wqe->recv.r2[0] = 0;
 916                 wqe->recv.r2[1] = 0;
 917                 wqe->recv.r2[2] = 0;
 918                 wqe->recv.len16 = len16;
 919                 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
 920                      (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
 921                 t4_rq_produce(&qhp->wq, len16);
 922                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 923                 wr = wr->next;
 924                 num_wrs--;
 925         }
 926         if (!qhp->rhp->rdev.status_page->db_off) {
 927                 t4_ring_rq_db(&qhp->wq, idx, wqe);
 928                 spin_unlock_irqrestore(&qhp->lock, flag);
 929         } else {
 930                 spin_unlock_irqrestore(&qhp->lock, flag);
 931                 ring_kernel_rq_db(qhp, idx);
 932         }
 933         return err;
 934 }
 935
 936 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
 937 {
 938         return -ENOSYS;
 939 }
 940
 941 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
 942                                     u8 *ecode)
 943 {
 944         int status;
 945         int tagged;
 946         int opcode;
 947         int rqtype;
 948         int send_inv;
 949
 950         if (!err_cqe) {
 951                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 952                 *ecode = 0;
 953                 return;
 954         }
 955
 956         status = CQE_STATUS(err_cqe);
 957         opcode = CQE_OPCODE(err_cqe);
 958         rqtype = RQ_TYPE(err_cqe);
 959         send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
 960                    (opcode == FW_RI_SEND_WITH_SE_INV);
 961         tagged = (opcode == FW_RI_RDMA_WRITE) ||
 962                  (rqtype && (opcode == FW_RI_READ_RESP));
 963
 964         switch (status) {
 965         case T4_ERR_STAG:
 966                 if (send_inv) {
 967                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 968                         *ecode = RDMAP_CANT_INV_STAG;
 969                 } else {
 970                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 971                         *ecode = RDMAP_INV_STAG;
 972                 }
 973                 break;
 974         case T4_ERR_PDID:
 975                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 976                 if ((opcode == FW_RI_SEND_WITH_INV) ||
 977                     (opcode == FW_RI_SEND_WITH_SE_INV))
 978                         *ecode = RDMAP_CANT_INV_STAG;
 979                 else
 980                         *ecode = RDMAP_STAG_NOT_ASSOC;
 981                 break;
 982         case T4_ERR_QPID:
 983                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 984                 *ecode = RDMAP_STAG_NOT_ASSOC;
 985                 break;
 986         case T4_ERR_ACCESS:
 987                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 988                 *ecode = RDMAP_ACC_VIOL;
 989                 break;
 990         case T4_ERR_WRAP:
 991                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 992                 *ecode = RDMAP_TO_WRAP;
 993                 break;
 994         case T4_ERR_BOUND:
 995                 if (tagged) {
 996                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 997                         *ecode = DDPT_BASE_BOUNDS;
 998                 } else {
 999                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1000                         *ecode = RDMAP_BASE_BOUNDS;
1001                 }
1002                 break;
1003         case T4_ERR_INVALIDATE_SHARED_MR:
1004         case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
1005                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1006                 *ecode = RDMAP_CANT_INV_STAG;
1007                 break;
1008         case T4_ERR_ECC:
1009         case T4_ERR_ECC_PSTAG:
1010         case T4_ERR_INTERNAL_ERR:
1011                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
1012                 *ecode = 0;
1013                 break;
1014         case T4_ERR_OUT_OF_RQE:
1015                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1016                 *ecode = DDPU_INV_MSN_NOBUF;
1017                 break;
1018         case T4_ERR_PBL_ADDR_BOUND:
1019                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1020                 *ecode = DDPT_BASE_BOUNDS;
1021                 break;
1022         case T4_ERR_CRC:
1023                 *layer_type = LAYER_MPA|DDP_LLP;
1024                 *ecode = MPA_CRC_ERR;
1025                 break;
1026         case T4_ERR_MARKER:
1027                 *layer_type = LAYER_MPA|DDP_LLP;
1028                 *ecode = MPA_MARKER_ERR;
1029                 break;
1030         case T4_ERR_PDU_LEN_ERR:
1031                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1032                 *ecode = DDPU_MSG_TOOBIG;
1033                 break;
1034         case T4_ERR_DDP_VERSION:
1035                 if (tagged) {
1036                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1037                         *ecode = DDPT_INV_VERS;
1038                 } else {
1039                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1040                         *ecode = DDPU_INV_VERS;
1041                 }
1042                 break;
1043         case T4_ERR_RDMA_VERSION:
1044                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1045                 *ecode = RDMAP_INV_VERS;
1046                 break;
1047         case T4_ERR_OPCODE:
1048                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1049                 *ecode = RDMAP_INV_OPCODE;
1050                 break;
1051         case T4_ERR_DDP_QUEUE_NUM:
1052                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1053                 *ecode = DDPU_INV_QN;
1054                 break;
1055         case T4_ERR_MSN:
1056         case T4_ERR_MSN_GAP:
1057         case T4_ERR_MSN_RANGE:
1058         case T4_ERR_IRD_OVERFLOW:
1059                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1060                 *ecode = DDPU_INV_MSN_RANGE;
1061                 break;
1062         case T4_ERR_TBIT:
1063                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1064                 *ecode = 0;
1065                 break;
1066         case T4_ERR_MO:
1067                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1068                 *ecode = DDPU_INV_MO;
1069                 break;
1070         default:
1071                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1072                 *ecode = 0;
1073                 break;
1074         }
1075 }
1076
1077 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1078                            gfp_t gfp)
1079 {
1080         struct fw_ri_wr *wqe;
1081         struct sk_buff *skb;
1082         struct terminate_message *term;
1083
1084         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1085              qhp->ep->hwtid);
1086
1087         skb = alloc_skb(sizeof *wqe, gfp);
1088         if (!skb)
1089                 return;
1090         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1091
1092         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1093         memset(wqe, 0, sizeof *wqe);
1094         wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR));
1095         wqe->flowid_len16 = cpu_to_be32(
1096                 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1097                 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1098
1099         wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1100         wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1101         term = (struct terminate_message *)wqe->u.terminate.termmsg;
1102         if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1103                 term->layer_etype = qhp->attr.layer_etype;
1104                 term->ecode = qhp->attr.ecode;
1105         } else
1106                 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1107         c4iw_ofld_send(&qhp->rhp->rdev, skb);
1108 }
1109
1110 /*
1111  * Assumes qhp lock is held.
1112  */
1113 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1114                        struct c4iw_cq *schp)
1115 {
1116         int count;
1117         int rq_flushed, sq_flushed;
1118         unsigned long flag;
1119
1120         PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
1121
1122         /* locking hierarchy: cq lock first, then qp lock. */
1123         spin_lock_irqsave(&rchp->lock, flag);
1124         spin_lock(&qhp->lock);
1125
1126         if (qhp->wq.flushed) {
1127                 spin_unlock(&qhp->lock);
1128                 spin_unlock_irqrestore(&rchp->lock, flag);
1129                 return;
1130         }
1131         qhp->wq.flushed = 1;
1132
1133         c4iw_flush_hw_cq(rchp);
1134         c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1135         rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1136         spin_unlock(&qhp->lock);
1137         spin_unlock_irqrestore(&rchp->lock, flag);
1138
1139         /* locking hierarchy: cq lock first, then qp lock. */
1140         spin_lock_irqsave(&schp->lock, flag);
1141         spin_lock(&qhp->lock);
1142         if (schp != rchp)
1143                 c4iw_flush_hw_cq(schp);
1144         sq_flushed = c4iw_flush_sq(qhp);
1145         spin_unlock(&qhp->lock);
1146         spin_unlock_irqrestore(&schp->lock, flag);
1147
1148         if (schp == rchp) {
1149                 if (t4_clear_cq_armed(&rchp->cq) &&
1150                     (rq_flushed || sq_flushed)) {
1151                         spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1152                         (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1153                                                    rchp->ibcq.cq_context);
1154                         spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1155                 }
1156         } else {
1157                 if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) {
1158                         spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1159                         (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1160                                                    rchp->ibcq.cq_context);
1161                         spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1162                 }
1163                 if (t4_clear_cq_armed(&schp->cq) && sq_flushed) {
1164                         spin_lock_irqsave(&schp->comp_handler_lock, flag);
1165                         (*schp->ibcq.comp_handler)(&schp->ibcq,
1166                                                    schp->ibcq.cq_context);
1167                         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1168                 }
1169         }
1170 }
1171
1172 static void flush_qp(struct c4iw_qp *qhp)
1173 {
1174         struct c4iw_cq *rchp, *schp;
1175         unsigned long flag;
1176
1177         rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1178         schp = to_c4iw_cq(qhp->ibqp.send_cq);
1179
1180         t4_set_wq_in_error(&qhp->wq);
1181         if (qhp->ibqp.uobject) {
1182                 t4_set_cq_in_error(&rchp->cq);
1183                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1184                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1185                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1186                 if (schp != rchp) {
1187                         t4_set_cq_in_error(&schp->cq);
1188                         spin_lock_irqsave(&schp->comp_handler_lock, flag);
1189                         (*schp->ibcq.comp_handler)(&schp->ibcq,
1190                                         schp->ibcq.cq_context);
1191                         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1192                 }
1193                 return;
1194         }
1195         __flush_qp(qhp, rchp, schp);
1196 }
1197
1198 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1199                      struct c4iw_ep *ep)
1200 {
1201         struct fw_ri_wr *wqe;
1202         int ret;
1203         struct sk_buff *skb;
1204
1205         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1206              ep->hwtid);
1207
1208         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1209         if (!skb)
1210                 return -ENOMEM;
1211         set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1212
1213         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1214         memset(wqe, 0, sizeof *wqe);
1215         wqe->op_compl = cpu_to_be32(
1216                 FW_WR_OP_V(FW_RI_INIT_WR) |
1217                 FW_WR_COMPL_F);
1218         wqe->flowid_len16 = cpu_to_be32(
1219                 FW_WR_FLOWID_V(ep->hwtid) |
1220                 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1221         wqe->cookie = (uintptr_t)&ep->com.wr_wait;
1222
1223         wqe->u.fini.type = FW_RI_TYPE_FINI;
1224         ret = c4iw_ofld_send(&rhp->rdev, skb);
1225         if (ret)
1226                 goto out;
1227
1228         ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1229                              qhp->wq.sq.qid, __func__);
1230 out:
1231         PDBG("%s ret %d\n", __func__, ret);
1232         return ret;
1233 }
1234
1235 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1236 {
1237         PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1238         memset(&init->u, 0, sizeof init->u);
1239         switch (p2p_type) {
1240         case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1241                 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1242                 init->u.write.stag_sink = cpu_to_be32(1);
1243                 init->u.write.to_sink = cpu_to_be64(1);
1244                 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1245                 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1246                                                    sizeof(struct fw_ri_immd),
1247                                                    16);
1248                 break;
1249         case FW_RI_INIT_P2PTYPE_READ_REQ:
1250                 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1251                 init->u.read.stag_src = cpu_to_be32(1);
1252                 init->u.read.to_src_lo = cpu_to_be32(1);
1253                 init->u.read.stag_sink = cpu_to_be32(1);
1254                 init->u.read.to_sink_lo = cpu_to_be32(1);
1255                 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1256                 break;
1257         }
1258 }
1259
1260 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1261 {
1262         struct fw_ri_wr *wqe;
1263         int ret;
1264         struct sk_buff *skb;
1265
1266         PDBG("%s qhp %p qid 0x%x tid %u ird %u ord %u\n", __func__, qhp,
1267              qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord);
1268
1269         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1270         if (!skb) {
1271                 ret = -ENOMEM;
1272                 goto out;
1273         }
1274         ret = alloc_ird(rhp, qhp->attr.max_ird);
1275         if (ret) {
1276                 qhp->attr.max_ird = 0;
1277                 kfree_skb(skb);
1278                 goto out;
1279         }
1280         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1281
1282         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1283         memset(wqe, 0, sizeof *wqe);
1284         wqe->op_compl = cpu_to_be32(
1285                 FW_WR_OP_V(FW_RI_INIT_WR) |
1286                 FW_WR_COMPL_F);
1287         wqe->flowid_len16 = cpu_to_be32(
1288                 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1289                 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1290
1291         wqe->cookie = (uintptr_t)&qhp->ep->com.wr_wait;
1292
1293         wqe->u.init.type = FW_RI_TYPE_INIT;
1294         wqe->u.init.mpareqbit_p2ptype =
1295                 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) |
1296                 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type);
1297         wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1298         if (qhp->attr.mpa_attr.recv_marker_enabled)
1299                 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1300         if (qhp->attr.mpa_attr.xmit_marker_enabled)
1301                 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1302         if (qhp->attr.mpa_attr.crc_enabled)
1303                 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1304
1305         wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1306                             FW_RI_QP_RDMA_WRITE_ENABLE |
1307                             FW_RI_QP_BIND_ENABLE;
1308         if (!qhp->ibqp.uobject)
1309                 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1310                                      FW_RI_QP_STAG0_ENABLE;
1311         wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1312         wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1313         wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1314         wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1315         wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1316         wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1317         wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1318         wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1319         wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1320         wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1321         wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1322         wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1323         wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1324                                          rhp->rdev.lldi.vr->rq.start);
1325         if (qhp->attr.mpa_attr.initiator)
1326                 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1327
1328         ret = c4iw_ofld_send(&rhp->rdev, skb);
1329         if (ret)
1330                 goto err1;
1331
1332         ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1333                                   qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1334         if (!ret)
1335                 goto out;
1336 err1:
1337         free_ird(rhp, qhp->attr.max_ird);
1338 out:
1339         PDBG("%s ret %d\n", __func__, ret);
1340         return ret;
1341 }
1342
1343 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1344                    enum c4iw_qp_attr_mask mask,
1345                    struct c4iw_qp_attributes *attrs,
1346                    int internal)
1347 {
1348         int ret = 0;
1349         struct c4iw_qp_attributes newattr = qhp->attr;
1350         int disconnect = 0;
1351         int terminate = 0;
1352         int abort = 0;
1353         int free = 0;
1354         struct c4iw_ep *ep = NULL;
1355
1356         PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1357              qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1358              (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1359
1360         mutex_lock(&qhp->mutex);
1361
1362         /* Process attr changes if in IDLE */
1363         if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1364                 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1365                         ret = -EIO;
1366                         goto out;
1367                 }
1368                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1369                         newattr.enable_rdma_read = attrs->enable_rdma_read;
1370                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1371                         newattr.enable_rdma_write = attrs->enable_rdma_write;
1372                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1373                         newattr.enable_bind = attrs->enable_bind;
1374                 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1375                         if (attrs->max_ord > c4iw_max_read_depth) {
1376                                 ret = -EINVAL;
1377                                 goto out;
1378                         }
1379                         newattr.max_ord = attrs->max_ord;
1380                 }
1381                 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1382                         if (attrs->max_ird > cur_max_read_depth(rhp)) {
1383                                 ret = -EINVAL;
1384                                 goto out;
1385                         }
1386                         newattr.max_ird = attrs->max_ird;
1387                 }
1388                 qhp->attr = newattr;
1389         }
1390
1391         if (mask & C4IW_QP_ATTR_SQ_DB) {
1392                 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1393                 goto out;
1394         }
1395         if (mask & C4IW_QP_ATTR_RQ_DB) {
1396                 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1397                 goto out;
1398         }
1399
1400         if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1401                 goto out;
1402         if (qhp->attr.state == attrs->next_state)
1403                 goto out;
1404
1405         switch (qhp->attr.state) {
1406         case C4IW_QP_STATE_IDLE:
1407                 switch (attrs->next_state) {
1408                 case C4IW_QP_STATE_RTS:
1409                         if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1410                                 ret = -EINVAL;
1411                                 goto out;
1412                         }
1413                         if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1414                                 ret = -EINVAL;
1415                                 goto out;
1416                         }
1417                         qhp->attr.mpa_attr = attrs->mpa_attr;
1418                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1419                         qhp->ep = qhp->attr.llp_stream_handle;
1420                         set_state(qhp, C4IW_QP_STATE_RTS);
1421
1422                         /*
1423                          * Ref the endpoint here and deref when we
1424                          * disassociate the endpoint from the QP.  This
1425                          * happens in CLOSING->IDLE transition or *->ERROR
1426                          * transition.
1427                          */
1428                         c4iw_get_ep(&qhp->ep->com);
1429                         ret = rdma_init(rhp, qhp);
1430                         if (ret)
1431                                 goto err;
1432                         break;
1433                 case C4IW_QP_STATE_ERROR:
1434                         set_state(qhp, C4IW_QP_STATE_ERROR);
1435                         flush_qp(qhp);
1436                         break;
1437                 default:
1438                         ret = -EINVAL;
1439                         goto out;
1440                 }
1441                 break;
1442         case C4IW_QP_STATE_RTS:
1443                 switch (attrs->next_state) {
1444                 case C4IW_QP_STATE_CLOSING:
1445                         BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1446                         t4_set_wq_in_error(&qhp->wq);
1447                         set_state(qhp, C4IW_QP_STATE_CLOSING);
1448                         ep = qhp->ep;
1449                         if (!internal) {
1450                                 abort = 0;
1451                                 disconnect = 1;
1452                                 c4iw_get_ep(&qhp->ep->com);
1453                         }
1454                         ret = rdma_fini(rhp, qhp, ep);
1455                         if (ret)
1456                                 goto err;
1457                         break;
1458                 case C4IW_QP_STATE_TERMINATE:
1459                         t4_set_wq_in_error(&qhp->wq);
1460                         set_state(qhp, C4IW_QP_STATE_TERMINATE);
1461                         qhp->attr.layer_etype = attrs->layer_etype;
1462                         qhp->attr.ecode = attrs->ecode;
1463                         ep = qhp->ep;
1464                         if (!internal) {
1465                                 c4iw_get_ep(&qhp->ep->com);
1466                                 terminate = 1;
1467                                 disconnect = 1;
1468                         } else {
1469                                 terminate = qhp->attr.send_term;
1470                                 ret = rdma_fini(rhp, qhp, ep);
1471                                 if (ret)
1472                                         goto err;
1473                         }
1474                         break;
1475                 case C4IW_QP_STATE_ERROR:
1476                         t4_set_wq_in_error(&qhp->wq);
1477                         set_state(qhp, C4IW_QP_STATE_ERROR);
1478                         if (!internal) {
1479                                 abort = 1;
1480                                 disconnect = 1;
1481                                 ep = qhp->ep;
1482                                 c4iw_get_ep(&qhp->ep->com);
1483                         }
1484                         goto err;
1485                         break;
1486                 default:
1487                         ret = -EINVAL;
1488                         goto out;
1489                 }
1490                 break;
1491         case C4IW_QP_STATE_CLOSING:
1492                 if (!internal) {
1493                         ret = -EINVAL;
1494                         goto out;
1495                 }
1496                 switch (attrs->next_state) {
1497                 case C4IW_QP_STATE_IDLE:
1498                         flush_qp(qhp);
1499                         set_state(qhp, C4IW_QP_STATE_IDLE);
1500                         qhp->attr.llp_stream_handle = NULL;
1501                         c4iw_put_ep(&qhp->ep->com);
1502                         qhp->ep = NULL;
1503                         wake_up(&qhp->wait);
1504                         break;
1505                 case C4IW_QP_STATE_ERROR:
1506                         goto err;
1507                 default:
1508                         ret = -EINVAL;
1509                         goto err;
1510                 }
1511                 break;
1512         case C4IW_QP_STATE_ERROR:
1513                 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1514                         ret = -EINVAL;
1515                         goto out;
1516                 }
1517                 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1518                         ret = -EINVAL;
1519                         goto out;
1520                 }
1521                 set_state(qhp, C4IW_QP_STATE_IDLE);
1522                 break;
1523         case C4IW_QP_STATE_TERMINATE:
1524                 if (!internal) {
1525                         ret = -EINVAL;
1526                         goto out;
1527                 }
1528                 goto err;
1529                 break;
1530         default:
1531                 printk(KERN_ERR "%s in a bad state %d\n",
1532                        __func__, qhp->attr.state);
1533                 ret = -EINVAL;
1534                 goto err;
1535                 break;
1536         }
1537         goto out;
1538 err:
1539         PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1540              qhp->wq.sq.qid);
1541
1542         /* disassociate the LLP connection */
1543         qhp->attr.llp_stream_handle = NULL;
1544         if (!ep)
1545                 ep = qhp->ep;
1546         qhp->ep = NULL;
1547         set_state(qhp, C4IW_QP_STATE_ERROR);
1548         free = 1;
1549         abort = 1;
1550         BUG_ON(!ep);
1551         flush_qp(qhp);
1552         wake_up(&qhp->wait);
1553 out:
1554         mutex_unlock(&qhp->mutex);
1555
1556         if (terminate)
1557                 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1558
1559         /*
1560          * If disconnect is 1, then we need to initiate a disconnect
1561          * on the EP.  This can be a normal close (RTS->CLOSING) or
1562          * an abnormal close (RTS/CLOSING->ERROR).
1563          */
1564         if (disconnect) {
1565                 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1566                                                          GFP_KERNEL);
1567                 c4iw_put_ep(&ep->com);
1568         }
1569
1570         /*
1571          * If free is 1, then we've disassociated the EP from the QP
1572          * and we need to dereference the EP.
1573          */
1574         if (free)
1575                 c4iw_put_ep(&ep->com);
1576         PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1577         return ret;
1578 }
1579
1580 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1581 {
1582         struct c4iw_dev *rhp;
1583         struct c4iw_qp *qhp;
1584         struct c4iw_qp_attributes attrs;
1585         struct c4iw_ucontext *ucontext;
1586
1587         qhp = to_c4iw_qp(ib_qp);
1588         rhp = qhp->rhp;
1589
1590         attrs.next_state = C4IW_QP_STATE_ERROR;
1591         if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1592                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1593         else
1594                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1595         wait_event(qhp->wait, !qhp->ep);
1596
1597         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1598         atomic_dec(&qhp->refcnt);
1599         wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1600
1601         spin_lock_irq(&rhp->lock);
1602         if (!list_empty(&qhp->db_fc_entry))
1603                 list_del_init(&qhp->db_fc_entry);
1604         spin_unlock_irq(&rhp->lock);
1605         free_ird(rhp, qhp->attr.max_ird);
1606
1607         ucontext = ib_qp->uobject ?
1608                    to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1609         destroy_qp(&rhp->rdev, &qhp->wq,
1610                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1611
1612         PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1613         kfree(qhp);
1614         return 0;
1615 }
1616
1617 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1618                              struct ib_udata *udata)
1619 {
1620         struct c4iw_dev *rhp;
1621         struct c4iw_qp *qhp;
1622         struct c4iw_pd *php;
1623         struct c4iw_cq *schp;
1624         struct c4iw_cq *rchp;
1625         struct c4iw_create_qp_resp uresp;
1626         unsigned int sqsize, rqsize;
1627         struct c4iw_ucontext *ucontext;
1628         int ret;
1629         struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
1630
1631         PDBG("%s ib_pd %p\n", __func__, pd);
1632
1633         if (attrs->qp_type != IB_QPT_RC)
1634                 return ERR_PTR(-EINVAL);
1635
1636         php = to_c4iw_pd(pd);
1637         rhp = php->rhp;
1638         schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1639         rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1640         if (!schp || !rchp)
1641                 return ERR_PTR(-EINVAL);
1642
1643         if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1644                 return ERR_PTR(-EINVAL);
1645
1646         if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size)
1647                 return ERR_PTR(-E2BIG);
1648         rqsize = attrs->cap.max_recv_wr + 1;
1649         if (rqsize < 8)
1650                 rqsize = 8;
1651
1652         if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size)
1653                 return ERR_PTR(-E2BIG);
1654         sqsize = attrs->cap.max_send_wr + 1;
1655         if (sqsize < 8)
1656                 sqsize = 8;
1657
1658         ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1659
1660         qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1661         if (!qhp)
1662                 return ERR_PTR(-ENOMEM);
1663         qhp->wq.sq.size = sqsize;
1664         qhp->wq.sq.memsize =
1665                 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1666                 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64);
1667         qhp->wq.sq.flush_cidx = -1;
1668         qhp->wq.rq.size = rqsize;
1669         qhp->wq.rq.memsize =
1670                 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1671                 sizeof(*qhp->wq.rq.queue);
1672
1673         if (ucontext) {
1674                 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1675                 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1676         }
1677
1678         ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1679                         ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1680         if (ret)
1681                 goto err1;
1682
1683         attrs->cap.max_recv_wr = rqsize - 1;
1684         attrs->cap.max_send_wr = sqsize - 1;
1685         attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1686
1687         qhp->rhp = rhp;
1688         qhp->attr.pd = php->pdid;
1689         qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1690         qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1691         qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1692         qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1693         qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1694         qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1695         qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1696         qhp->attr.state = C4IW_QP_STATE_IDLE;
1697         qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1698         qhp->attr.enable_rdma_read = 1;
1699         qhp->attr.enable_rdma_write = 1;
1700         qhp->attr.enable_bind = 1;
1701         qhp->attr.max_ord = 0;
1702         qhp->attr.max_ird = 0;
1703         qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
1704         spin_lock_init(&qhp->lock);
1705         mutex_init(&qhp->mutex);
1706         init_waitqueue_head(&qhp->wait);
1707         atomic_set(&qhp->refcnt, 1);
1708
1709         ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1710         if (ret)
1711                 goto err2;
1712
1713         if (udata) {
1714                 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1715                 if (!mm1) {
1716                         ret = -ENOMEM;
1717                         goto err3;
1718                 }
1719                 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1720                 if (!mm2) {
1721                         ret = -ENOMEM;
1722                         goto err4;
1723                 }
1724                 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1725                 if (!mm3) {
1726                         ret = -ENOMEM;
1727                         goto err5;
1728                 }
1729                 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1730                 if (!mm4) {
1731                         ret = -ENOMEM;
1732                         goto err6;
1733                 }
1734                 if (t4_sq_onchip(&qhp->wq.sq)) {
1735                         mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1736                         if (!mm5) {
1737                                 ret = -ENOMEM;
1738                                 goto err7;
1739                         }
1740                         uresp.flags = C4IW_QPF_ONCHIP;
1741                 } else
1742                         uresp.flags = 0;
1743                 uresp.qid_mask = rhp->rdev.qpmask;
1744                 uresp.sqid = qhp->wq.sq.qid;
1745                 uresp.sq_size = qhp->wq.sq.size;
1746                 uresp.sq_memsize = qhp->wq.sq.memsize;
1747                 uresp.rqid = qhp->wq.rq.qid;
1748                 uresp.rq_size = qhp->wq.rq.size;
1749                 uresp.rq_memsize = qhp->wq.rq.memsize;
1750                 spin_lock(&ucontext->mmap_lock);
1751                 if (mm5) {
1752                         uresp.ma_sync_key = ucontext->key;
1753                         ucontext->key += PAGE_SIZE;
1754                 } else {
1755                         uresp.ma_sync_key =  0;
1756                 }
1757                 uresp.sq_key = ucontext->key;
1758                 ucontext->key += PAGE_SIZE;
1759                 uresp.rq_key = ucontext->key;
1760                 ucontext->key += PAGE_SIZE;
1761                 uresp.sq_db_gts_key = ucontext->key;
1762                 ucontext->key += PAGE_SIZE;
1763                 uresp.rq_db_gts_key = ucontext->key;
1764                 ucontext->key += PAGE_SIZE;
1765                 spin_unlock(&ucontext->mmap_lock);
1766                 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1767                 if (ret)
1768                         goto err8;
1769                 mm1->key = uresp.sq_key;
1770                 mm1->addr = qhp->wq.sq.phys_addr;
1771                 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1772                 insert_mmap(ucontext, mm1);
1773                 mm2->key = uresp.rq_key;
1774                 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1775                 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1776                 insert_mmap(ucontext, mm2);
1777                 mm3->key = uresp.sq_db_gts_key;
1778                 mm3->addr = (__force unsigned long)qhp->wq.sq.bar2_pa;
1779                 mm3->len = PAGE_SIZE;
1780                 insert_mmap(ucontext, mm3);
1781                 mm4->key = uresp.rq_db_gts_key;
1782                 mm4->addr = (__force unsigned long)qhp->wq.rq.bar2_pa;
1783                 mm4->len = PAGE_SIZE;
1784                 insert_mmap(ucontext, mm4);
1785                 if (mm5) {
1786                         mm5->key = uresp.ma_sync_key;
1787                         mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1788                                     + PCIE_MA_SYNC_A) & PAGE_MASK;
1789                         mm5->len = PAGE_SIZE;
1790                         insert_mmap(ucontext, mm5);
1791                 }
1792         }
1793         qhp->ibqp.qp_num = qhp->wq.sq.qid;
1794         init_timer(&(qhp->timer));
1795         INIT_LIST_HEAD(&qhp->db_fc_entry);
1796         PDBG("%s sq id %u size %u memsize %zu num_entries %u "
1797              "rq id %u size %u memsize %zu num_entries %u\n", __func__,
1798              qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize,
1799              attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size,
1800              qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
1801         return &qhp->ibqp;
1802 err8:
1803         kfree(mm5);
1804 err7:
1805         kfree(mm4);
1806 err6:
1807         kfree(mm3);
1808 err5:
1809         kfree(mm2);
1810 err4:
1811         kfree(mm1);
1812 err3:
1813         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1814 err2:
1815         destroy_qp(&rhp->rdev, &qhp->wq,
1816                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1817 err1:
1818         kfree(qhp);
1819         return ERR_PTR(ret);
1820 }
1821
1822 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1823                       int attr_mask, struct ib_udata *udata)
1824 {
1825         struct c4iw_dev *rhp;
1826         struct c4iw_qp *qhp;
1827         enum c4iw_qp_attr_mask mask = 0;
1828         struct c4iw_qp_attributes attrs;
1829
1830         PDBG("%s ib_qp %p\n", __func__, ibqp);
1831
1832         /* iwarp does not support the RTR state */
1833         if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1834                 attr_mask &= ~IB_QP_STATE;
1835
1836         /* Make sure we still have something left to do */
1837         if (!attr_mask)
1838                 return 0;
1839
1840         memset(&attrs, 0, sizeof attrs);
1841         qhp = to_c4iw_qp(ibqp);
1842         rhp = qhp->rhp;
1843
1844         attrs.next_state = c4iw_convert_state(attr->qp_state);
1845         attrs.enable_rdma_read = (attr->qp_access_flags &
1846                                IB_ACCESS_REMOTE_READ) ?  1 : 0;
1847         attrs.enable_rdma_write = (attr->qp_access_flags &
1848                                 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1849         attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1850
1851
1852         mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1853         mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1854                         (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1855                          C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1856                          C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1857
1858         /*
1859          * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1860          * ringing the queue db when we're in DB_FULL mode.
1861          * Only allow this on T4 devices.
1862          */
1863         attrs.sq_db_inc = attr->sq_psn;
1864         attrs.rq_db_inc = attr->rq_psn;
1865         mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1866         mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1867         if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) &&
1868             (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB)))
1869                 return -EINVAL;
1870
1871         return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1872 }
1873
1874 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1875 {
1876         PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1877         return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1878 }
1879
1880 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1881                      int attr_mask, struct ib_qp_init_attr *init_attr)
1882 {
1883         struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1884
1885         memset(attr, 0, sizeof *attr);
1886         memset(init_attr, 0, sizeof *init_attr);
1887         attr->qp_state = to_ib_qp_state(qhp->attr.state);
1888         init_attr->cap.max_send_wr = qhp->attr.sq_num_entries;
1889         init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries;
1890         init_attr->cap.max_send_sge = qhp->attr.sq_max_sges;
1891         init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges;
1892         init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE;
1893         init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0;
1894         return 0;
1895 }