kernel/drivers/iio/accel/bmc150-accel-core.c

   1 /*
   2  * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
   3  *  - BMC150
   4  *  - BMI055
   5  *  - BMA255
   6  *  - BMA250E
   7  *  - BMA222E
   8  *  - BMA280
   9  *
  10  * Copyright (c) 2014, Intel Corporation.
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms and conditions of the GNU General Public License,
  14  * version 2, as published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  * more details.
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/i2c.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/acpi.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/pm.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/iio/iio.h>
  32 #include <linux/iio/sysfs.h>
  33 #include <linux/iio/buffer.h>
  34 #include <linux/iio/events.h>
  35 #include <linux/iio/trigger.h>
  36 #include <linux/iio/trigger_consumer.h>
  37 #include <linux/iio/triggered_buffer.h>
  38 #include <linux/regmap.h>
  39
  40 #include "bmc150-accel.h"
  41
  42 #define BMC150_ACCEL_DRV_NAME                   "bmc150_accel"
  43 #define BMC150_ACCEL_IRQ_NAME                   "bmc150_accel_event"
  44
  45 #define BMC150_ACCEL_REG_CHIP_ID                0x00
  46
  47 #define BMC150_ACCEL_REG_INT_STATUS_2           0x0B
  48 #define BMC150_ACCEL_ANY_MOTION_MASK            0x07
  49 #define BMC150_ACCEL_ANY_MOTION_BIT_X           BIT(0)
  50 #define BMC150_ACCEL_ANY_MOTION_BIT_Y           BIT(1)
  51 #define BMC150_ACCEL_ANY_MOTION_BIT_Z           BIT(2)
  52 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN        BIT(3)
  53
  54 #define BMC150_ACCEL_REG_PMU_LPW                0x11
  55 #define BMC150_ACCEL_PMU_MODE_MASK              0xE0
  56 #define BMC150_ACCEL_PMU_MODE_SHIFT             5
  57 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK     0x17
  58 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT    1
  59
  60 #define BMC150_ACCEL_REG_PMU_RANGE              0x0F
  61
  62 #define BMC150_ACCEL_DEF_RANGE_2G               0x03
  63 #define BMC150_ACCEL_DEF_RANGE_4G               0x05
  64 #define BMC150_ACCEL_DEF_RANGE_8G               0x08
  65 #define BMC150_ACCEL_DEF_RANGE_16G              0x0C
  66
  67 /* Default BW: 125Hz */
  68 #define BMC150_ACCEL_REG_PMU_BW         0x10
  69 #define BMC150_ACCEL_DEF_BW                     125
  70
  71 #define BMC150_ACCEL_REG_RESET                  0x14
  72 #define BMC150_ACCEL_RESET_VAL                  0xB6
  73
  74 #define BMC150_ACCEL_REG_INT_MAP_0              0x19
  75 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE        BIT(2)
  76
  77 #define BMC150_ACCEL_REG_INT_MAP_1              0x1A
  78 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA         BIT(0)
  79 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM          BIT(1)
  80 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL        BIT(2)
  81
  82 #define BMC150_ACCEL_REG_INT_RST_LATCH          0x21
  83 #define BMC150_ACCEL_INT_MODE_LATCH_RESET       0x80
  84 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
  85 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT     0x00
  86
  87 #define BMC150_ACCEL_REG_INT_EN_0               0x16
  88 #define BMC150_ACCEL_INT_EN_BIT_SLP_X           BIT(0)
  89 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y           BIT(1)
  90 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z           BIT(2)
  91
  92 #define BMC150_ACCEL_REG_INT_EN_1               0x17
  93 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN         BIT(4)
  94 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN        BIT(5)
  95 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN          BIT(6)
  96
  97 #define BMC150_ACCEL_REG_INT_OUT_CTRL           0x20
  98 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL      BIT(0)
  99
 100 #define BMC150_ACCEL_REG_INT_5                  0x27
 101 #define BMC150_ACCEL_SLOPE_DUR_MASK             0x03
 102
 103 #define BMC150_ACCEL_REG_INT_6                  0x28
 104 #define BMC150_ACCEL_SLOPE_THRES_MASK           0xFF
 105
 106 /* Slope duration in terms of number of samples */
 107 #define BMC150_ACCEL_DEF_SLOPE_DURATION         1
 108 /* in terms of multiples of g's/LSB, based on range */
 109 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD        1
 110
 111 #define BMC150_ACCEL_REG_XOUT_L         0x02
 112
 113 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS        100
 114
 115 /* Sleep Duration values */
 116 #define BMC150_ACCEL_SLEEP_500_MICRO            0x05
 117 #define BMC150_ACCEL_SLEEP_1_MS         0x06
 118 #define BMC150_ACCEL_SLEEP_2_MS         0x07
 119 #define BMC150_ACCEL_SLEEP_4_MS         0x08
 120 #define BMC150_ACCEL_SLEEP_6_MS         0x09
 121 #define BMC150_ACCEL_SLEEP_10_MS                0x0A
 122 #define BMC150_ACCEL_SLEEP_25_MS                0x0B
 123 #define BMC150_ACCEL_SLEEP_50_MS                0x0C
 124 #define BMC150_ACCEL_SLEEP_100_MS               0x0D
 125 #define BMC150_ACCEL_SLEEP_500_MS               0x0E
 126 #define BMC150_ACCEL_SLEEP_1_SEC                0x0F
 127
 128 #define BMC150_ACCEL_REG_TEMP                   0x08
 129 #define BMC150_ACCEL_TEMP_CENTER_VAL            24
 130
 131 #define BMC150_ACCEL_AXIS_TO_REG(axis)  (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
 132 #define BMC150_AUTO_SUSPEND_DELAY_MS            2000
 133
 134 #define BMC150_ACCEL_REG_FIFO_STATUS            0x0E
 135 #define BMC150_ACCEL_REG_FIFO_CONFIG0           0x30
 136 #define BMC150_ACCEL_REG_FIFO_CONFIG1           0x3E
 137 #define BMC150_ACCEL_REG_FIFO_DATA              0x3F
 138 #define BMC150_ACCEL_FIFO_LENGTH                32
 139
 140 enum bmc150_accel_axis {
 141         AXIS_X,
 142         AXIS_Y,
 143         AXIS_Z,
 144 };
 145
 146 enum bmc150_power_modes {
 147         BMC150_ACCEL_SLEEP_MODE_NORMAL,
 148         BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
 149         BMC150_ACCEL_SLEEP_MODE_LPM,
 150         BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
 151 };
 152
 153 struct bmc150_scale_info {
 154         int scale;
 155         u8 reg_range;
 156 };
 157
 158 struct bmc150_accel_chip_info {
 159         const char *name;
 160         u8 chip_id;
 161         const struct iio_chan_spec *channels;
 162         int num_channels;
 163         const struct bmc150_scale_info scale_table[4];
 164 };
 165
 166 struct bmc150_accel_interrupt {
 167         const struct bmc150_accel_interrupt_info *info;
 168         atomic_t users;
 169 };
 170
 171 struct bmc150_accel_trigger {
 172         struct bmc150_accel_data *data;
 173         struct iio_trigger *indio_trig;
 174         int (*setup)(struct bmc150_accel_trigger *t, bool state);
 175         int intr;
 176         bool enabled;
 177 };
 178
 179 enum bmc150_accel_interrupt_id {
 180         BMC150_ACCEL_INT_DATA_READY,
 181         BMC150_ACCEL_INT_ANY_MOTION,
 182         BMC150_ACCEL_INT_WATERMARK,
 183         BMC150_ACCEL_INTERRUPTS,
 184 };
 185
 186 enum bmc150_accel_trigger_id {
 187         BMC150_ACCEL_TRIGGER_DATA_READY,
 188         BMC150_ACCEL_TRIGGER_ANY_MOTION,
 189         BMC150_ACCEL_TRIGGERS,
 190 };
 191
 192 struct bmc150_accel_data {
 193         struct regmap *regmap;
 194         struct device *dev;
 195         int irq;
 196         struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
 197         atomic_t active_intr;
 198         struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
 199         struct mutex mutex;
 200         u8 fifo_mode, watermark;
 201         s16 buffer[8];
 202         u8 bw_bits;
 203         u32 slope_dur;
 204         u32 slope_thres;
 205         u32 range;
 206         int ev_enable_state;
 207         int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
 208         const struct bmc150_accel_chip_info *chip_info;
 209 };
 210
 211 static const struct {
 212         int val;
 213         int val2;
 214         u8 bw_bits;
 215 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
 216                                      {31, 260000, 0x09},
 217                                      {62, 500000, 0x0A},
 218                                      {125, 0, 0x0B},
 219                                      {250, 0, 0x0C},
 220                                      {500, 0, 0x0D},
 221                                      {1000, 0, 0x0E},
 222                                      {2000, 0, 0x0F} };
 223
 224 static const struct {
 225         int bw_bits;
 226         int msec;
 227 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
 228                                      {0x09, 32},
 229                                      {0x0A, 16},
 230                                      {0x0B, 8},
 231                                      {0x0C, 4},
 232                                      {0x0D, 2},
 233                                      {0x0E, 1},
 234                                      {0x0F, 1} };
 235
 236 static const struct {
 237         int sleep_dur;
 238         u8 reg_value;
 239 } bmc150_accel_sleep_value_table[] = { {0, 0},
 240                                        {500, BMC150_ACCEL_SLEEP_500_MICRO},
 241                                        {1000, BMC150_ACCEL_SLEEP_1_MS},
 242                                        {2000, BMC150_ACCEL_SLEEP_2_MS},
 243                                        {4000, BMC150_ACCEL_SLEEP_4_MS},
 244                                        {6000, BMC150_ACCEL_SLEEP_6_MS},
 245                                        {10000, BMC150_ACCEL_SLEEP_10_MS},
 246                                        {25000, BMC150_ACCEL_SLEEP_25_MS},
 247                                        {50000, BMC150_ACCEL_SLEEP_50_MS},
 248                                        {100000, BMC150_ACCEL_SLEEP_100_MS},
 249                                        {500000, BMC150_ACCEL_SLEEP_500_MS},
 250                                        {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
 251
 252 static const struct regmap_config bmc150_i2c_regmap_conf = {
 253         .reg_bits = 8,
 254         .val_bits = 8,
 255         .max_register = 0x3f,
 256 };
 257
 258 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
 259                                  enum bmc150_power_modes mode,
 260                                  int dur_us)
 261 {
 262         int i;
 263         int ret;
 264         u8 lpw_bits;
 265         int dur_val = -1;
 266
 267         if (dur_us > 0) {
 268                 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
 269                                                                          ++i) {
 270                         if (bmc150_accel_sleep_value_table[i].sleep_dur ==
 271                                                                         dur_us)
 272                                 dur_val =
 273                                 bmc150_accel_sleep_value_table[i].reg_value;
 274                 }
 275         } else {
 276                 dur_val = 0;
 277         }
 278
 279         if (dur_val < 0)
 280                 return -EINVAL;
 281
 282         lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
 283         lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
 284
 285         dev_dbg(data->dev, "Set Mode bits %x\n", lpw_bits);
 286
 287         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
 288         if (ret < 0) {
 289                 dev_err(data->dev, "Error writing reg_pmu_lpw\n");
 290                 return ret;
 291         }
 292
 293         return 0;
 294 }
 295
 296 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
 297                                int val2)
 298 {
 299         int i;
 300         int ret;
 301
 302         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 303                 if (bmc150_accel_samp_freq_table[i].val == val &&
 304                     bmc150_accel_samp_freq_table[i].val2 == val2) {
 305                         ret = regmap_write(data->regmap,
 306                                 BMC150_ACCEL_REG_PMU_BW,
 307                                 bmc150_accel_samp_freq_table[i].bw_bits);
 308                         if (ret < 0)
 309                                 return ret;
 310
 311                         data->bw_bits =
 312                                 bmc150_accel_samp_freq_table[i].bw_bits;
 313                         return 0;
 314                 }
 315         }
 316
 317         return -EINVAL;
 318 }
 319
 320 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
 321 {
 322         int ret;
 323
 324         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
 325                                         data->slope_thres);
 326         if (ret < 0) {
 327                 dev_err(data->dev, "Error writing reg_int_6\n");
 328                 return ret;
 329         }
 330
 331         ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
 332                                  BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
 333         if (ret < 0) {
 334                 dev_err(data->dev, "Error updating reg_int_5\n");
 335                 return ret;
 336         }
 337
 338         dev_dbg(data->dev, "%s: %x %x\n", __func__, data->slope_thres,
 339                 data->slope_dur);
 340
 341         return ret;
 342 }
 343
 344 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
 345                                          bool state)
 346 {
 347         if (state)
 348                 return bmc150_accel_update_slope(t->data);
 349
 350         return 0;
 351 }
 352
 353 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
 354                                int *val2)
 355 {
 356         int i;
 357
 358         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 359                 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
 360                         *val = bmc150_accel_samp_freq_table[i].val;
 361                         *val2 = bmc150_accel_samp_freq_table[i].val2;
 362                         return IIO_VAL_INT_PLUS_MICRO;
 363                 }
 364         }
 365
 366         return -EINVAL;
 367 }
 368
 369 #ifdef CONFIG_PM
 370 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
 371 {
 372         int i;
 373
 374         for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
 375                 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
 376                         return bmc150_accel_sample_upd_time[i].msec;
 377         }
 378
 379         return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
 380 }
 381
 382 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 383 {
 384         int ret;
 385
 386         if (on) {
 387                 ret = pm_runtime_get_sync(data->dev);
 388         } else {
 389                 pm_runtime_mark_last_busy(data->dev);
 390                 ret = pm_runtime_put_autosuspend(data->dev);
 391         }
 392
 393         if (ret < 0) {
 394                 dev_err(data->dev,
 395                         "Failed: bmc150_accel_set_power_state for %d\n", on);
 396                 if (on)
 397                         pm_runtime_put_noidle(data->dev);
 398
 399                 return ret;
 400         }
 401
 402         return 0;
 403 }
 404 #else
 405 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 406 {
 407         return 0;
 408 }
 409 #endif
 410
 411 static const struct bmc150_accel_interrupt_info {
 412         u8 map_reg;
 413         u8 map_bitmask;
 414         u8 en_reg;
 415         u8 en_bitmask;
 416 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
 417         { /* data ready interrupt */
 418                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 419                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
 420                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 421                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
 422         },
 423         {  /* motion interrupt */
 424                 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
 425                 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
 426                 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
 427                 .en_bitmask =  BMC150_ACCEL_INT_EN_BIT_SLP_X |
 428                         BMC150_ACCEL_INT_EN_BIT_SLP_Y |
 429                         BMC150_ACCEL_INT_EN_BIT_SLP_Z
 430         },
 431         { /* fifo watermark interrupt */
 432                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 433                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
 434                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 435                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
 436         },
 437 };
 438
 439 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
 440                                           struct bmc150_accel_data *data)
 441 {
 442         int i;
 443
 444         for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
 445                 data->interrupts[i].info = &bmc150_accel_interrupts[i];
 446 }
 447
 448 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
 449                                       bool state)
 450 {
 451         struct bmc150_accel_interrupt *intr = &data->interrupts[i];
 452         const struct bmc150_accel_interrupt_info *info = intr->info;
 453         int ret;
 454
 455         if (state) {
 456                 if (atomic_inc_return(&intr->users) > 1)
 457                         return 0;
 458         } else {
 459                 if (atomic_dec_return(&intr->users) > 0)
 460                         return 0;
 461         }
 462
 463         /*
 464          * We will expect the enable and disable to do operation in reverse
 465          * order. This will happen here anyway, as our resume operation uses
 466          * sync mode runtime pm calls. The suspend operation will be delayed
 467          * by autosuspend delay.
 468          * So the disable operation will still happen in reverse order of
 469          * enable operation. When runtime pm is disabled the mode is always on,
 470          * so sequence doesn't matter.
 471          */
 472         ret = bmc150_accel_set_power_state(data, state);
 473         if (ret < 0)
 474                 return ret;
 475
 476         /* map the interrupt to the appropriate pins */
 477         ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
 478                                  (state ? info->map_bitmask : 0));
 479         if (ret < 0) {
 480                 dev_err(data->dev, "Error updating reg_int_map\n");
 481                 goto out_fix_power_state;
 482         }
 483
 484         /* enable/disable the interrupt */
 485         ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
 486                                  (state ? info->en_bitmask : 0));
 487         if (ret < 0) {
 488                 dev_err(data->dev, "Error updating reg_int_en\n");
 489                 goto out_fix_power_state;
 490         }
 491
 492         if (state)
 493                 atomic_inc(&data->active_intr);
 494         else
 495                 atomic_dec(&data->active_intr);
 496
 497         return 0;
 498
 499 out_fix_power_state:
 500         bmc150_accel_set_power_state(data, false);
 501         return ret;
 502 }
 503
 504 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
 505 {
 506         int ret, i;
 507
 508         for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
 509                 if (data->chip_info->scale_table[i].scale == val) {
 510                         ret = regmap_write(data->regmap,
 511                                      BMC150_ACCEL_REG_PMU_RANGE,
 512                                      data->chip_info->scale_table[i].reg_range);
 513                         if (ret < 0) {
 514                                 dev_err(data->dev,
 515                                         "Error writing pmu_range\n");
 516                                 return ret;
 517                         }
 518
 519                         data->range = data->chip_info->scale_table[i].reg_range;
 520                         return 0;
 521                 }
 522         }
 523
 524         return -EINVAL;
 525 }
 526
 527 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
 528 {
 529         int ret;
 530         unsigned int value;
 531
 532         mutex_lock(&data->mutex);
 533
 534         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
 535         if (ret < 0) {
 536                 dev_err(data->dev, "Error reading reg_temp\n");
 537                 mutex_unlock(&data->mutex);
 538                 return ret;
 539         }
 540         *val = sign_extend32(value, 7);
 541
 542         mutex_unlock(&data->mutex);
 543
 544         return IIO_VAL_INT;
 545 }
 546
 547 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
 548                                  struct iio_chan_spec const *chan,
 549                                  int *val)
 550 {
 551         int ret;
 552         int axis = chan->scan_index;
 553         __le16 raw_val;
 554
 555         mutex_lock(&data->mutex);
 556         ret = bmc150_accel_set_power_state(data, true);
 557         if (ret < 0) {
 558                 mutex_unlock(&data->mutex);
 559                 return ret;
 560         }
 561
 562         ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
 563                                &raw_val, sizeof(raw_val));
 564         if (ret < 0) {
 565                 dev_err(data->dev, "Error reading axis %d\n", axis);
 566                 bmc150_accel_set_power_state(data, false);
 567                 mutex_unlock(&data->mutex);
 568                 return ret;
 569         }
 570         *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
 571                              chan->scan_type.realbits - 1);
 572         ret = bmc150_accel_set_power_state(data, false);
 573         mutex_unlock(&data->mutex);
 574         if (ret < 0)
 575                 return ret;
 576
 577         return IIO_VAL_INT;
 578 }
 579
 580 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
 581                                  struct iio_chan_spec const *chan,
 582                                  int *val, int *val2, long mask)
 583 {
 584         struct bmc150_accel_data *data = iio_priv(indio_dev);
 585         int ret;
 586
 587         switch (mask) {
 588         case IIO_CHAN_INFO_RAW:
 589                 switch (chan->type) {
 590                 case IIO_TEMP:
 591                         return bmc150_accel_get_temp(data, val);
 592                 case IIO_ACCEL:
 593                         if (iio_buffer_enabled(indio_dev))
 594                                 return -EBUSY;
 595                         else
 596                                 return bmc150_accel_get_axis(data, chan, val);
 597                 default:
 598                         return -EINVAL;
 599                 }
 600         case IIO_CHAN_INFO_OFFSET:
 601                 if (chan->type == IIO_TEMP) {
 602                         *val = BMC150_ACCEL_TEMP_CENTER_VAL;
 603                         return IIO_VAL_INT;
 604                 } else {
 605                         return -EINVAL;
 606                 }
 607         case IIO_CHAN_INFO_SCALE:
 608                 *val = 0;
 609                 switch (chan->type) {
 610                 case IIO_TEMP:
 611                         *val2 = 500000;
 612                         return IIO_VAL_INT_PLUS_MICRO;
 613                 case IIO_ACCEL:
 614                 {
 615                         int i;
 616                         const struct bmc150_scale_info *si;
 617                         int st_size = ARRAY_SIZE(data->chip_info->scale_table);
 618
 619                         for (i = 0; i < st_size; ++i) {
 620                                 si = &data->chip_info->scale_table[i];
 621                                 if (si->reg_range == data->range) {
 622                                         *val2 = si->scale;
 623                                         return IIO_VAL_INT_PLUS_MICRO;
 624                                 }
 625                         }
 626                         return -EINVAL;
 627                 }
 628                 default:
 629                         return -EINVAL;
 630                 }
 631         case IIO_CHAN_INFO_SAMP_FREQ:
 632                 mutex_lock(&data->mutex);
 633                 ret = bmc150_accel_get_bw(data, val, val2);
 634                 mutex_unlock(&data->mutex);
 635                 return ret;
 636         default:
 637                 return -EINVAL;
 638         }
 639 }
 640
 641 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
 642                                   struct iio_chan_spec const *chan,
 643                                   int val, int val2, long mask)
 644 {
 645         struct bmc150_accel_data *data = iio_priv(indio_dev);
 646         int ret;
 647
 648         switch (mask) {
 649         case IIO_CHAN_INFO_SAMP_FREQ:
 650                 mutex_lock(&data->mutex);
 651                 ret = bmc150_accel_set_bw(data, val, val2);
 652                 mutex_unlock(&data->mutex);
 653                 break;
 654         case IIO_CHAN_INFO_SCALE:
 655                 if (val)
 656                         return -EINVAL;
 657
 658                 mutex_lock(&data->mutex);
 659                 ret = bmc150_accel_set_scale(data, val2);
 660                 mutex_unlock(&data->mutex);
 661                 return ret;
 662         default:
 663                 ret = -EINVAL;
 664         }
 665
 666         return ret;
 667 }
 668
 669 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
 670                                    const struct iio_chan_spec *chan,
 671                                    enum iio_event_type type,
 672                                    enum iio_event_direction dir,
 673                                    enum iio_event_info info,
 674                                    int *val, int *val2)
 675 {
 676         struct bmc150_accel_data *data = iio_priv(indio_dev);
 677
 678         *val2 = 0;
 679         switch (info) {
 680         case IIO_EV_INFO_VALUE:
 681                 *val = data->slope_thres;
 682                 break;
 683         case IIO_EV_INFO_PERIOD:
 684                 *val = data->slope_dur;
 685                 break;
 686         default:
 687                 return -EINVAL;
 688         }
 689
 690         return IIO_VAL_INT;
 691 }
 692
 693 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
 694                                     const struct iio_chan_spec *chan,
 695                                     enum iio_event_type type,
 696                                     enum iio_event_direction dir,
 697                                     enum iio_event_info info,
 698                                     int val, int val2)
 699 {
 700         struct bmc150_accel_data *data = iio_priv(indio_dev);
 701
 702         if (data->ev_enable_state)
 703                 return -EBUSY;
 704
 705         switch (info) {
 706         case IIO_EV_INFO_VALUE:
 707                 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
 708                 break;
 709         case IIO_EV_INFO_PERIOD:
 710                 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
 711                 break;
 712         default:
 713                 return -EINVAL;
 714         }
 715
 716         return 0;
 717 }
 718
 719 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
 720                                           const struct iio_chan_spec *chan,
 721                                           enum iio_event_type type,
 722                                           enum iio_event_direction dir)
 723 {
 724         struct bmc150_accel_data *data = iio_priv(indio_dev);
 725
 726         return data->ev_enable_state;
 727 }
 728
 729 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
 730                                            const struct iio_chan_spec *chan,
 731                                            enum iio_event_type type,
 732                                            enum iio_event_direction dir,
 733                                            int state)
 734 {
 735         struct bmc150_accel_data *data = iio_priv(indio_dev);
 736         int ret;
 737
 738         if (state == data->ev_enable_state)
 739                 return 0;
 740
 741         mutex_lock(&data->mutex);
 742
 743         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
 744                                          state);
 745         if (ret < 0) {
 746                 mutex_unlock(&data->mutex);
 747                 return ret;
 748         }
 749
 750         data->ev_enable_state = state;
 751         mutex_unlock(&data->mutex);
 752
 753         return 0;
 754 }
 755
 756 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
 757                                          struct iio_trigger *trig)
 758 {
 759         struct bmc150_accel_data *data = iio_priv(indio_dev);
 760         int i;
 761
 762         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
 763                 if (data->triggers[i].indio_trig == trig)
 764                         return 0;
 765         }
 766
 767         return -EINVAL;
 768 }
 769
 770 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
 771                                                struct device_attribute *attr,
 772                                                char *buf)
 773 {
 774         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 775         struct bmc150_accel_data *data = iio_priv(indio_dev);
 776         int wm;
 777
 778         mutex_lock(&data->mutex);
 779         wm = data->watermark;
 780         mutex_unlock(&data->mutex);
 781
 782         return sprintf(buf, "%d\n", wm);
 783 }
 784
 785 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
 786                                            struct device_attribute *attr,
 787                                            char *buf)
 788 {
 789         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 790         struct bmc150_accel_data *data = iio_priv(indio_dev);
 791         bool state;
 792
 793         mutex_lock(&data->mutex);
 794         state = data->fifo_mode;
 795         mutex_unlock(&data->mutex);
 796
 797         return sprintf(buf, "%d\n", state);
 798 }
 799
 800 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
 801 static IIO_CONST_ATTR(hwfifo_watermark_max,
 802                       __stringify(BMC150_ACCEL_FIFO_LENGTH));
 803 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
 804                        bmc150_accel_get_fifo_state, NULL, 0);
 805 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
 806                        bmc150_accel_get_fifo_watermark, NULL, 0);
 807
 808 static const struct attribute *bmc150_accel_fifo_attributes[] = {
 809         &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
 810         &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
 811         &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
 812         &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
 813         NULL,
 814 };
 815
 816 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
 817 {
 818         struct bmc150_accel_data *data = iio_priv(indio_dev);
 819
 820         if (val > BMC150_ACCEL_FIFO_LENGTH)
 821                 val = BMC150_ACCEL_FIFO_LENGTH;
 822
 823         mutex_lock(&data->mutex);
 824         data->watermark = val;
 825         mutex_unlock(&data->mutex);
 826
 827         return 0;
 828 }
 829
 830 /*
 831  * We must read at least one full frame in one burst, otherwise the rest of the
 832  * frame data is discarded.
 833  */
 834 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
 835                                       char *buffer, int samples)
 836 {
 837         int sample_length = 3 * 2;
 838         int ret;
 839         int total_length = samples * sample_length;
 840         int i;
 841         size_t step = regmap_get_raw_read_max(data->regmap);
 842
 843         if (!step || step > total_length)
 844                 step = total_length;
 845         else if (step < total_length)
 846                 step = sample_length;
 847
 848         /*
 849          * Seems we have a bus with size limitation so we have to execute
 850          * multiple reads
 851          */
 852         for (i = 0; i < total_length; i += step) {
 853                 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
 854                                       &buffer[i], step);
 855                 if (ret)
 856                         break;
 857         }
 858
 859         if (ret)
 860                 dev_err(data->dev, "Error transferring data from fifo in single steps of %zu\n",
 861                         step);
 862
 863         return ret;
 864 }
 865
 866 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
 867                                      unsigned samples, bool irq)
 868 {
 869         struct bmc150_accel_data *data = iio_priv(indio_dev);
 870         int ret, i;
 871         u8 count;
 872         u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
 873         int64_t tstamp;
 874         uint64_t sample_period;
 875         unsigned int val;
 876
 877         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
 878         if (ret < 0) {
 879                 dev_err(data->dev, "Error reading reg_fifo_status\n");
 880                 return ret;
 881         }
 882
 883         count = val & 0x7F;
 884
 885         if (!count)
 886                 return 0;
 887
 888         /*
 889          * If we getting called from IRQ handler we know the stored timestamp is
 890          * fairly accurate for the last stored sample. Otherwise, if we are
 891          * called as a result of a read operation from userspace and hence
 892          * before the watermark interrupt was triggered, take a timestamp
 893          * now. We can fall anywhere in between two samples so the error in this
 894          * case is at most one sample period.
 895          */
 896         if (!irq) {
 897                 data->old_timestamp = data->timestamp;
 898                 data->timestamp = iio_get_time_ns();
 899         }
 900
 901         /*
 902          * Approximate timestamps for each of the sample based on the sampling
 903          * frequency, timestamp for last sample and number of samples.
 904          *
 905          * Note that we can't use the current bandwidth settings to compute the
 906          * sample period because the sample rate varies with the device
 907          * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
 908          * small variation adds when we store a large number of samples and
 909          * creates significant jitter between the last and first samples in
 910          * different batches (e.g. 32ms vs 21ms).
 911          *
 912          * To avoid this issue we compute the actual sample period ourselves
 913          * based on the timestamp delta between the last two flush operations.
 914          */
 915         sample_period = (data->timestamp - data->old_timestamp);
 916         do_div(sample_period, count);
 917         tstamp = data->timestamp - (count - 1) * sample_period;
 918
 919         if (samples && count > samples)
 920                 count = samples;
 921
 922         ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
 923         if (ret)
 924                 return ret;
 925
 926         /*
 927          * Ideally we want the IIO core to handle the demux when running in fifo
 928          * mode but not when running in triggered buffer mode. Unfortunately
 929          * this does not seem to be possible, so stick with driver demux for
 930          * now.
 931          */
 932         for (i = 0; i < count; i++) {
 933                 u16 sample[8];
 934                 int j, bit;
 935
 936                 j = 0;
 937                 for_each_set_bit(bit, indio_dev->active_scan_mask,
 938                                  indio_dev->masklength)
 939                         memcpy(&sample[j++], &buffer[i * 3 + bit], 2);
 940
 941                 iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp);
 942
 943                 tstamp += sample_period;
 944         }
 945
 946         return count;
 947 }
 948
 949 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
 950 {
 951         struct bmc150_accel_data *data = iio_priv(indio_dev);
 952         int ret;
 953
 954         mutex_lock(&data->mutex);
 955         ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
 956         mutex_unlock(&data->mutex);
 957
 958         return ret;
 959 }
 960
 961 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
 962                 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
 963
 964 static struct attribute *bmc150_accel_attributes[] = {
 965         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 966         NULL,
 967 };
 968
 969 static const struct attribute_group bmc150_accel_attrs_group = {
 970         .attrs = bmc150_accel_attributes,
 971 };
 972
 973 static const struct iio_event_spec bmc150_accel_event = {
 974                 .type = IIO_EV_TYPE_ROC,
 975                 .dir = IIO_EV_DIR_EITHER,
 976                 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
 977                                  BIT(IIO_EV_INFO_ENABLE) |
 978                                  BIT(IIO_EV_INFO_PERIOD)
 979 };
 980
 981 #define BMC150_ACCEL_CHANNEL(_axis, bits) {                             \
 982         .type = IIO_ACCEL,                                              \
 983         .modified = 1,                                                  \
 984         .channel2 = IIO_MOD_##_axis,                                    \
 985         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),                   \
 986         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |          \
 987                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),           \
 988         .scan_index = AXIS_##_axis,                                     \
 989         .scan_type = {                                                  \
 990                 .sign = 's',                                            \
 991                 .realbits = (bits),                                     \
 992                 .storagebits = 16,                                      \
 993                 .shift = 16 - (bits),                                   \
 994                 .endianness = IIO_LE,                                   \
 995         },                                                              \
 996         .event_spec = &bmc150_accel_event,                              \
 997         .num_event_specs = 1                                            \
 998 }
 999
1000 #define BMC150_ACCEL_CHANNELS(bits) {                                   \
1001         {                                                               \
1002                 .type = IIO_TEMP,                                       \
1003                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
1004                                       BIT(IIO_CHAN_INFO_SCALE) |        \
1005                                       BIT(IIO_CHAN_INFO_OFFSET),        \
1006                 .scan_index = -1,                                       \
1007         },                                                              \
1008         BMC150_ACCEL_CHANNEL(X, bits),                                  \
1009         BMC150_ACCEL_CHANNEL(Y, bits),                                  \
1010         BMC150_ACCEL_CHANNEL(Z, bits),                                  \
1011         IIO_CHAN_SOFT_TIMESTAMP(3),                                     \
1012 }
1013
1014 static const struct iio_chan_spec bma222e_accel_channels[] =
1015         BMC150_ACCEL_CHANNELS(8);
1016 static const struct iio_chan_spec bma250e_accel_channels[] =
1017         BMC150_ACCEL_CHANNELS(10);
1018 static const struct iio_chan_spec bmc150_accel_channels[] =
1019         BMC150_ACCEL_CHANNELS(12);
1020 static const struct iio_chan_spec bma280_accel_channels[] =
1021         BMC150_ACCEL_CHANNELS(14);
1022
1023 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1024         [bmc150] = {
1025                 .name = "BMC150A",
1026                 .chip_id = 0xFA,
1027                 .channels = bmc150_accel_channels,
1028                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1029                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1030                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1031                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1032                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1033         },
1034         [bmi055] = {
1035                 .name = "BMI055A",
1036                 .chip_id = 0xFA,
1037                 .channels = bmc150_accel_channels,
1038                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1039                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1040                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1041                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1042                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1043         },
1044         [bma255] = {
1045                 .name = "BMA0255",
1046                 .chip_id = 0xFA,
1047                 .channels = bmc150_accel_channels,
1048                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1049                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1050                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1051                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1052                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1053         },
1054         [bma250e] = {
1055                 .name = "BMA250E",
1056                 .chip_id = 0xF9,
1057                 .channels = bma250e_accel_channels,
1058                 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1059                 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1060                                  {76590, BMC150_ACCEL_DEF_RANGE_4G},
1061                                  {153277, BMC150_ACCEL_DEF_RANGE_8G},
1062                                  {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1063         },
1064         [bma222e] = {
1065                 .name = "BMA222E",
1066                 .chip_id = 0xF8,
1067                 .channels = bma222e_accel_channels,
1068                 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1069                 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1070                                  {306457, BMC150_ACCEL_DEF_RANGE_4G},
1071                                  {612915, BMC150_ACCEL_DEF_RANGE_8G},
1072                                  {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1073         },
1074         [bma280] = {
1075                 .name = "BMA0280",
1076                 .chip_id = 0xFB,
1077                 .channels = bma280_accel_channels,
1078                 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1079                 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1080                                  {4785, BMC150_ACCEL_DEF_RANGE_4G},
1081                                  {9581, BMC150_ACCEL_DEF_RANGE_8G},
1082                                  {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1083         },
1084 };
1085
1086 static const struct iio_info bmc150_accel_info = {
1087         .attrs                  = &bmc150_accel_attrs_group,
1088         .read_raw               = bmc150_accel_read_raw,
1089         .write_raw              = bmc150_accel_write_raw,
1090         .read_event_value       = bmc150_accel_read_event,
1091         .write_event_value      = bmc150_accel_write_event,
1092         .write_event_config     = bmc150_accel_write_event_config,
1093         .read_event_config      = bmc150_accel_read_event_config,
1094         .driver_module          = THIS_MODULE,
1095 };
1096
1097 static const struct iio_info bmc150_accel_info_fifo = {
1098         .attrs                  = &bmc150_accel_attrs_group,
1099         .read_raw               = bmc150_accel_read_raw,
1100         .write_raw              = bmc150_accel_write_raw,
1101         .read_event_value       = bmc150_accel_read_event,
1102         .write_event_value      = bmc150_accel_write_event,
1103         .write_event_config     = bmc150_accel_write_event_config,
1104         .read_event_config      = bmc150_accel_read_event_config,
1105         .validate_trigger       = bmc150_accel_validate_trigger,
1106         .hwfifo_set_watermark   = bmc150_accel_set_watermark,
1107         .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1108         .driver_module          = THIS_MODULE,
1109 };
1110
1111 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1112 {
1113         struct iio_poll_func *pf = p;
1114         struct iio_dev *indio_dev = pf->indio_dev;
1115         struct bmc150_accel_data *data = iio_priv(indio_dev);
1116         int bit, ret, i = 0;
1117         unsigned int raw_val;
1118
1119         mutex_lock(&data->mutex);
1120         for_each_set_bit(bit, indio_dev->active_scan_mask,
1121                          indio_dev->masklength) {
1122                 ret = regmap_bulk_read(data->regmap,
1123                                        BMC150_ACCEL_AXIS_TO_REG(bit), &raw_val,
1124                                        2);
1125                 if (ret < 0) {
1126                         mutex_unlock(&data->mutex);
1127                         goto err_read;
1128                 }
1129                 data->buffer[i++] = raw_val;
1130         }
1131         mutex_unlock(&data->mutex);
1132
1133         iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1134                                            pf->timestamp);
1135 err_read:
1136         iio_trigger_notify_done(indio_dev->trig);
1137
1138         return IRQ_HANDLED;
1139 }
1140
1141 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1142 {
1143         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1144         struct bmc150_accel_data *data = t->data;
1145         int ret;
1146
1147         /* new data interrupts don't need ack */
1148         if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1149                 return 0;
1150
1151         mutex_lock(&data->mutex);
1152         /* clear any latched interrupt */
1153         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1154                            BMC150_ACCEL_INT_MODE_LATCH_INT |
1155                            BMC150_ACCEL_INT_MODE_LATCH_RESET);
1156         mutex_unlock(&data->mutex);
1157         if (ret < 0) {
1158                 dev_err(data->dev,
1159                         "Error writing reg_int_rst_latch\n");
1160                 return ret;
1161         }
1162
1163         return 0;
1164 }
1165
1166 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1167                                           bool state)
1168 {
1169         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1170         struct bmc150_accel_data *data = t->data;
1171         int ret;
1172
1173         mutex_lock(&data->mutex);
1174
1175         if (t->enabled == state) {
1176                 mutex_unlock(&data->mutex);
1177                 return 0;
1178         }
1179
1180         if (t->setup) {
1181                 ret = t->setup(t, state);
1182                 if (ret < 0) {
1183                         mutex_unlock(&data->mutex);
1184                         return ret;
1185                 }
1186         }
1187
1188         ret = bmc150_accel_set_interrupt(data, t->intr, state);
1189         if (ret < 0) {
1190                 mutex_unlock(&data->mutex);
1191                 return ret;
1192         }
1193
1194         t->enabled = state;
1195
1196         mutex_unlock(&data->mutex);
1197
1198         return ret;
1199 }
1200
1201 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1202         .set_trigger_state = bmc150_accel_trigger_set_state,
1203         .try_reenable = bmc150_accel_trig_try_reen,
1204         .owner = THIS_MODULE,
1205 };
1206
1207 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1208 {
1209         struct bmc150_accel_data *data = iio_priv(indio_dev);
1210         int dir;
1211         int ret;
1212         unsigned int val;
1213
1214         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1215         if (ret < 0) {
1216                 dev_err(data->dev, "Error reading reg_int_status_2\n");
1217                 return ret;
1218         }
1219
1220         if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1221                 dir = IIO_EV_DIR_FALLING;
1222         else
1223                 dir = IIO_EV_DIR_RISING;
1224
1225         if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1226                 iio_push_event(indio_dev,
1227                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1228                                                   0,
1229                                                   IIO_MOD_X,
1230                                                   IIO_EV_TYPE_ROC,
1231                                                   dir),
1232                                data->timestamp);
1233
1234         if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1235                 iio_push_event(indio_dev,
1236                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1237                                                   0,
1238                                                   IIO_MOD_Y,
1239                                                   IIO_EV_TYPE_ROC,
1240                                                   dir),
1241                                data->timestamp);
1242
1243         if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1244                 iio_push_event(indio_dev,
1245                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1246                                                   0,
1247                                                   IIO_MOD_Z,
1248                                                   IIO_EV_TYPE_ROC,
1249                                                   dir),
1250                                data->timestamp);
1251
1252         return ret;
1253 }
1254
1255 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1256 {
1257         struct iio_dev *indio_dev = private;
1258         struct bmc150_accel_data *data = iio_priv(indio_dev);
1259         bool ack = false;
1260         int ret;
1261
1262         mutex_lock(&data->mutex);
1263
1264         if (data->fifo_mode) {
1265                 ret = __bmc150_accel_fifo_flush(indio_dev,
1266                                                 BMC150_ACCEL_FIFO_LENGTH, true);
1267                 if (ret > 0)
1268                         ack = true;
1269         }
1270
1271         if (data->ev_enable_state) {
1272                 ret = bmc150_accel_handle_roc_event(indio_dev);
1273                 if (ret > 0)
1274                         ack = true;
1275         }
1276
1277         if (ack) {
1278                 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1279                                    BMC150_ACCEL_INT_MODE_LATCH_INT |
1280                                    BMC150_ACCEL_INT_MODE_LATCH_RESET);
1281                 if (ret)
1282                         dev_err(data->dev, "Error writing reg_int_rst_latch\n");
1283
1284                 ret = IRQ_HANDLED;
1285         } else {
1286                 ret = IRQ_NONE;
1287         }
1288
1289         mutex_unlock(&data->mutex);
1290
1291         return ret;
1292 }
1293
1294 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1295 {
1296         struct iio_dev *indio_dev = private;
1297         struct bmc150_accel_data *data = iio_priv(indio_dev);
1298         bool ack = false;
1299         int i;
1300
1301         data->old_timestamp = data->timestamp;
1302         data->timestamp = iio_get_time_ns();
1303
1304         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1305                 if (data->triggers[i].enabled) {
1306                         iio_trigger_poll(data->triggers[i].indio_trig);
1307                         ack = true;
1308                         break;
1309                 }
1310         }
1311
1312         if (data->ev_enable_state || data->fifo_mode)
1313                 return IRQ_WAKE_THREAD;
1314
1315         if (ack)
1316                 return IRQ_HANDLED;
1317
1318         return IRQ_NONE;
1319 }
1320
1321 static const struct {
1322         int intr;
1323         const char *name;
1324         int (*setup)(struct bmc150_accel_trigger *t, bool state);
1325 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1326         {
1327                 .intr = 0,
1328                 .name = "%s-dev%d",
1329         },
1330         {
1331                 .intr = 1,
1332                 .name = "%s-any-motion-dev%d",
1333                 .setup = bmc150_accel_any_motion_setup,
1334         },
1335 };
1336
1337 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1338                                              int from)
1339 {
1340         int i;
1341
1342         for (i = from; i >= 0; i--) {
1343                 if (data->triggers[i].indio_trig) {
1344                         iio_trigger_unregister(data->triggers[i].indio_trig);
1345                         data->triggers[i].indio_trig = NULL;
1346                 }
1347         }
1348 }
1349
1350 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1351                                        struct bmc150_accel_data *data)
1352 {
1353         int i, ret;
1354
1355         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1356                 struct bmc150_accel_trigger *t = &data->triggers[i];
1357
1358                 t->indio_trig = devm_iio_trigger_alloc(data->dev,
1359                                                bmc150_accel_triggers[i].name,
1360                                                        indio_dev->name,
1361                                                        indio_dev->id);
1362                 if (!t->indio_trig) {
1363                         ret = -ENOMEM;
1364                         break;
1365                 }
1366
1367                 t->indio_trig->dev.parent = data->dev;
1368                 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1369                 t->intr = bmc150_accel_triggers[i].intr;
1370                 t->data = data;
1371                 t->setup = bmc150_accel_triggers[i].setup;
1372                 iio_trigger_set_drvdata(t->indio_trig, t);
1373
1374                 ret = iio_trigger_register(t->indio_trig);
1375                 if (ret)
1376                         break;
1377         }
1378
1379         if (ret)
1380                 bmc150_accel_unregister_triggers(data, i - 1);
1381
1382         return ret;
1383 }
1384
1385 #define BMC150_ACCEL_FIFO_MODE_STREAM          0x80
1386 #define BMC150_ACCEL_FIFO_MODE_FIFO            0x40
1387 #define BMC150_ACCEL_FIFO_MODE_BYPASS          0x00
1388
1389 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1390 {
1391         u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1392         int ret;
1393
1394         ret = regmap_write(data->regmap, reg, data->fifo_mode);
1395         if (ret < 0) {
1396                 dev_err(data->dev, "Error writing reg_fifo_config1\n");
1397                 return ret;
1398         }
1399
1400         if (!data->fifo_mode)
1401                 return 0;
1402
1403         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1404                            data->watermark);
1405         if (ret < 0)
1406                 dev_err(data->dev, "Error writing reg_fifo_config0\n");
1407
1408         return ret;
1409 }
1410
1411 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1412 {
1413         struct bmc150_accel_data *data = iio_priv(indio_dev);
1414
1415         return bmc150_accel_set_power_state(data, true);
1416 }
1417
1418 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1419 {
1420         struct bmc150_accel_data *data = iio_priv(indio_dev);
1421         int ret = 0;
1422
1423         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1424                 return iio_triggered_buffer_postenable(indio_dev);
1425
1426         mutex_lock(&data->mutex);
1427
1428         if (!data->watermark)
1429                 goto out;
1430
1431         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1432                                          true);
1433         if (ret)
1434                 goto out;
1435
1436         data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1437
1438         ret = bmc150_accel_fifo_set_mode(data);
1439         if (ret) {
1440                 data->fifo_mode = 0;
1441                 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1442                                            false);
1443         }
1444
1445 out:
1446         mutex_unlock(&data->mutex);
1447
1448         return ret;
1449 }
1450
1451 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1452 {
1453         struct bmc150_accel_data *data = iio_priv(indio_dev);
1454
1455         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1456                 return iio_triggered_buffer_predisable(indio_dev);
1457
1458         mutex_lock(&data->mutex);
1459
1460         if (!data->fifo_mode)
1461                 goto out;
1462
1463         bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1464         __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1465         data->fifo_mode = 0;
1466         bmc150_accel_fifo_set_mode(data);
1467
1468 out:
1469         mutex_unlock(&data->mutex);
1470
1471         return 0;
1472 }
1473
1474 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1475 {
1476         struct bmc150_accel_data *data = iio_priv(indio_dev);
1477
1478         return bmc150_accel_set_power_state(data, false);
1479 }
1480
1481 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1482         .preenable = bmc150_accel_buffer_preenable,
1483         .postenable = bmc150_accel_buffer_postenable,
1484         .predisable = bmc150_accel_buffer_predisable,
1485         .postdisable = bmc150_accel_buffer_postdisable,
1486 };
1487
1488 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1489 {
1490         int ret, i;
1491         unsigned int val;
1492
1493         /*
1494          * Reset chip to get it in a known good state. A delay of 1.8ms after
1495          * reset is required according to the data sheets of supported chips.
1496          */
1497         regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1498                      BMC150_ACCEL_RESET_VAL);
1499         usleep_range(1800, 2500);
1500
1501         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1502         if (ret < 0) {
1503                 dev_err(data->dev,
1504                         "Error: Reading chip id\n");
1505                 return ret;
1506         }
1507
1508         dev_dbg(data->dev, "Chip Id %x\n", val);
1509         for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1510                 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1511                         data->chip_info = &bmc150_accel_chip_info_tbl[i];
1512                         break;
1513                 }
1514         }
1515
1516         if (!data->chip_info) {
1517                 dev_err(data->dev, "Invalid chip %x\n", val);
1518                 return -ENODEV;
1519         }
1520
1521         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1522         if (ret < 0)
1523                 return ret;
1524
1525         /* Set Bandwidth */
1526         ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1527         if (ret < 0)
1528                 return ret;
1529
1530         /* Set Default Range */
1531         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1532                            BMC150_ACCEL_DEF_RANGE_4G);
1533         if (ret < 0) {
1534                 dev_err(data->dev,
1535                                         "Error writing reg_pmu_range\n");
1536                 return ret;
1537         }
1538
1539         data->range = BMC150_ACCEL_DEF_RANGE_4G;
1540
1541         /* Set default slope duration and thresholds */
1542         data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1543         data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1544         ret = bmc150_accel_update_slope(data);
1545         if (ret < 0)
1546                 return ret;
1547
1548         /* Set default as latched interrupts */
1549         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1550                            BMC150_ACCEL_INT_MODE_LATCH_INT |
1551                            BMC150_ACCEL_INT_MODE_LATCH_RESET);
1552         if (ret < 0) {
1553                 dev_err(data->dev,
1554                         "Error writing reg_int_rst_latch\n");
1555                 return ret;
1556         }
1557
1558         return 0;
1559 }
1560
1561 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1562                             const char *name, bool block_supported)
1563 {
1564         struct bmc150_accel_data *data;
1565         struct iio_dev *indio_dev;
1566         int ret;
1567
1568         indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1569         if (!indio_dev)
1570                 return -ENOMEM;
1571
1572         data = iio_priv(indio_dev);
1573         dev_set_drvdata(dev, indio_dev);
1574         data->dev = dev;
1575         data->irq = irq;
1576
1577         data->regmap = regmap;
1578
1579         ret = bmc150_accel_chip_init(data);
1580         if (ret < 0)
1581                 return ret;
1582
1583         mutex_init(&data->mutex);
1584
1585         indio_dev->dev.parent = dev;
1586         indio_dev->channels = data->chip_info->channels;
1587         indio_dev->num_channels = data->chip_info->num_channels;
1588         indio_dev->name = name ? name : data->chip_info->name;
1589         indio_dev->modes = INDIO_DIRECT_MODE;
1590         indio_dev->info = &bmc150_accel_info;
1591
1592         ret = iio_triggered_buffer_setup(indio_dev,
1593                                          &iio_pollfunc_store_time,
1594                                          bmc150_accel_trigger_handler,
1595                                          &bmc150_accel_buffer_ops);
1596         if (ret < 0) {
1597                 dev_err(data->dev, "Failed: iio triggered buffer setup\n");
1598                 return ret;
1599         }
1600
1601         if (data->irq > 0) {
1602                 ret = devm_request_threaded_irq(
1603                                                 data->dev, data->irq,
1604                                                 bmc150_accel_irq_handler,
1605                                                 bmc150_accel_irq_thread_handler,
1606                                                 IRQF_TRIGGER_RISING,
1607                                                 BMC150_ACCEL_IRQ_NAME,
1608                                                 indio_dev);
1609                 if (ret)
1610                         goto err_buffer_cleanup;
1611
1612                 /*
1613                  * Set latched mode interrupt. While certain interrupts are
1614                  * non-latched regardless of this settings (e.g. new data) we
1615                  * want to use latch mode when we can to prevent interrupt
1616                  * flooding.
1617                  */
1618                 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1619                                    BMC150_ACCEL_INT_MODE_LATCH_RESET);
1620                 if (ret < 0) {
1621                         dev_err(data->dev, "Error writing reg_int_rst_latch\n");
1622                         goto err_buffer_cleanup;
1623                 }
1624
1625                 bmc150_accel_interrupts_setup(indio_dev, data);
1626
1627                 ret = bmc150_accel_triggers_setup(indio_dev, data);
1628                 if (ret)
1629                         goto err_buffer_cleanup;
1630
1631                 if (block_supported) {
1632                         indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1633                         indio_dev->info = &bmc150_accel_info_fifo;
1634                         indio_dev->buffer->attrs = bmc150_accel_fifo_attributes;
1635                 }
1636         }
1637
1638         ret = iio_device_register(indio_dev);
1639         if (ret < 0) {
1640                 dev_err(dev, "Unable to register iio device\n");
1641                 goto err_trigger_unregister;
1642         }
1643
1644         ret = pm_runtime_set_active(dev);
1645         if (ret)
1646                 goto err_iio_unregister;
1647
1648         pm_runtime_enable(dev);
1649         pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1650         pm_runtime_use_autosuspend(dev);
1651
1652         return 0;
1653
1654 err_iio_unregister:
1655         iio_device_unregister(indio_dev);
1656 err_trigger_unregister:
1657         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1658 err_buffer_cleanup:
1659         iio_triggered_buffer_cleanup(indio_dev);
1660
1661         return ret;
1662 }
1663 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1664
1665 int bmc150_accel_core_remove(struct device *dev)
1666 {
1667         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1668         struct bmc150_accel_data *data = iio_priv(indio_dev);
1669
1670         pm_runtime_disable(data->dev);
1671         pm_runtime_set_suspended(data->dev);
1672         pm_runtime_put_noidle(data->dev);
1673
1674         iio_device_unregister(indio_dev);
1675
1676         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1677
1678         iio_triggered_buffer_cleanup(indio_dev);
1679
1680         mutex_lock(&data->mutex);
1681         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1682         mutex_unlock(&data->mutex);
1683
1684         return 0;
1685 }
1686 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1687
1688 #ifdef CONFIG_PM_SLEEP
1689 static int bmc150_accel_suspend(struct device *dev)
1690 {
1691         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1692         struct bmc150_accel_data *data = iio_priv(indio_dev);
1693
1694         mutex_lock(&data->mutex);
1695         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1696         mutex_unlock(&data->mutex);
1697
1698         return 0;
1699 }
1700
1701 static int bmc150_accel_resume(struct device *dev)
1702 {
1703         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1704         struct bmc150_accel_data *data = iio_priv(indio_dev);
1705
1706         mutex_lock(&data->mutex);
1707         if (atomic_read(&data->active_intr))
1708                 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1709         bmc150_accel_fifo_set_mode(data);
1710         mutex_unlock(&data->mutex);
1711
1712         return 0;
1713 }
1714 #endif
1715
1716 #ifdef CONFIG_PM
1717 static int bmc150_accel_runtime_suspend(struct device *dev)
1718 {
1719         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1720         struct bmc150_accel_data *data = iio_priv(indio_dev);
1721         int ret;
1722
1723         dev_dbg(data->dev,  __func__);
1724         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1725         if (ret < 0)
1726                 return -EAGAIN;
1727
1728         return 0;
1729 }
1730
1731 static int bmc150_accel_runtime_resume(struct device *dev)
1732 {
1733         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1734         struct bmc150_accel_data *data = iio_priv(indio_dev);
1735         int ret;
1736         int sleep_val;
1737
1738         dev_dbg(data->dev,  __func__);
1739
1740         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1741         if (ret < 0)
1742                 return ret;
1743         ret = bmc150_accel_fifo_set_mode(data);
1744         if (ret < 0)
1745                 return ret;
1746
1747         sleep_val = bmc150_accel_get_startup_times(data);
1748         if (sleep_val < 20)
1749                 usleep_range(sleep_val * 1000, 20000);
1750         else
1751                 msleep_interruptible(sleep_val);
1752
1753         return 0;
1754 }
1755 #endif
1756
1757 const struct dev_pm_ops bmc150_accel_pm_ops = {
1758         SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1759         SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1760                            bmc150_accel_runtime_resume, NULL)
1761 };
1762 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1763
1764 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1765 MODULE_LICENSE("GPL v2");
1766 MODULE_DESCRIPTION("BMC150 accelerometer driver");