kernel/drivers/idle/intel_idle.c

   1 /*
   2  * intel_idle.c - native hardware idle loop for modern Intel processors
   3  *
   4  * Copyright (c) 2013, Intel Corporation.
   5  * Len Brown <len.brown@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 /*
  22  * intel_idle is a cpuidle driver that loads on specific Intel processors
  23  * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  24  * make Linux more efficient on these processors, as intel_idle knows
  25  * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  26  */
  27
  28 /*
  29  * Design Assumptions
  30  *
  31  * All CPUs have same idle states as boot CPU
  32  *
  33  * Chipset BM_STS (bus master status) bit is a NOP
  34  *      for preventing entry into deep C-stats
  35  */
  36
  37 /*
  38  * Known limitations
  39  *
  40  * The driver currently initializes for_each_online_cpu() upon modprobe.
  41  * It it unaware of subsequent processors hot-added to the system.
  42  * This means that if you boot with maxcpus=n and later online
  43  * processors above n, those processors will use C1 only.
  44  *
  45  * ACPI has a .suspend hack to turn off deep c-statees during suspend
  46  * to avoid complications with the lapic timer workaround.
  47  * Have not seen issues with suspend, but may need same workaround here.
  48  *
  49  * There is currently no kernel-based automatic probing/loading mechanism
  50  * if the driver is built as a module.
  51  */
  52
  53 /* un-comment DEBUG to enable pr_debug() statements */
  54 #define DEBUG
  55
  56 #include <linux/kernel.h>
  57 #include <linux/cpuidle.h>
  58 #include <linux/tick.h>
  59 #include <trace/events/power.h>
  60 #include <linux/sched.h>
  61 #include <linux/notifier.h>
  62 #include <linux/cpu.h>
  63 #include <linux/module.h>
  64 #include <asm/cpu_device_id.h>
  65 #include <asm/mwait.h>
  66 #include <asm/msr.h>
  67
  68 #define INTEL_IDLE_VERSION "0.4"
  69 #define PREFIX "intel_idle: "
  70
  71 static struct cpuidle_driver intel_idle_driver = {
  72         .name = "intel_idle",
  73         .owner = THIS_MODULE,
  74 };
  75 /* intel_idle.max_cstate=0 disables driver */
  76 static int max_cstate = CPUIDLE_STATE_MAX - 1;
  77
  78 static unsigned int mwait_substates;
  79
  80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
  81 /* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
  82 static unsigned int lapic_timer_reliable_states = (1 << 1);      /* Default to only C1 */
  83
  84 struct idle_cpu {
  85         struct cpuidle_state *state_table;
  86
  87         /*
  88          * Hardware C-state auto-demotion may not always be optimal.
  89          * Indicate which enable bits to clear here.
  90          */
  91         unsigned long auto_demotion_disable_flags;
  92         bool byt_auto_demotion_disable_flag;
  93         bool disable_promotion_to_c1e;
  94 };
  95
  96 static const struct idle_cpu *icpu;
  97 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  98 static int intel_idle(struct cpuidle_device *dev,
  99                         struct cpuidle_driver *drv, int index);
 100 static void intel_idle_freeze(struct cpuidle_device *dev,
 101                               struct cpuidle_driver *drv, int index);
 102 static int intel_idle_cpu_init(int cpu);
 103
 104 static struct cpuidle_state *cpuidle_state_table;
 105
 106 /*
 107  * Set this flag for states where the HW flushes the TLB for us
 108  * and so we don't need cross-calls to keep it consistent.
 109  * If this flag is set, SW flushes the TLB, so even if the
 110  * HW doesn't do the flushing, this flag is safe to use.
 111  */
 112 #define CPUIDLE_FLAG_TLB_FLUSHED        0x10000
 113
 114 /*
 115  * MWAIT takes an 8-bit "hint" in EAX "suggesting"
 116  * the C-state (top nibble) and sub-state (bottom nibble)
 117  * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
 118  *
 119  * We store the hint at the top of our "flags" for each state.
 120  */
 121 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
 122 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
 123
 124 /*
 125  * States are indexed by the cstate number,
 126  * which is also the index into the MWAIT hint array.
 127  * Thus C0 is a dummy.
 128  */
 129 static struct cpuidle_state nehalem_cstates[] = {
 130         {
 131                 .name = "C1-NHM",
 132                 .desc = "MWAIT 0x00",
 133                 .flags = MWAIT2flg(0x00),
 134                 .exit_latency = 3,
 135                 .target_residency = 6,
 136                 .enter = &intel_idle,
 137                 .enter_freeze = intel_idle_freeze, },
 138         {
 139                 .name = "C1E-NHM",
 140                 .desc = "MWAIT 0x01",
 141                 .flags = MWAIT2flg(0x01),
 142                 .exit_latency = 10,
 143                 .target_residency = 20,
 144                 .enter = &intel_idle,
 145                 .enter_freeze = intel_idle_freeze, },
 146         {
 147                 .name = "C3-NHM",
 148                 .desc = "MWAIT 0x10",
 149                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 150                 .exit_latency = 20,
 151                 .target_residency = 80,
 152                 .enter = &intel_idle,
 153                 .enter_freeze = intel_idle_freeze, },
 154         {
 155                 .name = "C6-NHM",
 156                 .desc = "MWAIT 0x20",
 157                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 158                 .exit_latency = 200,
 159                 .target_residency = 800,
 160                 .enter = &intel_idle,
 161                 .enter_freeze = intel_idle_freeze, },
 162         {
 163                 .enter = NULL }
 164 };
 165
 166 static struct cpuidle_state snb_cstates[] = {
 167         {
 168                 .name = "C1-SNB",
 169                 .desc = "MWAIT 0x00",
 170                 .flags = MWAIT2flg(0x00),
 171                 .exit_latency = 2,
 172                 .target_residency = 2,
 173                 .enter = &intel_idle,
 174                 .enter_freeze = intel_idle_freeze, },
 175         {
 176                 .name = "C1E-SNB",
 177                 .desc = "MWAIT 0x01",
 178                 .flags = MWAIT2flg(0x01),
 179                 .exit_latency = 10,
 180                 .target_residency = 20,
 181                 .enter = &intel_idle,
 182                 .enter_freeze = intel_idle_freeze, },
 183         {
 184                 .name = "C3-SNB",
 185                 .desc = "MWAIT 0x10",
 186                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 187                 .exit_latency = 80,
 188                 .target_residency = 211,
 189                 .enter = &intel_idle,
 190                 .enter_freeze = intel_idle_freeze, },
 191         {
 192                 .name = "C6-SNB",
 193                 .desc = "MWAIT 0x20",
 194                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 195                 .exit_latency = 104,
 196                 .target_residency = 345,
 197                 .enter = &intel_idle,
 198                 .enter_freeze = intel_idle_freeze, },
 199         {
 200                 .name = "C7-SNB",
 201                 .desc = "MWAIT 0x30",
 202                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
 203                 .exit_latency = 109,
 204                 .target_residency = 345,
 205                 .enter = &intel_idle,
 206                 .enter_freeze = intel_idle_freeze, },
 207         {
 208                 .enter = NULL }
 209 };
 210
 211 static struct cpuidle_state byt_cstates[] = {
 212         {
 213                 .name = "C1-BYT",
 214                 .desc = "MWAIT 0x00",
 215                 .flags = MWAIT2flg(0x00),
 216                 .exit_latency = 1,
 217                 .target_residency = 1,
 218                 .enter = &intel_idle,
 219                 .enter_freeze = intel_idle_freeze, },
 220         {
 221                 .name = "C6N-BYT",
 222                 .desc = "MWAIT 0x58",
 223                 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
 224                 .exit_latency = 300,
 225                 .target_residency = 275,
 226                 .enter = &intel_idle,
 227                 .enter_freeze = intel_idle_freeze, },
 228         {
 229                 .name = "C6S-BYT",
 230                 .desc = "MWAIT 0x52",
 231                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
 232                 .exit_latency = 500,
 233                 .target_residency = 560,
 234                 .enter = &intel_idle,
 235                 .enter_freeze = intel_idle_freeze, },
 236         {
 237                 .name = "C7-BYT",
 238                 .desc = "MWAIT 0x60",
 239                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 240                 .exit_latency = 1200,
 241                 .target_residency = 4000,
 242                 .enter = &intel_idle,
 243                 .enter_freeze = intel_idle_freeze, },
 244         {
 245                 .name = "C7S-BYT",
 246                 .desc = "MWAIT 0x64",
 247                 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
 248                 .exit_latency = 10000,
 249                 .target_residency = 20000,
 250                 .enter = &intel_idle,
 251                 .enter_freeze = intel_idle_freeze, },
 252         {
 253                 .enter = NULL }
 254 };
 255
 256 static struct cpuidle_state cht_cstates[] = {
 257         {
 258                 .name = "C1-CHT",
 259                 .desc = "MWAIT 0x00",
 260                 .flags = MWAIT2flg(0x00),
 261                 .exit_latency = 1,
 262                 .target_residency = 1,
 263                 .enter = &intel_idle,
 264                 .enter_freeze = intel_idle_freeze, },
 265         {
 266                 .name = "C6N-CHT",
 267                 .desc = "MWAIT 0x58",
 268                 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
 269                 .exit_latency = 80,
 270                 .target_residency = 275,
 271                 .enter = &intel_idle,
 272                 .enter_freeze = intel_idle_freeze, },
 273         {
 274                 .name = "C6S-CHT",
 275                 .desc = "MWAIT 0x52",
 276                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
 277                 .exit_latency = 200,
 278                 .target_residency = 560,
 279                 .enter = &intel_idle,
 280                 .enter_freeze = intel_idle_freeze, },
 281         {
 282                 .name = "C7-CHT",
 283                 .desc = "MWAIT 0x60",
 284                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 285                 .exit_latency = 1200,
 286                 .target_residency = 4000,
 287                 .enter = &intel_idle,
 288                 .enter_freeze = intel_idle_freeze, },
 289         {
 290                 .name = "C7S-CHT",
 291                 .desc = "MWAIT 0x64",
 292                 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
 293                 .exit_latency = 10000,
 294                 .target_residency = 20000,
 295                 .enter = &intel_idle,
 296                 .enter_freeze = intel_idle_freeze, },
 297         {
 298                 .enter = NULL }
 299 };
 300
 301 static struct cpuidle_state ivb_cstates[] = {
 302         {
 303                 .name = "C1-IVB",
 304                 .desc = "MWAIT 0x00",
 305                 .flags = MWAIT2flg(0x00),
 306                 .exit_latency = 1,
 307                 .target_residency = 1,
 308                 .enter = &intel_idle,
 309                 .enter_freeze = intel_idle_freeze, },
 310         {
 311                 .name = "C1E-IVB",
 312                 .desc = "MWAIT 0x01",
 313                 .flags = MWAIT2flg(0x01),
 314                 .exit_latency = 10,
 315                 .target_residency = 20,
 316                 .enter = &intel_idle,
 317                 .enter_freeze = intel_idle_freeze, },
 318         {
 319                 .name = "C3-IVB",
 320                 .desc = "MWAIT 0x10",
 321                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 322                 .exit_latency = 59,
 323                 .target_residency = 156,
 324                 .enter = &intel_idle,
 325                 .enter_freeze = intel_idle_freeze, },
 326         {
 327                 .name = "C6-IVB",
 328                 .desc = "MWAIT 0x20",
 329                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 330                 .exit_latency = 80,
 331                 .target_residency = 300,
 332                 .enter = &intel_idle,
 333                 .enter_freeze = intel_idle_freeze, },
 334         {
 335                 .name = "C7-IVB",
 336                 .desc = "MWAIT 0x30",
 337                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
 338                 .exit_latency = 87,
 339                 .target_residency = 300,
 340                 .enter = &intel_idle,
 341                 .enter_freeze = intel_idle_freeze, },
 342         {
 343                 .enter = NULL }
 344 };
 345
 346 static struct cpuidle_state ivt_cstates[] = {
 347         {
 348                 .name = "C1-IVT",
 349                 .desc = "MWAIT 0x00",
 350                 .flags = MWAIT2flg(0x00),
 351                 .exit_latency = 1,
 352                 .target_residency = 1,
 353                 .enter = &intel_idle,
 354                 .enter_freeze = intel_idle_freeze, },
 355         {
 356                 .name = "C1E-IVT",
 357                 .desc = "MWAIT 0x01",
 358                 .flags = MWAIT2flg(0x01),
 359                 .exit_latency = 10,
 360                 .target_residency = 80,
 361                 .enter = &intel_idle,
 362                 .enter_freeze = intel_idle_freeze, },
 363         {
 364                 .name = "C3-IVT",
 365                 .desc = "MWAIT 0x10",
 366                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 367                 .exit_latency = 59,
 368                 .target_residency = 156,
 369                 .enter = &intel_idle,
 370                 .enter_freeze = intel_idle_freeze, },
 371         {
 372                 .name = "C6-IVT",
 373                 .desc = "MWAIT 0x20",
 374                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 375                 .exit_latency = 82,
 376                 .target_residency = 300,
 377                 .enter = &intel_idle,
 378                 .enter_freeze = intel_idle_freeze, },
 379         {
 380                 .enter = NULL }
 381 };
 382
 383 static struct cpuidle_state ivt_cstates_4s[] = {
 384         {
 385                 .name = "C1-IVT-4S",
 386                 .desc = "MWAIT 0x00",
 387                 .flags = MWAIT2flg(0x00),
 388                 .exit_latency = 1,
 389                 .target_residency = 1,
 390                 .enter = &intel_idle,
 391                 .enter_freeze = intel_idle_freeze, },
 392         {
 393                 .name = "C1E-IVT-4S",
 394                 .desc = "MWAIT 0x01",
 395                 .flags = MWAIT2flg(0x01),
 396                 .exit_latency = 10,
 397                 .target_residency = 250,
 398                 .enter = &intel_idle,
 399                 .enter_freeze = intel_idle_freeze, },
 400         {
 401                 .name = "C3-IVT-4S",
 402                 .desc = "MWAIT 0x10",
 403                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 404                 .exit_latency = 59,
 405                 .target_residency = 300,
 406                 .enter = &intel_idle,
 407                 .enter_freeze = intel_idle_freeze, },
 408         {
 409                 .name = "C6-IVT-4S",
 410                 .desc = "MWAIT 0x20",
 411                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 412                 .exit_latency = 84,
 413                 .target_residency = 400,
 414                 .enter = &intel_idle,
 415                 .enter_freeze = intel_idle_freeze, },
 416         {
 417                 .enter = NULL }
 418 };
 419
 420 static struct cpuidle_state ivt_cstates_8s[] = {
 421         {
 422                 .name = "C1-IVT-8S",
 423                 .desc = "MWAIT 0x00",
 424                 .flags = MWAIT2flg(0x00),
 425                 .exit_latency = 1,
 426                 .target_residency = 1,
 427                 .enter = &intel_idle,
 428                 .enter_freeze = intel_idle_freeze, },
 429         {
 430                 .name = "C1E-IVT-8S",
 431                 .desc = "MWAIT 0x01",
 432                 .flags = MWAIT2flg(0x01),
 433                 .exit_latency = 10,
 434                 .target_residency = 500,
 435                 .enter = &intel_idle,
 436                 .enter_freeze = intel_idle_freeze, },
 437         {
 438                 .name = "C3-IVT-8S",
 439                 .desc = "MWAIT 0x10",
 440                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 441                 .exit_latency = 59,
 442                 .target_residency = 600,
 443                 .enter = &intel_idle,
 444                 .enter_freeze = intel_idle_freeze, },
 445         {
 446                 .name = "C6-IVT-8S",
 447                 .desc = "MWAIT 0x20",
 448                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 449                 .exit_latency = 88,
 450                 .target_residency = 700,
 451                 .enter = &intel_idle,
 452                 .enter_freeze = intel_idle_freeze, },
 453         {
 454                 .enter = NULL }
 455 };
 456
 457 static struct cpuidle_state hsw_cstates[] = {
 458         {
 459                 .name = "C1-HSW",
 460                 .desc = "MWAIT 0x00",
 461                 .flags = MWAIT2flg(0x00),
 462                 .exit_latency = 2,
 463                 .target_residency = 2,
 464                 .enter = &intel_idle,
 465                 .enter_freeze = intel_idle_freeze, },
 466         {
 467                 .name = "C1E-HSW",
 468                 .desc = "MWAIT 0x01",
 469                 .flags = MWAIT2flg(0x01),
 470                 .exit_latency = 10,
 471                 .target_residency = 20,
 472                 .enter = &intel_idle,
 473                 .enter_freeze = intel_idle_freeze, },
 474         {
 475                 .name = "C3-HSW",
 476                 .desc = "MWAIT 0x10",
 477                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 478                 .exit_latency = 33,
 479                 .target_residency = 100,
 480                 .enter = &intel_idle,
 481                 .enter_freeze = intel_idle_freeze, },
 482         {
 483                 .name = "C6-HSW",
 484                 .desc = "MWAIT 0x20",
 485                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 486                 .exit_latency = 133,
 487                 .target_residency = 400,
 488                 .enter = &intel_idle,
 489                 .enter_freeze = intel_idle_freeze, },
 490         {
 491                 .name = "C7s-HSW",
 492                 .desc = "MWAIT 0x32",
 493                 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
 494                 .exit_latency = 166,
 495                 .target_residency = 500,
 496                 .enter = &intel_idle,
 497                 .enter_freeze = intel_idle_freeze, },
 498         {
 499                 .name = "C8-HSW",
 500                 .desc = "MWAIT 0x40",
 501                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
 502                 .exit_latency = 300,
 503                 .target_residency = 900,
 504                 .enter = &intel_idle,
 505                 .enter_freeze = intel_idle_freeze, },
 506         {
 507                 .name = "C9-HSW",
 508                 .desc = "MWAIT 0x50",
 509                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
 510                 .exit_latency = 600,
 511                 .target_residency = 1800,
 512                 .enter = &intel_idle,
 513                 .enter_freeze = intel_idle_freeze, },
 514         {
 515                 .name = "C10-HSW",
 516                 .desc = "MWAIT 0x60",
 517                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 518                 .exit_latency = 2600,
 519                 .target_residency = 7700,
 520                 .enter = &intel_idle,
 521                 .enter_freeze = intel_idle_freeze, },
 522         {
 523                 .enter = NULL }
 524 };
 525 static struct cpuidle_state bdw_cstates[] = {
 526         {
 527                 .name = "C1-BDW",
 528                 .desc = "MWAIT 0x00",
 529                 .flags = MWAIT2flg(0x00),
 530                 .exit_latency = 2,
 531                 .target_residency = 2,
 532                 .enter = &intel_idle,
 533                 .enter_freeze = intel_idle_freeze, },
 534         {
 535                 .name = "C1E-BDW",
 536                 .desc = "MWAIT 0x01",
 537                 .flags = MWAIT2flg(0x01),
 538                 .exit_latency = 10,
 539                 .target_residency = 20,
 540                 .enter = &intel_idle,
 541                 .enter_freeze = intel_idle_freeze, },
 542         {
 543                 .name = "C3-BDW",
 544                 .desc = "MWAIT 0x10",
 545                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 546                 .exit_latency = 40,
 547                 .target_residency = 100,
 548                 .enter = &intel_idle,
 549                 .enter_freeze = intel_idle_freeze, },
 550         {
 551                 .name = "C6-BDW",
 552                 .desc = "MWAIT 0x20",
 553                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 554                 .exit_latency = 133,
 555                 .target_residency = 400,
 556                 .enter = &intel_idle,
 557                 .enter_freeze = intel_idle_freeze, },
 558         {
 559                 .name = "C7s-BDW",
 560                 .desc = "MWAIT 0x32",
 561                 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
 562                 .exit_latency = 166,
 563                 .target_residency = 500,
 564                 .enter = &intel_idle,
 565                 .enter_freeze = intel_idle_freeze, },
 566         {
 567                 .name = "C8-BDW",
 568                 .desc = "MWAIT 0x40",
 569                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
 570                 .exit_latency = 300,
 571                 .target_residency = 900,
 572                 .enter = &intel_idle,
 573                 .enter_freeze = intel_idle_freeze, },
 574         {
 575                 .name = "C9-BDW",
 576                 .desc = "MWAIT 0x50",
 577                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
 578                 .exit_latency = 600,
 579                 .target_residency = 1800,
 580                 .enter = &intel_idle,
 581                 .enter_freeze = intel_idle_freeze, },
 582         {
 583                 .name = "C10-BDW",
 584                 .desc = "MWAIT 0x60",
 585                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 586                 .exit_latency = 2600,
 587                 .target_residency = 7700,
 588                 .enter = &intel_idle,
 589                 .enter_freeze = intel_idle_freeze, },
 590         {
 591                 .enter = NULL }
 592 };
 593
 594 static struct cpuidle_state atom_cstates[] = {
 595         {
 596                 .name = "C1E-ATM",
 597                 .desc = "MWAIT 0x00",
 598                 .flags = MWAIT2flg(0x00),
 599                 .exit_latency = 10,
 600                 .target_residency = 20,
 601                 .enter = &intel_idle,
 602                 .enter_freeze = intel_idle_freeze, },
 603         {
 604                 .name = "C2-ATM",
 605                 .desc = "MWAIT 0x10",
 606                 .flags = MWAIT2flg(0x10),
 607                 .exit_latency = 20,
 608                 .target_residency = 80,
 609                 .enter = &intel_idle,
 610                 .enter_freeze = intel_idle_freeze, },
 611         {
 612                 .name = "C4-ATM",
 613                 .desc = "MWAIT 0x30",
 614                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
 615                 .exit_latency = 100,
 616                 .target_residency = 400,
 617                 .enter = &intel_idle,
 618                 .enter_freeze = intel_idle_freeze, },
 619         {
 620                 .name = "C6-ATM",
 621                 .desc = "MWAIT 0x52",
 622                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
 623                 .exit_latency = 140,
 624                 .target_residency = 560,
 625                 .enter = &intel_idle,
 626                 .enter_freeze = intel_idle_freeze, },
 627         {
 628                 .enter = NULL }
 629 };
 630 static struct cpuidle_state avn_cstates[] = {
 631         {
 632                 .name = "C1-AVN",
 633                 .desc = "MWAIT 0x00",
 634                 .flags = MWAIT2flg(0x00),
 635                 .exit_latency = 2,
 636                 .target_residency = 2,
 637                 .enter = &intel_idle,
 638                 .enter_freeze = intel_idle_freeze, },
 639         {
 640                 .name = "C6-AVN",
 641                 .desc = "MWAIT 0x51",
 642                 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
 643                 .exit_latency = 15,
 644                 .target_residency = 45,
 645                 .enter = &intel_idle,
 646                 .enter_freeze = intel_idle_freeze, },
 647         {
 648                 .enter = NULL }
 649 };
 650
 651 /**
 652  * intel_idle
 653  * @dev: cpuidle_device
 654  * @drv: cpuidle driver
 655  * @index: index of cpuidle state
 656  *
 657  * Must be called under local_irq_disable().
 658  */
 659 static int intel_idle(struct cpuidle_device *dev,
 660                 struct cpuidle_driver *drv, int index)
 661 {
 662         unsigned long ecx = 1; /* break on interrupt flag */
 663         struct cpuidle_state *state = &drv->states[index];
 664         unsigned long eax = flg2MWAIT(state->flags);
 665         unsigned int cstate;
 666         int cpu = smp_processor_id();
 667
 668         cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
 669
 670         /*
 671          * leave_mm() to avoid costly and often unnecessary wakeups
 672          * for flushing the user TLB's associated with the active mm.
 673          */
 674         if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
 675                 leave_mm(cpu);
 676
 677         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 678                 tick_broadcast_enter();
 679
 680         mwait_idle_with_hints(eax, ecx);
 681
 682         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 683                 tick_broadcast_exit();
 684
 685         return index;
 686 }
 687
 688 /**
 689  * intel_idle_freeze - simplified "enter" callback routine for suspend-to-idle
 690  * @dev: cpuidle_device
 691  * @drv: cpuidle driver
 692  * @index: state index
 693  */
 694 static void intel_idle_freeze(struct cpuidle_device *dev,
 695                              struct cpuidle_driver *drv, int index)
 696 {
 697         unsigned long ecx = 1; /* break on interrupt flag */
 698         unsigned long eax = flg2MWAIT(drv->states[index].flags);
 699
 700         mwait_idle_with_hints(eax, ecx);
 701 }
 702
 703 static void __setup_broadcast_timer(void *arg)
 704 {
 705         unsigned long on = (unsigned long)arg;
 706
 707         if (on)
 708                 tick_broadcast_enable();
 709         else
 710                 tick_broadcast_disable();
 711 }
 712
 713 static int cpu_hotplug_notify(struct notifier_block *n,
 714                               unsigned long action, void *hcpu)
 715 {
 716         int hotcpu = (unsigned long)hcpu;
 717         struct cpuidle_device *dev;
 718
 719         switch (action & ~CPU_TASKS_FROZEN) {
 720         case CPU_ONLINE:
 721
 722                 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 723                         smp_call_function_single(hotcpu, __setup_broadcast_timer,
 724                                                  (void *)true, 1);
 725
 726                 /*
 727                  * Some systems can hotplug a cpu at runtime after
 728                  * the kernel has booted, we have to initialize the
 729                  * driver in this case
 730                  */
 731                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
 732                 if (!dev->registered)
 733                         intel_idle_cpu_init(hotcpu);
 734
 735                 break;
 736         }
 737         return NOTIFY_OK;
 738 }
 739
 740 static struct notifier_block cpu_hotplug_notifier = {
 741         .notifier_call = cpu_hotplug_notify,
 742 };
 743
 744 static void auto_demotion_disable(void *dummy)
 745 {
 746         unsigned long long msr_bits;
 747
 748         rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 749         msr_bits &= ~(icpu->auto_demotion_disable_flags);
 750         wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 751 }
 752 static void c1e_promotion_disable(void *dummy)
 753 {
 754         unsigned long long msr_bits;
 755
 756         rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
 757         msr_bits &= ~0x2;
 758         wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
 759 }
 760
 761 static const struct idle_cpu idle_cpu_nehalem = {
 762         .state_table = nehalem_cstates,
 763         .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
 764         .disable_promotion_to_c1e = true,
 765 };
 766
 767 static const struct idle_cpu idle_cpu_atom = {
 768         .state_table = atom_cstates,
 769 };
 770
 771 static const struct idle_cpu idle_cpu_lincroft = {
 772         .state_table = atom_cstates,
 773         .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
 774 };
 775
 776 static const struct idle_cpu idle_cpu_snb = {
 777         .state_table = snb_cstates,
 778         .disable_promotion_to_c1e = true,
 779 };
 780
 781 static const struct idle_cpu idle_cpu_byt = {
 782         .state_table = byt_cstates,
 783         .disable_promotion_to_c1e = true,
 784         .byt_auto_demotion_disable_flag = true,
 785 };
 786
 787 static const struct idle_cpu idle_cpu_cht = {
 788         .state_table = cht_cstates,
 789         .disable_promotion_to_c1e = true,
 790         .byt_auto_demotion_disable_flag = true,
 791 };
 792
 793 static const struct idle_cpu idle_cpu_ivb = {
 794         .state_table = ivb_cstates,
 795         .disable_promotion_to_c1e = true,
 796 };
 797
 798 static const struct idle_cpu idle_cpu_ivt = {
 799         .state_table = ivt_cstates,
 800         .disable_promotion_to_c1e = true,
 801 };
 802
 803 static const struct idle_cpu idle_cpu_hsw = {
 804         .state_table = hsw_cstates,
 805         .disable_promotion_to_c1e = true,
 806 };
 807
 808 static const struct idle_cpu idle_cpu_bdw = {
 809         .state_table = bdw_cstates,
 810         .disable_promotion_to_c1e = true,
 811 };
 812
 813 static const struct idle_cpu idle_cpu_avn = {
 814         .state_table = avn_cstates,
 815         .disable_promotion_to_c1e = true,
 816 };
 817
 818 #define ICPU(model, cpu) \
 819         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
 820
 821 static const struct x86_cpu_id intel_idle_ids[] __initconst = {
 822         ICPU(0x1a, idle_cpu_nehalem),
 823         ICPU(0x1e, idle_cpu_nehalem),
 824         ICPU(0x1f, idle_cpu_nehalem),
 825         ICPU(0x25, idle_cpu_nehalem),
 826         ICPU(0x2c, idle_cpu_nehalem),
 827         ICPU(0x2e, idle_cpu_nehalem),
 828         ICPU(0x1c, idle_cpu_atom),
 829         ICPU(0x26, idle_cpu_lincroft),
 830         ICPU(0x2f, idle_cpu_nehalem),
 831         ICPU(0x2a, idle_cpu_snb),
 832         ICPU(0x2d, idle_cpu_snb),
 833         ICPU(0x36, idle_cpu_atom),
 834         ICPU(0x37, idle_cpu_byt),
 835         ICPU(0x4c, idle_cpu_cht),
 836         ICPU(0x3a, idle_cpu_ivb),
 837         ICPU(0x3e, idle_cpu_ivt),
 838         ICPU(0x3c, idle_cpu_hsw),
 839         ICPU(0x3f, idle_cpu_hsw),
 840         ICPU(0x45, idle_cpu_hsw),
 841         ICPU(0x46, idle_cpu_hsw),
 842         ICPU(0x4d, idle_cpu_avn),
 843         ICPU(0x3d, idle_cpu_bdw),
 844         ICPU(0x47, idle_cpu_bdw),
 845         ICPU(0x4f, idle_cpu_bdw),
 846         ICPU(0x56, idle_cpu_bdw),
 847         {}
 848 };
 849 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
 850
 851 /*
 852  * intel_idle_probe()
 853  */
 854 static int __init intel_idle_probe(void)
 855 {
 856         unsigned int eax, ebx, ecx;
 857         const struct x86_cpu_id *id;
 858
 859         if (max_cstate == 0) {
 860                 pr_debug(PREFIX "disabled\n");
 861                 return -EPERM;
 862         }
 863
 864         id = x86_match_cpu(intel_idle_ids);
 865         if (!id) {
 866                 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 867                     boot_cpu_data.x86 == 6)
 868                         pr_debug(PREFIX "does not run on family %d model %d\n",
 869                                 boot_cpu_data.x86, boot_cpu_data.x86_model);
 870                 return -ENODEV;
 871         }
 872
 873         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
 874                 return -ENODEV;
 875
 876         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
 877
 878         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
 879             !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
 880             !mwait_substates)
 881                         return -ENODEV;
 882
 883         pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
 884
 885         icpu = (const struct idle_cpu *)id->driver_data;
 886         cpuidle_state_table = icpu->state_table;
 887
 888         if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
 889                 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
 890         else
 891                 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
 892
 893         pr_debug(PREFIX "v" INTEL_IDLE_VERSION
 894                 " model 0x%X\n", boot_cpu_data.x86_model);
 895
 896         pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
 897                 lapic_timer_reliable_states);
 898         return 0;
 899 }
 900
 901 /*
 902  * intel_idle_cpuidle_devices_uninit()
 903  * unregister, free cpuidle_devices
 904  */
 905 static void intel_idle_cpuidle_devices_uninit(void)
 906 {
 907         int i;
 908         struct cpuidle_device *dev;
 909
 910         for_each_online_cpu(i) {
 911                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 912                 cpuidle_unregister_device(dev);
 913         }
 914
 915         free_percpu(intel_idle_cpuidle_devices);
 916         return;
 917 }
 918
 919 /*
 920  * intel_idle_state_table_update()
 921  *
 922  * Update the default state_table for this CPU-id
 923  *
 924  * Currently used to access tuned IVT multi-socket targets
 925  * Assumption: num_sockets == (max_package_num + 1)
 926  */
 927 void intel_idle_state_table_update(void)
 928 {
 929         /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
 930         if (boot_cpu_data.x86_model == 0x3e) { /* IVT */
 931                 int cpu, package_num, num_sockets = 1;
 932
 933                 for_each_online_cpu(cpu) {
 934                         package_num = topology_physical_package_id(cpu);
 935                         if (package_num + 1 > num_sockets) {
 936                                 num_sockets = package_num + 1;
 937
 938                                 if (num_sockets > 4) {
 939                                         cpuidle_state_table = ivt_cstates_8s;
 940                                         return;
 941                                 }
 942                         }
 943                 }
 944
 945                 if (num_sockets > 2)
 946                         cpuidle_state_table = ivt_cstates_4s;
 947                 /* else, 1 and 2 socket systems use default ivt_cstates */
 948         }
 949         return;
 950 }
 951
 952 /*
 953  * intel_idle_cpuidle_driver_init()
 954  * allocate, initialize cpuidle_states
 955  */
 956 static int __init intel_idle_cpuidle_driver_init(void)
 957 {
 958         int cstate;
 959         struct cpuidle_driver *drv = &intel_idle_driver;
 960
 961         intel_idle_state_table_update();
 962
 963         drv->state_count = 1;
 964
 965         for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
 966                 int num_substates, mwait_hint, mwait_cstate;
 967
 968                 if (cpuidle_state_table[cstate].enter == NULL)
 969                         break;
 970
 971                 if (cstate + 1 > max_cstate) {
 972                         printk(PREFIX "max_cstate %d reached\n",
 973                                 max_cstate);
 974                         break;
 975                 }
 976
 977                 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
 978                 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
 979
 980                 /* number of sub-states for this state in CPUID.MWAIT */
 981                 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
 982                                         & MWAIT_SUBSTATE_MASK;
 983
 984                 /* if NO sub-states for this state in CPUID, skip it */
 985                 if (num_substates == 0)
 986                         continue;
 987
 988                 if (((mwait_cstate + 1) > 2) &&
 989                         !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 990                         mark_tsc_unstable("TSC halts in idle"
 991                                         " states deeper than C2");
 992
 993                 drv->states[drv->state_count] = /* structure copy */
 994                         cpuidle_state_table[cstate];
 995
 996                 drv->state_count += 1;
 997         }
 998
 999         if (icpu->auto_demotion_disable_flags)
1000                 on_each_cpu(auto_demotion_disable, NULL, 1);
1001
1002         if (icpu->byt_auto_demotion_disable_flag) {
1003                 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1004                 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1005         }
1006
1007         if (icpu->disable_promotion_to_c1e)     /* each-cpu is redundant */
1008                 on_each_cpu(c1e_promotion_disable, NULL, 1);
1009
1010         return 0;
1011 }
1012
1013
1014 /*
1015  * intel_idle_cpu_init()
1016  * allocate, initialize, register cpuidle_devices
1017  * @cpu: cpu/core to initialize
1018  */
1019 static int intel_idle_cpu_init(int cpu)
1020 {
1021         struct cpuidle_device *dev;
1022
1023         dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1024
1025         dev->cpu = cpu;
1026
1027         if (cpuidle_register_device(dev)) {
1028                 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
1029                 intel_idle_cpuidle_devices_uninit();
1030                 return -EIO;
1031         }
1032
1033         if (icpu->auto_demotion_disable_flags)
1034                 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
1035
1036         if (icpu->disable_promotion_to_c1e)
1037                 smp_call_function_single(cpu, c1e_promotion_disable, NULL, 1);
1038
1039         return 0;
1040 }
1041
1042 static int __init intel_idle_init(void)
1043 {
1044         int retval, i;
1045
1046         /* Do not load intel_idle at all for now if idle= is passed */
1047         if (boot_option_idle_override != IDLE_NO_OVERRIDE)
1048                 return -ENODEV;
1049
1050         retval = intel_idle_probe();
1051         if (retval)
1052                 return retval;
1053
1054         intel_idle_cpuidle_driver_init();
1055         retval = cpuidle_register_driver(&intel_idle_driver);
1056         if (retval) {
1057                 struct cpuidle_driver *drv = cpuidle_get_driver();
1058                 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
1059                         drv ? drv->name : "none");
1060                 return retval;
1061         }
1062
1063         intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
1064         if (intel_idle_cpuidle_devices == NULL)
1065                 return -ENOMEM;
1066
1067         cpu_notifier_register_begin();
1068
1069         for_each_online_cpu(i) {
1070                 retval = intel_idle_cpu_init(i);
1071                 if (retval) {
1072                         cpu_notifier_register_done();
1073                         cpuidle_unregister_driver(&intel_idle_driver);
1074                         return retval;
1075                 }
1076         }
1077         __register_cpu_notifier(&cpu_hotplug_notifier);
1078
1079         cpu_notifier_register_done();
1080
1081         return 0;
1082 }
1083
1084 static void __exit intel_idle_exit(void)
1085 {
1086         intel_idle_cpuidle_devices_uninit();
1087         cpuidle_unregister_driver(&intel_idle_driver);
1088
1089         cpu_notifier_register_begin();
1090
1091         if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
1092                 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
1093         __unregister_cpu_notifier(&cpu_hotplug_notifier);
1094
1095         cpu_notifier_register_done();
1096
1097         return;
1098 }
1099
1100 module_init(intel_idle_init);
1101 module_exit(intel_idle_exit);
1102
1103 module_param(max_cstate, int, 0444);
1104
1105 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
1106 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
1107 MODULE_LICENSE("GPL");