kernel/drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21  * Supports the following Intel I/O Controller Hubs (ICH):
  22  *
  23  *                                      I/O                     Block   I2C
  24  *                                      region  SMBus   Block   proc.   block
  25  * Chip name                    PCI ID  size    PEC     buffer  call    read
  26  * ---------------------------------------------------------------------------
  27  * 82801AA (ICH)                0x2413  16      no      no      no      no
  28  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40  * ICH10                        0x3a30  32      hard    yes     yes     yes
  41  * ICH10                        0x3a60  32      hard    yes     yes     yes
  42  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  62  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  63  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  64  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  65  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  66  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  67  *
  68  * Features supported by this driver:
  69  * Software PEC                         no
  70  * Hardware PEC                         yes
  71  * Block buffer                         yes
  72  * Block process call transaction       no
  73  * I2C block read transaction           yes (doesn't use the block buffer)
  74  * Slave mode                           no
  75  * Interrupt processing                 yes
  76  *
  77  * See the file Documentation/i2c/busses/i2c-i801 for details.
  78  */
  79
  80 #include <linux/interrupt.h>
  81 #include <linux/module.h>
  82 #include <linux/pci.h>
  83 #include <linux/kernel.h>
  84 #include <linux/stddef.h>
  85 #include <linux/delay.h>
  86 #include <linux/ioport.h>
  87 #include <linux/init.h>
  88 #include <linux/i2c.h>
  89 #include <linux/acpi.h>
  90 #include <linux/io.h>
  91 #include <linux/dmi.h>
  92 #include <linux/slab.h>
  93 #include <linux/wait.h>
  94 #include <linux/err.h>
  95 #include <linux/platform_device.h>
  96 #include <linux/platform_data/itco_wdt.h>
  97
  98 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
  99                 defined CONFIG_DMI
 100 #include <linux/gpio.h>
 101 #include <linux/i2c-mux-gpio.h>
 102 #endif
 103
 104 /* I801 SMBus address offsets */
 105 #define SMBHSTSTS(p)    (0 + (p)->smba)
 106 #define SMBHSTCNT(p)    (2 + (p)->smba)
 107 #define SMBHSTCMD(p)    (3 + (p)->smba)
 108 #define SMBHSTADD(p)    (4 + (p)->smba)
 109 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 110 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 111 #define SMBBLKDAT(p)    (7 + (p)->smba)
 112 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 113 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 114 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 115
 116 /* PCI Address Constants */
 117 #define SMBBAR          4
 118 #define SMBPCICTL       0x004
 119 #define SMBPCISTS       0x006
 120 #define SMBHSTCFG       0x040
 121 #define TCOBASE         0x050
 122 #define TCOCTL          0x054
 123
 124 #define ACPIBASE                0x040
 125 #define ACPIBASE_SMI_OFF        0x030
 126 #define ACPICTRL                0x044
 127 #define ACPICTRL_EN             0x080
 128
 129 #define SBREG_BAR               0x10
 130 #define SBREG_SMBCTRL           0xc6000c
 131
 132 /* Host status bits for SMBPCISTS */
 133 #define SMBPCISTS_INTS          0x08
 134
 135 /* Control bits for SMBPCICTL */
 136 #define SMBPCICTL_INTDIS        0x0400
 137
 138 /* Host configuration bits for SMBHSTCFG */
 139 #define SMBHSTCFG_HST_EN        1
 140 #define SMBHSTCFG_SMB_SMI_EN    2
 141 #define SMBHSTCFG_I2C_EN        4
 142
 143 /* TCO configuration bits for TCOCTL */
 144 #define TCOCTL_EN               0x0100
 145
 146 /* Auxiliary control register bits, ICH4+ only */
 147 #define SMBAUXCTL_CRC           1
 148 #define SMBAUXCTL_E32B          2
 149
 150 /* Other settings */
 151 #define MAX_RETRIES             400
 152
 153 /* I801 command constants */
 154 #define I801_QUICK              0x00
 155 #define I801_BYTE               0x04
 156 #define I801_BYTE_DATA          0x08
 157 #define I801_WORD_DATA          0x0C
 158 #define I801_PROC_CALL          0x10    /* unimplemented */
 159 #define I801_BLOCK_DATA         0x14
 160 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 161
 162 /* I801 Host Control register bits */
 163 #define SMBHSTCNT_INTREN        0x01
 164 #define SMBHSTCNT_KILL          0x02
 165 #define SMBHSTCNT_LAST_BYTE     0x20
 166 #define SMBHSTCNT_START         0x40
 167 #define SMBHSTCNT_PEC_EN        0x80    /* ICH3 and later */
 168
 169 /* I801 Hosts Status register bits */
 170 #define SMBHSTSTS_BYTE_DONE     0x80
 171 #define SMBHSTSTS_INUSE_STS     0x40
 172 #define SMBHSTSTS_SMBALERT_STS  0x20
 173 #define SMBHSTSTS_FAILED        0x10
 174 #define SMBHSTSTS_BUS_ERR       0x08
 175 #define SMBHSTSTS_DEV_ERR       0x04
 176 #define SMBHSTSTS_INTR          0x02
 177 #define SMBHSTSTS_HOST_BUSY     0x01
 178
 179 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 180                                  SMBHSTSTS_DEV_ERR)
 181
 182 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 183                                  STATUS_ERROR_FLAGS)
 184
 185 /* Older devices have their ID defined in <linux/pci_ids.h> */
 186 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 187 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 188 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 189 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 190 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 191 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 192 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 193 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 194 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 195 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 196 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 197 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 198 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 199 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 200 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 201 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 202 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 203 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 204 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 205 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 206 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 207 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 208 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 209 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 210 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 211 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 212 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 213
 214 struct i801_mux_config {
 215         char *gpio_chip;
 216         unsigned values[3];
 217         int n_values;
 218         unsigned classes[3];
 219         unsigned gpios[2];              /* Relative to gpio_chip->base */
 220         int n_gpios;
 221 };
 222
 223 struct i801_priv {
 224         struct i2c_adapter adapter;
 225         unsigned long smba;
 226         unsigned char original_hstcfg;
 227         struct pci_dev *pci_dev;
 228         unsigned int features;
 229
 230         /* isr processing */
 231         wait_queue_head_t waitq;
 232         u8 status;
 233
 234         /* Command state used by isr for byte-by-byte block transactions */
 235         u8 cmd;
 236         bool is_read;
 237         int count;
 238         int len;
 239         u8 *data;
 240
 241 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 242                 defined CONFIG_DMI
 243         const struct i801_mux_config *mux_drvdata;
 244         struct platform_device *mux_pdev;
 245 #endif
 246         struct platform_device *tco_pdev;
 247
 248         /*
 249          * If set to true the host controller registers are reserved for
 250          * ACPI AML use. Protected by acpi_lock.
 251          */
 252         bool acpi_reserved;
 253         struct mutex acpi_lock;
 254 };
 255
 256 #define FEATURE_SMBUS_PEC       (1 << 0)
 257 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 258 #define FEATURE_BLOCK_PROC      (1 << 2)
 259 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 260 #define FEATURE_IRQ             (1 << 4)
 261 /* Not really a feature, but it's convenient to handle it as such */
 262 #define FEATURE_IDF             (1 << 15)
 263 #define FEATURE_TCO             (1 << 16)
 264
 265 static const char *i801_feature_names[] = {
 266         "SMBus PEC",
 267         "Block buffer",
 268         "Block process call",
 269         "I2C block read",
 270         "Interrupt",
 271 };
 272
 273 static unsigned int disable_features;
 274 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 275 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 276         "\t\t  0x01  disable SMBus PEC\n"
 277         "\t\t  0x02  disable the block buffer\n"
 278         "\t\t  0x08  disable the I2C block read functionality\n"
 279         "\t\t  0x10  don't use interrupts ");
 280
 281 /* Make sure the SMBus host is ready to start transmitting.
 282    Return 0 if it is, -EBUSY if it is not. */
 283 static int i801_check_pre(struct i801_priv *priv)
 284 {
 285         int status;
 286
 287         status = inb_p(SMBHSTSTS(priv));
 288         if (status & SMBHSTSTS_HOST_BUSY) {
 289                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 290                 return -EBUSY;
 291         }
 292
 293         status &= STATUS_FLAGS;
 294         if (status) {
 295                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 296                         status);
 297                 outb_p(status, SMBHSTSTS(priv));
 298                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 299                 if (status) {
 300                         dev_err(&priv->pci_dev->dev,
 301                                 "Failed clearing status flags (%02x)\n",
 302                                 status);
 303                         return -EBUSY;
 304                 }
 305         }
 306
 307         return 0;
 308 }
 309
 310 /*
 311  * Convert the status register to an error code, and clear it.
 312  * Note that status only contains the bits we want to clear, not the
 313  * actual register value.
 314  */
 315 static int i801_check_post(struct i801_priv *priv, int status)
 316 {
 317         int result = 0;
 318
 319         /*
 320          * If the SMBus is still busy, we give up
 321          * Note: This timeout condition only happens when using polling
 322          * transactions.  For interrupt operation, NAK/timeout is indicated by
 323          * DEV_ERR.
 324          */
 325         if (unlikely(status < 0)) {
 326                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 327                 /* try to stop the current command */
 328                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 329                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 330                        SMBHSTCNT(priv));
 331                 usleep_range(1000, 2000);
 332                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 333                        SMBHSTCNT(priv));
 334
 335                 /* Check if it worked */
 336                 status = inb_p(SMBHSTSTS(priv));
 337                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 338                     !(status & SMBHSTSTS_FAILED))
 339                         dev_err(&priv->pci_dev->dev,
 340                                 "Failed terminating the transaction\n");
 341                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 342                 return -ETIMEDOUT;
 343         }
 344
 345         if (status & SMBHSTSTS_FAILED) {
 346                 result = -EIO;
 347                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 348         }
 349         if (status & SMBHSTSTS_DEV_ERR) {
 350                 result = -ENXIO;
 351                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 352         }
 353         if (status & SMBHSTSTS_BUS_ERR) {
 354                 result = -EAGAIN;
 355                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 356         }
 357
 358         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 359         outb_p(status, SMBHSTSTS(priv));
 360
 361         return result;
 362 }
 363
 364 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 365 static int i801_wait_intr(struct i801_priv *priv)
 366 {
 367         int timeout = 0;
 368         int status;
 369
 370         /* We will always wait for a fraction of a second! */
 371         do {
 372                 usleep_range(250, 500);
 373                 status = inb_p(SMBHSTSTS(priv));
 374         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 375                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 376                  (timeout++ < MAX_RETRIES));
 377
 378         if (timeout > MAX_RETRIES) {
 379                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 380                 return -ETIMEDOUT;
 381         }
 382         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 383 }
 384
 385 /* Wait for either BYTE_DONE or an error flag being set */
 386 static int i801_wait_byte_done(struct i801_priv *priv)
 387 {
 388         int timeout = 0;
 389         int status;
 390
 391         /* We will always wait for a fraction of a second! */
 392         do {
 393                 usleep_range(250, 500);
 394                 status = inb_p(SMBHSTSTS(priv));
 395         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 396                  (timeout++ < MAX_RETRIES));
 397
 398         if (timeout > MAX_RETRIES) {
 399                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 400                 return -ETIMEDOUT;
 401         }
 402         return status & STATUS_ERROR_FLAGS;
 403 }
 404
 405 static int i801_transaction(struct i801_priv *priv, int xact)
 406 {
 407         int status;
 408         int result;
 409         const struct i2c_adapter *adap = &priv->adapter;
 410
 411         result = i801_check_pre(priv);
 412         if (result < 0)
 413                 return result;
 414
 415         if (priv->features & FEATURE_IRQ) {
 416                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 417                        SMBHSTCNT(priv));
 418                 result = wait_event_timeout(priv->waitq,
 419                                             (status = priv->status),
 420                                             adap->timeout);
 421                 if (!result) {
 422                         status = -ETIMEDOUT;
 423                         dev_warn(&priv->pci_dev->dev,
 424                                  "Timeout waiting for interrupt!\n");
 425                 }
 426                 priv->status = 0;
 427                 return i801_check_post(priv, status);
 428         }
 429
 430         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 431          * SMBSCMD are passed in xact */
 432         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 433
 434         status = i801_wait_intr(priv);
 435         return i801_check_post(priv, status);
 436 }
 437
 438 static int i801_block_transaction_by_block(struct i801_priv *priv,
 439                                            union i2c_smbus_data *data,
 440                                            char read_write, int hwpec)
 441 {
 442         int i, len;
 443         int status;
 444
 445         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 446
 447         /* Use 32-byte buffer to process this transaction */
 448         if (read_write == I2C_SMBUS_WRITE) {
 449                 len = data->block[0];
 450                 outb_p(len, SMBHSTDAT0(priv));
 451                 for (i = 0; i < len; i++)
 452                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 453         }
 454
 455         status = i801_transaction(priv, I801_BLOCK_DATA |
 456                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 457         if (status)
 458                 return status;
 459
 460         if (read_write == I2C_SMBUS_READ) {
 461                 len = inb_p(SMBHSTDAT0(priv));
 462                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 463                         return -EPROTO;
 464
 465                 data->block[0] = len;
 466                 for (i = 0; i < len; i++)
 467                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 468         }
 469         return 0;
 470 }
 471
 472 static void i801_isr_byte_done(struct i801_priv *priv)
 473 {
 474         if (priv->is_read) {
 475                 /* For SMBus block reads, length is received with first byte */
 476                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 477                     (priv->count == 0)) {
 478                         priv->len = inb_p(SMBHSTDAT0(priv));
 479                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 480                                 dev_err(&priv->pci_dev->dev,
 481                                         "Illegal SMBus block read size %d\n",
 482                                         priv->len);
 483                                 /* FIXME: Recover */
 484                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 485                         } else {
 486                                 dev_dbg(&priv->pci_dev->dev,
 487                                         "SMBus block read size is %d\n",
 488                                         priv->len);
 489                         }
 490                         priv->data[-1] = priv->len;
 491                 }
 492
 493                 /* Read next byte */
 494                 if (priv->count < priv->len)
 495                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 496                 else
 497                         dev_dbg(&priv->pci_dev->dev,
 498                                 "Discarding extra byte on block read\n");
 499
 500                 /* Set LAST_BYTE for last byte of read transaction */
 501                 if (priv->count == priv->len - 1)
 502                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 503                                SMBHSTCNT(priv));
 504         } else if (priv->count < priv->len - 1) {
 505                 /* Write next byte, except for IRQ after last byte */
 506                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 507         }
 508
 509         /* Clear BYTE_DONE to continue with next byte */
 510         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 511 }
 512
 513 /*
 514  * There are two kinds of interrupts:
 515  *
 516  * 1) i801 signals transaction completion with one of these interrupts:
 517  *      INTR - Success
 518  *      DEV_ERR - Invalid command, NAK or communication timeout
 519  *      BUS_ERR - SMI# transaction collision
 520  *      FAILED - transaction was canceled due to a KILL request
 521  *    When any of these occur, update ->status and wake up the waitq.
 522  *    ->status must be cleared before kicking off the next transaction.
 523  *
 524  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 525  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 526  */
 527 static irqreturn_t i801_isr(int irq, void *dev_id)
 528 {
 529         struct i801_priv *priv = dev_id;
 530         u16 pcists;
 531         u8 status;
 532
 533         /* Confirm this is our interrupt */
 534         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 535         if (!(pcists & SMBPCISTS_INTS))
 536                 return IRQ_NONE;
 537
 538         status = inb_p(SMBHSTSTS(priv));
 539         if (status & SMBHSTSTS_BYTE_DONE)
 540                 i801_isr_byte_done(priv);
 541
 542         /*
 543          * Clear irq sources and report transaction result.
 544          * ->status must be cleared before the next transaction is started.
 545          */
 546         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 547         if (status) {
 548                 outb_p(status, SMBHSTSTS(priv));
 549                 priv->status |= status;
 550                 wake_up(&priv->waitq);
 551         }
 552
 553         return IRQ_HANDLED;
 554 }
 555
 556 /*
 557  * For "byte-by-byte" block transactions:
 558  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 559  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 560  */
 561 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 562                                                union i2c_smbus_data *data,
 563                                                char read_write, int command,
 564                                                int hwpec)
 565 {
 566         int i, len;
 567         int smbcmd;
 568         int status;
 569         int result;
 570         const struct i2c_adapter *adap = &priv->adapter;
 571
 572         result = i801_check_pre(priv);
 573         if (result < 0)
 574                 return result;
 575
 576         len = data->block[0];
 577
 578         if (read_write == I2C_SMBUS_WRITE) {
 579                 outb_p(len, SMBHSTDAT0(priv));
 580                 outb_p(data->block[1], SMBBLKDAT(priv));
 581         }
 582
 583         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 584             read_write == I2C_SMBUS_READ)
 585                 smbcmd = I801_I2C_BLOCK_DATA;
 586         else
 587                 smbcmd = I801_BLOCK_DATA;
 588
 589         if (priv->features & FEATURE_IRQ) {
 590                 priv->is_read = (read_write == I2C_SMBUS_READ);
 591                 if (len == 1 && priv->is_read)
 592                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 593                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 594                 priv->len = len;
 595                 priv->count = 0;
 596                 priv->data = &data->block[1];
 597
 598                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 599                 result = wait_event_timeout(priv->waitq,
 600                                             (status = priv->status),
 601                                             adap->timeout);
 602                 if (!result) {
 603                         status = -ETIMEDOUT;
 604                         dev_warn(&priv->pci_dev->dev,
 605                                  "Timeout waiting for interrupt!\n");
 606                 }
 607                 priv->status = 0;
 608                 return i801_check_post(priv, status);
 609         }
 610
 611         for (i = 1; i <= len; i++) {
 612                 if (i == len && read_write == I2C_SMBUS_READ)
 613                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 614                 outb_p(smbcmd, SMBHSTCNT(priv));
 615
 616                 if (i == 1)
 617                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 618                                SMBHSTCNT(priv));
 619
 620                 status = i801_wait_byte_done(priv);
 621                 if (status)
 622                         goto exit;
 623
 624                 if (i == 1 && read_write == I2C_SMBUS_READ
 625                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 626                         len = inb_p(SMBHSTDAT0(priv));
 627                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 628                                 dev_err(&priv->pci_dev->dev,
 629                                         "Illegal SMBus block read size %d\n",
 630                                         len);
 631                                 /* Recover */
 632                                 while (inb_p(SMBHSTSTS(priv)) &
 633                                        SMBHSTSTS_HOST_BUSY)
 634                                         outb_p(SMBHSTSTS_BYTE_DONE,
 635                                                SMBHSTSTS(priv));
 636                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 637                                 return -EPROTO;
 638                         }
 639                         data->block[0] = len;
 640                 }
 641
 642                 /* Retrieve/store value in SMBBLKDAT */
 643                 if (read_write == I2C_SMBUS_READ)
 644                         data->block[i] = inb_p(SMBBLKDAT(priv));
 645                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 646                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 647
 648                 /* signals SMBBLKDAT ready */
 649                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 650         }
 651
 652         status = i801_wait_intr(priv);
 653 exit:
 654         return i801_check_post(priv, status);
 655 }
 656
 657 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 658 {
 659         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 660         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 661                 return -EIO;
 662         return 0;
 663 }
 664
 665 /* Block transaction function */
 666 static int i801_block_transaction(struct i801_priv *priv,
 667                                   union i2c_smbus_data *data, char read_write,
 668                                   int command, int hwpec)
 669 {
 670         int result = 0;
 671         unsigned char hostc;
 672
 673         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 674                 if (read_write == I2C_SMBUS_WRITE) {
 675                         /* set I2C_EN bit in configuration register */
 676                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 677                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 678                                               hostc | SMBHSTCFG_I2C_EN);
 679                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 680                         dev_err(&priv->pci_dev->dev,
 681                                 "I2C block read is unsupported!\n");
 682                         return -EOPNOTSUPP;
 683                 }
 684         }
 685
 686         if (read_write == I2C_SMBUS_WRITE
 687          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 688                 if (data->block[0] < 1)
 689                         data->block[0] = 1;
 690                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 691                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 692         } else {
 693                 data->block[0] = 32;    /* max for SMBus block reads */
 694         }
 695
 696         /* Experience has shown that the block buffer can only be used for
 697            SMBus (not I2C) block transactions, even though the datasheet
 698            doesn't mention this limitation. */
 699         if ((priv->features & FEATURE_BLOCK_BUFFER)
 700          && command != I2C_SMBUS_I2C_BLOCK_DATA
 701          && i801_set_block_buffer_mode(priv) == 0)
 702                 result = i801_block_transaction_by_block(priv, data,
 703                                                          read_write, hwpec);
 704         else
 705                 result = i801_block_transaction_byte_by_byte(priv, data,
 706                                                              read_write,
 707                                                              command, hwpec);
 708
 709         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 710          && read_write == I2C_SMBUS_WRITE) {
 711                 /* restore saved configuration register value */
 712                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 713         }
 714         return result;
 715 }
 716
 717 /* Return negative errno on error. */
 718 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 719                        unsigned short flags, char read_write, u8 command,
 720                        int size, union i2c_smbus_data *data)
 721 {
 722         int hwpec;
 723         int block = 0;
 724         int ret = 0, xact = 0;
 725         struct i801_priv *priv = i2c_get_adapdata(adap);
 726
 727         mutex_lock(&priv->acpi_lock);
 728         if (priv->acpi_reserved) {
 729                 mutex_unlock(&priv->acpi_lock);
 730                 return -EBUSY;
 731         }
 732
 733         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 734                 && size != I2C_SMBUS_QUICK
 735                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 736
 737         switch (size) {
 738         case I2C_SMBUS_QUICK:
 739                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 740                        SMBHSTADD(priv));
 741                 xact = I801_QUICK;
 742                 break;
 743         case I2C_SMBUS_BYTE:
 744                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 745                        SMBHSTADD(priv));
 746                 if (read_write == I2C_SMBUS_WRITE)
 747                         outb_p(command, SMBHSTCMD(priv));
 748                 xact = I801_BYTE;
 749                 break;
 750         case I2C_SMBUS_BYTE_DATA:
 751                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 752                        SMBHSTADD(priv));
 753                 outb_p(command, SMBHSTCMD(priv));
 754                 if (read_write == I2C_SMBUS_WRITE)
 755                         outb_p(data->byte, SMBHSTDAT0(priv));
 756                 xact = I801_BYTE_DATA;
 757                 break;
 758         case I2C_SMBUS_WORD_DATA:
 759                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 760                        SMBHSTADD(priv));
 761                 outb_p(command, SMBHSTCMD(priv));
 762                 if (read_write == I2C_SMBUS_WRITE) {
 763                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 764                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 765                 }
 766                 xact = I801_WORD_DATA;
 767                 break;
 768         case I2C_SMBUS_BLOCK_DATA:
 769                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 770                        SMBHSTADD(priv));
 771                 outb_p(command, SMBHSTCMD(priv));
 772                 block = 1;
 773                 break;
 774         case I2C_SMBUS_I2C_BLOCK_DATA:
 775                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 776                  * bit should be cleared here, even when reading */
 777                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 778                 if (read_write == I2C_SMBUS_READ) {
 779                         /* NB: page 240 of ICH5 datasheet also shows
 780                          * that DATA1 is the cmd field when reading */
 781                         outb_p(command, SMBHSTDAT1(priv));
 782                 } else
 783                         outb_p(command, SMBHSTCMD(priv));
 784                 block = 1;
 785                 break;
 786         default:
 787                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 788                         size);
 789                 ret = -EOPNOTSUPP;
 790                 goto out;
 791         }
 792
 793         if (hwpec)      /* enable/disable hardware PEC */
 794                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 795         else
 796                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 797                        SMBAUXCTL(priv));
 798
 799         if (block)
 800                 ret = i801_block_transaction(priv, data, read_write, size,
 801                                              hwpec);
 802         else
 803                 ret = i801_transaction(priv, xact);
 804
 805         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 806            time, so we forcibly disable it after every transaction. Turn off
 807            E32B for the same reason. */
 808         if (hwpec || block)
 809                 outb_p(inb_p(SMBAUXCTL(priv)) &
 810                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 811
 812         if (block)
 813                 goto out;
 814         if (ret)
 815                 goto out;
 816         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 817                 goto out;
 818
 819         switch (xact & 0x7f) {
 820         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 821         case I801_BYTE_DATA:
 822                 data->byte = inb_p(SMBHSTDAT0(priv));
 823                 break;
 824         case I801_WORD_DATA:
 825                 data->word = inb_p(SMBHSTDAT0(priv)) +
 826                              (inb_p(SMBHSTDAT1(priv)) << 8);
 827                 break;
 828         }
 829
 830 out:
 831         mutex_unlock(&priv->acpi_lock);
 832         return ret;
 833 }
 834
 835
 836 static u32 i801_func(struct i2c_adapter *adapter)
 837 {
 838         struct i801_priv *priv = i2c_get_adapdata(adapter);
 839
 840         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 841                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 842                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 843                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 844                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 845                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 846 }
 847
 848 static const struct i2c_algorithm smbus_algorithm = {
 849         .smbus_xfer     = i801_access,
 850         .functionality  = i801_func,
 851 };
 852
 853 static const struct pci_device_id i801_ids[] = {
 854         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 855         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 856         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 857         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 858         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 859         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 860         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 861         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 862         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 863         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 864         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 865         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 866         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 867         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 868         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 869         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 870         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 871         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 872         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 873         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 874         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 875         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 876         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 877         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 878         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 879         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 880         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 881         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 882         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 883         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 884         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 885         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
 886         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
 887         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
 888         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
 889         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
 890         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
 891         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
 892         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
 893         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
 894         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
 895         { 0, }
 896 };
 897
 898 MODULE_DEVICE_TABLE(pci, i801_ids);
 899
 900 #if defined CONFIG_X86 && defined CONFIG_DMI
 901 static unsigned char apanel_addr;
 902
 903 /* Scan the system ROM for the signature "FJKEYINF" */
 904 static __init const void __iomem *bios_signature(const void __iomem *bios)
 905 {
 906         ssize_t offset;
 907         const unsigned char signature[] = "FJKEYINF";
 908
 909         for (offset = 0; offset < 0x10000; offset += 0x10) {
 910                 if (check_signature(bios + offset, signature,
 911                                     sizeof(signature)-1))
 912                         return bios + offset;
 913         }
 914         return NULL;
 915 }
 916
 917 static void __init input_apanel_init(void)
 918 {
 919         void __iomem *bios;
 920         const void __iomem *p;
 921
 922         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 923         p = bios_signature(bios);
 924         if (p) {
 925                 /* just use the first address */
 926                 apanel_addr = readb(p + 8 + 3) >> 1;
 927         }
 928         iounmap(bios);
 929 }
 930
 931 struct dmi_onboard_device_info {
 932         const char *name;
 933         u8 type;
 934         unsigned short i2c_addr;
 935         const char *i2c_type;
 936 };
 937
 938 static const struct dmi_onboard_device_info dmi_devices[] = {
 939         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 940         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 941         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 942 };
 943
 944 static void dmi_check_onboard_device(u8 type, const char *name,
 945                                      struct i2c_adapter *adap)
 946 {
 947         int i;
 948         struct i2c_board_info info;
 949
 950         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 951                 /* & ~0x80, ignore enabled/disabled bit */
 952                 if ((type & ~0x80) != dmi_devices[i].type)
 953                         continue;
 954                 if (strcasecmp(name, dmi_devices[i].name))
 955                         continue;
 956
 957                 memset(&info, 0, sizeof(struct i2c_board_info));
 958                 info.addr = dmi_devices[i].i2c_addr;
 959                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 960                 i2c_new_device(adap, &info);
 961                 break;
 962         }
 963 }
 964
 965 /* We use our own function to check for onboard devices instead of
 966    dmi_find_device() as some buggy BIOS's have the devices we are interested
 967    in marked as disabled */
 968 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
 969 {
 970         int i, count;
 971
 972         if (dm->type != 10)
 973                 return;
 974
 975         count = (dm->length - sizeof(struct dmi_header)) / 2;
 976         for (i = 0; i < count; i++) {
 977                 const u8 *d = (char *)(dm + 1) + (i * 2);
 978                 const char *name = ((char *) dm) + dm->length;
 979                 u8 type = d[0];
 980                 u8 s = d[1];
 981
 982                 if (!s)
 983                         continue;
 984                 s--;
 985                 while (s > 0 && name[0]) {
 986                         name += strlen(name) + 1;
 987                         s--;
 988                 }
 989                 if (name[0] == 0) /* Bogus string reference */
 990                         continue;
 991
 992                 dmi_check_onboard_device(type, name, adap);
 993         }
 994 }
 995
 996 /* Register optional slaves */
 997 static void i801_probe_optional_slaves(struct i801_priv *priv)
 998 {
 999         /* Only register slaves on main SMBus channel */
1000         if (priv->features & FEATURE_IDF)
1001                 return;
1002
1003         if (apanel_addr) {
1004                 struct i2c_board_info info;
1005
1006                 memset(&info, 0, sizeof(struct i2c_board_info));
1007                 info.addr = apanel_addr;
1008                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1009                 i2c_new_device(&priv->adapter, &info);
1010         }
1011
1012         if (dmi_name_in_vendors("FUJITSU"))
1013                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1014 }
1015 #else
1016 static void __init input_apanel_init(void) {}
1017 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1018 #endif  /* CONFIG_X86 && CONFIG_DMI */
1019
1020 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
1021                 defined CONFIG_DMI
1022 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1023         .gpio_chip = "gpio_ich",
1024         .values = { 0x02, 0x03 },
1025         .n_values = 2,
1026         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1027         .gpios = { 52, 53 },
1028         .n_gpios = 2,
1029 };
1030
1031 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1032         .gpio_chip = "gpio_ich",
1033         .values = { 0x02, 0x03, 0x01 },
1034         .n_values = 3,
1035         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1036         .gpios = { 52, 53 },
1037         .n_gpios = 2,
1038 };
1039
1040 static const struct dmi_system_id mux_dmi_table[] = {
1041         {
1042                 .matches = {
1043                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1044                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1045                 },
1046                 .driver_data = &i801_mux_config_asus_z8_d12,
1047         },
1048         {
1049                 .matches = {
1050                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1051                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1052                 },
1053                 .driver_data = &i801_mux_config_asus_z8_d12,
1054         },
1055         {
1056                 .matches = {
1057                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1058                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1059                 },
1060                 .driver_data = &i801_mux_config_asus_z8_d12,
1061         },
1062         {
1063                 .matches = {
1064                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1065                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1066                 },
1067                 .driver_data = &i801_mux_config_asus_z8_d12,
1068         },
1069         {
1070                 .matches = {
1071                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1072                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1073                 },
1074                 .driver_data = &i801_mux_config_asus_z8_d12,
1075         },
1076         {
1077                 .matches = {
1078                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1079                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1080                 },
1081                 .driver_data = &i801_mux_config_asus_z8_d12,
1082         },
1083         {
1084                 .matches = {
1085                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1086                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1087                 },
1088                 .driver_data = &i801_mux_config_asus_z8_d18,
1089         },
1090         {
1091                 .matches = {
1092                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1093                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1094                 },
1095                 .driver_data = &i801_mux_config_asus_z8_d18,
1096         },
1097         {
1098                 .matches = {
1099                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1100                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1101                 },
1102                 .driver_data = &i801_mux_config_asus_z8_d12,
1103         },
1104         { }
1105 };
1106
1107 /* Setup multiplexing if needed */
1108 static int i801_add_mux(struct i801_priv *priv)
1109 {
1110         struct device *dev = &priv->adapter.dev;
1111         const struct i801_mux_config *mux_config;
1112         struct i2c_mux_gpio_platform_data gpio_data;
1113         int err;
1114
1115         if (!priv->mux_drvdata)
1116                 return 0;
1117         mux_config = priv->mux_drvdata;
1118
1119         /* Prepare the platform data */
1120         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1121         gpio_data.parent = priv->adapter.nr;
1122         gpio_data.values = mux_config->values;
1123         gpio_data.n_values = mux_config->n_values;
1124         gpio_data.classes = mux_config->classes;
1125         gpio_data.gpio_chip = mux_config->gpio_chip;
1126         gpio_data.gpios = mux_config->gpios;
1127         gpio_data.n_gpios = mux_config->n_gpios;
1128         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1129
1130         /* Register the mux device */
1131         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1132                                 PLATFORM_DEVID_AUTO, &gpio_data,
1133                                 sizeof(struct i2c_mux_gpio_platform_data));
1134         if (IS_ERR(priv->mux_pdev)) {
1135                 err = PTR_ERR(priv->mux_pdev);
1136                 priv->mux_pdev = NULL;
1137                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1138                 return err;
1139         }
1140
1141         return 0;
1142 }
1143
1144 static void i801_del_mux(struct i801_priv *priv)
1145 {
1146         if (priv->mux_pdev)
1147                 platform_device_unregister(priv->mux_pdev);
1148 }
1149
1150 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1151 {
1152         const struct dmi_system_id *id;
1153         const struct i801_mux_config *mux_config;
1154         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1155         int i;
1156
1157         id = dmi_first_match(mux_dmi_table);
1158         if (id) {
1159                 /* Remove branch classes from trunk */
1160                 mux_config = id->driver_data;
1161                 for (i = 0; i < mux_config->n_values; i++)
1162                         class &= ~mux_config->classes[i];
1163
1164                 /* Remember for later */
1165                 priv->mux_drvdata = mux_config;
1166         }
1167
1168         return class;
1169 }
1170 #else
1171 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1172 static inline void i801_del_mux(struct i801_priv *priv) { }
1173
1174 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1175 {
1176         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1177 }
1178 #endif
1179
1180 static const struct itco_wdt_platform_data tco_platform_data = {
1181         .name = "Intel PCH",
1182         .version = 4,
1183 };
1184
1185 static DEFINE_SPINLOCK(p2sb_spinlock);
1186
1187 static void i801_add_tco(struct i801_priv *priv)
1188 {
1189         struct pci_dev *pci_dev = priv->pci_dev;
1190         struct resource tco_res[3], *res;
1191         struct platform_device *pdev;
1192         unsigned int devfn;
1193         u32 tco_base, tco_ctl;
1194         u32 base_addr, ctrl_val;
1195         u64 base64_addr;
1196
1197         if (!(priv->features & FEATURE_TCO))
1198                 return;
1199
1200         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1201         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1202         if (!(tco_ctl & TCOCTL_EN))
1203                 return;
1204
1205         memset(tco_res, 0, sizeof(tco_res));
1206
1207         res = &tco_res[ICH_RES_IO_TCO];
1208         res->start = tco_base & ~1;
1209         res->end = res->start + 32 - 1;
1210         res->flags = IORESOURCE_IO;
1211
1212         /*
1213          * Power Management registers.
1214          */
1215         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1216         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1217
1218         res = &tco_res[ICH_RES_IO_SMI];
1219         res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1220         res->end = res->start + 3;
1221         res->flags = IORESOURCE_IO;
1222
1223         /*
1224          * Enable the ACPI I/O space.
1225          */
1226         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1227         ctrl_val |= ACPICTRL_EN;
1228         pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1229
1230         /*
1231          * We must access the NO_REBOOT bit over the Primary to Sideband
1232          * bridge (P2SB). The BIOS prevents the P2SB device from being
1233          * enumerated by the PCI subsystem, so we need to unhide/hide it
1234          * to lookup the P2SB BAR.
1235          */
1236         spin_lock(&p2sb_spinlock);
1237
1238         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1239
1240         /* Unhide the P2SB device */
1241         pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1242
1243         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1244         base64_addr = base_addr & 0xfffffff0;
1245
1246         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1247         base64_addr |= (u64)base_addr << 32;
1248
1249         /* Hide the P2SB device */
1250         pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1251         spin_unlock(&p2sb_spinlock);
1252
1253         res = &tco_res[ICH_RES_MEM_OFF];
1254         res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1255         res->end = res->start + 3;
1256         res->flags = IORESOURCE_MEM;
1257
1258         pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1259                                                  tco_res, 3, &tco_platform_data,
1260                                                  sizeof(tco_platform_data));
1261         if (IS_ERR(pdev)) {
1262                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1263                 return;
1264         }
1265
1266         priv->tco_pdev = pdev;
1267 }
1268
1269 #ifdef CONFIG_ACPI
1270 static acpi_status
1271 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1272                      u64 *value, void *handler_context, void *region_context)
1273 {
1274         struct i801_priv *priv = handler_context;
1275         struct pci_dev *pdev = priv->pci_dev;
1276         acpi_status status;
1277
1278         /*
1279          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1280          * further access from the driver itself. This device is now owned
1281          * by the system firmware.
1282          */
1283         mutex_lock(&priv->acpi_lock);
1284
1285         if (!priv->acpi_reserved) {
1286                 priv->acpi_reserved = true;
1287
1288                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1289                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1290         }
1291
1292         if ((function & ACPI_IO_MASK) == ACPI_READ)
1293                 status = acpi_os_read_port(address, (u32 *)value, bits);
1294         else
1295                 status = acpi_os_write_port(address, (u32)*value, bits);
1296
1297         mutex_unlock(&priv->acpi_lock);
1298
1299         return status;
1300 }
1301
1302 static int i801_acpi_probe(struct i801_priv *priv)
1303 {
1304         struct acpi_device *adev;
1305         acpi_status status;
1306
1307         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1308         if (adev) {
1309                 status = acpi_install_address_space_handler(adev->handle,
1310                                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1311                                 NULL, priv);
1312                 if (ACPI_SUCCESS(status))
1313                         return 0;
1314         }
1315
1316         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1317 }
1318
1319 static void i801_acpi_remove(struct i801_priv *priv)
1320 {
1321         struct acpi_device *adev;
1322
1323         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1324         if (!adev)
1325                 return;
1326
1327         acpi_remove_address_space_handler(adev->handle,
1328                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1329 }
1330 #else
1331 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1332 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1333 #endif
1334
1335 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1336 {
1337         unsigned char temp;
1338         int err, i;
1339         struct i801_priv *priv;
1340
1341         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1342         if (!priv)
1343                 return -ENOMEM;
1344
1345         i2c_set_adapdata(&priv->adapter, priv);
1346         priv->adapter.owner = THIS_MODULE;
1347         priv->adapter.class = i801_get_adapter_class(priv);
1348         priv->adapter.algo = &smbus_algorithm;
1349         priv->adapter.dev.parent = &dev->dev;
1350         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1351         priv->adapter.retries = 3;
1352         mutex_init(&priv->acpi_lock);
1353
1354         priv->pci_dev = dev;
1355         switch (dev->device) {
1356         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1357         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1358         case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1359         case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1360         case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1361                 priv->features |= FEATURE_I2C_BLOCK_READ;
1362                 priv->features |= FEATURE_IRQ;
1363                 priv->features |= FEATURE_SMBUS_PEC;
1364                 priv->features |= FEATURE_BLOCK_BUFFER;
1365                 priv->features |= FEATURE_TCO;
1366                 break;
1367
1368         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1369         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1370         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1371         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1372         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1373         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1374                 priv->features |= FEATURE_IDF;
1375                 /* fall through */
1376         default:
1377                 priv->features |= FEATURE_I2C_BLOCK_READ;
1378                 priv->features |= FEATURE_IRQ;
1379                 /* fall through */
1380         case PCI_DEVICE_ID_INTEL_82801DB_3:
1381                 priv->features |= FEATURE_SMBUS_PEC;
1382                 priv->features |= FEATURE_BLOCK_BUFFER;
1383                 /* fall through */
1384         case PCI_DEVICE_ID_INTEL_82801CA_3:
1385         case PCI_DEVICE_ID_INTEL_82801BA_2:
1386         case PCI_DEVICE_ID_INTEL_82801AB_3:
1387         case PCI_DEVICE_ID_INTEL_82801AA_3:
1388                 break;
1389         }
1390
1391         /* Disable features on user request */
1392         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1393                 if (priv->features & disable_features & (1 << i))
1394                         dev_notice(&dev->dev, "%s disabled by user\n",
1395                                    i801_feature_names[i]);
1396         }
1397         priv->features &= ~disable_features;
1398
1399         err = pcim_enable_device(dev);
1400         if (err) {
1401                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1402                         err);
1403                 return err;
1404         }
1405         pcim_pin_device(dev);
1406
1407         /* Determine the address of the SMBus area */
1408         priv->smba = pci_resource_start(dev, SMBBAR);
1409         if (!priv->smba) {
1410                 dev_err(&dev->dev,
1411                         "SMBus base address uninitialized, upgrade BIOS\n");
1412                 return -ENODEV;
1413         }
1414
1415         if (i801_acpi_probe(priv))
1416                 return -ENODEV;
1417
1418         err = pcim_iomap_regions(dev, 1 << SMBBAR,
1419                                  dev_driver_string(&dev->dev));
1420         if (err) {
1421                 dev_err(&dev->dev,
1422                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1423                         priv->smba,
1424                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1425                 i801_acpi_remove(priv);
1426                 return err;
1427         }
1428
1429         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1430         priv->original_hstcfg = temp;
1431         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1432         if (!(temp & SMBHSTCFG_HST_EN)) {
1433                 dev_info(&dev->dev, "Enabling SMBus device\n");
1434                 temp |= SMBHSTCFG_HST_EN;
1435         }
1436         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1437
1438         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1439                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1440                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1441                 priv->features &= ~FEATURE_IRQ;
1442         }
1443
1444         /* Clear special mode bits */
1445         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1446                 outb_p(inb_p(SMBAUXCTL(priv)) &
1447                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1448
1449         /* Default timeout in interrupt mode: 200 ms */
1450         priv->adapter.timeout = HZ / 5;
1451
1452         if (priv->features & FEATURE_IRQ) {
1453                 u16 pcictl, pcists;
1454
1455                 /* Complain if an interrupt is already pending */
1456                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1457                 if (pcists & SMBPCISTS_INTS)
1458                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1459
1460                 /* Check if interrupts have been disabled */
1461                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1462                 if (pcictl & SMBPCICTL_INTDIS) {
1463                         dev_info(&dev->dev, "Interrupts are disabled\n");
1464                         priv->features &= ~FEATURE_IRQ;
1465                 }
1466         }
1467
1468         if (priv->features & FEATURE_IRQ) {
1469                 init_waitqueue_head(&priv->waitq);
1470
1471                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1472                                        IRQF_SHARED,
1473                                        dev_driver_string(&dev->dev), priv);
1474                 if (err) {
1475                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1476                                 dev->irq, err);
1477                         priv->features &= ~FEATURE_IRQ;
1478                 }
1479         }
1480         dev_info(&dev->dev, "SMBus using %s\n",
1481                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1482
1483         i801_add_tco(priv);
1484
1485         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1486                 "SMBus I801 adapter at %04lx", priv->smba);
1487         err = i2c_add_adapter(&priv->adapter);
1488         if (err) {
1489                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1490                 i801_acpi_remove(priv);
1491                 return err;
1492         }
1493
1494         i801_probe_optional_slaves(priv);
1495         /* We ignore errors - multiplexing is optional */
1496         i801_add_mux(priv);
1497
1498         pci_set_drvdata(dev, priv);
1499
1500         return 0;
1501 }
1502
1503 static void i801_remove(struct pci_dev *dev)
1504 {
1505         struct i801_priv *priv = pci_get_drvdata(dev);
1506
1507         i801_del_mux(priv);
1508         i2c_del_adapter(&priv->adapter);
1509         i801_acpi_remove(priv);
1510         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1511
1512         platform_device_unregister(priv->tco_pdev);
1513
1514         /*
1515          * do not call pci_disable_device(dev) since it can cause hard hangs on
1516          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1517          */
1518 }
1519
1520 #ifdef CONFIG_PM
1521 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1522 {
1523         struct i801_priv *priv = pci_get_drvdata(dev);
1524
1525         pci_save_state(dev);
1526         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1527         pci_set_power_state(dev, pci_choose_state(dev, mesg));
1528         return 0;
1529 }
1530
1531 static int i801_resume(struct pci_dev *dev)
1532 {
1533         pci_set_power_state(dev, PCI_D0);
1534         pci_restore_state(dev);
1535         return 0;
1536 }
1537 #else
1538 #define i801_suspend NULL
1539 #define i801_resume NULL
1540 #endif
1541
1542 static struct pci_driver i801_driver = {
1543         .name           = "i801_smbus",
1544         .id_table       = i801_ids,
1545         .probe          = i801_probe,
1546         .remove         = i801_remove,
1547         .suspend        = i801_suspend,
1548         .resume         = i801_resume,
1549 };
1550
1551 static int __init i2c_i801_init(void)
1552 {
1553         if (dmi_name_in_vendors("FUJITSU"))
1554                 input_apanel_init();
1555         return pci_register_driver(&i801_driver);
1556 }
1557
1558 static void __exit i2c_i801_exit(void)
1559 {
1560         pci_unregister_driver(&i801_driver);
1561 }
1562
1563 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1564 MODULE_DESCRIPTION("I801 SMBus driver");
1565 MODULE_LICENSE("GPL");
1566
1567 module_init(i2c_i801_init);
1568 module_exit(i2c_i801_exit);