kernel/drivers/i2c/busses/i2c-davinci.c

   1 /*
   2  * TI DAVINCI I2C adapter driver.
   3  *
   4  * Copyright (C) 2006 Texas Instruments.
   5  * Copyright (C) 2007 MontaVista Software Inc.
   6  *
   7  * Updated by Vinod & Sudhakar Feb 2005
   8  *
   9  * ----------------------------------------------------------------------------
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  * ----------------------------------------------------------------------------
  21  *
  22  */
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/delay.h>
  26 #include <linux/i2c.h>
  27 #include <linux/clk.h>
  28 #include <linux/errno.h>
  29 #include <linux/sched.h>
  30 #include <linux/err.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/io.h>
  34 #include <linux/slab.h>
  35 #include <linux/cpufreq.h>
  36 #include <linux/gpio.h>
  37 #include <linux/of_device.h>
  38 #include <linux/platform_data/i2c-davinci.h>
  39
  40 /* ----- global defines ----------------------------------------------- */
  41
  42 #define DAVINCI_I2C_TIMEOUT     (1*HZ)
  43 #define DAVINCI_I2C_MAX_TRIES   2
  44 #define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_AAS | \
  45                                  DAVINCI_I2C_IMR_SCD | \
  46                                  DAVINCI_I2C_IMR_ARDY | \
  47                                  DAVINCI_I2C_IMR_NACK | \
  48                                  DAVINCI_I2C_IMR_AL)
  49
  50 #define DAVINCI_I2C_OAR_REG     0x00
  51 #define DAVINCI_I2C_IMR_REG     0x04
  52 #define DAVINCI_I2C_STR_REG     0x08
  53 #define DAVINCI_I2C_CLKL_REG    0x0c
  54 #define DAVINCI_I2C_CLKH_REG    0x10
  55 #define DAVINCI_I2C_CNT_REG     0x14
  56 #define DAVINCI_I2C_DRR_REG     0x18
  57 #define DAVINCI_I2C_SAR_REG     0x1c
  58 #define DAVINCI_I2C_DXR_REG     0x20
  59 #define DAVINCI_I2C_MDR_REG     0x24
  60 #define DAVINCI_I2C_IVR_REG     0x28
  61 #define DAVINCI_I2C_EMDR_REG    0x2c
  62 #define DAVINCI_I2C_PSC_REG     0x30
  63 #define DAVINCI_I2C_FUNC_REG    0x48
  64 #define DAVINCI_I2C_DIR_REG     0x4c
  65 #define DAVINCI_I2C_DIN_REG     0x50
  66 #define DAVINCI_I2C_DOUT_REG    0x54
  67 #define DAVINCI_I2C_DSET_REG    0x58
  68 #define DAVINCI_I2C_DCLR_REG    0x5c
  69
  70 #define DAVINCI_I2C_IVR_AAS     0x07
  71 #define DAVINCI_I2C_IVR_SCD     0x06
  72 #define DAVINCI_I2C_IVR_XRDY    0x05
  73 #define DAVINCI_I2C_IVR_RDR     0x04
  74 #define DAVINCI_I2C_IVR_ARDY    0x03
  75 #define DAVINCI_I2C_IVR_NACK    0x02
  76 #define DAVINCI_I2C_IVR_AL      0x01
  77
  78 #define DAVINCI_I2C_STR_BB      BIT(12)
  79 #define DAVINCI_I2C_STR_RSFULL  BIT(11)
  80 #define DAVINCI_I2C_STR_SCD     BIT(5)
  81 #define DAVINCI_I2C_STR_ARDY    BIT(2)
  82 #define DAVINCI_I2C_STR_NACK    BIT(1)
  83 #define DAVINCI_I2C_STR_AL      BIT(0)
  84
  85 #define DAVINCI_I2C_MDR_NACK    BIT(15)
  86 #define DAVINCI_I2C_MDR_STT     BIT(13)
  87 #define DAVINCI_I2C_MDR_STP     BIT(11)
  88 #define DAVINCI_I2C_MDR_MST     BIT(10)
  89 #define DAVINCI_I2C_MDR_TRX     BIT(9)
  90 #define DAVINCI_I2C_MDR_XA      BIT(8)
  91 #define DAVINCI_I2C_MDR_RM      BIT(7)
  92 #define DAVINCI_I2C_MDR_IRS     BIT(5)
  93
  94 #define DAVINCI_I2C_IMR_AAS     BIT(6)
  95 #define DAVINCI_I2C_IMR_SCD     BIT(5)
  96 #define DAVINCI_I2C_IMR_XRDY    BIT(4)
  97 #define DAVINCI_I2C_IMR_RRDY    BIT(3)
  98 #define DAVINCI_I2C_IMR_ARDY    BIT(2)
  99 #define DAVINCI_I2C_IMR_NACK    BIT(1)
 100 #define DAVINCI_I2C_IMR_AL      BIT(0)
 101
 102 /* set SDA and SCL as GPIO */
 103 #define DAVINCI_I2C_FUNC_PFUNC0 BIT(0)
 104
 105 /* set SCL as output when used as GPIO*/
 106 #define DAVINCI_I2C_DIR_PDIR0   BIT(0)
 107 /* set SDA as output when used as GPIO*/
 108 #define DAVINCI_I2C_DIR_PDIR1   BIT(1)
 109
 110 /* read SCL GPIO level */
 111 #define DAVINCI_I2C_DIN_PDIN0 BIT(0)
 112 /* read SDA GPIO level */
 113 #define DAVINCI_I2C_DIN_PDIN1 BIT(1)
 114
 115 /*set the SCL GPIO high */
 116 #define DAVINCI_I2C_DSET_PDSET0 BIT(0)
 117 /*set the SDA GPIO high */
 118 #define DAVINCI_I2C_DSET_PDSET1 BIT(1)
 119
 120 /* set the SCL GPIO low */
 121 #define DAVINCI_I2C_DCLR_PDCLR0 BIT(0)
 122 /* set the SDA GPIO low */
 123 #define DAVINCI_I2C_DCLR_PDCLR1 BIT(1)
 124
 125 struct davinci_i2c_dev {
 126         struct device           *dev;
 127         void __iomem            *base;
 128         struct completion       cmd_complete;
 129         struct clk              *clk;
 130         int                     cmd_err;
 131         u8                      *buf;
 132         size_t                  buf_len;
 133         int                     irq;
 134         int                     stop;
 135         u8                      terminate;
 136         struct i2c_adapter      adapter;
 137 #ifdef CONFIG_CPU_FREQ
 138         struct completion       xfr_complete;
 139         struct notifier_block   freq_transition;
 140 #endif
 141         struct davinci_i2c_platform_data *pdata;
 142 };
 143
 144 /* default platform data to use if not supplied in the platform_device */
 145 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
 146         .bus_freq       = 100,
 147         .bus_delay      = 0,
 148 };
 149
 150 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
 151                                          int reg, u16 val)
 152 {
 153         writew_relaxed(val, i2c_dev->base + reg);
 154 }
 155
 156 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
 157 {
 158         return readw_relaxed(i2c_dev->base + reg);
 159 }
 160
 161 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
 162                                                                 int val)
 163 {
 164         u16 w;
 165
 166         w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
 167         if (!val)       /* put I2C into reset */
 168                 w &= ~DAVINCI_I2C_MDR_IRS;
 169         else            /* take I2C out of reset */
 170                 w |= DAVINCI_I2C_MDR_IRS;
 171
 172         davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
 173 }
 174
 175 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
 176 {
 177         struct davinci_i2c_platform_data *pdata = dev->pdata;
 178         u16 psc;
 179         u32 clk;
 180         u32 d;
 181         u32 clkh;
 182         u32 clkl;
 183         u32 input_clock = clk_get_rate(dev->clk);
 184
 185         /* NOTE: I2C Clock divider programming info
 186          * As per I2C specs the following formulas provide prescaler
 187          * and low/high divider values
 188          * input clk --> PSC Div -----------> ICCL/H Div --> output clock
 189          *                       module clk
 190          *
 191          * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
 192          *
 193          * Thus,
 194          * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
 195          *
 196          * where if PSC == 0, d = 7,
 197          *       if PSC == 1, d = 6
 198          *       if PSC > 1 , d = 5
 199          */
 200
 201         /* get minimum of 7 MHz clock, but max of 12 MHz */
 202         psc = (input_clock / 7000000) - 1;
 203         if ((input_clock / (psc + 1)) > 12000000)
 204                 psc++;  /* better to run under spec than over */
 205         d = (psc >= 2) ? 5 : 7 - psc;
 206
 207         clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
 208         clkh = clk >> 1;
 209         clkl = clk - clkh;
 210
 211         davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
 212         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
 213         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
 214
 215         dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
 216 }
 217
 218 /*
 219  * This function configures I2C and brings I2C out of reset.
 220  * This function is called during I2C init function. This function
 221  * also gets called if I2C encounters any errors.
 222  */
 223 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
 224 {
 225         struct davinci_i2c_platform_data *pdata = dev->pdata;
 226
 227         /* put I2C into reset */
 228         davinci_i2c_reset_ctrl(dev, 0);
 229
 230         /* compute clock dividers */
 231         i2c_davinci_calc_clk_dividers(dev);
 232
 233         /* Respond at reserved "SMBus Host" slave address" (and zero);
 234          * we seem to have no option to not respond...
 235          */
 236         davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
 237
 238         dev_dbg(dev->dev, "PSC  = %d\n",
 239                 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
 240         dev_dbg(dev->dev, "CLKL = %d\n",
 241                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
 242         dev_dbg(dev->dev, "CLKH = %d\n",
 243                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
 244         dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
 245                 pdata->bus_freq, pdata->bus_delay);
 246
 247
 248         /* Take the I2C module out of reset: */
 249         davinci_i2c_reset_ctrl(dev, 1);
 250
 251         /* Enable interrupts */
 252         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
 253
 254         return 0;
 255 }
 256
 257 /*
 258  * This routine does i2c bus recovery by using i2c_generic_gpio_recovery
 259  * which is provided by I2C Bus recovery infrastructure.
 260  */
 261 static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
 262 {
 263         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 264
 265         /* Disable interrupts */
 266         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
 267
 268         /* put I2C into reset */
 269         davinci_i2c_reset_ctrl(dev, 0);
 270 }
 271
 272 static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
 273 {
 274         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 275
 276         i2c_davinci_init(dev);
 277 }
 278
 279 static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
 280         .recover_bus = i2c_generic_gpio_recovery,
 281         .prepare_recovery = davinci_i2c_prepare_recovery,
 282         .unprepare_recovery = davinci_i2c_unprepare_recovery,
 283 };
 284
 285 static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
 286 {
 287         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 288
 289         if (val)
 290                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
 291                                       DAVINCI_I2C_DSET_PDSET0);
 292         else
 293                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
 294                                       DAVINCI_I2C_DCLR_PDCLR0);
 295 }
 296
 297 static int davinci_i2c_get_scl(struct i2c_adapter *adap)
 298 {
 299         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 300         int val;
 301
 302         /* read the state of SCL */
 303         val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
 304         return val & DAVINCI_I2C_DIN_PDIN0;
 305 }
 306
 307 static int davinci_i2c_get_sda(struct i2c_adapter *adap)
 308 {
 309         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 310         int val;
 311
 312         /* read the state of SDA */
 313         val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
 314         return val & DAVINCI_I2C_DIN_PDIN1;
 315 }
 316
 317 static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
 318 {
 319         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 320
 321         davinci_i2c_prepare_recovery(adap);
 322
 323         /* SCL output, SDA input */
 324         davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
 325
 326         /* change to GPIO mode */
 327         davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
 328                               DAVINCI_I2C_FUNC_PFUNC0);
 329 }
 330
 331 static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
 332 {
 333         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 334
 335         /* change back to I2C mode */
 336         davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
 337
 338         davinci_i2c_unprepare_recovery(adap);
 339 }
 340
 341 static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
 342         .recover_bus = i2c_generic_scl_recovery,
 343         .set_scl = davinci_i2c_set_scl,
 344         .get_scl = davinci_i2c_get_scl,
 345         .get_sda = davinci_i2c_get_sda,
 346         .prepare_recovery = davinci_i2c_scl_prepare_recovery,
 347         .unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
 348 };
 349
 350 /*
 351  * Waiting for bus not busy
 352  */
 353 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
 354                                          char allow_sleep)
 355 {
 356         unsigned long timeout;
 357         static u16 to_cnt;
 358
 359         timeout = jiffies + dev->adapter.timeout;
 360         while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
 361                & DAVINCI_I2C_STR_BB) {
 362                 if (to_cnt <= DAVINCI_I2C_MAX_TRIES) {
 363                         if (time_after(jiffies, timeout)) {
 364                                 dev_warn(dev->dev,
 365                                 "timeout waiting for bus ready\n");
 366                                 to_cnt++;
 367                                 return -ETIMEDOUT;
 368                         } else {
 369                                 to_cnt = 0;
 370                                 i2c_recover_bus(&dev->adapter);
 371                         }
 372                 }
 373                 if (allow_sleep)
 374                         schedule_timeout(1);
 375         }
 376
 377         return 0;
 378 }
 379
 380 /*
 381  * Low level master read/write transaction. This function is called
 382  * from i2c_davinci_xfer.
 383  */
 384 static int
 385 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
 386 {
 387         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 388         struct davinci_i2c_platform_data *pdata = dev->pdata;
 389         u32 flag;
 390         u16 w;
 391         unsigned long time_left;
 392
 393         /* Introduce a delay, required for some boards (e.g Davinci EVM) */
 394         if (pdata->bus_delay)
 395                 udelay(pdata->bus_delay);
 396
 397         /* set the slave address */
 398         davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
 399
 400         dev->buf = msg->buf;
 401         dev->buf_len = msg->len;
 402         dev->stop = stop;
 403
 404         davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
 405
 406         reinit_completion(&dev->cmd_complete);
 407         dev->cmd_err = 0;
 408
 409         /* Take I2C out of reset and configure it as master */
 410         flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
 411
 412         /* if the slave address is ten bit address, enable XA bit */
 413         if (msg->flags & I2C_M_TEN)
 414                 flag |= DAVINCI_I2C_MDR_XA;
 415         if (!(msg->flags & I2C_M_RD))
 416                 flag |= DAVINCI_I2C_MDR_TRX;
 417         if (msg->len == 0)
 418                 flag |= DAVINCI_I2C_MDR_RM;
 419
 420         /* Enable receive or transmit interrupts */
 421         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
 422         if (msg->flags & I2C_M_RD)
 423                 w |= DAVINCI_I2C_IMR_RRDY;
 424         else
 425                 w |= DAVINCI_I2C_IMR_XRDY;
 426         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
 427
 428         dev->terminate = 0;
 429
 430         /*
 431          * Write mode register first as needed for correct behaviour
 432          * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
 433          * occurring before we have loaded DXR
 434          */
 435         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 436
 437         /*
 438          * First byte should be set here, not after interrupt,
 439          * because transmit-data-ready interrupt can come before
 440          * NACK-interrupt during sending of previous message and
 441          * ICDXR may have wrong data
 442          * It also saves us one interrupt, slightly faster
 443          */
 444         if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
 445                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
 446                 dev->buf_len--;
 447         }
 448
 449         /* Set STT to begin transmit now DXR is loaded */
 450         flag |= DAVINCI_I2C_MDR_STT;
 451         if (stop && msg->len != 0)
 452                 flag |= DAVINCI_I2C_MDR_STP;
 453         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 454
 455         time_left = wait_for_completion_timeout(&dev->cmd_complete,
 456                                                 dev->adapter.timeout);
 457         if (!time_left) {
 458                 dev_err(dev->dev, "controller timed out\n");
 459                 i2c_recover_bus(adap);
 460                 dev->buf_len = 0;
 461                 return -ETIMEDOUT;
 462         }
 463         if (dev->buf_len) {
 464                 /* This should be 0 if all bytes were transferred
 465                  * or dev->cmd_err denotes an error.
 466                  */
 467                 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
 468                         dev->buf_len);
 469                 dev->terminate = 1;
 470                 wmb();
 471                 dev->buf_len = 0;
 472                 return -EREMOTEIO;
 473         }
 474
 475         /* no error */
 476         if (likely(!dev->cmd_err))
 477                 return msg->len;
 478
 479         /* We have an error */
 480         if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
 481                 i2c_davinci_init(dev);
 482                 return -EIO;
 483         }
 484
 485         if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
 486                 if (msg->flags & I2C_M_IGNORE_NAK)
 487                         return msg->len;
 488                 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 489                 w |= DAVINCI_I2C_MDR_STP;
 490                 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 491                 return -EREMOTEIO;
 492         }
 493         return -EIO;
 494 }
 495
 496 /*
 497  * Prepare controller for a transaction and call i2c_davinci_xfer_msg
 498  */
 499 static int
 500 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 501 {
 502         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 503         int i;
 504         int ret;
 505
 506         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 507
 508         ret = i2c_davinci_wait_bus_not_busy(dev, 1);
 509         if (ret < 0) {
 510                 dev_warn(dev->dev, "timeout waiting for bus ready\n");
 511                 return ret;
 512         }
 513
 514         for (i = 0; i < num; i++) {
 515                 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 516                 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
 517                         ret);
 518                 if (ret < 0)
 519                         return ret;
 520         }
 521
 522 #ifdef CONFIG_CPU_FREQ
 523         complete(&dev->xfr_complete);
 524 #endif
 525
 526         return num;
 527 }
 528
 529 static u32 i2c_davinci_func(struct i2c_adapter *adap)
 530 {
 531         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 532 }
 533
 534 static void terminate_read(struct davinci_i2c_dev *dev)
 535 {
 536         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 537         w |= DAVINCI_I2C_MDR_NACK;
 538         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 539
 540         /* Throw away data */
 541         davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
 542         if (!dev->terminate)
 543                 dev_err(dev->dev, "RDR IRQ while no data requested\n");
 544 }
 545 static void terminate_write(struct davinci_i2c_dev *dev)
 546 {
 547         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 548         w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
 549         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 550
 551         if (!dev->terminate)
 552                 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
 553 }
 554
 555 /*
 556  * Interrupt service routine. This gets called whenever an I2C interrupt
 557  * occurs.
 558  */
 559 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
 560 {
 561         struct davinci_i2c_dev *dev = dev_id;
 562         u32 stat;
 563         int count = 0;
 564         u16 w;
 565
 566         while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
 567                 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
 568                 if (count++ == 100) {
 569                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 570                         break;
 571                 }
 572
 573                 switch (stat) {
 574                 case DAVINCI_I2C_IVR_AL:
 575                         /* Arbitration lost, must retry */
 576                         dev->cmd_err |= DAVINCI_I2C_STR_AL;
 577                         dev->buf_len = 0;
 578                         complete(&dev->cmd_complete);
 579                         break;
 580
 581                 case DAVINCI_I2C_IVR_NACK:
 582                         dev->cmd_err |= DAVINCI_I2C_STR_NACK;
 583                         dev->buf_len = 0;
 584                         complete(&dev->cmd_complete);
 585                         break;
 586
 587                 case DAVINCI_I2C_IVR_ARDY:
 588                         davinci_i2c_write_reg(dev,
 589                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
 590                         if (((dev->buf_len == 0) && (dev->stop != 0)) ||
 591                             (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
 592                                 w = davinci_i2c_read_reg(dev,
 593                                                          DAVINCI_I2C_MDR_REG);
 594                                 w |= DAVINCI_I2C_MDR_STP;
 595                                 davinci_i2c_write_reg(dev,
 596                                                       DAVINCI_I2C_MDR_REG, w);
 597                         }
 598                         complete(&dev->cmd_complete);
 599                         break;
 600
 601                 case DAVINCI_I2C_IVR_RDR:
 602                         if (dev->buf_len) {
 603                                 *dev->buf++ =
 604                                     davinci_i2c_read_reg(dev,
 605                                                          DAVINCI_I2C_DRR_REG);
 606                                 dev->buf_len--;
 607                                 if (dev->buf_len)
 608                                         continue;
 609
 610                                 davinci_i2c_write_reg(dev,
 611                                         DAVINCI_I2C_STR_REG,
 612                                         DAVINCI_I2C_IMR_RRDY);
 613                         } else {
 614                                 /* signal can terminate transfer */
 615                                 terminate_read(dev);
 616                         }
 617                         break;
 618
 619                 case DAVINCI_I2C_IVR_XRDY:
 620                         if (dev->buf_len) {
 621                                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
 622                                                       *dev->buf++);
 623                                 dev->buf_len--;
 624                                 if (dev->buf_len)
 625                                         continue;
 626
 627                                 w = davinci_i2c_read_reg(dev,
 628                                                          DAVINCI_I2C_IMR_REG);
 629                                 w &= ~DAVINCI_I2C_IMR_XRDY;
 630                                 davinci_i2c_write_reg(dev,
 631                                                       DAVINCI_I2C_IMR_REG,
 632                                                       w);
 633                         } else {
 634                                 /* signal can terminate transfer */
 635                                 terminate_write(dev);
 636                         }
 637                         break;
 638
 639                 case DAVINCI_I2C_IVR_SCD:
 640                         davinci_i2c_write_reg(dev,
 641                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
 642                         complete(&dev->cmd_complete);
 643                         break;
 644
 645                 case DAVINCI_I2C_IVR_AAS:
 646                         dev_dbg(dev->dev, "Address as slave interrupt\n");
 647                         break;
 648
 649                 default:
 650                         dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
 651                         break;
 652                 }
 653         }
 654
 655         return count ? IRQ_HANDLED : IRQ_NONE;
 656 }
 657
 658 #ifdef CONFIG_CPU_FREQ
 659 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
 660                                      unsigned long val, void *data)
 661 {
 662         struct davinci_i2c_dev *dev;
 663
 664         dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
 665         if (val == CPUFREQ_PRECHANGE) {
 666                 wait_for_completion(&dev->xfr_complete);
 667                 davinci_i2c_reset_ctrl(dev, 0);
 668         } else if (val == CPUFREQ_POSTCHANGE) {
 669                 i2c_davinci_calc_clk_dividers(dev);
 670                 davinci_i2c_reset_ctrl(dev, 1);
 671         }
 672
 673         return 0;
 674 }
 675
 676 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
 677 {
 678         dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
 679
 680         return cpufreq_register_notifier(&dev->freq_transition,
 681                                          CPUFREQ_TRANSITION_NOTIFIER);
 682 }
 683
 684 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
 685 {
 686         cpufreq_unregister_notifier(&dev->freq_transition,
 687                                     CPUFREQ_TRANSITION_NOTIFIER);
 688 }
 689 #else
 690 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
 691 {
 692         return 0;
 693 }
 694
 695 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
 696 {
 697 }
 698 #endif
 699
 700 static struct i2c_algorithm i2c_davinci_algo = {
 701         .master_xfer    = i2c_davinci_xfer,
 702         .functionality  = i2c_davinci_func,
 703 };
 704
 705 static const struct of_device_id davinci_i2c_of_match[] = {
 706         {.compatible = "ti,davinci-i2c", },
 707         {},
 708 };
 709 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
 710
 711 static int davinci_i2c_probe(struct platform_device *pdev)
 712 {
 713         struct davinci_i2c_dev *dev;
 714         struct i2c_adapter *adap;
 715         struct resource *mem;
 716         int r, irq;
 717
 718         irq = platform_get_irq(pdev, 0);
 719         if (irq <= 0) {
 720                 if (!irq)
 721                         irq = -ENXIO;
 722                 if (irq != -EPROBE_DEFER)
 723                         dev_err(&pdev->dev,
 724                                 "can't get irq resource ret=%d\n", irq);
 725                 return irq;
 726         }
 727
 728         dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
 729                         GFP_KERNEL);
 730         if (!dev) {
 731                 dev_err(&pdev->dev, "Memory allocation failed\n");
 732                 return -ENOMEM;
 733         }
 734
 735         init_completion(&dev->cmd_complete);
 736 #ifdef CONFIG_CPU_FREQ
 737         init_completion(&dev->xfr_complete);
 738 #endif
 739         dev->dev = &pdev->dev;
 740         dev->irq = irq;
 741         dev->pdata = dev_get_platdata(&pdev->dev);
 742         platform_set_drvdata(pdev, dev);
 743
 744         if (!dev->pdata && pdev->dev.of_node) {
 745                 u32 prop;
 746
 747                 dev->pdata = devm_kzalloc(&pdev->dev,
 748                         sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
 749                 if (!dev->pdata)
 750                         return -ENOMEM;
 751
 752                 memcpy(dev->pdata, &davinci_i2c_platform_data_default,
 753                         sizeof(struct davinci_i2c_platform_data));
 754                 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 755                         &prop))
 756                         dev->pdata->bus_freq = prop / 1000;
 757
 758                 dev->pdata->has_pfunc =
 759                         of_property_read_bool(pdev->dev.of_node,
 760                                               "ti,has-pfunc");
 761         } else if (!dev->pdata) {
 762                 dev->pdata = &davinci_i2c_platform_data_default;
 763         }
 764
 765         dev->clk = devm_clk_get(&pdev->dev, NULL);
 766         if (IS_ERR(dev->clk))
 767                 return -ENODEV;
 768         clk_prepare_enable(dev->clk);
 769
 770         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 771         dev->base = devm_ioremap_resource(&pdev->dev, mem);
 772         if (IS_ERR(dev->base)) {
 773                 r = PTR_ERR(dev->base);
 774                 goto err_unuse_clocks;
 775         }
 776
 777         i2c_davinci_init(dev);
 778
 779         r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
 780                         pdev->name, dev);
 781         if (r) {
 782                 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
 783                 goto err_unuse_clocks;
 784         }
 785
 786         r = i2c_davinci_cpufreq_register(dev);
 787         if (r) {
 788                 dev_err(&pdev->dev, "failed to register cpufreq\n");
 789                 goto err_unuse_clocks;
 790         }
 791
 792         adap = &dev->adapter;
 793         i2c_set_adapdata(adap, dev);
 794         adap->owner = THIS_MODULE;
 795         adap->class = I2C_CLASS_DEPRECATED;
 796         strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
 797         adap->algo = &i2c_davinci_algo;
 798         adap->dev.parent = &pdev->dev;
 799         adap->timeout = DAVINCI_I2C_TIMEOUT;
 800         adap->dev.of_node = pdev->dev.of_node;
 801
 802         if (dev->pdata->has_pfunc)
 803                 adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
 804         else if (dev->pdata->scl_pin) {
 805                 adap->bus_recovery_info = &davinci_i2c_gpio_recovery_info;
 806                 adap->bus_recovery_info->scl_gpio = dev->pdata->scl_pin;
 807                 adap->bus_recovery_info->sda_gpio = dev->pdata->sda_pin;
 808         }
 809
 810         adap->nr = pdev->id;
 811         r = i2c_add_numbered_adapter(adap);
 812         if (r) {
 813                 dev_err(&pdev->dev, "failure adding adapter\n");
 814                 goto err_unuse_clocks;
 815         }
 816
 817         return 0;
 818
 819 err_unuse_clocks:
 820         clk_disable_unprepare(dev->clk);
 821         dev->clk = NULL;
 822         return r;
 823 }
 824
 825 static int davinci_i2c_remove(struct platform_device *pdev)
 826 {
 827         struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
 828
 829         i2c_davinci_cpufreq_deregister(dev);
 830
 831         i2c_del_adapter(&dev->adapter);
 832
 833         clk_disable_unprepare(dev->clk);
 834         dev->clk = NULL;
 835
 836         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
 837
 838         return 0;
 839 }
 840
 841 #ifdef CONFIG_PM
 842 static int davinci_i2c_suspend(struct device *dev)
 843 {
 844         struct platform_device *pdev = to_platform_device(dev);
 845         struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 846
 847         /* put I2C into reset */
 848         davinci_i2c_reset_ctrl(i2c_dev, 0);
 849         clk_disable_unprepare(i2c_dev->clk);
 850
 851         return 0;
 852 }
 853
 854 static int davinci_i2c_resume(struct device *dev)
 855 {
 856         struct platform_device *pdev = to_platform_device(dev);
 857         struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 858
 859         clk_prepare_enable(i2c_dev->clk);
 860         /* take I2C out of reset */
 861         davinci_i2c_reset_ctrl(i2c_dev, 1);
 862
 863         return 0;
 864 }
 865
 866 static const struct dev_pm_ops davinci_i2c_pm = {
 867         .suspend        = davinci_i2c_suspend,
 868         .resume         = davinci_i2c_resume,
 869 };
 870
 871 #define davinci_i2c_pm_ops (&davinci_i2c_pm)
 872 #else
 873 #define davinci_i2c_pm_ops NULL
 874 #endif
 875
 876 /* work with hotplug and coldplug */
 877 MODULE_ALIAS("platform:i2c_davinci");
 878
 879 static struct platform_driver davinci_i2c_driver = {
 880         .probe          = davinci_i2c_probe,
 881         .remove         = davinci_i2c_remove,
 882         .driver         = {
 883                 .name   = "i2c_davinci",
 884                 .pm     = davinci_i2c_pm_ops,
 885                 .of_match_table = davinci_i2c_of_match,
 886         },
 887 };
 888
 889 /* I2C may be needed to bring up other drivers */
 890 static int __init davinci_i2c_init_driver(void)
 891 {
 892         return platform_driver_register(&davinci_i2c_driver);
 893 }
 894 subsys_initcall(davinci_i2c_init_driver);
 895
 896 static void __exit davinci_i2c_exit_driver(void)
 897 {
 898         platform_driver_unregister(&davinci_i2c_driver);
 899 }
 900 module_exit(davinci_i2c_exit_driver);
 901
 902 MODULE_AUTHOR("Texas Instruments India");
 903 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
 904 MODULE_LICENSE("GPL");