kernel/drivers/i2c/busses/i2c-cadence.c

   1 /*
   2  * I2C bus driver for the Cadence I2C controller.
   3  *
   4  * Copyright (C) 2009 - 2014 Xilinx, Inc.
   5  *
   6  * This program is free software; you can redistribute it
   7  * and/or modify it under the terms of the GNU General Public
   8  * License as published by the Free Software Foundation;
   9  * either version 2 of the License, or (at your option) any
  10  * later version.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/i2c.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20
  21 /* Register offsets for the I2C device. */
  22 #define CDNS_I2C_CR_OFFSET              0x00 /* Control Register, RW */
  23 #define CDNS_I2C_SR_OFFSET              0x04 /* Status Register, RO */
  24 #define CDNS_I2C_ADDR_OFFSET            0x08 /* I2C Address Register, RW */
  25 #define CDNS_I2C_DATA_OFFSET            0x0C /* I2C Data Register, RW */
  26 #define CDNS_I2C_ISR_OFFSET             0x10 /* IRQ Status Register, RW */
  27 #define CDNS_I2C_XFER_SIZE_OFFSET       0x14 /* Transfer Size Register, RW */
  28 #define CDNS_I2C_TIME_OUT_OFFSET        0x1C /* Time Out Register, RW */
  29 #define CDNS_I2C_IER_OFFSET             0x24 /* IRQ Enable Register, WO */
  30 #define CDNS_I2C_IDR_OFFSET             0x28 /* IRQ Disable Register, WO */
  31
  32 /* Control Register Bit mask definitions */
  33 #define CDNS_I2C_CR_HOLD                BIT(4) /* Hold Bus bit */
  34 #define CDNS_I2C_CR_ACK_EN              BIT(3)
  35 #define CDNS_I2C_CR_NEA                 BIT(2)
  36 #define CDNS_I2C_CR_MS                  BIT(1)
  37 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
  38 #define CDNS_I2C_CR_RW                  BIT(0)
  39 /* 1 = Auto init FIFO to zeroes */
  40 #define CDNS_I2C_CR_CLR_FIFO            BIT(6)
  41 #define CDNS_I2C_CR_DIVA_SHIFT          14
  42 #define CDNS_I2C_CR_DIVA_MASK           (3 << CDNS_I2C_CR_DIVA_SHIFT)
  43 #define CDNS_I2C_CR_DIVB_SHIFT          8
  44 #define CDNS_I2C_CR_DIVB_MASK           (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
  45
  46 /* Status Register Bit mask definitions */
  47 #define CDNS_I2C_SR_BA          BIT(8)
  48 #define CDNS_I2C_SR_RXDV        BIT(5)
  49
  50 /*
  51  * I2C Address Register Bit mask definitions
  52  * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
  53  * bits. A write access to this register always initiates a transfer if the I2C
  54  * is in master mode.
  55  */
  56 #define CDNS_I2C_ADDR_MASK      0x000003FF /* I2C Address Mask */
  57
  58 /*
  59  * I2C Interrupt Registers Bit mask definitions
  60  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  61  * bit definitions.
  62  */
  63 #define CDNS_I2C_IXR_ARB_LOST           BIT(9)
  64 #define CDNS_I2C_IXR_RX_UNF             BIT(7)
  65 #define CDNS_I2C_IXR_TX_OVF             BIT(6)
  66 #define CDNS_I2C_IXR_RX_OVF             BIT(5)
  67 #define CDNS_I2C_IXR_SLV_RDY            BIT(4)
  68 #define CDNS_I2C_IXR_TO                 BIT(3)
  69 #define CDNS_I2C_IXR_NACK               BIT(2)
  70 #define CDNS_I2C_IXR_DATA               BIT(1)
  71 #define CDNS_I2C_IXR_COMP               BIT(0)
  72
  73 #define CDNS_I2C_IXR_ALL_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  74                                          CDNS_I2C_IXR_RX_UNF | \
  75                                          CDNS_I2C_IXR_TX_OVF | \
  76                                          CDNS_I2C_IXR_RX_OVF | \
  77                                          CDNS_I2C_IXR_SLV_RDY | \
  78                                          CDNS_I2C_IXR_TO | \
  79                                          CDNS_I2C_IXR_NACK | \
  80                                          CDNS_I2C_IXR_DATA | \
  81                                          CDNS_I2C_IXR_COMP)
  82
  83 #define CDNS_I2C_IXR_ERR_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  84                                          CDNS_I2C_IXR_RX_UNF | \
  85                                          CDNS_I2C_IXR_TX_OVF | \
  86                                          CDNS_I2C_IXR_RX_OVF | \
  87                                          CDNS_I2C_IXR_NACK)
  88
  89 #define CDNS_I2C_ENABLED_INTR_MASK      (CDNS_I2C_IXR_ARB_LOST | \
  90                                          CDNS_I2C_IXR_RX_UNF | \
  91                                          CDNS_I2C_IXR_TX_OVF | \
  92                                          CDNS_I2C_IXR_RX_OVF | \
  93                                          CDNS_I2C_IXR_NACK | \
  94                                          CDNS_I2C_IXR_DATA | \
  95                                          CDNS_I2C_IXR_COMP)
  96
  97 #define CDNS_I2C_TIMEOUT                msecs_to_jiffies(1000)
  98
  99 #define CDNS_I2C_FIFO_DEPTH             16
 100 /* FIFO depth at which the DATA interrupt occurs */
 101 #define CDNS_I2C_DATA_INTR_DEPTH        (CDNS_I2C_FIFO_DEPTH - 2)
 102 #define CDNS_I2C_MAX_TRANSFER_SIZE      255
 103 /* Transfer size in multiples of data interrupt depth */
 104 #define CDNS_I2C_TRANSFER_SIZE  (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
 105
 106 #define DRIVER_NAME             "cdns-i2c"
 107
 108 #define CDNS_I2C_SPEED_MAX      400000
 109 #define CDNS_I2C_SPEED_DEFAULT  100000
 110
 111 #define CDNS_I2C_DIVA_MAX       4
 112 #define CDNS_I2C_DIVB_MAX       64
 113
 114 #define CDNS_I2C_TIMEOUT_MAX    0xFF
 115
 116 #define cdns_i2c_readreg(offset)       readl_relaxed(id->membase + offset)
 117 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
 118
 119 /**
 120  * struct cdns_i2c - I2C device private data structure
 121  * @membase:            Base address of the I2C device
 122  * @adap:               I2C adapter instance
 123  * @p_msg:              Message pointer
 124  * @err_status:         Error status in Interrupt Status Register
 125  * @xfer_done:          Transfer complete status
 126  * @p_send_buf:         Pointer to transmit buffer
 127  * @p_recv_buf:         Pointer to receive buffer
 128  * @suspended:          Flag holding the device's PM status
 129  * @send_count:         Number of bytes still expected to send
 130  * @recv_count:         Number of bytes still expected to receive
 131  * @curr_recv_count:    Number of bytes to be received in current transfer
 132  * @irq:                IRQ number
 133  * @input_clk:          Input clock to I2C controller
 134  * @i2c_clk:            Maximum I2C clock speed
 135  * @bus_hold_flag:      Flag used in repeated start for clearing HOLD bit
 136  * @clk:                Pointer to struct clk
 137  * @clk_rate_change_nb: Notifier block for clock rate changes
 138  */
 139 struct cdns_i2c {
 140         void __iomem *membase;
 141         struct i2c_adapter adap;
 142         struct i2c_msg *p_msg;
 143         int err_status;
 144         struct completion xfer_done;
 145         unsigned char *p_send_buf;
 146         unsigned char *p_recv_buf;
 147         u8 suspended;
 148         unsigned int send_count;
 149         unsigned int recv_count;
 150         unsigned int curr_recv_count;
 151         int irq;
 152         unsigned long input_clk;
 153         unsigned int i2c_clk;
 154         unsigned int bus_hold_flag;
 155         struct clk *clk;
 156         struct notifier_block clk_rate_change_nb;
 157 };
 158
 159 #define to_cdns_i2c(_nb)        container_of(_nb, struct cdns_i2c, \
 160                                              clk_rate_change_nb)
 161
 162 /**
 163  * cdns_i2c_clear_bus_hold() - Clear bus hold bit
 164  * @id: Pointer to driver data struct
 165  *
 166  * Helper to clear the controller's bus hold bit.
 167  */
 168 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
 169 {
 170         u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 171         if (reg & CDNS_I2C_CR_HOLD)
 172                 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
 173 }
 174
 175 /**
 176  * cdns_i2c_isr - Interrupt handler for the I2C device
 177  * @irq:        irq number for the I2C device
 178  * @ptr:        void pointer to cdns_i2c structure
 179  *
 180  * This function handles the data interrupt, transfer complete interrupt and
 181  * the error interrupts of the I2C device.
 182  *
 183  * Return: IRQ_HANDLED always
 184  */
 185 static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
 186 {
 187         unsigned int isr_status, avail_bytes, updatetx;
 188         unsigned int bytes_to_send;
 189         struct cdns_i2c *id = ptr;
 190         /* Signal completion only after everything is updated */
 191         int done_flag = 0;
 192         irqreturn_t status = IRQ_NONE;
 193
 194         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 195         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 196
 197         /* Handling nack and arbitration lost interrupt */
 198         if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
 199                 done_flag = 1;
 200                 status = IRQ_HANDLED;
 201         }
 202
 203         /*
 204          * Check if transfer size register needs to be updated again for a
 205          * large data receive operation.
 206          */
 207         updatetx = 0;
 208         if (id->recv_count > id->curr_recv_count)
 209                 updatetx = 1;
 210
 211         /* When receiving, handle data interrupt and completion interrupt */
 212         if (id->p_recv_buf &&
 213             ((isr_status & CDNS_I2C_IXR_COMP) ||
 214              (isr_status & CDNS_I2C_IXR_DATA))) {
 215                 /* Read data if receive data valid is set */
 216                 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
 217                        CDNS_I2C_SR_RXDV) {
 218                         /*
 219                          * Clear hold bit that was set for FIFO control if
 220                          * RX data left is less than FIFO depth, unless
 221                          * repeated start is selected.
 222                          */
 223                         if ((id->recv_count < CDNS_I2C_FIFO_DEPTH) &&
 224                             !id->bus_hold_flag)
 225                                 cdns_i2c_clear_bus_hold(id);
 226
 227                         *(id->p_recv_buf)++ =
 228                                 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
 229                         id->recv_count--;
 230                         id->curr_recv_count--;
 231
 232                         if (updatetx &&
 233                             (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1))
 234                                 break;
 235                 }
 236
 237                 /*
 238                  * The controller sends NACK to the slave when transfer size
 239                  * register reaches zero without considering the HOLD bit.
 240                  * This workaround is implemented for large data transfers to
 241                  * maintain transfer size non-zero while performing a large
 242                  * receive operation.
 243                  */
 244                 if (updatetx &&
 245                     (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)) {
 246                         /* wait while fifo is full */
 247                         while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
 248                                (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
 249                                 ;
 250
 251                         /*
 252                          * Check number of bytes to be received against maximum
 253                          * transfer size and update register accordingly.
 254                          */
 255                         if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) >
 256                             CDNS_I2C_TRANSFER_SIZE) {
 257                                 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
 258                                                   CDNS_I2C_XFER_SIZE_OFFSET);
 259                                 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
 260                                                       CDNS_I2C_FIFO_DEPTH;
 261                         } else {
 262                                 cdns_i2c_writereg(id->recv_count -
 263                                                   CDNS_I2C_FIFO_DEPTH,
 264                                                   CDNS_I2C_XFER_SIZE_OFFSET);
 265                                 id->curr_recv_count = id->recv_count;
 266                         }
 267                 }
 268
 269                 /* Clear hold (if not repeated start) and signal completion */
 270                 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) {
 271                         if (!id->bus_hold_flag)
 272                                 cdns_i2c_clear_bus_hold(id);
 273                         done_flag = 1;
 274                 }
 275
 276                 status = IRQ_HANDLED;
 277         }
 278
 279         /* When sending, handle transfer complete interrupt */
 280         if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) {
 281                 /*
 282                  * If there is more data to be sent, calculate the
 283                  * space available in FIFO and fill with that many bytes.
 284                  */
 285                 if (id->send_count) {
 286                         avail_bytes = CDNS_I2C_FIFO_DEPTH -
 287                             cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
 288                         if (id->send_count > avail_bytes)
 289                                 bytes_to_send = avail_bytes;
 290                         else
 291                                 bytes_to_send = id->send_count;
 292
 293                         while (bytes_to_send--) {
 294                                 cdns_i2c_writereg(
 295                                         (*(id->p_send_buf)++),
 296                                          CDNS_I2C_DATA_OFFSET);
 297                                 id->send_count--;
 298                         }
 299                 } else {
 300                         /*
 301                          * Signal the completion of transaction and
 302                          * clear the hold bus bit if there are no
 303                          * further messages to be processed.
 304                          */
 305                         done_flag = 1;
 306                 }
 307                 if (!id->send_count && !id->bus_hold_flag)
 308                         cdns_i2c_clear_bus_hold(id);
 309
 310                 status = IRQ_HANDLED;
 311         }
 312
 313         /* Update the status for errors */
 314         id->err_status = isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
 315         if (id->err_status)
 316                 status = IRQ_HANDLED;
 317
 318         if (done_flag)
 319                 complete(&id->xfer_done);
 320
 321         return status;
 322 }
 323
 324 /**
 325  * cdns_i2c_mrecv - Prepare and start a master receive operation
 326  * @id:         pointer to the i2c device structure
 327  */
 328 static void cdns_i2c_mrecv(struct cdns_i2c *id)
 329 {
 330         unsigned int ctrl_reg;
 331         unsigned int isr_status;
 332
 333         id->p_recv_buf = id->p_msg->buf;
 334         id->recv_count = id->p_msg->len;
 335
 336         /* Put the controller in master receive mode and clear the FIFO */
 337         ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 338         ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
 339
 340         if (id->p_msg->flags & I2C_M_RECV_LEN)
 341                 id->recv_count = I2C_SMBUS_BLOCK_MAX + 1;
 342
 343         id->curr_recv_count = id->recv_count;
 344
 345         /*
 346          * Check for the message size against FIFO depth and set the
 347          * 'hold bus' bit if it is greater than FIFO depth.
 348          */
 349         if (id->recv_count > CDNS_I2C_FIFO_DEPTH)
 350                 ctrl_reg |= CDNS_I2C_CR_HOLD;
 351
 352         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 353
 354         /* Clear the interrupts in interrupt status register */
 355         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 356         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 357
 358         /*
 359          * The no. of bytes to receive is checked against the limit of
 360          * max transfer size. Set transfer size register with no of bytes
 361          * receive if it is less than transfer size and transfer size if
 362          * it is more. Enable the interrupts.
 363          */
 364         if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
 365                 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
 366                                   CDNS_I2C_XFER_SIZE_OFFSET);
 367                 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
 368         } else {
 369                 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
 370         }
 371
 372         /* Clear the bus hold flag if bytes to receive is less than FIFO size */
 373         if (!id->bus_hold_flag &&
 374                 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&
 375                 (id->recv_count <= CDNS_I2C_FIFO_DEPTH))
 376                         cdns_i2c_clear_bus_hold(id);
 377         /* Set the slave address in address register - triggers operation */
 378         cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
 379                                                 CDNS_I2C_ADDR_OFFSET);
 380         cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
 381 }
 382
 383 /**
 384  * cdns_i2c_msend - Prepare and start a master send operation
 385  * @id:         pointer to the i2c device
 386  */
 387 static void cdns_i2c_msend(struct cdns_i2c *id)
 388 {
 389         unsigned int avail_bytes;
 390         unsigned int bytes_to_send;
 391         unsigned int ctrl_reg;
 392         unsigned int isr_status;
 393
 394         id->p_recv_buf = NULL;
 395         id->p_send_buf = id->p_msg->buf;
 396         id->send_count = id->p_msg->len;
 397
 398         /* Set the controller in Master transmit mode and clear the FIFO. */
 399         ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 400         ctrl_reg &= ~CDNS_I2C_CR_RW;
 401         ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
 402
 403         /*
 404          * Check for the message size against FIFO depth and set the
 405          * 'hold bus' bit if it is greater than FIFO depth.
 406          */
 407         if (id->send_count > CDNS_I2C_FIFO_DEPTH)
 408                 ctrl_reg |= CDNS_I2C_CR_HOLD;
 409         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 410
 411         /* Clear the interrupts in interrupt status register. */
 412         isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 413         cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
 414
 415         /*
 416          * Calculate the space available in FIFO. Check the message length
 417          * against the space available, and fill the FIFO accordingly.
 418          * Enable the interrupts.
 419          */
 420         avail_bytes = CDNS_I2C_FIFO_DEPTH -
 421                                 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
 422
 423         if (id->send_count > avail_bytes)
 424                 bytes_to_send = avail_bytes;
 425         else
 426                 bytes_to_send = id->send_count;
 427
 428         while (bytes_to_send--) {
 429                 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
 430                 id->send_count--;
 431         }
 432
 433         /*
 434          * Clear the bus hold flag if there is no more data
 435          * and if it is the last message.
 436          */
 437         if (!id->bus_hold_flag && !id->send_count)
 438                 cdns_i2c_clear_bus_hold(id);
 439         /* Set the slave address in address register - triggers operation. */
 440         cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
 441                                                 CDNS_I2C_ADDR_OFFSET);
 442
 443         cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
 444 }
 445
 446 /**
 447  * cdns_i2c_master_reset - Reset the interface
 448  * @adap:       pointer to the i2c adapter driver instance
 449  *
 450  * This function cleanup the fifos, clear the hold bit and status
 451  * and disable the interrupts.
 452  */
 453 static void cdns_i2c_master_reset(struct i2c_adapter *adap)
 454 {
 455         struct cdns_i2c *id = adap->algo_data;
 456         u32 regval;
 457
 458         /* Disable the interrupts */
 459         cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
 460         /* Clear the hold bit and fifos */
 461         regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 462         regval &= ~CDNS_I2C_CR_HOLD;
 463         regval |= CDNS_I2C_CR_CLR_FIFO;
 464         cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
 465         /* Update the transfercount register to zero */
 466         cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
 467         /* Clear the interupt status register */
 468         regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
 469         cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
 470         /* Clear the status register */
 471         regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
 472         cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
 473 }
 474
 475 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
 476                 struct i2c_adapter *adap)
 477 {
 478         unsigned long time_left;
 479         u32 reg;
 480
 481         id->p_msg = msg;
 482         id->err_status = 0;
 483         reinit_completion(&id->xfer_done);
 484
 485         /* Check for the TEN Bit mode on each msg */
 486         reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 487         if (msg->flags & I2C_M_TEN) {
 488                 if (reg & CDNS_I2C_CR_NEA)
 489                         cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
 490                                         CDNS_I2C_CR_OFFSET);
 491         } else {
 492                 if (!(reg & CDNS_I2C_CR_NEA))
 493                         cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
 494                                         CDNS_I2C_CR_OFFSET);
 495         }
 496
 497         /* Check for the R/W flag on each msg */
 498         if (msg->flags & I2C_M_RD)
 499                 cdns_i2c_mrecv(id);
 500         else
 501                 cdns_i2c_msend(id);
 502
 503         /* Wait for the signal of completion */
 504         time_left = wait_for_completion_timeout(&id->xfer_done, adap->timeout);
 505         if (time_left == 0) {
 506                 cdns_i2c_master_reset(adap);
 507                 dev_err(id->adap.dev.parent,
 508                                 "timeout waiting on completion\n");
 509                 return -ETIMEDOUT;
 510         }
 511
 512         cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
 513                           CDNS_I2C_IDR_OFFSET);
 514
 515         /* If it is bus arbitration error, try again */
 516         if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
 517                 return -EAGAIN;
 518
 519         return 0;
 520 }
 521
 522 /**
 523  * cdns_i2c_master_xfer - The main i2c transfer function
 524  * @adap:       pointer to the i2c adapter driver instance
 525  * @msgs:       pointer to the i2c message structure
 526  * @num:        the number of messages to transfer
 527  *
 528  * Initiates the send/recv activity based on the transfer message received.
 529  *
 530  * Return: number of msgs processed on success, negative error otherwise
 531  */
 532 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 533                                 int num)
 534 {
 535         int ret, count;
 536         u32 reg;
 537         struct cdns_i2c *id = adap->algo_data;
 538
 539         /* Check if the bus is free */
 540         if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA)
 541                 return -EAGAIN;
 542
 543         /*
 544          * Set the flag to one when multiple messages are to be
 545          * processed with a repeated start.
 546          */
 547         if (num > 1) {
 548                 /*
 549                  * This controller does not give completion interrupt after a
 550                  * master receive message if HOLD bit is set (repeated start),
 551                  * resulting in SW timeout. Hence, if a receive message is
 552                  * followed by any other message, an error is returned
 553                  * indicating that this sequence is not supported.
 554                  */
 555                 for (count = 0; count < num - 1; count++) {
 556                         if (msgs[count].flags & I2C_M_RD) {
 557                                 dev_warn(adap->dev.parent,
 558                                          "Can't do repeated start after a receive message\n");
 559                                 return -EOPNOTSUPP;
 560                         }
 561                 }
 562                 id->bus_hold_flag = 1;
 563                 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 564                 reg |= CDNS_I2C_CR_HOLD;
 565                 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
 566         } else {
 567                 id->bus_hold_flag = 0;
 568         }
 569
 570         /* Process the msg one by one */
 571         for (count = 0; count < num; count++, msgs++) {
 572                 if (count == (num - 1))
 573                         id->bus_hold_flag = 0;
 574
 575                 ret = cdns_i2c_process_msg(id, msgs, adap);
 576                 if (ret)
 577                         return ret;
 578
 579                 /* Report the other error interrupts to application */
 580                 if (id->err_status) {
 581                         cdns_i2c_master_reset(adap);
 582
 583                         if (id->err_status & CDNS_I2C_IXR_NACK)
 584                                 return -ENXIO;
 585
 586                         return -EIO;
 587                 }
 588         }
 589
 590         return num;
 591 }
 592
 593 /**
 594  * cdns_i2c_func - Returns the supported features of the I2C driver
 595  * @adap:       pointer to the i2c adapter structure
 596  *
 597  * Return: 32 bit value, each bit corresponding to a feature
 598  */
 599 static u32 cdns_i2c_func(struct i2c_adapter *adap)
 600 {
 601         return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
 602                 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
 603                 I2C_FUNC_SMBUS_BLOCK_DATA;
 604 }
 605
 606 static const struct i2c_algorithm cdns_i2c_algo = {
 607         .master_xfer    = cdns_i2c_master_xfer,
 608         .functionality  = cdns_i2c_func,
 609 };
 610
 611 /**
 612  * cdns_i2c_calc_divs - Calculate clock dividers
 613  * @f:          I2C clock frequency
 614  * @input_clk:  Input clock frequency
 615  * @a:          First divider (return value)
 616  * @b:          Second divider (return value)
 617  *
 618  * f is used as input and output variable. As input it is used as target I2C
 619  * frequency. On function exit f holds the actually resulting I2C frequency.
 620  *
 621  * Return: 0 on success, negative errno otherwise.
 622  */
 623 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
 624                 unsigned int *a, unsigned int *b)
 625 {
 626         unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
 627         unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
 628         unsigned int last_error, current_error;
 629
 630         /* calculate (divisor_a+1) x (divisor_b+1) */
 631         temp = input_clk / (22 * fscl);
 632
 633         /*
 634          * If the calculated value is negative or 0, the fscl input is out of
 635          * range. Return error.
 636          */
 637         if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
 638                 return -EINVAL;
 639
 640         last_error = -1;
 641         for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
 642                 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
 643
 644                 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
 645                         continue;
 646                 div_b--;
 647
 648                 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
 649
 650                 if (actual_fscl > fscl)
 651                         continue;
 652
 653                 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
 654                                                         (fscl - actual_fscl));
 655
 656                 if (last_error > current_error) {
 657                         calc_div_a = div_a;
 658                         calc_div_b = div_b;
 659                         best_fscl = actual_fscl;
 660                         last_error = current_error;
 661                 }
 662         }
 663
 664         *a = calc_div_a;
 665         *b = calc_div_b;
 666         *f = best_fscl;
 667
 668         return 0;
 669 }
 670
 671 /**
 672  * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
 673  * @clk_in:     I2C clock input frequency in Hz
 674  * @id:         Pointer to the I2C device structure
 675  *
 676  * The device must be idle rather than busy transferring data before setting
 677  * these device options.
 678  * The data rate is set by values in the control register.
 679  * The formula for determining the correct register values is
 680  *      Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
 681  * See the hardware data sheet for a full explanation of setting the serial
 682  * clock rate. The clock can not be faster than the input clock divide by 22.
 683  * The two most common clock rates are 100KHz and 400KHz.
 684  *
 685  * Return: 0 on success, negative error otherwise
 686  */
 687 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
 688 {
 689         unsigned int div_a, div_b;
 690         unsigned int ctrl_reg;
 691         int ret = 0;
 692         unsigned long fscl = id->i2c_clk;
 693
 694         ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
 695         if (ret)
 696                 return ret;
 697
 698         ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
 699         ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
 700         ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
 701                         (div_b << CDNS_I2C_CR_DIVB_SHIFT));
 702         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
 703
 704         return 0;
 705 }
 706
 707 /**
 708  * cdns_i2c_clk_notifier_cb - Clock rate change callback
 709  * @nb:         Pointer to notifier block
 710  * @event:      Notification reason
 711  * @data:       Pointer to notification data object
 712  *
 713  * This function is called when the cdns_i2c input clock frequency changes.
 714  * The callback checks whether a valid bus frequency can be generated after the
 715  * change. If so, the change is acknowledged, otherwise the change is aborted.
 716  * New dividers are written to the HW in the pre- or post change notification
 717  * depending on the scaling direction.
 718  *
 719  * Return:      NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
 720  *              to acknowedge the change, NOTIFY_DONE if the notification is
 721  *              considered irrelevant.
 722  */
 723 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
 724                 event, void *data)
 725 {
 726         struct clk_notifier_data *ndata = data;
 727         struct cdns_i2c *id = to_cdns_i2c(nb);
 728
 729         if (id->suspended)
 730                 return NOTIFY_OK;
 731
 732         switch (event) {
 733         case PRE_RATE_CHANGE:
 734         {
 735                 unsigned long input_clk = ndata->new_rate;
 736                 unsigned long fscl = id->i2c_clk;
 737                 unsigned int div_a, div_b;
 738                 int ret;
 739
 740                 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
 741                 if (ret) {
 742                         dev_warn(id->adap.dev.parent,
 743                                         "clock rate change rejected\n");
 744                         return NOTIFY_STOP;
 745                 }
 746
 747                 /* scale up */
 748                 if (ndata->new_rate > ndata->old_rate)
 749                         cdns_i2c_setclk(ndata->new_rate, id);
 750
 751                 return NOTIFY_OK;
 752         }
 753         case POST_RATE_CHANGE:
 754                 id->input_clk = ndata->new_rate;
 755                 /* scale down */
 756                 if (ndata->new_rate < ndata->old_rate)
 757                         cdns_i2c_setclk(ndata->new_rate, id);
 758                 return NOTIFY_OK;
 759         case ABORT_RATE_CHANGE:
 760                 /* scale up */
 761                 if (ndata->new_rate > ndata->old_rate)
 762                         cdns_i2c_setclk(ndata->old_rate, id);
 763                 return NOTIFY_OK;
 764         default:
 765                 return NOTIFY_DONE;
 766         }
 767 }
 768
 769 /**
 770  * cdns_i2c_suspend - Suspend method for the driver
 771  * @_dev:       Address of the platform_device structure
 772  *
 773  * Put the driver into low power mode.
 774  *
 775  * Return: 0 always
 776  */
 777 static int __maybe_unused cdns_i2c_suspend(struct device *_dev)
 778 {
 779         struct platform_device *pdev = container_of(_dev,
 780                         struct platform_device, dev);
 781         struct cdns_i2c *xi2c = platform_get_drvdata(pdev);
 782
 783         clk_disable(xi2c->clk);
 784         xi2c->suspended = 1;
 785
 786         return 0;
 787 }
 788
 789 /**
 790  * cdns_i2c_resume - Resume from suspend
 791  * @_dev:       Address of the platform_device structure
 792  *
 793  * Resume operation after suspend.
 794  *
 795  * Return: 0 on success and error value on error
 796  */
 797 static int __maybe_unused cdns_i2c_resume(struct device *_dev)
 798 {
 799         struct platform_device *pdev = container_of(_dev,
 800                         struct platform_device, dev);
 801         struct cdns_i2c *xi2c = platform_get_drvdata(pdev);
 802         int ret;
 803
 804         ret = clk_enable(xi2c->clk);
 805         if (ret) {
 806                 dev_err(_dev, "Cannot enable clock.\n");
 807                 return ret;
 808         }
 809
 810         xi2c->suspended = 0;
 811
 812         return 0;
 813 }
 814
 815 static SIMPLE_DEV_PM_OPS(cdns_i2c_dev_pm_ops, cdns_i2c_suspend,
 816                          cdns_i2c_resume);
 817
 818 /**
 819  * cdns_i2c_probe - Platform registration call
 820  * @pdev:       Handle to the platform device structure
 821  *
 822  * This function does all the memory allocation and registration for the i2c
 823  * device. User can modify the address mode to 10 bit address mode using the
 824  * ioctl call with option I2C_TENBIT.
 825  *
 826  * Return: 0 on success, negative error otherwise
 827  */
 828 static int cdns_i2c_probe(struct platform_device *pdev)
 829 {
 830         struct resource *r_mem;
 831         struct cdns_i2c *id;
 832         int ret;
 833
 834         id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
 835         if (!id)
 836                 return -ENOMEM;
 837
 838         platform_set_drvdata(pdev, id);
 839
 840         r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 841         id->membase = devm_ioremap_resource(&pdev->dev, r_mem);
 842         if (IS_ERR(id->membase))
 843                 return PTR_ERR(id->membase);
 844
 845         id->irq = platform_get_irq(pdev, 0);
 846
 847         id->adap.dev.of_node = pdev->dev.of_node;
 848         id->adap.algo = &cdns_i2c_algo;
 849         id->adap.timeout = CDNS_I2C_TIMEOUT;
 850         id->adap.retries = 3;           /* Default retry value. */
 851         id->adap.algo_data = id;
 852         id->adap.dev.parent = &pdev->dev;
 853         init_completion(&id->xfer_done);
 854         snprintf(id->adap.name, sizeof(id->adap.name),
 855                  "Cadence I2C at %08lx", (unsigned long)r_mem->start);
 856
 857         id->clk = devm_clk_get(&pdev->dev, NULL);
 858         if (IS_ERR(id->clk)) {
 859                 dev_err(&pdev->dev, "input clock not found.\n");
 860                 return PTR_ERR(id->clk);
 861         }
 862         ret = clk_prepare_enable(id->clk);
 863         if (ret) {
 864                 dev_err(&pdev->dev, "Unable to enable clock.\n");
 865                 return ret;
 866         }
 867         id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
 868         if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
 869                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
 870         id->input_clk = clk_get_rate(id->clk);
 871
 872         ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 873                         &id->i2c_clk);
 874         if (ret || (id->i2c_clk > CDNS_I2C_SPEED_MAX))
 875                 id->i2c_clk = CDNS_I2C_SPEED_DEFAULT;
 876
 877         cdns_i2c_writereg(CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS,
 878                           CDNS_I2C_CR_OFFSET);
 879
 880         ret = cdns_i2c_setclk(id->input_clk, id);
 881         if (ret) {
 882                 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
 883                 ret = -EINVAL;
 884                 goto err_clk_dis;
 885         }
 886
 887         ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0,
 888                                  DRIVER_NAME, id);
 889         if (ret) {
 890                 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
 891                 goto err_clk_dis;
 892         }
 893
 894         ret = i2c_add_adapter(&id->adap);
 895         if (ret < 0) {
 896                 dev_err(&pdev->dev, "reg adap failed: %d\n", ret);
 897                 goto err_clk_dis;
 898         }
 899
 900         /*
 901          * Cadence I2C controller has a bug wherein it generates
 902          * invalid read transaction after HW timeout in master receiver mode.
 903          * HW timeout is not used by this driver and the interrupt is disabled.
 904          * But the feature itself cannot be disabled. Hence maximum value
 905          * is written to this register to reduce the chances of error.
 906          */
 907         cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
 908
 909         dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
 910                  id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);
 911
 912         return 0;
 913
 914 err_clk_dis:
 915         clk_disable_unprepare(id->clk);
 916         return ret;
 917 }
 918
 919 /**
 920  * cdns_i2c_remove - Unregister the device after releasing the resources
 921  * @pdev:       Handle to the platform device structure
 922  *
 923  * This function frees all the resources allocated to the device.
 924  *
 925  * Return: 0 always
 926  */
 927 static int cdns_i2c_remove(struct platform_device *pdev)
 928 {
 929         struct cdns_i2c *id = platform_get_drvdata(pdev);
 930
 931         i2c_del_adapter(&id->adap);
 932         clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
 933         clk_disable_unprepare(id->clk);
 934
 935         return 0;
 936 }
 937
 938 static const struct of_device_id cdns_i2c_of_match[] = {
 939         { .compatible = "cdns,i2c-r1p10", },
 940         { /* end of table */ }
 941 };
 942 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
 943
 944 static struct platform_driver cdns_i2c_drv = {
 945         .driver = {
 946                 .name  = DRIVER_NAME,
 947                 .of_match_table = cdns_i2c_of_match,
 948                 .pm = &cdns_i2c_dev_pm_ops,
 949         },
 950         .probe  = cdns_i2c_probe,
 951         .remove = cdns_i2c_remove,
 952 };
 953
 954 module_platform_driver(cdns_i2c_drv);
 955
 956 MODULE_AUTHOR("Xilinx Inc.");
 957 MODULE_DESCRIPTION("Cadence I2C bus driver");
 958 MODULE_LICENSE("GPL");