kernel/drivers/i2c/busses/i2c-at91.c

   1 /*
   2  *  i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
   3  *
   4  *  Copyright (C) 2011 Weinmann Medical GmbH
   5  *  Author: Nikolaus Voss <n.voss@weinmann.de>
   6  *
   7  *  Evolved from original work by:
   8  *  Copyright (C) 2004 Rick Bronson
   9  *  Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
  10  *
  11  *  Borrowed heavily from original work by:
  12  *  Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
  13  *
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License as published by
  16  *  the Free Software Foundation; either version 2 of the License, or
  17  *  (at your option) any later version.
  18  */
  19
  20 #include <linux/clk.h>
  21 #include <linux/completion.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/err.h>
  25 #include <linux/i2c.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/slab.h>
  33 #include <linux/platform_data/dma-atmel.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/pinctrl/consumer.h>
  36
  37 #define DEFAULT_TWI_CLK_HZ              100000          /* max 400 Kbits/s */
  38 #define AT91_I2C_TIMEOUT        msecs_to_jiffies(100)   /* transfer timeout */
  39 #define AT91_I2C_DMA_THRESHOLD  8                       /* enable DMA if transfer size is bigger than this threshold */
  40 #define AUTOSUSPEND_TIMEOUT             2000
  41
  42 /* AT91 TWI register definitions */
  43 #define AT91_TWI_CR             0x0000  /* Control Register */
  44 #define AT91_TWI_START          0x0001  /* Send a Start Condition */
  45 #define AT91_TWI_STOP           0x0002  /* Send a Stop Condition */
  46 #define AT91_TWI_MSEN           0x0004  /* Master Transfer Enable */
  47 #define AT91_TWI_SVDIS          0x0020  /* Slave Transfer Disable */
  48 #define AT91_TWI_QUICK          0x0040  /* SMBus quick command */
  49 #define AT91_TWI_SWRST          0x0080  /* Software Reset */
  50
  51 #define AT91_TWI_MMR            0x0004  /* Master Mode Register */
  52 #define AT91_TWI_IADRSZ_1       0x0100  /* Internal Device Address Size */
  53 #define AT91_TWI_MREAD          0x1000  /* Master Read Direction */
  54
  55 #define AT91_TWI_IADR           0x000c  /* Internal Address Register */
  56
  57 #define AT91_TWI_CWGR           0x0010  /* Clock Waveform Generator Reg */
  58
  59 #define AT91_TWI_SR             0x0020  /* Status Register */
  60 #define AT91_TWI_TXCOMP         0x0001  /* Transmission Complete */
  61 #define AT91_TWI_RXRDY          0x0002  /* Receive Holding Register Ready */
  62 #define AT91_TWI_TXRDY          0x0004  /* Transmit Holding Register Ready */
  63
  64 #define AT91_TWI_OVRE           0x0040  /* Overrun Error */
  65 #define AT91_TWI_UNRE           0x0080  /* Underrun Error */
  66 #define AT91_TWI_NACK           0x0100  /* Not Acknowledged */
  67
  68 #define AT91_TWI_INT_MASK \
  69         (AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK)
  70
  71 #define AT91_TWI_IER            0x0024  /* Interrupt Enable Register */
  72 #define AT91_TWI_IDR            0x0028  /* Interrupt Disable Register */
  73 #define AT91_TWI_IMR            0x002c  /* Interrupt Mask Register */
  74 #define AT91_TWI_RHR            0x0030  /* Receive Holding Register */
  75 #define AT91_TWI_THR            0x0034  /* Transmit Holding Register */
  76
  77 struct at91_twi_pdata {
  78         unsigned clk_max_div;
  79         unsigned clk_offset;
  80         bool has_unre_flag;
  81         struct at_dma_slave dma_slave;
  82 };
  83
  84 struct at91_twi_dma {
  85         struct dma_chan *chan_rx;
  86         struct dma_chan *chan_tx;
  87         struct scatterlist sg;
  88         struct dma_async_tx_descriptor *data_desc;
  89         enum dma_data_direction direction;
  90         bool buf_mapped;
  91         bool xfer_in_progress;
  92 };
  93
  94 struct at91_twi_dev {
  95         struct device *dev;
  96         void __iomem *base;
  97         struct completion cmd_complete;
  98         struct clk *clk;
  99         u8 *buf;
 100         size_t buf_len;
 101         struct i2c_msg *msg;
 102         int irq;
 103         unsigned imr;
 104         unsigned transfer_status;
 105         struct i2c_adapter adapter;
 106         unsigned twi_cwgr_reg;
 107         struct at91_twi_pdata *pdata;
 108         bool use_dma;
 109         bool recv_len_abort;
 110         struct at91_twi_dma dma;
 111 };
 112
 113 static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
 114 {
 115         return readl_relaxed(dev->base + reg);
 116 }
 117
 118 static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
 119 {
 120         writel_relaxed(val, dev->base + reg);
 121 }
 122
 123 static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
 124 {
 125         at91_twi_write(dev, AT91_TWI_IDR, AT91_TWI_INT_MASK);
 126 }
 127
 128 static void at91_twi_irq_save(struct at91_twi_dev *dev)
 129 {
 130         dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & AT91_TWI_INT_MASK;
 131         at91_disable_twi_interrupts(dev);
 132 }
 133
 134 static void at91_twi_irq_restore(struct at91_twi_dev *dev)
 135 {
 136         at91_twi_write(dev, AT91_TWI_IER, dev->imr);
 137 }
 138
 139 static void at91_init_twi_bus(struct at91_twi_dev *dev)
 140 {
 141         at91_disable_twi_interrupts(dev);
 142         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
 143         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
 144         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
 145         at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
 146 }
 147
 148 /*
 149  * Calculate symmetric clock as stated in datasheet:
 150  * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
 151  */
 152 static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
 153 {
 154         int ckdiv, cdiv, div;
 155         struct at91_twi_pdata *pdata = dev->pdata;
 156         int offset = pdata->clk_offset;
 157         int max_ckdiv = pdata->clk_max_div;
 158
 159         div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
 160                                        2 * twi_clk) - offset);
 161         ckdiv = fls(div >> 8);
 162         cdiv = div >> ckdiv;
 163
 164         if (ckdiv > max_ckdiv) {
 165                 dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
 166                          ckdiv, max_ckdiv);
 167                 ckdiv = max_ckdiv;
 168                 cdiv = 255;
 169         }
 170
 171         dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
 172         dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
 173 }
 174
 175 static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
 176 {
 177         struct at91_twi_dma *dma = &dev->dma;
 178
 179         at91_twi_irq_save(dev);
 180
 181         if (dma->xfer_in_progress) {
 182                 if (dma->direction == DMA_FROM_DEVICE)
 183                         dmaengine_terminate_all(dma->chan_rx);
 184                 else
 185                         dmaengine_terminate_all(dma->chan_tx);
 186                 dma->xfer_in_progress = false;
 187         }
 188         if (dma->buf_mapped) {
 189                 dma_unmap_single(dev->dev, sg_dma_address(&dma->sg),
 190                                  dev->buf_len, dma->direction);
 191                 dma->buf_mapped = false;
 192         }
 193
 194         at91_twi_irq_restore(dev);
 195 }
 196
 197 static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
 198 {
 199         if (dev->buf_len <= 0)
 200                 return;
 201
 202         at91_twi_write(dev, AT91_TWI_THR, *dev->buf);
 203
 204         /* send stop when last byte has been written */
 205         if (--dev->buf_len == 0)
 206                 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
 207
 208         dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len);
 209
 210         ++dev->buf;
 211 }
 212
 213 static void at91_twi_write_data_dma_callback(void *data)
 214 {
 215         struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
 216
 217         dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg),
 218                          dev->buf_len, DMA_TO_DEVICE);
 219
 220         /*
 221          * When this callback is called, THR/TX FIFO is likely not to be empty
 222          * yet. So we have to wait for TXCOMP or NACK bits to be set into the
 223          * Status Register to be sure that the STOP bit has been sent and the
 224          * transfer is completed. The NACK interrupt has already been enabled,
 225          * we just have to enable TXCOMP one.
 226          */
 227         at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
 228         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
 229 }
 230
 231 static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
 232 {
 233         dma_addr_t dma_addr;
 234         struct dma_async_tx_descriptor *txdesc;
 235         struct at91_twi_dma *dma = &dev->dma;
 236         struct dma_chan *chan_tx = dma->chan_tx;
 237
 238         if (dev->buf_len <= 0)
 239                 return;
 240
 241         dma->direction = DMA_TO_DEVICE;
 242
 243         at91_twi_irq_save(dev);
 244         dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len,
 245                                   DMA_TO_DEVICE);
 246         if (dma_mapping_error(dev->dev, dma_addr)) {
 247                 dev_err(dev->dev, "dma map failed\n");
 248                 return;
 249         }
 250         dma->buf_mapped = true;
 251         at91_twi_irq_restore(dev);
 252         sg_dma_len(&dma->sg) = dev->buf_len;
 253         sg_dma_address(&dma->sg) = dma_addr;
 254
 255         txdesc = dmaengine_prep_slave_sg(chan_tx, &dma->sg, 1, DMA_MEM_TO_DEV,
 256                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 257         if (!txdesc) {
 258                 dev_err(dev->dev, "dma prep slave sg failed\n");
 259                 goto error;
 260         }
 261
 262         txdesc->callback = at91_twi_write_data_dma_callback;
 263         txdesc->callback_param = dev;
 264
 265         dma->xfer_in_progress = true;
 266         dmaengine_submit(txdesc);
 267         dma_async_issue_pending(chan_tx);
 268
 269         return;
 270
 271 error:
 272         at91_twi_dma_cleanup(dev);
 273 }
 274
 275 static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
 276 {
 277         if (dev->buf_len <= 0)
 278                 return;
 279
 280         *dev->buf = at91_twi_read(dev, AT91_TWI_RHR) & 0xff;
 281         --dev->buf_len;
 282
 283         /* return if aborting, we only needed to read RHR to clear RXRDY*/
 284         if (dev->recv_len_abort)
 285                 return;
 286
 287         /* handle I2C_SMBUS_BLOCK_DATA */
 288         if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) {
 289                 /* ensure length byte is a valid value */
 290                 if (*dev->buf <= I2C_SMBUS_BLOCK_MAX && *dev->buf > 0) {
 291                         dev->msg->flags &= ~I2C_M_RECV_LEN;
 292                         dev->buf_len += *dev->buf;
 293                         dev->msg->len = dev->buf_len + 1;
 294                         dev_dbg(dev->dev, "received block length %d\n",
 295                                          dev->buf_len);
 296                 } else {
 297                         /* abort and send the stop by reading one more byte */
 298                         dev->recv_len_abort = true;
 299                         dev->buf_len = 1;
 300                 }
 301         }
 302
 303         /* send stop if second but last byte has been read */
 304         if (dev->buf_len == 1)
 305                 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
 306
 307         dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len);
 308
 309         ++dev->buf;
 310 }
 311
 312 static void at91_twi_read_data_dma_callback(void *data)
 313 {
 314         struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
 315
 316         dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg),
 317                          dev->buf_len, DMA_FROM_DEVICE);
 318
 319         /* The last two bytes have to be read without using dma */
 320         dev->buf += dev->buf_len - 2;
 321         dev->buf_len = 2;
 322         at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_RXRDY | AT91_TWI_TXCOMP);
 323 }
 324
 325 static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
 326 {
 327         dma_addr_t dma_addr;
 328         struct dma_async_tx_descriptor *rxdesc;
 329         struct at91_twi_dma *dma = &dev->dma;
 330         struct dma_chan *chan_rx = dma->chan_rx;
 331
 332         dma->direction = DMA_FROM_DEVICE;
 333
 334         /* Keep in mind that we won't use dma to read the last two bytes */
 335         at91_twi_irq_save(dev);
 336         dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len - 2,
 337                                   DMA_FROM_DEVICE);
 338         if (dma_mapping_error(dev->dev, dma_addr)) {
 339                 dev_err(dev->dev, "dma map failed\n");
 340                 return;
 341         }
 342         dma->buf_mapped = true;
 343         at91_twi_irq_restore(dev);
 344         dma->sg.dma_address = dma_addr;
 345         sg_dma_len(&dma->sg) = dev->buf_len - 2;
 346
 347         rxdesc = dmaengine_prep_slave_sg(chan_rx, &dma->sg, 1, DMA_DEV_TO_MEM,
 348                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 349         if (!rxdesc) {
 350                 dev_err(dev->dev, "dma prep slave sg failed\n");
 351                 goto error;
 352         }
 353
 354         rxdesc->callback = at91_twi_read_data_dma_callback;
 355         rxdesc->callback_param = dev;
 356
 357         dma->xfer_in_progress = true;
 358         dmaengine_submit(rxdesc);
 359         dma_async_issue_pending(dma->chan_rx);
 360
 361         return;
 362
 363 error:
 364         at91_twi_dma_cleanup(dev);
 365 }
 366
 367 static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
 368 {
 369         struct at91_twi_dev *dev = dev_id;
 370         const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
 371         const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
 372
 373         if (!irqstatus)
 374                 return IRQ_NONE;
 375         else if (irqstatus & AT91_TWI_RXRDY)
 376                 at91_twi_read_next_byte(dev);
 377         else if (irqstatus & AT91_TWI_TXRDY)
 378                 at91_twi_write_next_byte(dev);
 379
 380         /* catch error flags */
 381         dev->transfer_status |= status;
 382
 383         if (irqstatus & (AT91_TWI_TXCOMP | AT91_TWI_NACK)) {
 384                 at91_disable_twi_interrupts(dev);
 385                 complete(&dev->cmd_complete);
 386         }
 387
 388         return IRQ_HANDLED;
 389 }
 390
 391 static int at91_do_twi_transfer(struct at91_twi_dev *dev)
 392 {
 393         int ret;
 394         unsigned long time_left;
 395         bool has_unre_flag = dev->pdata->has_unre_flag;
 396
 397         /*
 398          * WARNING: the TXCOMP bit in the Status Register is NOT a clear on
 399          * read flag but shows the state of the transmission at the time the
 400          * Status Register is read. According to the programmer datasheet,
 401          * TXCOMP is set when both holding register and internal shifter are
 402          * empty and STOP condition has been sent.
 403          * Consequently, we should enable NACK interrupt rather than TXCOMP to
 404          * detect transmission failure.
 405          *
 406          * Besides, the TXCOMP bit is already set before the i2c transaction
 407          * has been started. For read transactions, this bit is cleared when
 408          * writing the START bit into the Control Register. So the
 409          * corresponding interrupt can safely be enabled just after.
 410          * However for write transactions managed by the CPU, we first write
 411          * into THR, so TXCOMP is cleared. Then we can safely enable TXCOMP
 412          * interrupt. If TXCOMP interrupt were enabled before writing into THR,
 413          * the interrupt handler would be called immediately and the i2c command
 414          * would be reported as completed.
 415          * Also when a write transaction is managed by the DMA controller,
 416          * enabling the TXCOMP interrupt in this function may lead to a race
 417          * condition since we don't know whether the TXCOMP interrupt is enabled
 418          * before or after the DMA has started to write into THR. So the TXCOMP
 419          * interrupt is enabled later by at91_twi_write_data_dma_callback().
 420          * Immediately after in that DMA callback, we still need to send the
 421          * STOP condition manually writing the corresponding bit into the
 422          * Control Register.
 423          */
 424
 425         dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
 426                 (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
 427
 428         reinit_completion(&dev->cmd_complete);
 429         dev->transfer_status = 0;
 430
 431         if (!dev->buf_len) {
 432                 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
 433                 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
 434         } else if (dev->msg->flags & I2C_M_RD) {
 435                 unsigned start_flags = AT91_TWI_START;
 436
 437                 if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) {
 438                         dev_err(dev->dev, "RXRDY still set!");
 439                         at91_twi_read(dev, AT91_TWI_RHR);
 440                 }
 441
 442                 /* if only one byte is to be read, immediately stop transfer */
 443                 if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN))
 444                         start_flags |= AT91_TWI_STOP;
 445                 at91_twi_write(dev, AT91_TWI_CR, start_flags);
 446                 /*
 447                  * When using dma, the last byte has to be read manually in
 448                  * order to not send the stop command too late and then
 449                  * to receive extra data. In practice, there are some issues
 450                  * if you use the dma to read n-1 bytes because of latency.
 451                  * Reading n-2 bytes with dma and the two last ones manually
 452                  * seems to be the best solution.
 453                  */
 454                 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
 455                         at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
 456                         at91_twi_read_data_dma(dev);
 457                 } else {
 458                         at91_twi_write(dev, AT91_TWI_IER,
 459                                        AT91_TWI_TXCOMP |
 460                                        AT91_TWI_NACK |
 461                                        AT91_TWI_RXRDY);
 462                 }
 463         } else {
 464                 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
 465                         at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
 466                         at91_twi_write_data_dma(dev);
 467                 } else {
 468                         at91_twi_write_next_byte(dev);
 469                         at91_twi_write(dev, AT91_TWI_IER,
 470                                        AT91_TWI_TXCOMP |
 471                                        AT91_TWI_NACK |
 472                                        AT91_TWI_TXRDY);
 473                 }
 474         }
 475
 476         time_left = wait_for_completion_timeout(&dev->cmd_complete,
 477                                               dev->adapter.timeout);
 478         if (time_left == 0) {
 479                 dev_err(dev->dev, "controller timed out\n");
 480                 at91_init_twi_bus(dev);
 481                 ret = -ETIMEDOUT;
 482                 goto error;
 483         }
 484         if (dev->transfer_status & AT91_TWI_NACK) {
 485                 dev_dbg(dev->dev, "received nack\n");
 486                 ret = -EREMOTEIO;
 487                 goto error;
 488         }
 489         if (dev->transfer_status & AT91_TWI_OVRE) {
 490                 dev_err(dev->dev, "overrun while reading\n");
 491                 ret = -EIO;
 492                 goto error;
 493         }
 494         if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
 495                 dev_err(dev->dev, "underrun while writing\n");
 496                 ret = -EIO;
 497                 goto error;
 498         }
 499         if (dev->recv_len_abort) {
 500                 dev_err(dev->dev, "invalid smbus block length recvd\n");
 501                 ret = -EPROTO;
 502                 goto error;
 503         }
 504
 505         dev_dbg(dev->dev, "transfer complete\n");
 506
 507         return 0;
 508
 509 error:
 510         at91_twi_dma_cleanup(dev);
 511         return ret;
 512 }
 513
 514 static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
 515 {
 516         struct at91_twi_dev *dev = i2c_get_adapdata(adap);
 517         int ret;
 518         unsigned int_addr_flag = 0;
 519         struct i2c_msg *m_start = msg;
 520
 521         dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
 522
 523         ret = pm_runtime_get_sync(dev->dev);
 524         if (ret < 0)
 525                 goto out;
 526
 527         if (num == 2) {
 528                 int internal_address = 0;
 529                 int i;
 530
 531                 /* 1st msg is put into the internal address, start with 2nd */
 532                 m_start = &msg[1];
 533                 for (i = 0; i < msg->len; ++i) {
 534                         const unsigned addr = msg->buf[msg->len - 1 - i];
 535
 536                         internal_address |= addr << (8 * i);
 537                         int_addr_flag += AT91_TWI_IADRSZ_1;
 538                 }
 539                 at91_twi_write(dev, AT91_TWI_IADR, internal_address);
 540         }
 541
 542         at91_twi_write(dev, AT91_TWI_MMR, (m_start->addr << 16) | int_addr_flag
 543                        | ((m_start->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0));
 544
 545         dev->buf_len = m_start->len;
 546         dev->buf = m_start->buf;
 547         dev->msg = m_start;
 548         dev->recv_len_abort = false;
 549
 550         ret = at91_do_twi_transfer(dev);
 551
 552         ret = (ret < 0) ? ret : num;
 553 out:
 554         pm_runtime_mark_last_busy(dev->dev);
 555         pm_runtime_put_autosuspend(dev->dev);
 556
 557         return ret;
 558 }
 559
 560 /*
 561  * The hardware can handle at most two messages concatenated by a
 562  * repeated start via it's internal address feature.
 563  */
 564 static struct i2c_adapter_quirks at91_twi_quirks = {
 565         .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | I2C_AQ_COMB_SAME_ADDR,
 566         .max_comb_1st_msg_len = 3,
 567 };
 568
 569 static u32 at91_twi_func(struct i2c_adapter *adapter)
 570 {
 571         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
 572                 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
 573 }
 574
 575 static struct i2c_algorithm at91_twi_algorithm = {
 576         .master_xfer    = at91_twi_xfer,
 577         .functionality  = at91_twi_func,
 578 };
 579
 580 static struct at91_twi_pdata at91rm9200_config = {
 581         .clk_max_div = 5,
 582         .clk_offset = 3,
 583         .has_unre_flag = true,
 584 };
 585
 586 static struct at91_twi_pdata at91sam9261_config = {
 587         .clk_max_div = 5,
 588         .clk_offset = 4,
 589         .has_unre_flag = false,
 590 };
 591
 592 static struct at91_twi_pdata at91sam9260_config = {
 593         .clk_max_div = 7,
 594         .clk_offset = 4,
 595         .has_unre_flag = false,
 596 };
 597
 598 static struct at91_twi_pdata at91sam9g20_config = {
 599         .clk_max_div = 7,
 600         .clk_offset = 4,
 601         .has_unre_flag = false,
 602 };
 603
 604 static struct at91_twi_pdata at91sam9g10_config = {
 605         .clk_max_div = 7,
 606         .clk_offset = 4,
 607         .has_unre_flag = false,
 608 };
 609
 610 static const struct platform_device_id at91_twi_devtypes[] = {
 611         {
 612                 .name = "i2c-at91rm9200",
 613                 .driver_data = (unsigned long) &at91rm9200_config,
 614         }, {
 615                 .name = "i2c-at91sam9261",
 616                 .driver_data = (unsigned long) &at91sam9261_config,
 617         }, {
 618                 .name = "i2c-at91sam9260",
 619                 .driver_data = (unsigned long) &at91sam9260_config,
 620         }, {
 621                 .name = "i2c-at91sam9g20",
 622                 .driver_data = (unsigned long) &at91sam9g20_config,
 623         }, {
 624                 .name = "i2c-at91sam9g10",
 625                 .driver_data = (unsigned long) &at91sam9g10_config,
 626         }, {
 627                 /* sentinel */
 628         }
 629 };
 630
 631 #if defined(CONFIG_OF)
 632 static struct at91_twi_pdata at91sam9x5_config = {
 633         .clk_max_div = 7,
 634         .clk_offset = 4,
 635         .has_unre_flag = false,
 636 };
 637
 638 static const struct of_device_id atmel_twi_dt_ids[] = {
 639         {
 640                 .compatible = "atmel,at91rm9200-i2c",
 641                 .data = &at91rm9200_config,
 642         } , {
 643                 .compatible = "atmel,at91sam9260-i2c",
 644                 .data = &at91sam9260_config,
 645         } , {
 646                 .compatible = "atmel,at91sam9261-i2c",
 647                 .data = &at91sam9261_config,
 648         } , {
 649                 .compatible = "atmel,at91sam9g20-i2c",
 650                 .data = &at91sam9g20_config,
 651         } , {
 652                 .compatible = "atmel,at91sam9g10-i2c",
 653                 .data = &at91sam9g10_config,
 654         }, {
 655                 .compatible = "atmel,at91sam9x5-i2c",
 656                 .data = &at91sam9x5_config,
 657         }, {
 658                 /* sentinel */
 659         }
 660 };
 661 MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
 662 #endif
 663
 664 static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
 665 {
 666         int ret = 0;
 667         struct dma_slave_config slave_config;
 668         struct at91_twi_dma *dma = &dev->dma;
 669
 670         memset(&slave_config, 0, sizeof(slave_config));
 671         slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
 672         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 673         slave_config.src_maxburst = 1;
 674         slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR;
 675         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 676         slave_config.dst_maxburst = 1;
 677         slave_config.device_fc = false;
 678
 679         dma->chan_tx = dma_request_slave_channel_reason(dev->dev, "tx");
 680         if (IS_ERR(dma->chan_tx)) {
 681                 ret = PTR_ERR(dma->chan_tx);
 682                 dma->chan_tx = NULL;
 683                 goto error;
 684         }
 685
 686         dma->chan_rx = dma_request_slave_channel_reason(dev->dev, "rx");
 687         if (IS_ERR(dma->chan_rx)) {
 688                 ret = PTR_ERR(dma->chan_rx);
 689                 dma->chan_rx = NULL;
 690                 goto error;
 691         }
 692
 693         slave_config.direction = DMA_MEM_TO_DEV;
 694         if (dmaengine_slave_config(dma->chan_tx, &slave_config)) {
 695                 dev_err(dev->dev, "failed to configure tx channel\n");
 696                 ret = -EINVAL;
 697                 goto error;
 698         }
 699
 700         slave_config.direction = DMA_DEV_TO_MEM;
 701         if (dmaengine_slave_config(dma->chan_rx, &slave_config)) {
 702                 dev_err(dev->dev, "failed to configure rx channel\n");
 703                 ret = -EINVAL;
 704                 goto error;
 705         }
 706
 707         sg_init_table(&dma->sg, 1);
 708         dma->buf_mapped = false;
 709         dma->xfer_in_progress = false;
 710         dev->use_dma = true;
 711
 712         dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n",
 713                  dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
 714
 715         return ret;
 716
 717 error:
 718         if (ret != -EPROBE_DEFER)
 719                 dev_info(dev->dev, "can't use DMA, error %d\n", ret);
 720         if (dma->chan_rx)
 721                 dma_release_channel(dma->chan_rx);
 722         if (dma->chan_tx)
 723                 dma_release_channel(dma->chan_tx);
 724         return ret;
 725 }
 726
 727 static struct at91_twi_pdata *at91_twi_get_driver_data(
 728                                         struct platform_device *pdev)
 729 {
 730         if (pdev->dev.of_node) {
 731                 const struct of_device_id *match;
 732                 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
 733                 if (!match)
 734                         return NULL;
 735                 return (struct at91_twi_pdata *)match->data;
 736         }
 737         return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
 738 }
 739
 740 static int at91_twi_probe(struct platform_device *pdev)
 741 {
 742         struct at91_twi_dev *dev;
 743         struct resource *mem;
 744         int rc;
 745         u32 phy_addr;
 746         u32 bus_clk_rate;
 747
 748         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
 749         if (!dev)
 750                 return -ENOMEM;
 751         init_completion(&dev->cmd_complete);
 752         dev->dev = &pdev->dev;
 753
 754         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 755         if (!mem)
 756                 return -ENODEV;
 757         phy_addr = mem->start;
 758
 759         dev->pdata = at91_twi_get_driver_data(pdev);
 760         if (!dev->pdata)
 761                 return -ENODEV;
 762
 763         dev->base = devm_ioremap_resource(&pdev->dev, mem);
 764         if (IS_ERR(dev->base))
 765                 return PTR_ERR(dev->base);
 766
 767         dev->irq = platform_get_irq(pdev, 0);
 768         if (dev->irq < 0)
 769                 return dev->irq;
 770
 771         rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
 772                          dev_name(dev->dev), dev);
 773         if (rc) {
 774                 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
 775                 return rc;
 776         }
 777
 778         platform_set_drvdata(pdev, dev);
 779
 780         dev->clk = devm_clk_get(dev->dev, NULL);
 781         if (IS_ERR(dev->clk)) {
 782                 dev_err(dev->dev, "no clock defined\n");
 783                 return -ENODEV;
 784         }
 785         clk_prepare_enable(dev->clk);
 786
 787         if (dev->dev->of_node) {
 788                 rc = at91_twi_configure_dma(dev, phy_addr);
 789                 if (rc == -EPROBE_DEFER)
 790                         return rc;
 791         }
 792
 793         rc = of_property_read_u32(dev->dev->of_node, "clock-frequency",
 794                         &bus_clk_rate);
 795         if (rc)
 796                 bus_clk_rate = DEFAULT_TWI_CLK_HZ;
 797
 798         at91_calc_twi_clock(dev, bus_clk_rate);
 799         at91_init_twi_bus(dev);
 800
 801         snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
 802         i2c_set_adapdata(&dev->adapter, dev);
 803         dev->adapter.owner = THIS_MODULE;
 804         dev->adapter.class = I2C_CLASS_DEPRECATED;
 805         dev->adapter.algo = &at91_twi_algorithm;
 806         dev->adapter.quirks = &at91_twi_quirks;
 807         dev->adapter.dev.parent = dev->dev;
 808         dev->adapter.nr = pdev->id;
 809         dev->adapter.timeout = AT91_I2C_TIMEOUT;
 810         dev->adapter.dev.of_node = pdev->dev.of_node;
 811
 812         pm_runtime_set_autosuspend_delay(dev->dev, AUTOSUSPEND_TIMEOUT);
 813         pm_runtime_use_autosuspend(dev->dev);
 814         pm_runtime_set_active(dev->dev);
 815         pm_runtime_enable(dev->dev);
 816
 817         rc = i2c_add_numbered_adapter(&dev->adapter);
 818         if (rc) {
 819                 dev_err(dev->dev, "Adapter %s registration failed\n",
 820                         dev->adapter.name);
 821                 clk_disable_unprepare(dev->clk);
 822
 823                 pm_runtime_disable(dev->dev);
 824                 pm_runtime_set_suspended(dev->dev);
 825
 826                 return rc;
 827         }
 828
 829         dev_info(dev->dev, "AT91 i2c bus driver.\n");
 830         return 0;
 831 }
 832
 833 static int at91_twi_remove(struct platform_device *pdev)
 834 {
 835         struct at91_twi_dev *dev = platform_get_drvdata(pdev);
 836
 837         i2c_del_adapter(&dev->adapter);
 838         clk_disable_unprepare(dev->clk);
 839
 840         pm_runtime_disable(dev->dev);
 841         pm_runtime_set_suspended(dev->dev);
 842
 843         return 0;
 844 }
 845
 846 #ifdef CONFIG_PM
 847
 848 static int at91_twi_runtime_suspend(struct device *dev)
 849 {
 850         struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
 851
 852         clk_disable_unprepare(twi_dev->clk);
 853
 854         pinctrl_pm_select_sleep_state(dev);
 855
 856         return 0;
 857 }
 858
 859 static int at91_twi_runtime_resume(struct device *dev)
 860 {
 861         struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
 862
 863         pinctrl_pm_select_default_state(dev);
 864
 865         return clk_prepare_enable(twi_dev->clk);
 866 }
 867
 868 static int at91_twi_suspend_noirq(struct device *dev)
 869 {
 870         if (!pm_runtime_status_suspended(dev))
 871                 at91_twi_runtime_suspend(dev);
 872
 873         return 0;
 874 }
 875
 876 static int at91_twi_resume_noirq(struct device *dev)
 877 {
 878         int ret;
 879
 880         if (!pm_runtime_status_suspended(dev)) {
 881                 ret = at91_twi_runtime_resume(dev);
 882                 if (ret)
 883                         return ret;
 884         }
 885
 886         pm_runtime_mark_last_busy(dev);
 887         pm_request_autosuspend(dev);
 888
 889         return 0;
 890 }
 891
 892 static const struct dev_pm_ops at91_twi_pm = {
 893         .suspend_noirq  = at91_twi_suspend_noirq,
 894         .resume_noirq   = at91_twi_resume_noirq,
 895         .runtime_suspend        = at91_twi_runtime_suspend,
 896         .runtime_resume         = at91_twi_runtime_resume,
 897 };
 898
 899 #define at91_twi_pm_ops (&at91_twi_pm)
 900 #else
 901 #define at91_twi_pm_ops NULL
 902 #endif
 903
 904 static struct platform_driver at91_twi_driver = {
 905         .probe          = at91_twi_probe,
 906         .remove         = at91_twi_remove,
 907         .id_table       = at91_twi_devtypes,
 908         .driver         = {
 909                 .name   = "at91_i2c",
 910                 .of_match_table = of_match_ptr(atmel_twi_dt_ids),
 911                 .pm     = at91_twi_pm_ops,
 912         },
 913 };
 914
 915 static int __init at91_twi_init(void)
 916 {
 917         return platform_driver_register(&at91_twi_driver);
 918 }
 919
 920 static void __exit at91_twi_exit(void)
 921 {
 922         platform_driver_unregister(&at91_twi_driver);
 923 }
 924
 925 subsys_initcall(at91_twi_init);
 926 module_exit(at91_twi_exit);
 927
 928 MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
 929 MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
 930 MODULE_LICENSE("GPL");
 931 MODULE_ALIAS("platform:at91_i2c");