These changes are the raw update to linux-4.4.6-rt14. Kernel sources
[kvmfornfv.git] / kernel / drivers / gpu / drm / vc4 / vc4_plane.c
1 /*
2  * Copyright (C) 2015 Broadcom
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8
9 /**
10  * DOC: VC4 plane module
11  *
12  * Each DRM plane is a layer of pixels being scanned out by the HVS.
13  *
14  * At atomic modeset check time, we compute the HVS display element
15  * state that would be necessary for displaying the plane (giving us a
16  * chance to figure out if a plane configuration is invalid), then at
17  * atomic flush time the CRTC will ask us to write our element state
18  * into the region of the HVS that it has allocated for us.
19  */
20
21 #include "vc4_drv.h"
22 #include "vc4_regs.h"
23 #include "drm_atomic_helper.h"
24 #include "drm_fb_cma_helper.h"
25 #include "drm_plane_helper.h"
26
27 struct vc4_plane_state {
28         struct drm_plane_state base;
29         u32 *dlist;
30         u32 dlist_size; /* Number of dwords in allocated for the display list */
31         u32 dlist_count; /* Number of used dwords in the display list. */
32 };
33
34 static inline struct vc4_plane_state *
35 to_vc4_plane_state(struct drm_plane_state *state)
36 {
37         return (struct vc4_plane_state *)state;
38 }
39
40 static const struct hvs_format {
41         u32 drm; /* DRM_FORMAT_* */
42         u32 hvs; /* HVS_FORMAT_* */
43         u32 pixel_order;
44         bool has_alpha;
45 } hvs_formats[] = {
46         {
47                 .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
48                 .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = false,
49         },
50         {
51                 .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
52                 .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = true,
53         },
54 };
55
56 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
57 {
58         unsigned i;
59
60         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
61                 if (hvs_formats[i].drm == drm_format)
62                         return &hvs_formats[i];
63         }
64
65         return NULL;
66 }
67
68 static bool plane_enabled(struct drm_plane_state *state)
69 {
70         return state->fb && state->crtc;
71 }
72
73 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
74 {
75         struct vc4_plane_state *vc4_state;
76
77         if (WARN_ON(!plane->state))
78                 return NULL;
79
80         vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
81         if (!vc4_state)
82                 return NULL;
83
84         __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
85
86         if (vc4_state->dlist) {
87                 vc4_state->dlist = kmemdup(vc4_state->dlist,
88                                            vc4_state->dlist_count * 4,
89                                            GFP_KERNEL);
90                 if (!vc4_state->dlist) {
91                         kfree(vc4_state);
92                         return NULL;
93                 }
94                 vc4_state->dlist_size = vc4_state->dlist_count;
95         }
96
97         return &vc4_state->base;
98 }
99
100 static void vc4_plane_destroy_state(struct drm_plane *plane,
101                                     struct drm_plane_state *state)
102 {
103         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
104
105         kfree(vc4_state->dlist);
106         __drm_atomic_helper_plane_destroy_state(plane, &vc4_state->base);
107         kfree(state);
108 }
109
110 /* Called during init to allocate the plane's atomic state. */
111 static void vc4_plane_reset(struct drm_plane *plane)
112 {
113         struct vc4_plane_state *vc4_state;
114
115         WARN_ON(plane->state);
116
117         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
118         if (!vc4_state)
119                 return;
120
121         plane->state = &vc4_state->base;
122         vc4_state->base.plane = plane;
123 }
124
125 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
126 {
127         if (vc4_state->dlist_count == vc4_state->dlist_size) {
128                 u32 new_size = max(4u, vc4_state->dlist_count * 2);
129                 u32 *new_dlist = kmalloc(new_size * 4, GFP_KERNEL);
130
131                 if (!new_dlist)
132                         return;
133                 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
134
135                 kfree(vc4_state->dlist);
136                 vc4_state->dlist = new_dlist;
137                 vc4_state->dlist_size = new_size;
138         }
139
140         vc4_state->dlist[vc4_state->dlist_count++] = val;
141 }
142
143 /* Writes out a full display list for an active plane to the plane's
144  * private dlist state.
145  */
146 static int vc4_plane_mode_set(struct drm_plane *plane,
147                               struct drm_plane_state *state)
148 {
149         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
150         struct drm_framebuffer *fb = state->fb;
151         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
152         u32 ctl0_offset = vc4_state->dlist_count;
153         const struct hvs_format *format = vc4_get_hvs_format(fb->pixel_format);
154         uint32_t offset = fb->offsets[0];
155         int crtc_x = state->crtc_x;
156         int crtc_y = state->crtc_y;
157         int crtc_w = state->crtc_w;
158         int crtc_h = state->crtc_h;
159
160         if (state->crtc_w << 16 != state->src_w ||
161             state->crtc_h << 16 != state->src_h) {
162                 /* We don't support scaling yet, which involves
163                  * allocating the LBM memory for scaling temporary
164                  * storage, and putting filter kernels in the HVS
165                  * context.
166                  */
167                 return -EINVAL;
168         }
169
170         if (crtc_x < 0) {
171                 offset += drm_format_plane_cpp(fb->pixel_format, 0) * -crtc_x;
172                 crtc_w += crtc_x;
173                 crtc_x = 0;
174         }
175
176         if (crtc_y < 0) {
177                 offset += fb->pitches[0] * -crtc_y;
178                 crtc_h += crtc_y;
179                 crtc_y = 0;
180         }
181
182         vc4_dlist_write(vc4_state,
183                         SCALER_CTL0_VALID |
184                         (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
185                         (format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
186                         SCALER_CTL0_UNITY);
187
188         /* Position Word 0: Image Positions and Alpha Value */
189         vc4_dlist_write(vc4_state,
190                         VC4_SET_FIELD(0xff, SCALER_POS0_FIXED_ALPHA) |
191                         VC4_SET_FIELD(crtc_x, SCALER_POS0_START_X) |
192                         VC4_SET_FIELD(crtc_y, SCALER_POS0_START_Y));
193
194         /* Position Word 1: Scaled Image Dimensions.
195          * Skipped due to SCALER_CTL0_UNITY scaling.
196          */
197
198         /* Position Word 2: Source Image Size, Alpha Mode */
199         vc4_dlist_write(vc4_state,
200                         VC4_SET_FIELD(format->has_alpha ?
201                                       SCALER_POS2_ALPHA_MODE_PIPELINE :
202                                       SCALER_POS2_ALPHA_MODE_FIXED,
203                                       SCALER_POS2_ALPHA_MODE) |
204                         VC4_SET_FIELD(crtc_w, SCALER_POS2_WIDTH) |
205                         VC4_SET_FIELD(crtc_h, SCALER_POS2_HEIGHT));
206
207         /* Position Word 3: Context.  Written by the HVS. */
208         vc4_dlist_write(vc4_state, 0xc0c0c0c0);
209
210         /* Pointer Word 0: RGB / Y Pointer */
211         vc4_dlist_write(vc4_state, bo->paddr + offset);
212
213         /* Pointer Context Word 0: Written by the HVS */
214         vc4_dlist_write(vc4_state, 0xc0c0c0c0);
215
216         /* Pitch word 0: Pointer 0 Pitch */
217         vc4_dlist_write(vc4_state,
218                         VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH));
219
220         vc4_state->dlist[ctl0_offset] |=
221                 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
222
223         return 0;
224 }
225
226 /* If a modeset involves changing the setup of a plane, the atomic
227  * infrastructure will call this to validate a proposed plane setup.
228  * However, if a plane isn't getting updated, this (and the
229  * corresponding vc4_plane_atomic_update) won't get called.  Thus, we
230  * compute the dlist here and have all active plane dlists get updated
231  * in the CRTC's flush.
232  */
233 static int vc4_plane_atomic_check(struct drm_plane *plane,
234                                   struct drm_plane_state *state)
235 {
236         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
237
238         vc4_state->dlist_count = 0;
239
240         if (plane_enabled(state))
241                 return vc4_plane_mode_set(plane, state);
242         else
243                 return 0;
244 }
245
246 static void vc4_plane_atomic_update(struct drm_plane *plane,
247                                     struct drm_plane_state *old_state)
248 {
249         /* No contents here.  Since we don't know where in the CRTC's
250          * dlist we should be stored, our dlist is uploaded to the
251          * hardware with vc4_plane_write_dlist() at CRTC atomic_flush
252          * time.
253          */
254 }
255
256 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
257 {
258         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
259         int i;
260
261         /* Can't memcpy_toio() because it needs to be 32-bit writes. */
262         for (i = 0; i < vc4_state->dlist_count; i++)
263                 writel(vc4_state->dlist[i], &dlist[i]);
264
265         return vc4_state->dlist_count;
266 }
267
268 u32 vc4_plane_dlist_size(struct drm_plane_state *state)
269 {
270         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
271
272         return vc4_state->dlist_count;
273 }
274
275 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
276         .prepare_fb = NULL,
277         .cleanup_fb = NULL,
278         .atomic_check = vc4_plane_atomic_check,
279         .atomic_update = vc4_plane_atomic_update,
280 };
281
282 static void vc4_plane_destroy(struct drm_plane *plane)
283 {
284         drm_plane_helper_disable(plane);
285         drm_plane_cleanup(plane);
286 }
287
288 static const struct drm_plane_funcs vc4_plane_funcs = {
289         .update_plane = drm_atomic_helper_update_plane,
290         .disable_plane = drm_atomic_helper_disable_plane,
291         .destroy = vc4_plane_destroy,
292         .set_property = NULL,
293         .reset = vc4_plane_reset,
294         .atomic_duplicate_state = vc4_plane_duplicate_state,
295         .atomic_destroy_state = vc4_plane_destroy_state,
296 };
297
298 struct drm_plane *vc4_plane_init(struct drm_device *dev,
299                                  enum drm_plane_type type)
300 {
301         struct drm_plane *plane = NULL;
302         struct vc4_plane *vc4_plane;
303         u32 formats[ARRAY_SIZE(hvs_formats)];
304         int ret = 0;
305         unsigned i;
306
307         vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
308                                  GFP_KERNEL);
309         if (!vc4_plane) {
310                 ret = -ENOMEM;
311                 goto fail;
312         }
313
314         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++)
315                 formats[i] = hvs_formats[i].drm;
316         plane = &vc4_plane->base;
317         ret = drm_universal_plane_init(dev, plane, 0xff,
318                                        &vc4_plane_funcs,
319                                        formats, ARRAY_SIZE(formats),
320                                        type);
321
322         drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
323
324         return plane;
325 fail:
326         if (plane)
327                 vc4_plane_destroy(plane);
328
329         return ERR_PTR(ret);
330 }