kernel/drivers/gpu/drm/radeon/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "radeon_asic.h"
  27 #include "sid.h"
  28 #include "r600_dpm.h"
  29 #include "si_dpm.h"
  30 #include "atom.h"
  31 #include <linux/math64.h>
  32 #include <linux/seq_file.h>
  33
  34 #define MC_CG_ARB_FREQ_F0           0x0a
  35 #define MC_CG_ARB_FREQ_F1           0x0b
  36 #define MC_CG_ARB_FREQ_F2           0x0c
  37 #define MC_CG_ARB_FREQ_F3           0x0d
  38
  39 #define SMC_RAM_END                 0x20000
  40
  41 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  42
  43 static const struct si_cac_config_reg cac_weights_tahiti[] =
  44 {
  45         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
  46         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  47         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
  48         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
  49         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  50         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  51         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  52         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  53         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  54         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
  55         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  56         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
  57         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
  58         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
  59         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
  60         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  61         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  62         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
  63         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  64         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
  65         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
  66         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
  67         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  68         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  69         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  70         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  71         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  72         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  73         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  74         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  75         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
  76         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  77         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  78         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  79         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
  80         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  81         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  82         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
  83         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  84         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
  85         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  86         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  87         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  88         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  89         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  90         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  91         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  92         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  93         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  94         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  95         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  96         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  97         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  98         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  99         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 100         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 101         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 102         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 103         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 104         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 105         { 0xFFFFFFFF }
 106 };
 107
 108 static const struct si_cac_config_reg lcac_tahiti[] =
 109 {
 110         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 111         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 112         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 113         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 114         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 115         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 116         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 117         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 118         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 119         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 120         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 121         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 122         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 123         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 124         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 125         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 126         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 127         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 128         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 129         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 130         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 131         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 132         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 133         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 134         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 135         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 136         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 137         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 138         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 139         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 140         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 141         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 142         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 143         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 144         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 145         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 146         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 147         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 148         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 149         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 150         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 151         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 152         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 153         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 154         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 155         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 156         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 157         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 158         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 159         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 160         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 161         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 162         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 163         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 164         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 165         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 166         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 167         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 168         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 169         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 172         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 173         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 174         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 175         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 176         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 177         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 178         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 179         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 180         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 181         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 182         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 183         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 184         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 185         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 186         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 187         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 188         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 189         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 190         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 191         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 192         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 193         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 194         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 195         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 196         { 0xFFFFFFFF }
 197
 198 };
 199
 200 static const struct si_cac_config_reg cac_override_tahiti[] =
 201 {
 202         { 0xFFFFFFFF }
 203 };
 204
 205 static const struct si_powertune_data powertune_data_tahiti =
 206 {
 207         ((1 << 16) | 27027),
 208         6,
 209         0,
 210         4,
 211         95,
 212         {
 213                 0UL,
 214                 0UL,
 215                 4521550UL,
 216                 309631529UL,
 217                 -1270850L,
 218                 4513710L,
 219                 40
 220         },
 221         595000000UL,
 222         12,
 223         {
 224                 0,
 225                 0,
 226                 0,
 227                 0,
 228                 0,
 229                 0,
 230                 0,
 231                 0
 232         },
 233         true
 234 };
 235
 236 static const struct si_dte_data dte_data_tahiti =
 237 {
 238         { 1159409, 0, 0, 0, 0 },
 239         { 777, 0, 0, 0, 0 },
 240         2,
 241         54000,
 242         127000,
 243         25,
 244         2,
 245         10,
 246         13,
 247         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 248         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 249         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 250         85,
 251         false
 252 };
 253
 254 static const struct si_dte_data dte_data_tahiti_le =
 255 {
 256         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 257         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 258         0x5,
 259         0xAFC8,
 260         0x64,
 261         0x32,
 262         1,
 263         0,
 264         0x10,
 265         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 266         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 267         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 268         85,
 269         true
 270 };
 271
 272 static const struct si_dte_data dte_data_tahiti_pro =
 273 {
 274         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 275         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 276         5,
 277         45000,
 278         100,
 279         0xA,
 280         1,
 281         0,
 282         0x10,
 283         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 284         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 285         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 286         90,
 287         true
 288 };
 289
 290 static const struct si_dte_data dte_data_new_zealand =
 291 {
 292         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 293         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 294         0x5,
 295         0xAFC8,
 296         0x69,
 297         0x32,
 298         1,
 299         0,
 300         0x10,
 301         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 302         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 303         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 304         85,
 305         true
 306 };
 307
 308 static const struct si_dte_data dte_data_aruba_pro =
 309 {
 310         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 311         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 312         5,
 313         45000,
 314         100,
 315         0xA,
 316         1,
 317         0,
 318         0x10,
 319         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 320         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 321         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 322         90,
 323         true
 324 };
 325
 326 static const struct si_dte_data dte_data_malta =
 327 {
 328         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 329         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 330         5,
 331         45000,
 332         100,
 333         0xA,
 334         1,
 335         0,
 336         0x10,
 337         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 338         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 339         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 340         90,
 341         true
 342 };
 343
 344 struct si_cac_config_reg cac_weights_pitcairn[] =
 345 {
 346         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 347         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 348         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 349         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 350         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 351         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 352         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 353         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 354         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 355         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 356         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 357         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 358         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 359         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 360         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 361         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 362         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 363         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 364         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 365         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 366         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 367         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 368         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 369         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 370         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 371         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 372         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 373         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 374         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 375         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 376         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 377         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 378         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 379         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 380         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 381         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 382         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 383         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 384         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 385         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 386         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 387         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 388         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 389         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 390         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 391         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 392         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 393         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 394         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 395         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 396         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 397         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 398         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 399         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 400         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 401         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 402         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 403         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 404         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 405         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 406         { 0xFFFFFFFF }
 407 };
 408
 409 static const struct si_cac_config_reg lcac_pitcairn[] =
 410 {
 411         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 412         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 413         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 414         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 415         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 416         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 417         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 418         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 419         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 420         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 421         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 422         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 423         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 424         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 425         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 426         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 427         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 428         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 429         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 430         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 431         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 432         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 433         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 434         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 435         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 436         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 437         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 438         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 439         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 440         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 441         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 442         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 443         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 444         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 445         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 446         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 447         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 448         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 449         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 450         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 451         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 452         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 453         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 454         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 455         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 456         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 457         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 458         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 459         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 460         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 461         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 462         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 463         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 464         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 465         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 466         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 467         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 468         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 469         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 470         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 471         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 472         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 473         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 474         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 475         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 476         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 477         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 478         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 479         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 480         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 481         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 482         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 483         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 484         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 485         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 486         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 487         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 488         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 489         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 490         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 491         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 492         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 493         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 494         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 495         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 496         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 497         { 0xFFFFFFFF }
 498 };
 499
 500 static const struct si_cac_config_reg cac_override_pitcairn[] =
 501 {
 502     { 0xFFFFFFFF }
 503 };
 504
 505 static const struct si_powertune_data powertune_data_pitcairn =
 506 {
 507         ((1 << 16) | 27027),
 508         5,
 509         0,
 510         6,
 511         100,
 512         {
 513                 51600000UL,
 514                 1800000UL,
 515                 7194395UL,
 516                 309631529UL,
 517                 -1270850L,
 518                 4513710L,
 519                 100
 520         },
 521         117830498UL,
 522         12,
 523         {
 524                 0,
 525                 0,
 526                 0,
 527                 0,
 528                 0,
 529                 0,
 530                 0,
 531                 0
 532         },
 533         true
 534 };
 535
 536 static const struct si_dte_data dte_data_pitcairn =
 537 {
 538         { 0, 0, 0, 0, 0 },
 539         { 0, 0, 0, 0, 0 },
 540         0,
 541         0,
 542         0,
 543         0,
 544         0,
 545         0,
 546         0,
 547         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 548         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 549         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 550         0,
 551         false
 552 };
 553
 554 static const struct si_dte_data dte_data_curacao_xt =
 555 {
 556         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 557         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 558         5,
 559         45000,
 560         100,
 561         0xA,
 562         1,
 563         0,
 564         0x10,
 565         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 566         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 567         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 568         90,
 569         true
 570 };
 571
 572 static const struct si_dte_data dte_data_curacao_pro =
 573 {
 574         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 575         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 576         5,
 577         45000,
 578         100,
 579         0xA,
 580         1,
 581         0,
 582         0x10,
 583         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 584         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 585         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 586         90,
 587         true
 588 };
 589
 590 static const struct si_dte_data dte_data_neptune_xt =
 591 {
 592         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 593         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 594         5,
 595         45000,
 596         100,
 597         0xA,
 598         1,
 599         0,
 600         0x10,
 601         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 602         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 603         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 604         90,
 605         true
 606 };
 607
 608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 609 {
 610         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 611         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 612         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 613         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 614         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 615         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 616         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 617         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 618         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 619         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 620         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 621         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 622         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 623         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 624         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 625         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 626         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 627         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 628         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 629         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 630         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 631         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 632         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 633         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 634         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 635         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 636         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 637         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 638         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 639         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 640         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 641         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 642         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 643         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 644         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 645         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 646         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 647         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 648         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 649         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 650         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 651         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 652         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 653         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 654         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 655         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 656         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 657         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 658         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 659         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 660         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 661         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 662         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 663         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 664         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 665         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 666         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 667         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 668         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 669         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 670         { 0xFFFFFFFF }
 671 };
 672
 673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 674 {
 675         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 676         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 677         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 678         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 679         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 680         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 681         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 682         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 683         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 684         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 685         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 686         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 687         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 688         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 689         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 690         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 691         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 692         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 693         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 694         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 695         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 696         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 697         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 698         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 699         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 700         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 701         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 702         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 703         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 704         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 705         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 706         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 707         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 708         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 709         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 710         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 711         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 712         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 713         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 714         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 715         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 716         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 717         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 718         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 719         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 720         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 721         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 722         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 723         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 724         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 725         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 726         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 727         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 728         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 731         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 733         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 734         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 735         { 0xFFFFFFFF }
 736 };
 737
 738 static const struct si_cac_config_reg cac_weights_heathrow[] =
 739 {
 740         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 741         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 742         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 743         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 744         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 746         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 747         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 748         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 749         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 750         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 751         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 752         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 753         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 754         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 755         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 756         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 757         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 758         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 759         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 760         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 761         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 762         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 763         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 764         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 765         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 766         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 767         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 768         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 769         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 770         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 771         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 772         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 773         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 774         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 775         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 776         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 777         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 778         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 779         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 780         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 781         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 782         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 783         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 784         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 785         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 786         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 787         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 788         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 789         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 790         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 791         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 792         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 793         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 796         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 798         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 799         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 800         { 0xFFFFFFFF }
 801 };
 802
 803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 804 {
 805         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 806         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 807         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 808         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 809         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 811         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 812         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 813         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 814         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 815         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 816         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 817         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 818         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 819         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 820         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 821         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 822         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 823         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 824         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 825         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 826         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 827         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 828         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 829         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 830         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 831         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 832         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 833         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 834         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 835         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 836         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 837         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 838         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 839         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 840         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 841         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 842         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 843         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 844         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 845         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 846         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 847         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 848         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 849         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 850         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 851         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 852         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 853         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 854         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 855         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 856         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 857         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 858         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 861         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 863         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 864         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 865         { 0xFFFFFFFF }
 866 };
 867
 868 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 869 {
 870         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 871         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 872         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 873         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 874         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 876         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 877         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 878         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 879         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 880         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 881         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 882         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 883         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 884         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 885         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 886         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 887         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 888         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 889         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 890         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 891         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 892         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 893         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 894         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 895         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 896         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 897         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 898         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 899         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 900         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 901         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 902         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 903         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 904         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 905         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 906         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 907         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 908         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 909         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 910         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 911         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 912         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 913         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 914         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 915         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 916         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 917         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 918         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 919         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 920         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 921         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 922         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 923         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 926         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 928         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 929         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 930         { 0xFFFFFFFF }
 931 };
 932
 933 static const struct si_cac_config_reg lcac_cape_verde[] =
 934 {
 935         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 936         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 937         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 938         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 939         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 940         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 941         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 942         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 943         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 944         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 945         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 946         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 947         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 948         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 949         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 950         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 951         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 952         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 953         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 954         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 955         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 956         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 957         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 958         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 959         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 960         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 961         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 962         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 963         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 964         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 965         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 966         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 967         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 968         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 969         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 970         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 971         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 972         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 973         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 974         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 975         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 976         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 977         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 978         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 979         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 980         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 981         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 982         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 983         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 984         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 985         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 986         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 987         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 988         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 989         { 0xFFFFFFFF }
 990 };
 991
 992 static const struct si_cac_config_reg cac_override_cape_verde[] =
 993 {
 994     { 0xFFFFFFFF }
 995 };
 996
 997 static const struct si_powertune_data powertune_data_cape_verde =
 998 {
 999         ((1 << 16) | 0x6993),
1000         5,
1001         0,
1002         7,
1003         105,
1004         {
1005                 0UL,
1006                 0UL,
1007                 7194395UL,
1008                 309631529UL,
1009                 -1270850L,
1010                 4513710L,
1011                 100
1012         },
1013         117830498UL,
1014         12,
1015         {
1016                 0,
1017                 0,
1018                 0,
1019                 0,
1020                 0,
1021                 0,
1022                 0,
1023                 0
1024         },
1025         true
1026 };
1027
1028 static const struct si_dte_data dte_data_cape_verde =
1029 {
1030         { 0, 0, 0, 0, 0 },
1031         { 0, 0, 0, 0, 0 },
1032         0,
1033         0,
1034         0,
1035         0,
1036         0,
1037         0,
1038         0,
1039         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042         0,
1043         false
1044 };
1045
1046 static const struct si_dte_data dte_data_venus_xtx =
1047 {
1048         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1050         5,
1051         55000,
1052         0x69,
1053         0xA,
1054         1,
1055         0,
1056         0x3,
1057         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060         90,
1061         true
1062 };
1063
1064 static const struct si_dte_data dte_data_venus_xt =
1065 {
1066         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1068         5,
1069         55000,
1070         0x69,
1071         0xA,
1072         1,
1073         0,
1074         0x3,
1075         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078         90,
1079         true
1080 };
1081
1082 static const struct si_dte_data dte_data_venus_pro =
1083 {
1084         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1086         5,
1087         55000,
1088         0x69,
1089         0xA,
1090         1,
1091         0,
1092         0x3,
1093         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096         90,
1097         true
1098 };
1099
1100 struct si_cac_config_reg cac_weights_oland[] =
1101 {
1102         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1162         { 0xFFFFFFFF }
1163 };
1164
1165 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1166 {
1167         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1227         { 0xFFFFFFFF }
1228 };
1229
1230 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1231 {
1232         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1292         { 0xFFFFFFFF }
1293 };
1294
1295 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1296 {
1297         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1357         { 0xFFFFFFFF }
1358 };
1359
1360 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1361 {
1362         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1422         { 0xFFFFFFFF }
1423 };
1424
1425 static const struct si_cac_config_reg lcac_oland[] =
1426 {
1427         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469         { 0xFFFFFFFF }
1470 };
1471
1472 static const struct si_cac_config_reg lcac_mars_pro[] =
1473 {
1474         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516         { 0xFFFFFFFF }
1517 };
1518
1519 static const struct si_cac_config_reg cac_override_oland[] =
1520 {
1521         { 0xFFFFFFFF }
1522 };
1523
1524 static const struct si_powertune_data powertune_data_oland =
1525 {
1526         ((1 << 16) | 0x6993),
1527         5,
1528         0,
1529         7,
1530         105,
1531         {
1532                 0UL,
1533                 0UL,
1534                 7194395UL,
1535                 309631529UL,
1536                 -1270850L,
1537                 4513710L,
1538                 100
1539         },
1540         117830498UL,
1541         12,
1542         {
1543                 0,
1544                 0,
1545                 0,
1546                 0,
1547                 0,
1548                 0,
1549                 0,
1550                 0
1551         },
1552         true
1553 };
1554
1555 static const struct si_powertune_data powertune_data_mars_pro =
1556 {
1557         ((1 << 16) | 0x6993),
1558         5,
1559         0,
1560         7,
1561         105,
1562         {
1563                 0UL,
1564                 0UL,
1565                 7194395UL,
1566                 309631529UL,
1567                 -1270850L,
1568                 4513710L,
1569                 100
1570         },
1571         117830498UL,
1572         12,
1573         {
1574                 0,
1575                 0,
1576                 0,
1577                 0,
1578                 0,
1579                 0,
1580                 0,
1581                 0
1582         },
1583         true
1584 };
1585
1586 static const struct si_dte_data dte_data_oland =
1587 {
1588         { 0, 0, 0, 0, 0 },
1589         { 0, 0, 0, 0, 0 },
1590         0,
1591         0,
1592         0,
1593         0,
1594         0,
1595         0,
1596         0,
1597         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600         0,
1601         false
1602 };
1603
1604 static const struct si_dte_data dte_data_mars_pro =
1605 {
1606         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1608         5,
1609         55000,
1610         105,
1611         0xA,
1612         1,
1613         0,
1614         0x10,
1615         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1618         90,
1619         true
1620 };
1621
1622 static const struct si_dte_data dte_data_sun_xt =
1623 {
1624         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1626         5,
1627         55000,
1628         105,
1629         0xA,
1630         1,
1631         0,
1632         0x10,
1633         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1636         90,
1637         true
1638 };
1639
1640
1641 static const struct si_cac_config_reg cac_weights_hainan[] =
1642 {
1643         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1703         { 0xFFFFFFFF }
1704 };
1705
1706 static const struct si_powertune_data powertune_data_hainan =
1707 {
1708         ((1 << 16) | 0x6993),
1709         5,
1710         0,
1711         9,
1712         105,
1713         {
1714                 0UL,
1715                 0UL,
1716                 7194395UL,
1717                 309631529UL,
1718                 -1270850L,
1719                 4513710L,
1720                 100
1721         },
1722         117830498UL,
1723         12,
1724         {
1725                 0,
1726                 0,
1727                 0,
1728                 0,
1729                 0,
1730                 0,
1731                 0,
1732                 0
1733         },
1734         true
1735 };
1736
1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1741
1742 extern int si_mc_load_microcode(struct radeon_device *rdev);
1743
1744 static int si_populate_voltage_value(struct radeon_device *rdev,
1745                                      const struct atom_voltage_table *table,
1746                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1747 static int si_get_std_voltage_value(struct radeon_device *rdev,
1748                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1749                                     u16 *std_voltage);
1750 static int si_write_smc_soft_register(struct radeon_device *rdev,
1751                                       u16 reg_offset, u32 value);
1752 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1753                                          struct rv7xx_pl *pl,
1754                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1755 static int si_calculate_sclk_params(struct radeon_device *rdev,
1756                                     u32 engine_clock,
1757                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1758
1759 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1760 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1761
1762 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1763 {
1764         struct si_power_info *pi = rdev->pm.dpm.priv;
1765
1766         return pi;
1767 }
1768
1769 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1770                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1771 {
1772         s64 kt, kv, leakage_w, i_leakage, vddc;
1773         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1774         s64 tmp;
1775
1776         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1777         vddc = div64_s64(drm_int2fixp(v), 1000);
1778         temperature = div64_s64(drm_int2fixp(t), 1000);
1779
1780         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1781         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1782         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1783         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1784         t_ref = drm_int2fixp(coeff->t_ref);
1785
1786         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1787         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1788         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1789         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1790
1791         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1792
1793         *leakage = drm_fixp2int(leakage_w * 1000);
1794 }
1795
1796 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1797                                              const struct ni_leakage_coeffients *coeff,
1798                                              u16 v,
1799                                              s32 t,
1800                                              u32 i_leakage,
1801                                              u32 *leakage)
1802 {
1803         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1804 }
1805
1806 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1807                                                const u32 fixed_kt, u16 v,
1808                                                u32 ileakage, u32 *leakage)
1809 {
1810         s64 kt, kv, leakage_w, i_leakage, vddc;
1811
1812         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1813         vddc = div64_s64(drm_int2fixp(v), 1000);
1814
1815         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1816         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1817                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1818
1819         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1820
1821         *leakage = drm_fixp2int(leakage_w * 1000);
1822 }
1823
1824 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1825                                        const struct ni_leakage_coeffients *coeff,
1826                                        const u32 fixed_kt,
1827                                        u16 v,
1828                                        u32 i_leakage,
1829                                        u32 *leakage)
1830 {
1831         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1832 }
1833
1834
1835 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1836                                    struct si_dte_data *dte_data)
1837 {
1838         u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1839         u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1840         u32 k = dte_data->k;
1841         u32 t_max = dte_data->max_t;
1842         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1843         u32 t_0 = dte_data->t0;
1844         u32 i;
1845
1846         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1847                 dte_data->tdep_count = 3;
1848
1849                 for (i = 0; i < k; i++) {
1850                         dte_data->r[i] =
1851                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1852                                 (p_limit2  * (u32)100);
1853                 }
1854
1855                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1856
1857                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1858                         dte_data->tdep_r[i] = dte_data->r[4];
1859                 }
1860         } else {
1861                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1862         }
1863 }
1864
1865 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1866 {
1867         struct ni_power_info *ni_pi = ni_get_pi(rdev);
1868         struct si_power_info *si_pi = si_get_pi(rdev);
1869         bool update_dte_from_pl2 = false;
1870
1871         if (rdev->family == CHIP_TAHITI) {
1872                 si_pi->cac_weights = cac_weights_tahiti;
1873                 si_pi->lcac_config = lcac_tahiti;
1874                 si_pi->cac_override = cac_override_tahiti;
1875                 si_pi->powertune_data = &powertune_data_tahiti;
1876                 si_pi->dte_data = dte_data_tahiti;
1877
1878                 switch (rdev->pdev->device) {
1879                 case 0x6798:
1880                         si_pi->dte_data.enable_dte_by_default = true;
1881                         break;
1882                 case 0x6799:
1883                         si_pi->dte_data = dte_data_new_zealand;
1884                         break;
1885                 case 0x6790:
1886                 case 0x6791:
1887                 case 0x6792:
1888                 case 0x679E:
1889                         si_pi->dte_data = dte_data_aruba_pro;
1890                         update_dte_from_pl2 = true;
1891                         break;
1892                 case 0x679B:
1893                         si_pi->dte_data = dte_data_malta;
1894                         update_dte_from_pl2 = true;
1895                         break;
1896                 case 0x679A:
1897                         si_pi->dte_data = dte_data_tahiti_pro;
1898                         update_dte_from_pl2 = true;
1899                         break;
1900                 default:
1901                         if (si_pi->dte_data.enable_dte_by_default == true)
1902                                 DRM_ERROR("DTE is not enabled!\n");
1903                         break;
1904                 }
1905         } else if (rdev->family == CHIP_PITCAIRN) {
1906                 switch (rdev->pdev->device) {
1907                 case 0x6810:
1908                 case 0x6818:
1909                         si_pi->cac_weights = cac_weights_pitcairn;
1910                         si_pi->lcac_config = lcac_pitcairn;
1911                         si_pi->cac_override = cac_override_pitcairn;
1912                         si_pi->powertune_data = &powertune_data_pitcairn;
1913                         si_pi->dte_data = dte_data_curacao_xt;
1914                         update_dte_from_pl2 = true;
1915                         break;
1916                 case 0x6819:
1917                 case 0x6811:
1918                         si_pi->cac_weights = cac_weights_pitcairn;
1919                         si_pi->lcac_config = lcac_pitcairn;
1920                         si_pi->cac_override = cac_override_pitcairn;
1921                         si_pi->powertune_data = &powertune_data_pitcairn;
1922                         si_pi->dte_data = dte_data_curacao_pro;
1923                         update_dte_from_pl2 = true;
1924                         break;
1925                 case 0x6800:
1926                 case 0x6806:
1927                         si_pi->cac_weights = cac_weights_pitcairn;
1928                         si_pi->lcac_config = lcac_pitcairn;
1929                         si_pi->cac_override = cac_override_pitcairn;
1930                         si_pi->powertune_data = &powertune_data_pitcairn;
1931                         si_pi->dte_data = dte_data_neptune_xt;
1932                         update_dte_from_pl2 = true;
1933                         break;
1934                 default:
1935                         si_pi->cac_weights = cac_weights_pitcairn;
1936                         si_pi->lcac_config = lcac_pitcairn;
1937                         si_pi->cac_override = cac_override_pitcairn;
1938                         si_pi->powertune_data = &powertune_data_pitcairn;
1939                         si_pi->dte_data = dte_data_pitcairn;
1940                         break;
1941                 }
1942         } else if (rdev->family == CHIP_VERDE) {
1943                 si_pi->lcac_config = lcac_cape_verde;
1944                 si_pi->cac_override = cac_override_cape_verde;
1945                 si_pi->powertune_data = &powertune_data_cape_verde;
1946
1947                 switch (rdev->pdev->device) {
1948                 case 0x683B:
1949                 case 0x683F:
1950                 case 0x6829:
1951                 case 0x6835:
1952                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1953                         si_pi->dte_data = dte_data_cape_verde;
1954                         break;
1955                 case 0x682C:
1956                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1957                         si_pi->dte_data = dte_data_sun_xt;
1958                         break;
1959                 case 0x6825:
1960                 case 0x6827:
1961                         si_pi->cac_weights = cac_weights_heathrow;
1962                         si_pi->dte_data = dte_data_cape_verde;
1963                         break;
1964                 case 0x6824:
1965                 case 0x682D:
1966                         si_pi->cac_weights = cac_weights_chelsea_xt;
1967                         si_pi->dte_data = dte_data_cape_verde;
1968                         break;
1969                 case 0x682F:
1970                         si_pi->cac_weights = cac_weights_chelsea_pro;
1971                         si_pi->dte_data = dte_data_cape_verde;
1972                         break;
1973                 case 0x6820:
1974                         si_pi->cac_weights = cac_weights_heathrow;
1975                         si_pi->dte_data = dte_data_venus_xtx;
1976                         break;
1977                 case 0x6821:
1978                         si_pi->cac_weights = cac_weights_heathrow;
1979                         si_pi->dte_data = dte_data_venus_xt;
1980                         break;
1981                 case 0x6823:
1982                 case 0x682B:
1983                 case 0x6822:
1984                 case 0x682A:
1985                         si_pi->cac_weights = cac_weights_chelsea_pro;
1986                         si_pi->dte_data = dte_data_venus_pro;
1987                         break;
1988                 default:
1989                         si_pi->cac_weights = cac_weights_cape_verde;
1990                         si_pi->dte_data = dte_data_cape_verde;
1991                         break;
1992                 }
1993         } else if (rdev->family == CHIP_OLAND) {
1994                 switch (rdev->pdev->device) {
1995                 case 0x6601:
1996                 case 0x6621:
1997                 case 0x6603:
1998                 case 0x6605:
1999                         si_pi->cac_weights = cac_weights_mars_pro;
2000                         si_pi->lcac_config = lcac_mars_pro;
2001                         si_pi->cac_override = cac_override_oland;
2002                         si_pi->powertune_data = &powertune_data_mars_pro;
2003                         si_pi->dte_data = dte_data_mars_pro;
2004                         update_dte_from_pl2 = true;
2005                         break;
2006                 case 0x6600:
2007                 case 0x6606:
2008                 case 0x6620:
2009                 case 0x6604:
2010                         si_pi->cac_weights = cac_weights_mars_xt;
2011                         si_pi->lcac_config = lcac_mars_pro;
2012                         si_pi->cac_override = cac_override_oland;
2013                         si_pi->powertune_data = &powertune_data_mars_pro;
2014                         si_pi->dte_data = dte_data_mars_pro;
2015                         update_dte_from_pl2 = true;
2016                         break;
2017                 case 0x6611:
2018                 case 0x6613:
2019                 case 0x6608:
2020                         si_pi->cac_weights = cac_weights_oland_pro;
2021                         si_pi->lcac_config = lcac_mars_pro;
2022                         si_pi->cac_override = cac_override_oland;
2023                         si_pi->powertune_data = &powertune_data_mars_pro;
2024                         si_pi->dte_data = dte_data_mars_pro;
2025                         update_dte_from_pl2 = true;
2026                         break;
2027                 case 0x6610:
2028                         si_pi->cac_weights = cac_weights_oland_xt;
2029                         si_pi->lcac_config = lcac_mars_pro;
2030                         si_pi->cac_override = cac_override_oland;
2031                         si_pi->powertune_data = &powertune_data_mars_pro;
2032                         si_pi->dte_data = dte_data_mars_pro;
2033                         update_dte_from_pl2 = true;
2034                         break;
2035                 default:
2036                         si_pi->cac_weights = cac_weights_oland;
2037                         si_pi->lcac_config = lcac_oland;
2038                         si_pi->cac_override = cac_override_oland;
2039                         si_pi->powertune_data = &powertune_data_oland;
2040                         si_pi->dte_data = dte_data_oland;
2041                         break;
2042                 }
2043         } else if (rdev->family == CHIP_HAINAN) {
2044                 si_pi->cac_weights = cac_weights_hainan;
2045                 si_pi->lcac_config = lcac_oland;
2046                 si_pi->cac_override = cac_override_oland;
2047                 si_pi->powertune_data = &powertune_data_hainan;
2048                 si_pi->dte_data = dte_data_sun_xt;
2049                 update_dte_from_pl2 = true;
2050         } else {
2051                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2052                 return;
2053         }
2054
2055         ni_pi->enable_power_containment = false;
2056         ni_pi->enable_cac = false;
2057         ni_pi->enable_sq_ramping = false;
2058         si_pi->enable_dte = false;
2059
2060         if (si_pi->powertune_data->enable_powertune_by_default) {
2061                 ni_pi->enable_power_containment= true;
2062                 ni_pi->enable_cac = true;
2063                 if (si_pi->dte_data.enable_dte_by_default) {
2064                         si_pi->enable_dte = true;
2065                         if (update_dte_from_pl2)
2066                                 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2067
2068                 }
2069                 ni_pi->enable_sq_ramping = true;
2070         }
2071
2072         ni_pi->driver_calculate_cac_leakage = true;
2073         ni_pi->cac_configuration_required = true;
2074
2075         if (ni_pi->cac_configuration_required) {
2076                 ni_pi->support_cac_long_term_average = true;
2077                 si_pi->dyn_powertune_data.l2_lta_window_size =
2078                         si_pi->powertune_data->l2_lta_window_size_default;
2079                 si_pi->dyn_powertune_data.lts_truncate =
2080                         si_pi->powertune_data->lts_truncate_default;
2081         } else {
2082                 ni_pi->support_cac_long_term_average = false;
2083                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2084                 si_pi->dyn_powertune_data.lts_truncate = 0;
2085         }
2086
2087         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2088 }
2089
2090 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2091 {
2092         return 1;
2093 }
2094
2095 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2096 {
2097         u32 xclk;
2098         u32 wintime;
2099         u32 cac_window;
2100         u32 cac_window_size;
2101
2102         xclk = radeon_get_xclk(rdev);
2103
2104         if (xclk == 0)
2105                 return 0;
2106
2107         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2108         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2109
2110         wintime = (cac_window_size * 100) / xclk;
2111
2112         return wintime;
2113 }
2114
2115 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2116 {
2117         return power_in_watts;
2118 }
2119
2120 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2121                                             bool adjust_polarity,
2122                                             u32 tdp_adjustment,
2123                                             u32 *tdp_limit,
2124                                             u32 *near_tdp_limit)
2125 {
2126         u32 adjustment_delta, max_tdp_limit;
2127
2128         if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2129                 return -EINVAL;
2130
2131         max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2132
2133         if (adjust_polarity) {
2134                 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2135                 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2136         } else {
2137                 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2138                 adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;
2139                 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2140                         *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2141                 else
2142                         *near_tdp_limit = 0;
2143         }
2144
2145         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2146                 return -EINVAL;
2147         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2148                 return -EINVAL;
2149
2150         return 0;
2151 }
2152
2153 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2154                                       struct radeon_ps *radeon_state)
2155 {
2156         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2157         struct si_power_info *si_pi = si_get_pi(rdev);
2158
2159         if (ni_pi->enable_power_containment) {
2160                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2161                 PP_SIslands_PAPMParameters *papm_parm;
2162                 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2163                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2164                 u32 tdp_limit;
2165                 u32 near_tdp_limit;
2166                 int ret;
2167
2168                 if (scaling_factor == 0)
2169                         return -EINVAL;
2170
2171                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2172
2173                 ret = si_calculate_adjusted_tdp_limits(rdev,
2174                                                        false, /* ??? */
2175                                                        rdev->pm.dpm.tdp_adjustment,
2176                                                        &tdp_limit,
2177                                                        &near_tdp_limit);
2178                 if (ret)
2179                         return ret;
2180
2181                 smc_table->dpm2Params.TDPLimit =
2182                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2183                 smc_table->dpm2Params.NearTDPLimit =
2184                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2185                 smc_table->dpm2Params.SafePowerLimit =
2186                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2187
2188                 ret = si_copy_bytes_to_smc(rdev,
2189                                            (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2190                                                  offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2191                                            (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2192                                            sizeof(u32) * 3,
2193                                            si_pi->sram_end);
2194                 if (ret)
2195                         return ret;
2196
2197                 if (si_pi->enable_ppm) {
2198                         papm_parm = &si_pi->papm_parm;
2199                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2200                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2201                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2202                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2203                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2204                         papm_parm->PlatformPowerLimit = 0xffffffff;
2205                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2206
2207                         ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2208                                                    (u8 *)papm_parm,
2209                                                    sizeof(PP_SIslands_PAPMParameters),
2210                                                    si_pi->sram_end);
2211                         if (ret)
2212                                 return ret;
2213                 }
2214         }
2215         return 0;
2216 }
2217
2218 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2219                                         struct radeon_ps *radeon_state)
2220 {
2221         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2222         struct si_power_info *si_pi = si_get_pi(rdev);
2223
2224         if (ni_pi->enable_power_containment) {
2225                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2226                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2227                 int ret;
2228
2229                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2230
2231                 smc_table->dpm2Params.NearTDPLimit =
2232                         cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2233                 smc_table->dpm2Params.SafePowerLimit =
2234                         cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2235
2236                 ret = si_copy_bytes_to_smc(rdev,
2237                                            (si_pi->state_table_start +
2238                                             offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2239                                             offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2240                                            (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2241                                            sizeof(u32) * 2,
2242                                            si_pi->sram_end);
2243                 if (ret)
2244                         return ret;
2245         }
2246
2247         return 0;
2248 }
2249
2250 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2251                                                const u16 prev_std_vddc,
2252                                                const u16 curr_std_vddc)
2253 {
2254         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2255         u64 prev_vddc = (u64)prev_std_vddc;
2256         u64 curr_vddc = (u64)curr_std_vddc;
2257         u64 pwr_efficiency_ratio, n, d;
2258
2259         if ((prev_vddc == 0) || (curr_vddc == 0))
2260                 return 0;
2261
2262         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2263         d = prev_vddc * prev_vddc;
2264         pwr_efficiency_ratio = div64_u64(n, d);
2265
2266         if (pwr_efficiency_ratio > (u64)0xFFFF)
2267                 return 0;
2268
2269         return (u16)pwr_efficiency_ratio;
2270 }
2271
2272 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2273                                             struct radeon_ps *radeon_state)
2274 {
2275         struct si_power_info *si_pi = si_get_pi(rdev);
2276
2277         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2278             radeon_state->vclk && radeon_state->dclk)
2279                 return true;
2280
2281         return false;
2282 }
2283
2284 static int si_populate_power_containment_values(struct radeon_device *rdev,
2285                                                 struct radeon_ps *radeon_state,
2286                                                 SISLANDS_SMC_SWSTATE *smc_state)
2287 {
2288         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2289         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2290         struct ni_ps *state = ni_get_ps(radeon_state);
2291         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2292         u32 prev_sclk;
2293         u32 max_sclk;
2294         u32 min_sclk;
2295         u16 prev_std_vddc;
2296         u16 curr_std_vddc;
2297         int i;
2298         u16 pwr_efficiency_ratio;
2299         u8 max_ps_percent;
2300         bool disable_uvd_power_tune;
2301         int ret;
2302
2303         if (ni_pi->enable_power_containment == false)
2304                 return 0;
2305
2306         if (state->performance_level_count == 0)
2307                 return -EINVAL;
2308
2309         if (smc_state->levelCount != state->performance_level_count)
2310                 return -EINVAL;
2311
2312         disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2313
2314         smc_state->levels[0].dpm2.MaxPS = 0;
2315         smc_state->levels[0].dpm2.NearTDPDec = 0;
2316         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2317         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2318         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2319
2320         for (i = 1; i < state->performance_level_count; i++) {
2321                 prev_sclk = state->performance_levels[i-1].sclk;
2322                 max_sclk  = state->performance_levels[i].sclk;
2323                 if (i == 1)
2324                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2325                 else
2326                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2327
2328                 if (prev_sclk > max_sclk)
2329                         return -EINVAL;
2330
2331                 if ((max_ps_percent == 0) ||
2332                     (prev_sclk == max_sclk) ||
2333                     disable_uvd_power_tune) {
2334                         min_sclk = max_sclk;
2335                 } else if (i == 1) {
2336                         min_sclk = prev_sclk;
2337                 } else {
2338                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2339                 }
2340
2341                 if (min_sclk < state->performance_levels[0].sclk)
2342                         min_sclk = state->performance_levels[0].sclk;
2343
2344                 if (min_sclk == 0)
2345                         return -EINVAL;
2346
2347                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2348                                                 state->performance_levels[i-1].vddc, &vddc);
2349                 if (ret)
2350                         return ret;
2351
2352                 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2353                 if (ret)
2354                         return ret;
2355
2356                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2357                                                 state->performance_levels[i].vddc, &vddc);
2358                 if (ret)
2359                         return ret;
2360
2361                 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2362                 if (ret)
2363                         return ret;
2364
2365                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2366                                                                            prev_std_vddc, curr_std_vddc);
2367
2368                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2369                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2370                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2371                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2372                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2373         }
2374
2375         return 0;
2376 }
2377
2378 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2379                                          struct radeon_ps *radeon_state,
2380                                          SISLANDS_SMC_SWSTATE *smc_state)
2381 {
2382         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2383         struct ni_ps *state = ni_get_ps(radeon_state);
2384         u32 sq_power_throttle, sq_power_throttle2;
2385         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2386         int i;
2387
2388         if (state->performance_level_count == 0)
2389                 return -EINVAL;
2390
2391         if (smc_state->levelCount != state->performance_level_count)
2392                 return -EINVAL;
2393
2394         if (rdev->pm.dpm.sq_ramping_threshold == 0)
2395                 return -EINVAL;
2396
2397         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2398                 enable_sq_ramping = false;
2399
2400         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2401                 enable_sq_ramping = false;
2402
2403         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2404                 enable_sq_ramping = false;
2405
2406         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2407                 enable_sq_ramping = false;
2408
2409         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2410                 enable_sq_ramping = false;
2411
2412         for (i = 0; i < state->performance_level_count; i++) {
2413                 sq_power_throttle = 0;
2414                 sq_power_throttle2 = 0;
2415
2416                 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2417                     enable_sq_ramping) {
2418                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2419                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2420                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2421                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2422                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2423                 } else {
2424                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2425                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2426                 }
2427
2428                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2429                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2430         }
2431
2432         return 0;
2433 }
2434
2435 static int si_enable_power_containment(struct radeon_device *rdev,
2436                                        struct radeon_ps *radeon_new_state,
2437                                        bool enable)
2438 {
2439         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2440         PPSMC_Result smc_result;
2441         int ret = 0;
2442
2443         if (ni_pi->enable_power_containment) {
2444                 if (enable) {
2445                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2446                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2447                                 if (smc_result != PPSMC_Result_OK) {
2448                                         ret = -EINVAL;
2449                                         ni_pi->pc_enabled = false;
2450                                 } else {
2451                                         ni_pi->pc_enabled = true;
2452                                 }
2453                         }
2454                 } else {
2455                         smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2456                         if (smc_result != PPSMC_Result_OK)
2457                                 ret = -EINVAL;
2458                         ni_pi->pc_enabled = false;
2459                 }
2460         }
2461
2462         return ret;
2463 }
2464
2465 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2466 {
2467         struct si_power_info *si_pi = si_get_pi(rdev);
2468         int ret = 0;
2469         struct si_dte_data *dte_data = &si_pi->dte_data;
2470         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2471         u32 table_size;
2472         u8 tdep_count;
2473         u32 i;
2474
2475         if (dte_data == NULL)
2476                 si_pi->enable_dte = false;
2477
2478         if (si_pi->enable_dte == false)
2479                 return 0;
2480
2481         if (dte_data->k <= 0)
2482                 return -EINVAL;
2483
2484         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2485         if (dte_tables == NULL) {
2486                 si_pi->enable_dte = false;
2487                 return -ENOMEM;
2488         }
2489
2490         table_size = dte_data->k;
2491
2492         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2493                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2494
2495         tdep_count = dte_data->tdep_count;
2496         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2497                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2498
2499         dte_tables->K = cpu_to_be32(table_size);
2500         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2501         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2502         dte_tables->WindowSize = dte_data->window_size;
2503         dte_tables->temp_select = dte_data->temp_select;
2504         dte_tables->DTE_mode = dte_data->dte_mode;
2505         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2506
2507         if (tdep_count > 0)
2508                 table_size--;
2509
2510         for (i = 0; i < table_size; i++) {
2511                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2512                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2513         }
2514
2515         dte_tables->Tdep_count = tdep_count;
2516
2517         for (i = 0; i < (u32)tdep_count; i++) {
2518                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2519                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2520                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2521         }
2522
2523         ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2524                                    sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2525         kfree(dte_tables);
2526
2527         return ret;
2528 }
2529
2530 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2531                                           u16 *max, u16 *min)
2532 {
2533         struct si_power_info *si_pi = si_get_pi(rdev);
2534         struct radeon_cac_leakage_table *table =
2535                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2536         u32 i;
2537         u32 v0_loadline;
2538
2539
2540         if (table == NULL)
2541                 return -EINVAL;
2542
2543         *max = 0;
2544         *min = 0xFFFF;
2545
2546         for (i = 0; i < table->count; i++) {
2547                 if (table->entries[i].vddc > *max)
2548                         *max = table->entries[i].vddc;
2549                 if (table->entries[i].vddc < *min)
2550                         *min = table->entries[i].vddc;
2551         }
2552
2553         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2554                 return -EINVAL;
2555
2556         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2557
2558         if (v0_loadline > 0xFFFFUL)
2559                 return -EINVAL;
2560
2561         *min = (u16)v0_loadline;
2562
2563         if ((*min > *max) || (*max == 0) || (*min == 0))
2564                 return -EINVAL;
2565
2566         return 0;
2567 }
2568
2569 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2570 {
2571         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2572                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2573 }
2574
2575 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2576                                      PP_SIslands_CacConfig *cac_tables,
2577                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2578                                      u16 t0, u16 t_step)
2579 {
2580         struct si_power_info *si_pi = si_get_pi(rdev);
2581         u32 leakage;
2582         unsigned int i, j;
2583         s32 t;
2584         u32 smc_leakage;
2585         u32 scaling_factor;
2586         u16 voltage;
2587
2588         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2589
2590         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2591                 t = (1000 * (i * t_step + t0));
2592
2593                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2594                         voltage = vddc_max - (vddc_step * j);
2595
2596                         si_calculate_leakage_for_v_and_t(rdev,
2597                                                          &si_pi->powertune_data->leakage_coefficients,
2598                                                          voltage,
2599                                                          t,
2600                                                          si_pi->dyn_powertune_data.cac_leakage,
2601                                                          &leakage);
2602
2603                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2604
2605                         if (smc_leakage > 0xFFFF)
2606                                 smc_leakage = 0xFFFF;
2607
2608                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2609                                 cpu_to_be16((u16)smc_leakage);
2610                 }
2611         }
2612         return 0;
2613 }
2614
2615 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2616                                             PP_SIslands_CacConfig *cac_tables,
2617                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2618 {
2619         struct si_power_info *si_pi = si_get_pi(rdev);
2620         u32 leakage;
2621         unsigned int i, j;
2622         u32 smc_leakage;
2623         u32 scaling_factor;
2624         u16 voltage;
2625
2626         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2627
2628         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2629                 voltage = vddc_max - (vddc_step * j);
2630
2631                 si_calculate_leakage_for_v(rdev,
2632                                            &si_pi->powertune_data->leakage_coefficients,
2633                                            si_pi->powertune_data->fixed_kt,
2634                                            voltage,
2635                                            si_pi->dyn_powertune_data.cac_leakage,
2636                                            &leakage);
2637
2638                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2639
2640                 if (smc_leakage > 0xFFFF)
2641                         smc_leakage = 0xFFFF;
2642
2643                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2644                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2645                                 cpu_to_be16((u16)smc_leakage);
2646         }
2647         return 0;
2648 }
2649
2650 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2651 {
2652         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2653         struct si_power_info *si_pi = si_get_pi(rdev);
2654         PP_SIslands_CacConfig *cac_tables = NULL;
2655         u16 vddc_max, vddc_min, vddc_step;
2656         u16 t0, t_step;
2657         u32 load_line_slope, reg;
2658         int ret = 0;
2659         u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2660
2661         if (ni_pi->enable_cac == false)
2662                 return 0;
2663
2664         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2665         if (!cac_tables)
2666                 return -ENOMEM;
2667
2668         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2669         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2670         WREG32(CG_CAC_CTRL, reg);
2671
2672         si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2673         si_pi->dyn_powertune_data.dc_pwr_value =
2674                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2675         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2676         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2677
2678         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2679
2680         ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2681         if (ret)
2682                 goto done_free;
2683
2684         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2685         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2686         t_step = 4;
2687         t0 = 60;
2688
2689         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2690                 ret = si_init_dte_leakage_table(rdev, cac_tables,
2691                                                 vddc_max, vddc_min, vddc_step,
2692                                                 t0, t_step);
2693         else
2694                 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2695                                                        vddc_max, vddc_min, vddc_step);
2696         if (ret)
2697                 goto done_free;
2698
2699         load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2700
2701         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2702         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2703         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2704         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2705         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2706         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2707         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2708         cac_tables->calculation_repeats = cpu_to_be32(2);
2709         cac_tables->dc_cac = cpu_to_be32(0);
2710         cac_tables->log2_PG_LKG_SCALE = 12;
2711         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2712         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2713         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2714
2715         ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2716                                    sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2717
2718         if (ret)
2719                 goto done_free;
2720
2721         ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2722
2723 done_free:
2724         if (ret) {
2725                 ni_pi->enable_cac = false;
2726                 ni_pi->enable_power_containment = false;
2727         }
2728
2729         kfree(cac_tables);
2730
2731         return 0;
2732 }
2733
2734 static int si_program_cac_config_registers(struct radeon_device *rdev,
2735                                            const struct si_cac_config_reg *cac_config_regs)
2736 {
2737         const struct si_cac_config_reg *config_regs = cac_config_regs;
2738         u32 data = 0, offset;
2739
2740         if (!config_regs)
2741                 return -EINVAL;
2742
2743         while (config_regs->offset != 0xFFFFFFFF) {
2744                 switch (config_regs->type) {
2745                 case SISLANDS_CACCONFIG_CGIND:
2746                         offset = SMC_CG_IND_START + config_regs->offset;
2747                         if (offset < SMC_CG_IND_END)
2748                                 data = RREG32_SMC(offset);
2749                         break;
2750                 default:
2751                         data = RREG32(config_regs->offset << 2);
2752                         break;
2753                 }
2754
2755                 data &= ~config_regs->mask;
2756                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2757
2758                 switch (config_regs->type) {
2759                 case SISLANDS_CACCONFIG_CGIND:
2760                         offset = SMC_CG_IND_START + config_regs->offset;
2761                         if (offset < SMC_CG_IND_END)
2762                                 WREG32_SMC(offset, data);
2763                         break;
2764                 default:
2765                         WREG32(config_regs->offset << 2, data);
2766                         break;
2767                 }
2768                 config_regs++;
2769         }
2770         return 0;
2771 }
2772
2773 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2774 {
2775         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2776         struct si_power_info *si_pi = si_get_pi(rdev);
2777         int ret;
2778
2779         if ((ni_pi->enable_cac == false) ||
2780             (ni_pi->cac_configuration_required == false))
2781                 return 0;
2782
2783         ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2784         if (ret)
2785                 return ret;
2786         ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2787         if (ret)
2788                 return ret;
2789         ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2790         if (ret)
2791                 return ret;
2792
2793         return 0;
2794 }
2795
2796 static int si_enable_smc_cac(struct radeon_device *rdev,
2797                              struct radeon_ps *radeon_new_state,
2798                              bool enable)
2799 {
2800         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2801         struct si_power_info *si_pi = si_get_pi(rdev);
2802         PPSMC_Result smc_result;
2803         int ret = 0;
2804
2805         if (ni_pi->enable_cac) {
2806                 if (enable) {
2807                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2808                                 if (ni_pi->support_cac_long_term_average) {
2809                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2810                                         if (smc_result != PPSMC_Result_OK)
2811                                                 ni_pi->support_cac_long_term_average = false;
2812                                 }
2813
2814                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2815                                 if (smc_result != PPSMC_Result_OK) {
2816                                         ret = -EINVAL;
2817                                         ni_pi->cac_enabled = false;
2818                                 } else {
2819                                         ni_pi->cac_enabled = true;
2820                                 }
2821
2822                                 if (si_pi->enable_dte) {
2823                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2824                                         if (smc_result != PPSMC_Result_OK)
2825                                                 ret = -EINVAL;
2826                                 }
2827                         }
2828                 } else if (ni_pi->cac_enabled) {
2829                         if (si_pi->enable_dte)
2830                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2831
2832                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2833
2834                         ni_pi->cac_enabled = false;
2835
2836                         if (ni_pi->support_cac_long_term_average)
2837                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2838                 }
2839         }
2840         return ret;
2841 }
2842
2843 static int si_init_smc_spll_table(struct radeon_device *rdev)
2844 {
2845         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2846         struct si_power_info *si_pi = si_get_pi(rdev);
2847         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2848         SISLANDS_SMC_SCLK_VALUE sclk_params;
2849         u32 fb_div, p_div;
2850         u32 clk_s, clk_v;
2851         u32 sclk = 0;
2852         int ret = 0;
2853         u32 tmp;
2854         int i;
2855
2856         if (si_pi->spll_table_start == 0)
2857                 return -EINVAL;
2858
2859         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2860         if (spll_table == NULL)
2861                 return -ENOMEM;
2862
2863         for (i = 0; i < 256; i++) {
2864                 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2865                 if (ret)
2866                         break;
2867
2868                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2869                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2870                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2871                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2872
2873                 fb_div &= ~0x00001FFF;
2874                 fb_div >>= 1;
2875                 clk_v >>= 6;
2876
2877                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2878                         ret = -EINVAL;
2879                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2880                         ret = -EINVAL;
2881                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2882                         ret = -EINVAL;
2883                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2884                         ret = -EINVAL;
2885
2886                 if (ret)
2887                         break;
2888
2889                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2890                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2891                 spll_table->freq[i] = cpu_to_be32(tmp);
2892
2893                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2894                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2895                 spll_table->ss[i] = cpu_to_be32(tmp);
2896
2897                 sclk += 512;
2898         }
2899
2900
2901         if (!ret)
2902                 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2903                                            (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2904                                            si_pi->sram_end);
2905
2906         if (ret)
2907                 ni_pi->enable_power_containment = false;
2908
2909         kfree(spll_table);
2910
2911         return ret;
2912 }
2913
2914 struct si_dpm_quirk {
2915         u32 chip_vendor;
2916         u32 chip_device;
2917         u32 subsys_vendor;
2918         u32 subsys_device;
2919         u32 max_sclk;
2920         u32 max_mclk;
2921 };
2922
2923 /* cards with dpm stability problems */
2924 static struct si_dpm_quirk si_dpm_quirk_list[] = {
2925         /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2926         { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2927         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
2928         { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
2929         { 0, 0, 0, 0 },
2930 };
2931
2932 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2933                                         struct radeon_ps *rps)
2934 {
2935         struct ni_ps *ps = ni_get_ps(rps);
2936         struct radeon_clock_and_voltage_limits *max_limits;
2937         bool disable_mclk_switching = false;
2938         bool disable_sclk_switching = false;
2939         u32 mclk, sclk;
2940         u16 vddc, vddci;
2941         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2942         u32 max_sclk = 0, max_mclk = 0;
2943         int i;
2944         struct si_dpm_quirk *p = si_dpm_quirk_list;
2945
2946         /* Apply dpm quirks */
2947         while (p && p->chip_device != 0) {
2948                 if (rdev->pdev->vendor == p->chip_vendor &&
2949                     rdev->pdev->device == p->chip_device &&
2950                     rdev->pdev->subsystem_vendor == p->subsys_vendor &&
2951                     rdev->pdev->subsystem_device == p->subsys_device) {
2952                         max_sclk = p->max_sclk;
2953                         max_mclk = p->max_mclk;
2954                         break;
2955                 }
2956                 ++p;
2957         }
2958
2959         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2960             ni_dpm_vblank_too_short(rdev))
2961                 disable_mclk_switching = true;
2962
2963         if (rps->vclk || rps->dclk) {
2964                 disable_mclk_switching = true;
2965                 disable_sclk_switching = true;
2966         }
2967
2968         if (rdev->pm.dpm.ac_power)
2969                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2970         else
2971                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2972
2973         for (i = ps->performance_level_count - 2; i >= 0; i--) {
2974                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
2975                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
2976         }
2977         if (rdev->pm.dpm.ac_power == false) {
2978                 for (i = 0; i < ps->performance_level_count; i++) {
2979                         if (ps->performance_levels[i].mclk > max_limits->mclk)
2980                                 ps->performance_levels[i].mclk = max_limits->mclk;
2981                         if (ps->performance_levels[i].sclk > max_limits->sclk)
2982                                 ps->performance_levels[i].sclk = max_limits->sclk;
2983                         if (ps->performance_levels[i].vddc > max_limits->vddc)
2984                                 ps->performance_levels[i].vddc = max_limits->vddc;
2985                         if (ps->performance_levels[i].vddci > max_limits->vddci)
2986                                 ps->performance_levels[i].vddci = max_limits->vddci;
2987                 }
2988         }
2989
2990         /* limit clocks to max supported clocks based on voltage dependency tables */
2991         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2992                                                         &max_sclk_vddc);
2993         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2994                                                         &max_mclk_vddci);
2995         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2996                                                         &max_mclk_vddc);
2997
2998         for (i = 0; i < ps->performance_level_count; i++) {
2999                 if (max_sclk_vddc) {
3000                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3001                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3002                 }
3003                 if (max_mclk_vddci) {
3004                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3005                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3006                 }
3007                 if (max_mclk_vddc) {
3008                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3009                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3010                 }
3011                 if (max_mclk) {
3012                         if (ps->performance_levels[i].mclk > max_mclk)
3013                                 ps->performance_levels[i].mclk = max_mclk;
3014                 }
3015                 if (max_sclk) {
3016                         if (ps->performance_levels[i].sclk > max_sclk)
3017                                 ps->performance_levels[i].sclk = max_sclk;
3018                 }
3019         }
3020
3021         /* XXX validate the min clocks required for display */
3022
3023         if (disable_mclk_switching) {
3024                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3025                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3026         } else {
3027                 mclk = ps->performance_levels[0].mclk;
3028                 vddci = ps->performance_levels[0].vddci;
3029         }
3030
3031         if (disable_sclk_switching) {
3032                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3033                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3034         } else {
3035                 sclk = ps->performance_levels[0].sclk;
3036                 vddc = ps->performance_levels[0].vddc;
3037         }
3038
3039         /* adjusted low state */
3040         ps->performance_levels[0].sclk = sclk;
3041         ps->performance_levels[0].mclk = mclk;
3042         ps->performance_levels[0].vddc = vddc;
3043         ps->performance_levels[0].vddci = vddci;
3044
3045         if (disable_sclk_switching) {
3046                 sclk = ps->performance_levels[0].sclk;
3047                 for (i = 1; i < ps->performance_level_count; i++) {
3048                         if (sclk < ps->performance_levels[i].sclk)
3049                                 sclk = ps->performance_levels[i].sclk;
3050                 }
3051                 for (i = 0; i < ps->performance_level_count; i++) {
3052                         ps->performance_levels[i].sclk = sclk;
3053                         ps->performance_levels[i].vddc = vddc;
3054                 }
3055         } else {
3056                 for (i = 1; i < ps->performance_level_count; i++) {
3057                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3058                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3059                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3060                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3061                 }
3062         }
3063
3064         if (disable_mclk_switching) {
3065                 mclk = ps->performance_levels[0].mclk;
3066                 for (i = 1; i < ps->performance_level_count; i++) {
3067                         if (mclk < ps->performance_levels[i].mclk)
3068                                 mclk = ps->performance_levels[i].mclk;
3069                 }
3070                 for (i = 0; i < ps->performance_level_count; i++) {
3071                         ps->performance_levels[i].mclk = mclk;
3072                         ps->performance_levels[i].vddci = vddci;
3073                 }
3074         } else {
3075                 for (i = 1; i < ps->performance_level_count; i++) {
3076                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3077                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3078                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3079                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3080                 }
3081         }
3082
3083         for (i = 0; i < ps->performance_level_count; i++)
3084                 btc_adjust_clock_combinations(rdev, max_limits,
3085                                               &ps->performance_levels[i]);
3086
3087         for (i = 0; i < ps->performance_level_count; i++) {
3088                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3089                                                    ps->performance_levels[i].sclk,
3090                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3091                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3092                                                    ps->performance_levels[i].mclk,
3093                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3094                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3095                                                    ps->performance_levels[i].mclk,
3096                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3097                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3098                                                    rdev->clock.current_dispclk,
3099                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3100         }
3101
3102         for (i = 0; i < ps->performance_level_count; i++) {
3103                 btc_apply_voltage_delta_rules(rdev,
3104                                               max_limits->vddc, max_limits->vddci,
3105                                               &ps->performance_levels[i].vddc,
3106                                               &ps->performance_levels[i].vddci);
3107         }
3108
3109         ps->dc_compatible = true;
3110         for (i = 0; i < ps->performance_level_count; i++) {
3111                 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3112                         ps->dc_compatible = false;
3113         }
3114
3115 }
3116
3117 #if 0
3118 static int si_read_smc_soft_register(struct radeon_device *rdev,
3119                                      u16 reg_offset, u32 *value)
3120 {
3121         struct si_power_info *si_pi = si_get_pi(rdev);
3122
3123         return si_read_smc_sram_dword(rdev,
3124                                       si_pi->soft_regs_start + reg_offset, value,
3125                                       si_pi->sram_end);
3126 }
3127 #endif
3128
3129 static int si_write_smc_soft_register(struct radeon_device *rdev,
3130                                       u16 reg_offset, u32 value)
3131 {
3132         struct si_power_info *si_pi = si_get_pi(rdev);
3133
3134         return si_write_smc_sram_dword(rdev,
3135                                        si_pi->soft_regs_start + reg_offset,
3136                                        value, si_pi->sram_end);
3137 }
3138
3139 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3140 {
3141         bool ret = false;
3142         u32 tmp, width, row, column, bank, density;
3143         bool is_memory_gddr5, is_special;
3144
3145         tmp = RREG32(MC_SEQ_MISC0);
3146         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3147         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3148                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3149
3150         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3151         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3152
3153         tmp = RREG32(MC_ARB_RAMCFG);
3154         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3155         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3156         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3157
3158         density = (1 << (row + column - 20 + bank)) * width;
3159
3160         if ((rdev->pdev->device == 0x6819) &&
3161             is_memory_gddr5 && is_special && (density == 0x400))
3162                 ret = true;
3163
3164         return ret;
3165 }
3166
3167 static void si_get_leakage_vddc(struct radeon_device *rdev)
3168 {
3169         struct si_power_info *si_pi = si_get_pi(rdev);
3170         u16 vddc, count = 0;
3171         int i, ret;
3172
3173         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3174                 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3175
3176                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3177                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3178                         si_pi->leakage_voltage.entries[count].leakage_index =
3179                                 SISLANDS_LEAKAGE_INDEX0 + i;
3180                         count++;
3181                 }
3182         }
3183         si_pi->leakage_voltage.count = count;
3184 }
3185
3186 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3187                                                      u32 index, u16 *leakage_voltage)
3188 {
3189         struct si_power_info *si_pi = si_get_pi(rdev);
3190         int i;
3191
3192         if (leakage_voltage == NULL)
3193                 return -EINVAL;
3194
3195         if ((index & 0xff00) != 0xff00)
3196                 return -EINVAL;
3197
3198         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3199                 return -EINVAL;
3200
3201         if (index < SISLANDS_LEAKAGE_INDEX0)
3202                 return -EINVAL;
3203
3204         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3205                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3206                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3207                         return 0;
3208                 }
3209         }
3210         return -EAGAIN;
3211 }
3212
3213 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3214 {
3215         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3216         bool want_thermal_protection;
3217         enum radeon_dpm_event_src dpm_event_src;
3218
3219         switch (sources) {
3220         case 0:
3221         default:
3222                 want_thermal_protection = false;
3223                 break;
3224         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3225                 want_thermal_protection = true;
3226                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3227                 break;
3228         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3229                 want_thermal_protection = true;
3230                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3231                 break;
3232         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3233               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3234                 want_thermal_protection = true;
3235                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3236                 break;
3237         }
3238
3239         if (want_thermal_protection) {
3240                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3241                 if (pi->thermal_protection)
3242                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3243         } else {
3244                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3245         }
3246 }
3247
3248 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3249                                            enum radeon_dpm_auto_throttle_src source,
3250                                            bool enable)
3251 {
3252         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3253
3254         if (enable) {
3255                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3256                         pi->active_auto_throttle_sources |= 1 << source;
3257                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3258                 }
3259         } else {
3260                 if (pi->active_auto_throttle_sources & (1 << source)) {
3261                         pi->active_auto_throttle_sources &= ~(1 << source);
3262                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3263                 }
3264         }
3265 }
3266
3267 static void si_start_dpm(struct radeon_device *rdev)
3268 {
3269         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3270 }
3271
3272 static void si_stop_dpm(struct radeon_device *rdev)
3273 {
3274         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3275 }
3276
3277 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3278 {
3279         if (enable)
3280                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3281         else
3282                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3283
3284 }
3285
3286 #if 0
3287 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3288                                                u32 thermal_level)
3289 {
3290         PPSMC_Result ret;
3291
3292         if (thermal_level == 0) {
3293                 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3294                 if (ret == PPSMC_Result_OK)
3295                         return 0;
3296                 else
3297                         return -EINVAL;
3298         }
3299         return 0;
3300 }
3301
3302 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3303 {
3304         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3305 }
3306 #endif
3307
3308 #if 0
3309 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3310 {
3311         if (ac_power)
3312                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3313                         0 : -EINVAL;
3314
3315         return 0;
3316 }
3317 #endif
3318
3319 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3320                                                       PPSMC_Msg msg, u32 parameter)
3321 {
3322         WREG32(SMC_SCRATCH0, parameter);
3323         return si_send_msg_to_smc(rdev, msg);
3324 }
3325
3326 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3327 {
3328         if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3329                 return -EINVAL;
3330
3331         return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3332                 0 : -EINVAL;
3333 }
3334
3335 int si_dpm_force_performance_level(struct radeon_device *rdev,
3336                                    enum radeon_dpm_forced_level level)
3337 {
3338         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3339         struct ni_ps *ps = ni_get_ps(rps);
3340         u32 levels = ps->performance_level_count;
3341
3342         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3343                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3344                         return -EINVAL;
3345
3346                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3347                         return -EINVAL;
3348         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3349                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3350                         return -EINVAL;
3351
3352                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3353                         return -EINVAL;
3354         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3355                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3356                         return -EINVAL;
3357
3358                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3359                         return -EINVAL;
3360         }
3361
3362         rdev->pm.dpm.forced_level = level;
3363
3364         return 0;
3365 }
3366
3367 #if 0
3368 static int si_set_boot_state(struct radeon_device *rdev)
3369 {
3370         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3371                 0 : -EINVAL;
3372 }
3373 #endif
3374
3375 static int si_set_sw_state(struct radeon_device *rdev)
3376 {
3377         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3378                 0 : -EINVAL;
3379 }
3380
3381 static int si_halt_smc(struct radeon_device *rdev)
3382 {
3383         if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3384                 return -EINVAL;
3385
3386         return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3387                 0 : -EINVAL;
3388 }
3389
3390 static int si_resume_smc(struct radeon_device *rdev)
3391 {
3392         if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3393                 return -EINVAL;
3394
3395         return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3396                 0 : -EINVAL;
3397 }
3398
3399 static void si_dpm_start_smc(struct radeon_device *rdev)
3400 {
3401         si_program_jump_on_start(rdev);
3402         si_start_smc(rdev);
3403         si_start_smc_clock(rdev);
3404 }
3405
3406 static void si_dpm_stop_smc(struct radeon_device *rdev)
3407 {
3408         si_reset_smc(rdev);
3409         si_stop_smc_clock(rdev);
3410 }
3411
3412 static int si_process_firmware_header(struct radeon_device *rdev)
3413 {
3414         struct si_power_info *si_pi = si_get_pi(rdev);
3415         u32 tmp;
3416         int ret;
3417
3418         ret = si_read_smc_sram_dword(rdev,
3419                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3420                                      SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3421                                      &tmp, si_pi->sram_end);
3422         if (ret)
3423                 return ret;
3424
3425         si_pi->state_table_start = tmp;
3426
3427         ret = si_read_smc_sram_dword(rdev,
3428                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3429                                      SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3430                                      &tmp, si_pi->sram_end);
3431         if (ret)
3432                 return ret;
3433
3434         si_pi->soft_regs_start = tmp;
3435
3436         ret = si_read_smc_sram_dword(rdev,
3437                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3438                                      SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3439                                      &tmp, si_pi->sram_end);
3440         if (ret)
3441                 return ret;
3442
3443         si_pi->mc_reg_table_start = tmp;
3444
3445         ret = si_read_smc_sram_dword(rdev,
3446                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3447                                      SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3448                                      &tmp, si_pi->sram_end);
3449         if (ret)
3450                 return ret;
3451
3452         si_pi->fan_table_start = tmp;
3453
3454         ret = si_read_smc_sram_dword(rdev,
3455                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3456                                      SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3457                                      &tmp, si_pi->sram_end);
3458         if (ret)
3459                 return ret;
3460
3461         si_pi->arb_table_start = tmp;
3462
3463         ret = si_read_smc_sram_dword(rdev,
3464                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3465                                      SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3466                                      &tmp, si_pi->sram_end);
3467         if (ret)
3468                 return ret;
3469
3470         si_pi->cac_table_start = tmp;
3471
3472         ret = si_read_smc_sram_dword(rdev,
3473                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3474                                      SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3475                                      &tmp, si_pi->sram_end);
3476         if (ret)
3477                 return ret;
3478
3479         si_pi->dte_table_start = tmp;
3480
3481         ret = si_read_smc_sram_dword(rdev,
3482                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3483                                      SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3484                                      &tmp, si_pi->sram_end);
3485         if (ret)
3486                 return ret;
3487
3488         si_pi->spll_table_start = tmp;
3489
3490         ret = si_read_smc_sram_dword(rdev,
3491                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3492                                      SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3493                                      &tmp, si_pi->sram_end);
3494         if (ret)
3495                 return ret;
3496
3497         si_pi->papm_cfg_table_start = tmp;
3498
3499         return ret;
3500 }
3501
3502 static void si_read_clock_registers(struct radeon_device *rdev)
3503 {
3504         struct si_power_info *si_pi = si_get_pi(rdev);
3505
3506         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3507         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3508         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3509         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3510         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3511         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3512         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3513         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3514         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3515         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3516         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3517         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3518         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3519         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3520         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3521 }
3522
3523 static void si_enable_thermal_protection(struct radeon_device *rdev,
3524                                           bool enable)
3525 {
3526         if (enable)
3527                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3528         else
3529                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3530 }
3531
3532 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3533 {
3534         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3535 }
3536
3537 #if 0
3538 static int si_enter_ulp_state(struct radeon_device *rdev)
3539 {
3540         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3541
3542         udelay(25000);
3543
3544         return 0;
3545 }
3546
3547 static int si_exit_ulp_state(struct radeon_device *rdev)
3548 {
3549         int i;
3550
3551         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3552
3553         udelay(7000);
3554
3555         for (i = 0; i < rdev->usec_timeout; i++) {
3556                 if (RREG32(SMC_RESP_0) == 1)
3557                         break;
3558                 udelay(1000);
3559         }
3560
3561         return 0;
3562 }
3563 #endif
3564
3565 static int si_notify_smc_display_change(struct radeon_device *rdev,
3566                                      bool has_display)
3567 {
3568         PPSMC_Msg msg = has_display ?
3569                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3570
3571         return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3572                 0 : -EINVAL;
3573 }
3574
3575 static void si_program_response_times(struct radeon_device *rdev)
3576 {
3577         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3578         u32 vddc_dly, acpi_dly, vbi_dly;
3579         u32 reference_clock;
3580
3581         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3582
3583         voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3584         backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3585
3586         if (voltage_response_time == 0)
3587                 voltage_response_time = 1000;
3588
3589         acpi_delay_time = 15000;
3590         vbi_time_out = 100000;
3591
3592         reference_clock = radeon_get_xclk(rdev);
3593
3594         vddc_dly = (voltage_response_time  * reference_clock) / 100;
3595         acpi_dly = (acpi_delay_time * reference_clock) / 100;
3596         vbi_dly  = (vbi_time_out * reference_clock) / 100;
3597
3598         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
3599         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
3600         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3601         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3602 }
3603
3604 static void si_program_ds_registers(struct radeon_device *rdev)
3605 {
3606         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3607         u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3608
3609         if (eg_pi->sclk_deep_sleep) {
3610                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3611                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3612                          ~AUTOSCALE_ON_SS_CLEAR);
3613         }
3614 }
3615
3616 static void si_program_display_gap(struct radeon_device *rdev)
3617 {
3618         u32 tmp, pipe;
3619         int i;
3620
3621         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3622         if (rdev->pm.dpm.new_active_crtc_count > 0)
3623                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3624         else
3625                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3626
3627         if (rdev->pm.dpm.new_active_crtc_count > 1)
3628                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3629         else
3630                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3631
3632         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3633
3634         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3635         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3636
3637         if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3638             (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3639                 /* find the first active crtc */
3640                 for (i = 0; i < rdev->num_crtc; i++) {
3641                         if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3642                                 break;
3643                 }
3644                 if (i == rdev->num_crtc)
3645                         pipe = 0;
3646                 else
3647                         pipe = i;
3648
3649                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3650                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3651                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3652         }
3653
3654         /* Setting this to false forces the performance state to low if the crtcs are disabled.
3655          * This can be a problem on PowerXpress systems or if you want to use the card
3656          * for offscreen rendering or compute if there are no crtcs enabled.
3657          */
3658         si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3659 }
3660
3661 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3662 {
3663         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3664
3665         if (enable) {
3666                 if (pi->sclk_ss)
3667                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3668         } else {
3669                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3670                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3671         }
3672 }
3673
3674 static void si_setup_bsp(struct radeon_device *rdev)
3675 {
3676         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3677         u32 xclk = radeon_get_xclk(rdev);
3678
3679         r600_calculate_u_and_p(pi->asi,
3680                                xclk,
3681                                16,
3682                                &pi->bsp,
3683                                &pi->bsu);
3684
3685         r600_calculate_u_and_p(pi->pasi,
3686                                xclk,
3687                                16,
3688                                &pi->pbsp,
3689                                &pi->pbsu);
3690
3691
3692         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3693         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3694
3695         WREG32(CG_BSP, pi->dsp);
3696 }
3697
3698 static void si_program_git(struct radeon_device *rdev)
3699 {
3700         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3701 }
3702
3703 static void si_program_tp(struct radeon_device *rdev)
3704 {
3705         int i;
3706         enum r600_td td = R600_TD_DFLT;
3707
3708         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3709                 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3710
3711         if (td == R600_TD_AUTO)
3712                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3713         else
3714                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3715
3716         if (td == R600_TD_UP)
3717                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3718
3719         if (td == R600_TD_DOWN)
3720                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3721 }
3722
3723 static void si_program_tpp(struct radeon_device *rdev)
3724 {
3725         WREG32(CG_TPC, R600_TPC_DFLT);
3726 }
3727
3728 static void si_program_sstp(struct radeon_device *rdev)
3729 {
3730         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3731 }
3732
3733 static void si_enable_display_gap(struct radeon_device *rdev)
3734 {
3735         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3736
3737         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3738         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3739                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3740
3741         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3742         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3743                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3744         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3745 }
3746
3747 static void si_program_vc(struct radeon_device *rdev)
3748 {
3749         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3750
3751         WREG32(CG_FTV, pi->vrc);
3752 }
3753
3754 static void si_clear_vc(struct radeon_device *rdev)
3755 {
3756         WREG32(CG_FTV, 0);
3757 }
3758
3759 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3760 {
3761         u8 mc_para_index;
3762
3763         if (memory_clock < 10000)
3764                 mc_para_index = 0;
3765         else if (memory_clock >= 80000)
3766                 mc_para_index = 0x0f;
3767         else
3768                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3769         return mc_para_index;
3770 }
3771
3772 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3773 {
3774         u8 mc_para_index;
3775
3776         if (strobe_mode) {
3777                 if (memory_clock < 12500)
3778                         mc_para_index = 0x00;
3779                 else if (memory_clock > 47500)
3780                         mc_para_index = 0x0f;
3781                 else
3782                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
3783         } else {
3784                 if (memory_clock < 65000)
3785                         mc_para_index = 0x00;
3786                 else if (memory_clock > 135000)
3787                         mc_para_index = 0x0f;
3788                 else
3789                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
3790         }
3791         return mc_para_index;
3792 }
3793
3794 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3795 {
3796         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3797         bool strobe_mode = false;
3798         u8 result = 0;
3799
3800         if (mclk <= pi->mclk_strobe_mode_threshold)
3801                 strobe_mode = true;
3802
3803         if (pi->mem_gddr5)
3804                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3805         else
3806                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3807
3808         if (strobe_mode)
3809                 result |= SISLANDS_SMC_STROBE_ENABLE;
3810
3811         return result;
3812 }
3813
3814 static int si_upload_firmware(struct radeon_device *rdev)
3815 {
3816         struct si_power_info *si_pi = si_get_pi(rdev);
3817         int ret;
3818
3819         si_reset_smc(rdev);
3820         si_stop_smc_clock(rdev);
3821
3822         ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3823
3824         return ret;
3825 }
3826
3827 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3828                                               const struct atom_voltage_table *table,
3829                                               const struct radeon_phase_shedding_limits_table *limits)
3830 {
3831         u32 data, num_bits, num_levels;
3832
3833         if ((table == NULL) || (limits == NULL))
3834                 return false;
3835
3836         data = table->mask_low;
3837
3838         num_bits = hweight32(data);
3839
3840         if (num_bits == 0)
3841                 return false;
3842
3843         num_levels = (1 << num_bits);
3844
3845         if (table->count != num_levels)
3846                 return false;
3847
3848         if (limits->count != (num_levels - 1))
3849                 return false;
3850
3851         return true;
3852 }
3853
3854 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3855                                               u32 max_voltage_steps,
3856                                               struct atom_voltage_table *voltage_table)
3857 {
3858         unsigned int i, diff;
3859
3860         if (voltage_table->count <= max_voltage_steps)
3861                 return;
3862
3863         diff = voltage_table->count - max_voltage_steps;
3864
3865         for (i= 0; i < max_voltage_steps; i++)
3866                 voltage_table->entries[i] = voltage_table->entries[i + diff];
3867
3868         voltage_table->count = max_voltage_steps;
3869 }
3870
3871 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3872                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3873                                      struct atom_voltage_table *voltage_table)
3874 {
3875         u32 i;
3876
3877         if (voltage_dependency_table == NULL)
3878                 return -EINVAL;
3879
3880         voltage_table->mask_low = 0;
3881         voltage_table->phase_delay = 0;
3882
3883         voltage_table->count = voltage_dependency_table->count;
3884         for (i = 0; i < voltage_table->count; i++) {
3885                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3886                 voltage_table->entries[i].smio_low = 0;
3887         }
3888
3889         return 0;
3890 }
3891
3892 static int si_construct_voltage_tables(struct radeon_device *rdev)
3893 {
3894         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3895         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3896         struct si_power_info *si_pi = si_get_pi(rdev);
3897         int ret;
3898
3899         if (pi->voltage_control) {
3900                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3901                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3902                 if (ret)
3903                         return ret;
3904
3905                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3906                         si_trim_voltage_table_to_fit_state_table(rdev,
3907                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3908                                                                  &eg_pi->vddc_voltage_table);
3909         } else if (si_pi->voltage_control_svi2) {
3910                 ret = si_get_svi2_voltage_table(rdev,
3911                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3912                                                 &eg_pi->vddc_voltage_table);
3913                 if (ret)
3914                         return ret;
3915         } else {
3916                 return -EINVAL;
3917         }
3918
3919         if (eg_pi->vddci_control) {
3920                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3921                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3922                 if (ret)
3923                         return ret;
3924
3925                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3926                         si_trim_voltage_table_to_fit_state_table(rdev,
3927                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3928                                                                  &eg_pi->vddci_voltage_table);
3929         }
3930         if (si_pi->vddci_control_svi2) {
3931                 ret = si_get_svi2_voltage_table(rdev,
3932                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3933                                                 &eg_pi->vddci_voltage_table);
3934                 if (ret)
3935                         return ret;
3936         }
3937
3938         if (pi->mvdd_control) {
3939                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3940                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3941
3942                 if (ret) {
3943                         pi->mvdd_control = false;
3944                         return ret;
3945                 }
3946
3947                 if (si_pi->mvdd_voltage_table.count == 0) {
3948                         pi->mvdd_control = false;
3949                         return -EINVAL;
3950                 }
3951
3952                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3953                         si_trim_voltage_table_to_fit_state_table(rdev,
3954                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3955                                                                  &si_pi->mvdd_voltage_table);
3956         }
3957
3958         if (si_pi->vddc_phase_shed_control) {
3959                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3960                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3961                 if (ret)
3962                         si_pi->vddc_phase_shed_control = false;
3963
3964                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
3965                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3966                         si_pi->vddc_phase_shed_control = false;
3967         }
3968
3969         return 0;
3970 }
3971
3972 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3973                                           const struct atom_voltage_table *voltage_table,
3974                                           SISLANDS_SMC_STATETABLE *table)
3975 {
3976         unsigned int i;
3977
3978         for (i = 0; i < voltage_table->count; i++)
3979                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3980 }
3981
3982 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3983                                           SISLANDS_SMC_STATETABLE *table)
3984 {
3985         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3986         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3987         struct si_power_info *si_pi = si_get_pi(rdev);
3988         u8 i;
3989
3990         if (si_pi->voltage_control_svi2) {
3991                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
3992                         si_pi->svc_gpio_id);
3993                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
3994                         si_pi->svd_gpio_id);
3995                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
3996                                            2);
3997         } else {
3998                 if (eg_pi->vddc_voltage_table.count) {
3999                         si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4000                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4001                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4002
4003                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4004                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4005                                         table->maxVDDCIndexInPPTable = i;
4006                                         break;
4007                                 }
4008                         }
4009                 }
4010
4011                 if (eg_pi->vddci_voltage_table.count) {
4012                         si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4013
4014                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4015                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4016                 }
4017
4018
4019                 if (si_pi->mvdd_voltage_table.count) {
4020                         si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4021
4022                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4023                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4024                 }
4025
4026                 if (si_pi->vddc_phase_shed_control) {
4027                         if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4028                                                               &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4029                                 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4030
4031                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4032                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4033
4034                                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4035                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4036                         } else {
4037                                 si_pi->vddc_phase_shed_control = false;
4038                         }
4039                 }
4040         }
4041
4042         return 0;
4043 }
4044
4045 static int si_populate_voltage_value(struct radeon_device *rdev,
4046                                      const struct atom_voltage_table *table,
4047                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4048 {
4049         unsigned int i;
4050
4051         for (i = 0; i < table->count; i++) {
4052                 if (value <= table->entries[i].value) {
4053                         voltage->index = (u8)i;
4054                         voltage->value = cpu_to_be16(table->entries[i].value);
4055                         break;
4056                 }
4057         }
4058
4059         if (i >= table->count)
4060                 return -EINVAL;
4061
4062         return 0;
4063 }
4064
4065 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4066                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4067 {
4068         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4069         struct si_power_info *si_pi = si_get_pi(rdev);
4070
4071         if (pi->mvdd_control) {
4072                 if (mclk <= pi->mvdd_split_frequency)
4073                         voltage->index = 0;
4074                 else
4075                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4076
4077                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4078         }
4079         return 0;
4080 }
4081
4082 static int si_get_std_voltage_value(struct radeon_device *rdev,
4083                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4084                                     u16 *std_voltage)
4085 {
4086         u16 v_index;
4087         bool voltage_found = false;
4088         *std_voltage = be16_to_cpu(voltage->value);
4089
4090         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4091                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4092                         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4093                                 return -EINVAL;
4094
4095                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4096                                 if (be16_to_cpu(voltage->value) ==
4097                                     (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4098                                         voltage_found = true;
4099                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4100                                                 *std_voltage =
4101                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4102                                         else
4103                                                 *std_voltage =
4104                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4105                                         break;
4106                                 }
4107                         }
4108
4109                         if (!voltage_found) {
4110                                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4111                                         if (be16_to_cpu(voltage->value) <=
4112                                             (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4113                                                 voltage_found = true;
4114                                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4115                                                         *std_voltage =
4116                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4117                                                 else
4118                                                         *std_voltage =
4119                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4120                                                 break;
4121                                         }
4122                                 }
4123                         }
4124                 } else {
4125                         if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4126                                 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4127                 }
4128         }
4129
4130         return 0;
4131 }
4132
4133 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4134                                          u16 value, u8 index,
4135                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4136 {
4137         voltage->index = index;
4138         voltage->value = cpu_to_be16(value);
4139
4140         return 0;
4141 }
4142
4143 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4144                                             const struct radeon_phase_shedding_limits_table *limits,
4145                                             u16 voltage, u32 sclk, u32 mclk,
4146                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4147 {
4148         unsigned int i;
4149
4150         for (i = 0; i < limits->count; i++) {
4151                 if ((voltage <= limits->entries[i].voltage) &&
4152                     (sclk <= limits->entries[i].sclk) &&
4153                     (mclk <= limits->entries[i].mclk))
4154                         break;
4155         }
4156
4157         smc_voltage->phase_settings = (u8)i;
4158
4159         return 0;
4160 }
4161
4162 static int si_init_arb_table_index(struct radeon_device *rdev)
4163 {
4164         struct si_power_info *si_pi = si_get_pi(rdev);
4165         u32 tmp;
4166         int ret;
4167
4168         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4169         if (ret)
4170                 return ret;
4171
4172         tmp &= 0x00FFFFFF;
4173         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4174
4175         return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);
4176 }
4177
4178 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4179 {
4180         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4181 }
4182
4183 static int si_reset_to_default(struct radeon_device *rdev)
4184 {
4185         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4186                 0 : -EINVAL;
4187 }
4188
4189 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4190 {
4191         struct si_power_info *si_pi = si_get_pi(rdev);
4192         u32 tmp;
4193         int ret;
4194
4195         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4196                                      &tmp, si_pi->sram_end);
4197         if (ret)
4198                 return ret;
4199
4200         tmp = (tmp >> 24) & 0xff;
4201
4202         if (tmp == MC_CG_ARB_FREQ_F0)
4203                 return 0;
4204
4205         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4206 }
4207
4208 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4209                                             u32 engine_clock)
4210 {
4211         u32 dram_rows;
4212         u32 dram_refresh_rate;
4213         u32 mc_arb_rfsh_rate;
4214         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4215
4216         if (tmp >= 4)
4217                 dram_rows = 16384;
4218         else
4219                 dram_rows = 1 << (tmp + 10);
4220
4221         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4222         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4223
4224         return mc_arb_rfsh_rate;
4225 }
4226
4227 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4228                                                 struct rv7xx_pl *pl,
4229                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4230 {
4231         u32 dram_timing;
4232         u32 dram_timing2;
4233         u32 burst_time;
4234
4235         arb_regs->mc_arb_rfsh_rate =
4236                 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4237
4238         radeon_atom_set_engine_dram_timings(rdev,
4239                                             pl->sclk,
4240                                             pl->mclk);
4241
4242         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4243         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4244         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4245
4246         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4247         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4248         arb_regs->mc_arb_burst_time = (u8)burst_time;
4249
4250         return 0;
4251 }
4252
4253 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4254                                                   struct radeon_ps *radeon_state,
4255                                                   unsigned int first_arb_set)
4256 {
4257         struct si_power_info *si_pi = si_get_pi(rdev);
4258         struct ni_ps *state = ni_get_ps(radeon_state);
4259         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4260         int i, ret = 0;
4261
4262         for (i = 0; i < state->performance_level_count; i++) {
4263                 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4264                 if (ret)
4265                         break;
4266                 ret = si_copy_bytes_to_smc(rdev,
4267                                            si_pi->arb_table_start +
4268                                            offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4269                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4270                                            (u8 *)&arb_regs,
4271                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4272                                            si_pi->sram_end);
4273                 if (ret)
4274                         break;
4275         }
4276
4277         return ret;
4278 }
4279
4280 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4281                                                struct radeon_ps *radeon_new_state)
4282 {
4283         return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4284                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4285 }
4286
4287 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4288                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4289 {
4290         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4291         struct si_power_info *si_pi = si_get_pi(rdev);
4292
4293         if (pi->mvdd_control)
4294                 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4295                                                  si_pi->mvdd_bootup_value, voltage);
4296
4297         return 0;
4298 }
4299
4300 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4301                                          struct radeon_ps *radeon_initial_state,
4302                                          SISLANDS_SMC_STATETABLE *table)
4303 {
4304         struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4305         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4306         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4307         struct si_power_info *si_pi = si_get_pi(rdev);
4308         u32 reg;
4309         int ret;
4310
4311         table->initialState.levels[0].mclk.vDLL_CNTL =
4312                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4313         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4314                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4315         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4316                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4317         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4318                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4319         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4320                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4321         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4322                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4323         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4324                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4325         table->initialState.levels[0].mclk.vMPLL_SS =
4326                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4327         table->initialState.levels[0].mclk.vMPLL_SS2 =
4328                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4329
4330         table->initialState.levels[0].mclk.mclk_value =
4331                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4332
4333         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4334                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4335         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4336                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4337         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4338                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4339         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4340                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4341         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4342                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4343         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4344                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4345
4346         table->initialState.levels[0].sclk.sclk_value =
4347                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4348
4349         table->initialState.levels[0].arbRefreshState =
4350                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4351
4352         table->initialState.levels[0].ACIndex = 0;
4353
4354         ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4355                                         initial_state->performance_levels[0].vddc,
4356                                         &table->initialState.levels[0].vddc);
4357
4358         if (!ret) {
4359                 u16 std_vddc;
4360
4361                 ret = si_get_std_voltage_value(rdev,
4362                                                &table->initialState.levels[0].vddc,
4363                                                &std_vddc);
4364                 if (!ret)
4365                         si_populate_std_voltage_value(rdev, std_vddc,
4366                                                       table->initialState.levels[0].vddc.index,
4367                                                       &table->initialState.levels[0].std_vddc);
4368         }
4369
4370         if (eg_pi->vddci_control)
4371                 si_populate_voltage_value(rdev,
4372                                           &eg_pi->vddci_voltage_table,
4373                                           initial_state->performance_levels[0].vddci,
4374                                           &table->initialState.levels[0].vddci);
4375
4376         if (si_pi->vddc_phase_shed_control)
4377                 si_populate_phase_shedding_value(rdev,
4378                                                  &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4379                                                  initial_state->performance_levels[0].vddc,
4380                                                  initial_state->performance_levels[0].sclk,
4381                                                  initial_state->performance_levels[0].mclk,
4382                                                  &table->initialState.levels[0].vddc);
4383
4384         si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4385
4386         reg = CG_R(0xffff) | CG_L(0);
4387         table->initialState.levels[0].aT = cpu_to_be32(reg);
4388
4389         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4390
4391         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4392
4393         if (pi->mem_gddr5) {
4394                 table->initialState.levels[0].strobeMode =
4395                         si_get_strobe_mode_settings(rdev,
4396                                                     initial_state->performance_levels[0].mclk);
4397
4398                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4399                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4400                 else
4401                         table->initialState.levels[0].mcFlags =  0;
4402         }
4403
4404         table->initialState.levelCount = 1;
4405
4406         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4407
4408         table->initialState.levels[0].dpm2.MaxPS = 0;
4409         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4410         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4411         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4412         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4413
4414         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4415         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4416
4417         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4418         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4419
4420         return 0;
4421 }
4422
4423 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4424                                       SISLANDS_SMC_STATETABLE *table)
4425 {
4426         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4427         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4428         struct si_power_info *si_pi = si_get_pi(rdev);
4429         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4430         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4431         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4432         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4433         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4434         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4435         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4436         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4437         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4438         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4439         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4440         u32 reg;
4441         int ret;
4442
4443         table->ACPIState = table->initialState;
4444
4445         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4446
4447         if (pi->acpi_vddc) {
4448                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4449                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4450                 if (!ret) {
4451                         u16 std_vddc;
4452
4453                         ret = si_get_std_voltage_value(rdev,
4454                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4455                         if (!ret)
4456                                 si_populate_std_voltage_value(rdev, std_vddc,
4457                                                               table->ACPIState.levels[0].vddc.index,
4458                                                               &table->ACPIState.levels[0].std_vddc);
4459                 }
4460                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4461
4462                 if (si_pi->vddc_phase_shed_control) {
4463                         si_populate_phase_shedding_value(rdev,
4464                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4465                                                          pi->acpi_vddc,
4466                                                          0,
4467                                                          0,
4468                                                          &table->ACPIState.levels[0].vddc);
4469                 }
4470         } else {
4471                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4472                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4473                 if (!ret) {
4474                         u16 std_vddc;
4475
4476                         ret = si_get_std_voltage_value(rdev,
4477                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4478
4479                         if (!ret)
4480                                 si_populate_std_voltage_value(rdev, std_vddc,
4481                                                               table->ACPIState.levels[0].vddc.index,
4482                                                               &table->ACPIState.levels[0].std_vddc);
4483                 }
4484                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4485                                                                                     si_pi->sys_pcie_mask,
4486                                                                                     si_pi->boot_pcie_gen,
4487                                                                                     RADEON_PCIE_GEN1);
4488
4489                 if (si_pi->vddc_phase_shed_control)
4490                         si_populate_phase_shedding_value(rdev,
4491                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4492                                                          pi->min_vddc_in_table,
4493                                                          0,
4494                                                          0,
4495                                                          &table->ACPIState.levels[0].vddc);
4496         }
4497
4498         if (pi->acpi_vddc) {
4499                 if (eg_pi->acpi_vddci)
4500                         si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4501                                                   eg_pi->acpi_vddci,
4502                                                   &table->ACPIState.levels[0].vddci);
4503         }
4504
4505         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4506         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4507
4508         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4509
4510         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4511         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4512
4513         table->ACPIState.levels[0].mclk.vDLL_CNTL =
4514                 cpu_to_be32(dll_cntl);
4515         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4516                 cpu_to_be32(mclk_pwrmgt_cntl);
4517         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4518                 cpu_to_be32(mpll_ad_func_cntl);
4519         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4520                 cpu_to_be32(mpll_dq_func_cntl);
4521         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4522                 cpu_to_be32(mpll_func_cntl);
4523         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4524                 cpu_to_be32(mpll_func_cntl_1);
4525         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4526                 cpu_to_be32(mpll_func_cntl_2);
4527         table->ACPIState.levels[0].mclk.vMPLL_SS =
4528                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4529         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4530                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4531
4532         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4533                 cpu_to_be32(spll_func_cntl);
4534         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4535                 cpu_to_be32(spll_func_cntl_2);
4536         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4537                 cpu_to_be32(spll_func_cntl_3);
4538         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4539                 cpu_to_be32(spll_func_cntl_4);
4540
4541         table->ACPIState.levels[0].mclk.mclk_value = 0;
4542         table->ACPIState.levels[0].sclk.sclk_value = 0;
4543
4544         si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4545
4546         if (eg_pi->dynamic_ac_timing)
4547                 table->ACPIState.levels[0].ACIndex = 0;
4548
4549         table->ACPIState.levels[0].dpm2.MaxPS = 0;
4550         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4551         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4552         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4553         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4554
4555         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4556         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4557
4558         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4559         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4560
4561         return 0;
4562 }
4563
4564 static int si_populate_ulv_state(struct radeon_device *rdev,
4565                                  SISLANDS_SMC_SWSTATE *state)
4566 {
4567         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4568         struct si_power_info *si_pi = si_get_pi(rdev);
4569         struct si_ulv_param *ulv = &si_pi->ulv;
4570         u32 sclk_in_sr = 1350; /* ??? */
4571         int ret;
4572
4573         ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4574                                             &state->levels[0]);
4575         if (!ret) {
4576                 if (eg_pi->sclk_deep_sleep) {
4577                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4578                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4579                         else
4580                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4581                 }
4582                 if (ulv->one_pcie_lane_in_ulv)
4583                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4584                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4585                 state->levels[0].ACIndex = 1;
4586                 state->levels[0].std_vddc = state->levels[0].vddc;
4587                 state->levelCount = 1;
4588
4589                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4590         }
4591
4592         return ret;
4593 }
4594
4595 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4596 {
4597         struct si_power_info *si_pi = si_get_pi(rdev);
4598         struct si_ulv_param *ulv = &si_pi->ulv;
4599         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4600         int ret;
4601
4602         ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4603                                                    &arb_regs);
4604         if (ret)
4605                 return ret;
4606
4607         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4608                                    ulv->volt_change_delay);
4609
4610         ret = si_copy_bytes_to_smc(rdev,
4611                                    si_pi->arb_table_start +
4612                                    offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4613                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4614                                    (u8 *)&arb_regs,
4615                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4616                                    si_pi->sram_end);
4617
4618         return ret;
4619 }
4620
4621 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4622 {
4623         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4624
4625         pi->mvdd_split_frequency = 30000;
4626 }
4627
4628 static int si_init_smc_table(struct radeon_device *rdev)
4629 {
4630         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4631         struct si_power_info *si_pi = si_get_pi(rdev);
4632         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4633         const struct si_ulv_param *ulv = &si_pi->ulv;
4634         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
4635         int ret;
4636         u32 lane_width;
4637         u32 vr_hot_gpio;
4638
4639         si_populate_smc_voltage_tables(rdev, table);
4640
4641         switch (rdev->pm.int_thermal_type) {
4642         case THERMAL_TYPE_SI:
4643         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4644                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4645                 break;
4646         case THERMAL_TYPE_NONE:
4647                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4648                 break;
4649         default:
4650                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4651                 break;
4652         }
4653
4654         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4655                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4656
4657         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4658                 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4659                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4660         }
4661
4662         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4663                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4664
4665         if (pi->mem_gddr5)
4666                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4667
4668         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4669                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4670
4671         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4672                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4673                 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4674                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4675                                            vr_hot_gpio);
4676         }
4677
4678         ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4679         if (ret)
4680                 return ret;
4681
4682         ret = si_populate_smc_acpi_state(rdev, table);
4683         if (ret)
4684                 return ret;
4685
4686         table->driverState = table->initialState;
4687
4688         ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4689                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
4690         if (ret)
4691                 return ret;
4692
4693         if (ulv->supported && ulv->pl.vddc) {
4694                 ret = si_populate_ulv_state(rdev, &table->ULVState);
4695                 if (ret)
4696                         return ret;
4697
4698                 ret = si_program_ulv_memory_timing_parameters(rdev);
4699                 if (ret)
4700                         return ret;
4701
4702                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4703                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4704
4705                 lane_width = radeon_get_pcie_lanes(rdev);
4706                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4707         } else {
4708                 table->ULVState = table->initialState;
4709         }
4710
4711         return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4712                                     (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4713                                     si_pi->sram_end);
4714 }
4715
4716 static int si_calculate_sclk_params(struct radeon_device *rdev,
4717                                     u32 engine_clock,
4718                                     SISLANDS_SMC_SCLK_VALUE *sclk)
4719 {
4720         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4721         struct si_power_info *si_pi = si_get_pi(rdev);
4722         struct atom_clock_dividers dividers;
4723         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4724         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4725         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4726         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4727         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4728         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4729         u64 tmp;
4730         u32 reference_clock = rdev->clock.spll.reference_freq;
4731         u32 reference_divider;
4732         u32 fbdiv;
4733         int ret;
4734
4735         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4736                                              engine_clock, false, &dividers);
4737         if (ret)
4738                 return ret;
4739
4740         reference_divider = 1 + dividers.ref_div;
4741
4742         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4743         do_div(tmp, reference_clock);
4744         fbdiv = (u32) tmp;
4745
4746         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4747         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4748         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4749
4750         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4751         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4752
4753         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4754         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4755         spll_func_cntl_3 |= SPLL_DITHEN;
4756
4757         if (pi->sclk_ss) {
4758                 struct radeon_atom_ss ss;
4759                 u32 vco_freq = engine_clock * dividers.post_div;
4760
4761                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4762                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4763                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4764                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4765
4766                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
4767                         cg_spll_spread_spectrum |= CLK_S(clk_s);
4768                         cg_spll_spread_spectrum |= SSEN;
4769
4770                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4771                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4772                 }
4773         }
4774
4775         sclk->sclk_value = engine_clock;
4776         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4777         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4778         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4779         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4780         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4781         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4782
4783         return 0;
4784 }
4785
4786 static int si_populate_sclk_value(struct radeon_device *rdev,
4787                                   u32 engine_clock,
4788                                   SISLANDS_SMC_SCLK_VALUE *sclk)
4789 {
4790         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4791         int ret;
4792
4793         ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4794         if (!ret) {
4795                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4796                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4797                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4798                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4799                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4800                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4801                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4802         }
4803
4804         return ret;
4805 }
4806
4807 static int si_populate_mclk_value(struct radeon_device *rdev,
4808                                   u32 engine_clock,
4809                                   u32 memory_clock,
4810                                   SISLANDS_SMC_MCLK_VALUE *mclk,
4811                                   bool strobe_mode,
4812                                   bool dll_state_on)
4813 {
4814         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4815         struct si_power_info *si_pi = si_get_pi(rdev);
4816         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
4817         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4818         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4819         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4820         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4821         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4822         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4823         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4824         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4825         struct atom_mpll_param mpll_param;
4826         int ret;
4827
4828         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4829         if (ret)
4830                 return ret;
4831
4832         mpll_func_cntl &= ~BWCTRL_MASK;
4833         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4834
4835         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4836         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4837                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4838
4839         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4840         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4841
4842         if (pi->mem_gddr5) {
4843                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4844                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4845                         YCLK_POST_DIV(mpll_param.post_div);
4846         }
4847
4848         if (pi->mclk_ss) {
4849                 struct radeon_atom_ss ss;
4850                 u32 freq_nom;
4851                 u32 tmp;
4852                 u32 reference_clock = rdev->clock.mpll.reference_freq;
4853
4854                 if (pi->mem_gddr5)
4855                         freq_nom = memory_clock * 4;
4856                 else
4857                         freq_nom = memory_clock * 2;
4858
4859                 tmp = freq_nom / reference_clock;
4860                 tmp = tmp * tmp;
4861                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4862                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4863                         u32 clks = reference_clock * 5 / ss.rate;
4864                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4865
4866                         mpll_ss1 &= ~CLKV_MASK;
4867                         mpll_ss1 |= CLKV(clkv);
4868
4869                         mpll_ss2 &= ~CLKS_MASK;
4870                         mpll_ss2 |= CLKS(clks);
4871                 }
4872         }
4873
4874         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4875         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4876
4877         if (dll_state_on)
4878                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4879         else
4880                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4881
4882         mclk->mclk_value = cpu_to_be32(memory_clock);
4883         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4884         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4885         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4886         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4887         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4888         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4889         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4890         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4891         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4892
4893         return 0;
4894 }
4895
4896 static void si_populate_smc_sp(struct radeon_device *rdev,
4897                                struct radeon_ps *radeon_state,
4898                                SISLANDS_SMC_SWSTATE *smc_state)
4899 {
4900         struct ni_ps *ps = ni_get_ps(radeon_state);
4901         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4902         int i;
4903
4904         for (i = 0; i < ps->performance_level_count - 1; i++)
4905                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4906
4907         smc_state->levels[ps->performance_level_count - 1].bSP =
4908                 cpu_to_be32(pi->psp);
4909 }
4910
4911 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4912                                          struct rv7xx_pl *pl,
4913                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4914 {
4915         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4916         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4917         struct si_power_info *si_pi = si_get_pi(rdev);
4918         int ret;
4919         bool dll_state_on;
4920         u16 std_vddc;
4921         bool gmc_pg = false;
4922
4923         if (eg_pi->pcie_performance_request &&
4924             (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4925                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4926         else
4927                 level->gen2PCIE = (u8)pl->pcie_gen;
4928
4929         ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4930         if (ret)
4931                 return ret;
4932
4933         level->mcFlags =  0;
4934
4935         if (pi->mclk_stutter_mode_threshold &&
4936             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4937             !eg_pi->uvd_enabled &&
4938             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4939             (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4940                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4941
4942                 if (gmc_pg)
4943                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4944         }
4945
4946         if (pi->mem_gddr5) {
4947                 if (pl->mclk > pi->mclk_edc_enable_threshold)
4948                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4949
4950                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4951                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4952
4953                 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4954
4955                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4956                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4957                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4958                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4959                         else
4960                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4961                 } else {
4962                         dll_state_on = false;
4963                 }
4964         } else {
4965                 level->strobeMode = si_get_strobe_mode_settings(rdev,
4966                                                                 pl->mclk);
4967
4968                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4969         }
4970
4971         ret = si_populate_mclk_value(rdev,
4972                                      pl->sclk,
4973                                      pl->mclk,
4974                                      &level->mclk,
4975                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4976         if (ret)
4977                 return ret;
4978
4979         ret = si_populate_voltage_value(rdev,
4980                                         &eg_pi->vddc_voltage_table,
4981                                         pl->vddc, &level->vddc);
4982         if (ret)
4983                 return ret;
4984
4985
4986         ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4987         if (ret)
4988                 return ret;
4989
4990         ret = si_populate_std_voltage_value(rdev, std_vddc,
4991                                             level->vddc.index, &level->std_vddc);
4992         if (ret)
4993                 return ret;
4994
4995         if (eg_pi->vddci_control) {
4996                 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4997                                                 pl->vddci, &level->vddci);
4998                 if (ret)
4999                         return ret;
5000         }
5001
5002         if (si_pi->vddc_phase_shed_control) {
5003                 ret = si_populate_phase_shedding_value(rdev,
5004                                                        &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5005                                                        pl->vddc,
5006                                                        pl->sclk,
5007                                                        pl->mclk,
5008                                                        &level->vddc);
5009                 if (ret)
5010                         return ret;
5011         }
5012
5013         level->MaxPoweredUpCU = si_pi->max_cu;
5014
5015         ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5016
5017         return ret;
5018 }
5019
5020 static int si_populate_smc_t(struct radeon_device *rdev,
5021                              struct radeon_ps *radeon_state,
5022                              SISLANDS_SMC_SWSTATE *smc_state)
5023 {
5024         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5025         struct ni_ps *state = ni_get_ps(radeon_state);
5026         u32 a_t;
5027         u32 t_l, t_h;
5028         u32 high_bsp;
5029         int i, ret;
5030
5031         if (state->performance_level_count >= 9)
5032                 return -EINVAL;
5033
5034         if (state->performance_level_count < 2) {
5035                 a_t = CG_R(0xffff) | CG_L(0);
5036                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5037                 return 0;
5038         }
5039
5040         smc_state->levels[0].aT = cpu_to_be32(0);
5041
5042         for (i = 0; i <= state->performance_level_count - 2; i++) {
5043                 ret = r600_calculate_at(
5044                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5045                         100 * R600_AH_DFLT,
5046                         state->performance_levels[i + 1].sclk,
5047                         state->performance_levels[i].sclk,
5048                         &t_l,
5049                         &t_h);
5050
5051                 if (ret) {
5052                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5053                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5054                 }
5055
5056                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5057                 a_t |= CG_R(t_l * pi->bsp / 20000);
5058                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5059
5060                 high_bsp = (i == state->performance_level_count - 2) ?
5061                         pi->pbsp : pi->bsp;
5062                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5063                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5064         }
5065
5066         return 0;
5067 }
5068
5069 static int si_disable_ulv(struct radeon_device *rdev)
5070 {
5071         struct si_power_info *si_pi = si_get_pi(rdev);
5072         struct si_ulv_param *ulv = &si_pi->ulv;
5073
5074         if (ulv->supported)
5075                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5076                         0 : -EINVAL;
5077
5078         return 0;
5079 }
5080
5081 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5082                                        struct radeon_ps *radeon_state)
5083 {
5084         const struct si_power_info *si_pi = si_get_pi(rdev);
5085         const struct si_ulv_param *ulv = &si_pi->ulv;
5086         const struct ni_ps *state = ni_get_ps(radeon_state);
5087         int i;
5088
5089         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5090                 return false;
5091
5092         /* XXX validate against display requirements! */
5093
5094         for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5095                 if (rdev->clock.current_dispclk <=
5096                     rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5097                         if (ulv->pl.vddc <
5098                             rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5099                                 return false;
5100                 }
5101         }
5102
5103         if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5104                 return false;
5105
5106         return true;
5107 }
5108
5109 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5110                                                        struct radeon_ps *radeon_new_state)
5111 {
5112         const struct si_power_info *si_pi = si_get_pi(rdev);
5113         const struct si_ulv_param *ulv = &si_pi->ulv;
5114
5115         if (ulv->supported) {
5116                 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5117                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5118                                 0 : -EINVAL;
5119         }
5120         return 0;
5121 }
5122
5123 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5124                                          struct radeon_ps *radeon_state,
5125                                          SISLANDS_SMC_SWSTATE *smc_state)
5126 {
5127         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5128         struct ni_power_info *ni_pi = ni_get_pi(rdev);
5129         struct si_power_info *si_pi = si_get_pi(rdev);
5130         struct ni_ps *state = ni_get_ps(radeon_state);
5131         int i, ret;
5132         u32 threshold;
5133         u32 sclk_in_sr = 1350; /* ??? */
5134
5135         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5136                 return -EINVAL;
5137
5138         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5139
5140         if (radeon_state->vclk && radeon_state->dclk) {
5141                 eg_pi->uvd_enabled = true;
5142                 if (eg_pi->smu_uvd_hs)
5143                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5144         } else {
5145                 eg_pi->uvd_enabled = false;
5146         }
5147
5148         if (state->dc_compatible)
5149                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5150
5151         smc_state->levelCount = 0;
5152         for (i = 0; i < state->performance_level_count; i++) {
5153                 if (eg_pi->sclk_deep_sleep) {
5154                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5155                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5156                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5157                                 else
5158                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5159                         }
5160                 }
5161
5162                 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5163                                                     &smc_state->levels[i]);
5164                 smc_state->levels[i].arbRefreshState =
5165                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5166
5167                 if (ret)
5168                         return ret;
5169
5170                 if (ni_pi->enable_power_containment)
5171                         smc_state->levels[i].displayWatermark =
5172                                 (state->performance_levels[i].sclk < threshold) ?
5173                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5174                 else
5175                         smc_state->levels[i].displayWatermark = (i < 2) ?
5176                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5177
5178                 if (eg_pi->dynamic_ac_timing)
5179                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5180                 else
5181                         smc_state->levels[i].ACIndex = 0;
5182
5183                 smc_state->levelCount++;
5184         }
5185
5186         si_write_smc_soft_register(rdev,
5187                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5188                                    threshold / 512);
5189
5190         si_populate_smc_sp(rdev, radeon_state, smc_state);
5191
5192         ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5193         if (ret)
5194                 ni_pi->enable_power_containment = false;
5195
5196         ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5197         if (ret)
5198                 ni_pi->enable_sq_ramping = false;
5199
5200         return si_populate_smc_t(rdev, radeon_state, smc_state);
5201 }
5202
5203 static int si_upload_sw_state(struct radeon_device *rdev,
5204                               struct radeon_ps *radeon_new_state)
5205 {
5206         struct si_power_info *si_pi = si_get_pi(rdev);
5207         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5208         int ret;
5209         u32 address = si_pi->state_table_start +
5210                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5211         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5212                 ((new_state->performance_level_count - 1) *
5213                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5214         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5215
5216         memset(smc_state, 0, state_size);
5217
5218         ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5219         if (ret)
5220                 return ret;
5221
5222         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5223                                    state_size, si_pi->sram_end);
5224
5225         return ret;
5226 }
5227
5228 static int si_upload_ulv_state(struct radeon_device *rdev)
5229 {
5230         struct si_power_info *si_pi = si_get_pi(rdev);
5231         struct si_ulv_param *ulv = &si_pi->ulv;
5232         int ret = 0;
5233
5234         if (ulv->supported && ulv->pl.vddc) {
5235                 u32 address = si_pi->state_table_start +
5236                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5237                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5238                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5239
5240                 memset(smc_state, 0, state_size);
5241
5242                 ret = si_populate_ulv_state(rdev, smc_state);
5243                 if (!ret)
5244                         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5245                                                    state_size, si_pi->sram_end);
5246         }
5247
5248         return ret;
5249 }
5250
5251 static int si_upload_smc_data(struct radeon_device *rdev)
5252 {
5253         struct radeon_crtc *radeon_crtc = NULL;
5254         int i;
5255
5256         if (rdev->pm.dpm.new_active_crtc_count == 0)
5257                 return 0;
5258
5259         for (i = 0; i < rdev->num_crtc; i++) {
5260                 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5261                         radeon_crtc = rdev->mode_info.crtcs[i];
5262                         break;
5263                 }
5264         }
5265
5266         if (radeon_crtc == NULL)
5267                 return 0;
5268
5269         if (radeon_crtc->line_time <= 0)
5270                 return 0;
5271
5272         if (si_write_smc_soft_register(rdev,
5273                                        SI_SMC_SOFT_REGISTER_crtc_index,
5274                                        radeon_crtc->crtc_id) != PPSMC_Result_OK)
5275                 return 0;
5276
5277         if (si_write_smc_soft_register(rdev,
5278                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5279                                        radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5280                 return 0;
5281
5282         if (si_write_smc_soft_register(rdev,
5283                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5284                                        radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5285                 return 0;
5286
5287         return 0;
5288 }
5289
5290 static int si_set_mc_special_registers(struct radeon_device *rdev,
5291                                        struct si_mc_reg_table *table)
5292 {
5293         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5294         u8 i, j, k;
5295         u32 temp_reg;
5296
5297         for (i = 0, j = table->last; i < table->last; i++) {
5298                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5299                         return -EINVAL;
5300                 switch (table->mc_reg_address[i].s1 << 2) {
5301                 case MC_SEQ_MISC1:
5302                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5303                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5304                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5305                         for (k = 0; k < table->num_entries; k++)
5306                                 table->mc_reg_table_entry[k].mc_data[j] =
5307                                         ((temp_reg & 0xffff0000)) |
5308                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5309                         j++;
5310                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5311                                 return -EINVAL;
5312
5313                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5314                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5315                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5316                         for (k = 0; k < table->num_entries; k++) {
5317                                 table->mc_reg_table_entry[k].mc_data[j] =
5318                                         (temp_reg & 0xffff0000) |
5319                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5320                                 if (!pi->mem_gddr5)
5321                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5322                         }
5323                         j++;
5324                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5325                                 return -EINVAL;
5326
5327                         if (!pi->mem_gddr5) {
5328                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5329                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5330                                 for (k = 0; k < table->num_entries; k++)
5331                                         table->mc_reg_table_entry[k].mc_data[j] =
5332                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5333                                 j++;
5334                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5335                                         return -EINVAL;
5336                         }
5337                         break;
5338                 case MC_SEQ_RESERVE_M:
5339                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5340                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5341                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5342                         for(k = 0; k < table->num_entries; k++)
5343                                 table->mc_reg_table_entry[k].mc_data[j] =
5344                                         (temp_reg & 0xffff0000) |
5345                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5346                         j++;
5347                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5348                                 return -EINVAL;
5349                         break;
5350                 default:
5351                         break;
5352                 }
5353         }
5354
5355         table->last = j;
5356
5357         return 0;
5358 }
5359
5360 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5361 {
5362         bool result = true;
5363
5364         switch (in_reg) {
5365         case  MC_SEQ_RAS_TIMING >> 2:
5366                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5367                 break;
5368         case MC_SEQ_CAS_TIMING >> 2:
5369                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5370                 break;
5371         case MC_SEQ_MISC_TIMING >> 2:
5372                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5373                 break;
5374         case MC_SEQ_MISC_TIMING2 >> 2:
5375                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5376                 break;
5377         case MC_SEQ_RD_CTL_D0 >> 2:
5378                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5379                 break;
5380         case MC_SEQ_RD_CTL_D1 >> 2:
5381                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5382                 break;
5383         case MC_SEQ_WR_CTL_D0 >> 2:
5384                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5385                 break;
5386         case MC_SEQ_WR_CTL_D1 >> 2:
5387                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5388                 break;
5389         case MC_PMG_CMD_EMRS >> 2:
5390                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5391                 break;
5392         case MC_PMG_CMD_MRS >> 2:
5393                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5394                 break;
5395         case MC_PMG_CMD_MRS1 >> 2:
5396                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5397                 break;
5398         case MC_SEQ_PMG_TIMING >> 2:
5399                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5400                 break;
5401         case MC_PMG_CMD_MRS2 >> 2:
5402                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5403                 break;
5404         case MC_SEQ_WR_CTL_2 >> 2:
5405                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5406                 break;
5407         default:
5408                 result = false;
5409                 break;
5410         }
5411
5412         return result;
5413 }
5414
5415 static void si_set_valid_flag(struct si_mc_reg_table *table)
5416 {
5417         u8 i, j;
5418
5419         for (i = 0; i < table->last; i++) {
5420                 for (j = 1; j < table->num_entries; j++) {
5421                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5422                                 table->valid_flag |= 1 << i;
5423                                 break;
5424                         }
5425                 }
5426         }
5427 }
5428
5429 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5430 {
5431         u32 i;
5432         u16 address;
5433
5434         for (i = 0; i < table->last; i++)
5435                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5436                         address : table->mc_reg_address[i].s1;
5437
5438 }
5439
5440 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5441                                       struct si_mc_reg_table *si_table)
5442 {
5443         u8 i, j;
5444
5445         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5446                 return -EINVAL;
5447         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5448                 return -EINVAL;
5449
5450         for (i = 0; i < table->last; i++)
5451                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5452         si_table->last = table->last;
5453
5454         for (i = 0; i < table->num_entries; i++) {
5455                 si_table->mc_reg_table_entry[i].mclk_max =
5456                         table->mc_reg_table_entry[i].mclk_max;
5457                 for (j = 0; j < table->last; j++) {
5458                         si_table->mc_reg_table_entry[i].mc_data[j] =
5459                                 table->mc_reg_table_entry[i].mc_data[j];
5460                 }
5461         }
5462         si_table->num_entries = table->num_entries;
5463
5464         return 0;
5465 }
5466
5467 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5468 {
5469         struct si_power_info *si_pi = si_get_pi(rdev);
5470         struct atom_mc_reg_table *table;
5471         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5472         u8 module_index = rv770_get_memory_module_index(rdev);
5473         int ret;
5474
5475         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5476         if (!table)
5477                 return -ENOMEM;
5478
5479         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5480         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5481         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5482         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5483         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5484         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5485         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5486         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5487         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5488         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5489         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5490         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5491         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5492         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5493
5494         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5495         if (ret)
5496                 goto init_mc_done;
5497
5498         ret = si_copy_vbios_mc_reg_table(table, si_table);
5499         if (ret)
5500                 goto init_mc_done;
5501
5502         si_set_s0_mc_reg_index(si_table);
5503
5504         ret = si_set_mc_special_registers(rdev, si_table);
5505         if (ret)
5506                 goto init_mc_done;
5507
5508         si_set_valid_flag(si_table);
5509
5510 init_mc_done:
5511         kfree(table);
5512
5513         return ret;
5514
5515 }
5516
5517 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5518                                          SMC_SIslands_MCRegisters *mc_reg_table)
5519 {
5520         struct si_power_info *si_pi = si_get_pi(rdev);
5521         u32 i, j;
5522
5523         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5524                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5525                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5526                                 break;
5527                         mc_reg_table->address[i].s0 =
5528                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5529                         mc_reg_table->address[i].s1 =
5530                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5531                         i++;
5532                 }
5533         }
5534         mc_reg_table->last = (u8)i;
5535 }
5536
5537 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5538                                     SMC_SIslands_MCRegisterSet *data,
5539                                     u32 num_entries, u32 valid_flag)
5540 {
5541         u32 i, j;
5542
5543         for(i = 0, j = 0; j < num_entries; j++) {
5544                 if (valid_flag & (1 << j)) {
5545                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
5546                         i++;
5547                 }
5548         }
5549 }
5550
5551 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5552                                                  struct rv7xx_pl *pl,
5553                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5554 {
5555         struct si_power_info *si_pi = si_get_pi(rdev);
5556         u32 i = 0;
5557
5558         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5559                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5560                         break;
5561         }
5562
5563         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5564                 --i;
5565
5566         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5567                                 mc_reg_table_data, si_pi->mc_reg_table.last,
5568                                 si_pi->mc_reg_table.valid_flag);
5569 }
5570
5571 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5572                                            struct radeon_ps *radeon_state,
5573                                            SMC_SIslands_MCRegisters *mc_reg_table)
5574 {
5575         struct ni_ps *state = ni_get_ps(radeon_state);
5576         int i;
5577
5578         for (i = 0; i < state->performance_level_count; i++) {
5579                 si_convert_mc_reg_table_entry_to_smc(rdev,
5580                                                      &state->performance_levels[i],
5581                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5582         }
5583 }
5584
5585 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5586                                     struct radeon_ps *radeon_boot_state)
5587 {
5588         struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5589         struct si_power_info *si_pi = si_get_pi(rdev);
5590         struct si_ulv_param *ulv = &si_pi->ulv;
5591         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5592
5593         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5594
5595         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5596
5597         si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5598
5599         si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5600                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5601
5602         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5603                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5604                                 si_pi->mc_reg_table.last,
5605                                 si_pi->mc_reg_table.valid_flag);
5606
5607         if (ulv->supported && ulv->pl.vddc != 0)
5608                 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5609                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5610         else
5611                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5612                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5613                                         si_pi->mc_reg_table.last,
5614                                         si_pi->mc_reg_table.valid_flag);
5615
5616         si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5617
5618         return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5619                                     (u8 *)smc_mc_reg_table,
5620                                     sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5621 }
5622
5623 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5624                                   struct radeon_ps *radeon_new_state)
5625 {
5626         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5627         struct si_power_info *si_pi = si_get_pi(rdev);
5628         u32 address = si_pi->mc_reg_table_start +
5629                 offsetof(SMC_SIslands_MCRegisters,
5630                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5631         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5632
5633         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5634
5635         si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5636
5637
5638         return si_copy_bytes_to_smc(rdev, address,
5639                                     (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5640                                     sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5641                                     si_pi->sram_end);
5642
5643 }
5644
5645 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5646 {
5647         if (enable)
5648                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5649         else
5650                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5651 }
5652
5653 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5654                                                       struct radeon_ps *radeon_state)
5655 {
5656         struct ni_ps *state = ni_get_ps(radeon_state);
5657         int i;
5658         u16 pcie_speed, max_speed = 0;
5659
5660         for (i = 0; i < state->performance_level_count; i++) {
5661                 pcie_speed = state->performance_levels[i].pcie_gen;
5662                 if (max_speed < pcie_speed)
5663                         max_speed = pcie_speed;
5664         }
5665         return max_speed;
5666 }
5667
5668 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5669 {
5670         u32 speed_cntl;
5671
5672         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5673         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5674
5675         return (u16)speed_cntl;
5676 }
5677
5678 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5679                                                              struct radeon_ps *radeon_new_state,
5680                                                              struct radeon_ps *radeon_current_state)
5681 {
5682         struct si_power_info *si_pi = si_get_pi(rdev);
5683         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5684         enum radeon_pcie_gen current_link_speed;
5685
5686         if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5687                 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5688         else
5689                 current_link_speed = si_pi->force_pcie_gen;
5690
5691         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5692         si_pi->pspp_notify_required = false;
5693         if (target_link_speed > current_link_speed) {
5694                 switch (target_link_speed) {
5695 #if defined(CONFIG_ACPI)
5696                 case RADEON_PCIE_GEN3:
5697                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5698                                 break;
5699                         si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5700                         if (current_link_speed == RADEON_PCIE_GEN2)
5701                                 break;
5702                 case RADEON_PCIE_GEN2:
5703                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5704                                 break;
5705 #endif
5706                 default:
5707                         si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5708                         break;
5709                 }
5710         } else {
5711                 if (target_link_speed < current_link_speed)
5712                         si_pi->pspp_notify_required = true;
5713         }
5714 }
5715
5716 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5717                                                            struct radeon_ps *radeon_new_state,
5718                                                            struct radeon_ps *radeon_current_state)
5719 {
5720         struct si_power_info *si_pi = si_get_pi(rdev);
5721         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5722         u8 request;
5723
5724         if (si_pi->pspp_notify_required) {
5725                 if (target_link_speed == RADEON_PCIE_GEN3)
5726                         request = PCIE_PERF_REQ_PECI_GEN3;
5727                 else if (target_link_speed == RADEON_PCIE_GEN2)
5728                         request = PCIE_PERF_REQ_PECI_GEN2;
5729                 else
5730                         request = PCIE_PERF_REQ_PECI_GEN1;
5731
5732                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5733                     (si_get_current_pcie_speed(rdev) > 0))
5734                         return;
5735
5736 #if defined(CONFIG_ACPI)
5737                 radeon_acpi_pcie_performance_request(rdev, request, false);
5738 #endif
5739         }
5740 }
5741
5742 #if 0
5743 static int si_ds_request(struct radeon_device *rdev,
5744                          bool ds_status_on, u32 count_write)
5745 {
5746         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5747
5748         if (eg_pi->sclk_deep_sleep) {
5749                 if (ds_status_on)
5750                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5751                                 PPSMC_Result_OK) ?
5752                                 0 : -EINVAL;
5753                 else
5754                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5755                                 PPSMC_Result_OK) ? 0 : -EINVAL;
5756         }
5757         return 0;
5758 }
5759 #endif
5760
5761 static void si_set_max_cu_value(struct radeon_device *rdev)
5762 {
5763         struct si_power_info *si_pi = si_get_pi(rdev);
5764
5765         if (rdev->family == CHIP_VERDE) {
5766                 switch (rdev->pdev->device) {
5767                 case 0x6820:
5768                 case 0x6825:
5769                 case 0x6821:
5770                 case 0x6823:
5771                 case 0x6827:
5772                         si_pi->max_cu = 10;
5773                         break;
5774                 case 0x682D:
5775                 case 0x6824:
5776                 case 0x682F:
5777                 case 0x6826:
5778                         si_pi->max_cu = 8;
5779                         break;
5780                 case 0x6828:
5781                 case 0x6830:
5782                 case 0x6831:
5783                 case 0x6838:
5784                 case 0x6839:
5785                 case 0x683D:
5786                         si_pi->max_cu = 10;
5787                         break;
5788                 case 0x683B:
5789                 case 0x683F:
5790                 case 0x6829:
5791                         si_pi->max_cu = 8;
5792                         break;
5793                 default:
5794                         si_pi->max_cu = 0;
5795                         break;
5796                 }
5797         } else {
5798                 si_pi->max_cu = 0;
5799         }
5800 }
5801
5802 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5803                                                              struct radeon_clock_voltage_dependency_table *table)
5804 {
5805         u32 i;
5806         int j;
5807         u16 leakage_voltage;
5808
5809         if (table) {
5810                 for (i = 0; i < table->count; i++) {
5811                         switch (si_get_leakage_voltage_from_leakage_index(rdev,
5812                                                                           table->entries[i].v,
5813                                                                           &leakage_voltage)) {
5814                         case 0:
5815                                 table->entries[i].v = leakage_voltage;
5816                                 break;
5817                         case -EAGAIN:
5818                                 return -EINVAL;
5819                         case -EINVAL:
5820                         default:
5821                                 break;
5822                         }
5823                 }
5824
5825                 for (j = (table->count - 2); j >= 0; j--) {
5826                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5827                                 table->entries[j].v : table->entries[j + 1].v;
5828                 }
5829         }
5830         return 0;
5831 }
5832
5833 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5834 {
5835         int ret = 0;
5836
5837         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5838                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5839         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5840                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5841         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5842                                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5843         return ret;
5844 }
5845
5846 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5847                                           struct radeon_ps *radeon_new_state,
5848                                           struct radeon_ps *radeon_current_state)
5849 {
5850         u32 lane_width;
5851         u32 new_lane_width =
5852                 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5853         u32 current_lane_width =
5854                 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5855
5856         if (new_lane_width != current_lane_width) {
5857                 radeon_set_pcie_lanes(rdev, new_lane_width);
5858                 lane_width = radeon_get_pcie_lanes(rdev);
5859                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5860         }
5861 }
5862
5863 void si_dpm_setup_asic(struct radeon_device *rdev)
5864 {
5865         int r;
5866
5867         r = si_mc_load_microcode(rdev);
5868         if (r)
5869                 DRM_ERROR("Failed to load MC firmware!\n");
5870         rv770_get_memory_type(rdev);
5871         si_read_clock_registers(rdev);
5872         si_enable_acpi_power_management(rdev);
5873 }
5874
5875 static int si_thermal_enable_alert(struct radeon_device *rdev,
5876                                    bool enable)
5877 {
5878         u32 thermal_int = RREG32(CG_THERMAL_INT);
5879
5880         if (enable) {
5881                 PPSMC_Result result;
5882
5883                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5884                 WREG32(CG_THERMAL_INT, thermal_int);
5885                 rdev->irq.dpm_thermal = false;
5886                 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5887                 if (result != PPSMC_Result_OK) {
5888                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5889                         return -EINVAL;
5890                 }
5891         } else {
5892                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
5893                 WREG32(CG_THERMAL_INT, thermal_int);
5894                 rdev->irq.dpm_thermal = true;
5895         }
5896
5897         return 0;
5898 }
5899
5900 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
5901                                             int min_temp, int max_temp)
5902 {
5903         int low_temp = 0 * 1000;
5904         int high_temp = 255 * 1000;
5905
5906         if (low_temp < min_temp)
5907                 low_temp = min_temp;
5908         if (high_temp > max_temp)
5909                 high_temp = max_temp;
5910         if (high_temp < low_temp) {
5911                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5912                 return -EINVAL;
5913         }
5914
5915         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5916         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5917         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5918
5919         rdev->pm.dpm.thermal.min_temp = low_temp;
5920         rdev->pm.dpm.thermal.max_temp = high_temp;
5921
5922         return 0;
5923 }
5924
5925 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
5926 {
5927         struct si_power_info *si_pi = si_get_pi(rdev);
5928         u32 tmp;
5929
5930         if (si_pi->fan_ctrl_is_in_default_mode) {
5931                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
5932                 si_pi->fan_ctrl_default_mode = tmp;
5933                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
5934                 si_pi->t_min = tmp;
5935                 si_pi->fan_ctrl_is_in_default_mode = false;
5936         }
5937
5938         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
5939         tmp |= TMIN(0);
5940         WREG32(CG_FDO_CTRL2, tmp);
5941
5942         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
5943         tmp |= FDO_PWM_MODE(mode);
5944         WREG32(CG_FDO_CTRL2, tmp);
5945 }
5946
5947 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
5948 {
5949         struct si_power_info *si_pi = si_get_pi(rdev);
5950         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
5951         u32 duty100;
5952         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
5953         u16 fdo_min, slope1, slope2;
5954         u32 reference_clock, tmp;
5955         int ret;
5956         u64 tmp64;
5957
5958         if (!si_pi->fan_table_start) {
5959                 rdev->pm.dpm.fan.ucode_fan_control = false;
5960                 return 0;
5961         }
5962
5963         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
5964
5965         if (duty100 == 0) {
5966                 rdev->pm.dpm.fan.ucode_fan_control = false;
5967                 return 0;
5968         }
5969
5970         tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
5971         do_div(tmp64, 10000);
5972         fdo_min = (u16)tmp64;
5973
5974         t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
5975         t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
5976
5977         pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
5978         pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
5979
5980         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
5981         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
5982
5983         fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
5984         fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
5985         fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
5986
5987         fan_table.slope1 = cpu_to_be16(slope1);
5988         fan_table.slope2 = cpu_to_be16(slope2);
5989
5990         fan_table.fdo_min = cpu_to_be16(fdo_min);
5991
5992         fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
5993
5994         fan_table.hys_up = cpu_to_be16(1);
5995
5996         fan_table.hys_slope = cpu_to_be16(1);
5997
5998         fan_table.temp_resp_lim = cpu_to_be16(5);
5999
6000         reference_clock = radeon_get_xclk(rdev);
6001
6002         fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6003                                                 reference_clock) / 1600);
6004
6005         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6006
6007         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6008         fan_table.temp_src = (uint8_t)tmp;
6009
6010         ret = si_copy_bytes_to_smc(rdev,
6011                                    si_pi->fan_table_start,
6012                                    (u8 *)(&fan_table),
6013                                    sizeof(fan_table),
6014                                    si_pi->sram_end);
6015
6016         if (ret) {
6017                 DRM_ERROR("Failed to load fan table to the SMC.");
6018                 rdev->pm.dpm.fan.ucode_fan_control = false;
6019         }
6020
6021         return 0;
6022 }
6023
6024 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6025 {
6026         struct si_power_info *si_pi = si_get_pi(rdev);
6027         PPSMC_Result ret;
6028
6029         ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6030         if (ret == PPSMC_Result_OK) {
6031                 si_pi->fan_is_controlled_by_smc = true;
6032                 return 0;
6033         } else {
6034                 return -EINVAL;
6035         }
6036 }
6037
6038 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6039 {
6040         struct si_power_info *si_pi = si_get_pi(rdev);
6041         PPSMC_Result ret;
6042
6043         ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6044
6045         if (ret == PPSMC_Result_OK) {
6046                 si_pi->fan_is_controlled_by_smc = false;
6047                 return 0;
6048         } else {
6049                 return -EINVAL;
6050         }
6051 }
6052
6053 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6054                                       u32 *speed)
6055 {
6056         u32 duty, duty100;
6057         u64 tmp64;
6058
6059         if (rdev->pm.no_fan)
6060                 return -ENOENT;
6061
6062         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6063         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6064
6065         if (duty100 == 0)
6066                 return -EINVAL;
6067
6068         tmp64 = (u64)duty * 100;
6069         do_div(tmp64, duty100);
6070         *speed = (u32)tmp64;
6071
6072         if (*speed > 100)
6073                 *speed = 100;
6074
6075         return 0;
6076 }
6077
6078 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6079                                       u32 speed)
6080 {
6081         struct si_power_info *si_pi = si_get_pi(rdev);
6082         u32 tmp;
6083         u32 duty, duty100;
6084         u64 tmp64;
6085
6086         if (rdev->pm.no_fan)
6087                 return -ENOENT;
6088
6089         if (si_pi->fan_is_controlled_by_smc)
6090                 return -EINVAL;
6091
6092         if (speed > 100)
6093                 return -EINVAL;
6094
6095         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6096
6097         if (duty100 == 0)
6098                 return -EINVAL;
6099
6100         tmp64 = (u64)speed * duty100;
6101         do_div(tmp64, 100);
6102         duty = (u32)tmp64;
6103
6104         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6105         tmp |= FDO_STATIC_DUTY(duty);
6106         WREG32(CG_FDO_CTRL0, tmp);
6107
6108         return 0;
6109 }
6110
6111 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6112 {
6113         if (mode) {
6114                 /* stop auto-manage */
6115                 if (rdev->pm.dpm.fan.ucode_fan_control)
6116                         si_fan_ctrl_stop_smc_fan_control(rdev);
6117                 si_fan_ctrl_set_static_mode(rdev, mode);
6118         } else {
6119                 /* restart auto-manage */
6120                 if (rdev->pm.dpm.fan.ucode_fan_control)
6121                         si_thermal_start_smc_fan_control(rdev);
6122                 else
6123                         si_fan_ctrl_set_default_mode(rdev);
6124         }
6125 }
6126
6127 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6128 {
6129         struct si_power_info *si_pi = si_get_pi(rdev);
6130         u32 tmp;
6131
6132         if (si_pi->fan_is_controlled_by_smc)
6133                 return 0;
6134
6135         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6136         return (tmp >> FDO_PWM_MODE_SHIFT);
6137 }
6138
6139 #if 0
6140 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6141                                          u32 *speed)
6142 {
6143         u32 tach_period;
6144         u32 xclk = radeon_get_xclk(rdev);
6145
6146         if (rdev->pm.no_fan)
6147                 return -ENOENT;
6148
6149         if (rdev->pm.fan_pulses_per_revolution == 0)
6150                 return -ENOENT;
6151
6152         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6153         if (tach_period == 0)
6154                 return -ENOENT;
6155
6156         *speed = 60 * xclk * 10000 / tach_period;
6157
6158         return 0;
6159 }
6160
6161 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6162                                          u32 speed)
6163 {
6164         u32 tach_period, tmp;
6165         u32 xclk = radeon_get_xclk(rdev);
6166
6167         if (rdev->pm.no_fan)
6168                 return -ENOENT;
6169
6170         if (rdev->pm.fan_pulses_per_revolution == 0)
6171                 return -ENOENT;
6172
6173         if ((speed < rdev->pm.fan_min_rpm) ||
6174             (speed > rdev->pm.fan_max_rpm))
6175                 return -EINVAL;
6176
6177         if (rdev->pm.dpm.fan.ucode_fan_control)
6178                 si_fan_ctrl_stop_smc_fan_control(rdev);
6179
6180         tach_period = 60 * xclk * 10000 / (8 * speed);
6181         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6182         tmp |= TARGET_PERIOD(tach_period);
6183         WREG32(CG_TACH_CTRL, tmp);
6184
6185         si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6186
6187         return 0;
6188 }
6189 #endif
6190
6191 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6192 {
6193         struct si_power_info *si_pi = si_get_pi(rdev);
6194         u32 tmp;
6195
6196         if (!si_pi->fan_ctrl_is_in_default_mode) {
6197                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6198                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6199                 WREG32(CG_FDO_CTRL2, tmp);
6200
6201                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6202                 tmp |= TMIN(si_pi->t_min);
6203                 WREG32(CG_FDO_CTRL2, tmp);
6204                 si_pi->fan_ctrl_is_in_default_mode = true;
6205         }
6206 }
6207
6208 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6209 {
6210         if (rdev->pm.dpm.fan.ucode_fan_control) {
6211                 si_fan_ctrl_start_smc_fan_control(rdev);
6212                 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6213         }
6214 }
6215
6216 static void si_thermal_initialize(struct radeon_device *rdev)
6217 {
6218         u32 tmp;
6219
6220         if (rdev->pm.fan_pulses_per_revolution) {
6221                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6222                 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6223                 WREG32(CG_TACH_CTRL, tmp);
6224         }
6225
6226         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6227         tmp |= TACH_PWM_RESP_RATE(0x28);
6228         WREG32(CG_FDO_CTRL2, tmp);
6229 }
6230
6231 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6232 {
6233         int ret;
6234
6235         si_thermal_initialize(rdev);
6236         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6237         if (ret)
6238                 return ret;
6239         ret = si_thermal_enable_alert(rdev, true);
6240         if (ret)
6241                 return ret;
6242         if (rdev->pm.dpm.fan.ucode_fan_control) {
6243                 ret = si_halt_smc(rdev);
6244                 if (ret)
6245                         return ret;
6246                 ret = si_thermal_setup_fan_table(rdev);
6247                 if (ret)
6248                         return ret;
6249                 ret = si_resume_smc(rdev);
6250                 if (ret)
6251                         return ret;
6252                 si_thermal_start_smc_fan_control(rdev);
6253         }
6254
6255         return 0;
6256 }
6257
6258 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6259 {
6260         if (!rdev->pm.no_fan) {
6261                 si_fan_ctrl_set_default_mode(rdev);
6262                 si_fan_ctrl_stop_smc_fan_control(rdev);
6263         }
6264 }
6265
6266 int si_dpm_enable(struct radeon_device *rdev)
6267 {
6268         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6269         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6270         struct si_power_info *si_pi = si_get_pi(rdev);
6271         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6272         int ret;
6273
6274         if (si_is_smc_running(rdev))
6275                 return -EINVAL;
6276         if (pi->voltage_control || si_pi->voltage_control_svi2)
6277                 si_enable_voltage_control(rdev, true);
6278         if (pi->mvdd_control)
6279                 si_get_mvdd_configuration(rdev);
6280         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6281                 ret = si_construct_voltage_tables(rdev);
6282                 if (ret) {
6283                         DRM_ERROR("si_construct_voltage_tables failed\n");
6284                         return ret;
6285                 }
6286         }
6287         if (eg_pi->dynamic_ac_timing) {
6288                 ret = si_initialize_mc_reg_table(rdev);
6289                 if (ret)
6290                         eg_pi->dynamic_ac_timing = false;
6291         }
6292         if (pi->dynamic_ss)
6293                 si_enable_spread_spectrum(rdev, true);
6294         if (pi->thermal_protection)
6295                 si_enable_thermal_protection(rdev, true);
6296         si_setup_bsp(rdev);
6297         si_program_git(rdev);
6298         si_program_tp(rdev);
6299         si_program_tpp(rdev);
6300         si_program_sstp(rdev);
6301         si_enable_display_gap(rdev);
6302         si_program_vc(rdev);
6303         ret = si_upload_firmware(rdev);
6304         if (ret) {
6305                 DRM_ERROR("si_upload_firmware failed\n");
6306                 return ret;
6307         }
6308         ret = si_process_firmware_header(rdev);
6309         if (ret) {
6310                 DRM_ERROR("si_process_firmware_header failed\n");
6311                 return ret;
6312         }
6313         ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6314         if (ret) {
6315                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6316                 return ret;
6317         }
6318         ret = si_init_smc_table(rdev);
6319         if (ret) {
6320                 DRM_ERROR("si_init_smc_table failed\n");
6321                 return ret;
6322         }
6323         ret = si_init_smc_spll_table(rdev);
6324         if (ret) {
6325                 DRM_ERROR("si_init_smc_spll_table failed\n");
6326                 return ret;
6327         }
6328         ret = si_init_arb_table_index(rdev);
6329         if (ret) {
6330                 DRM_ERROR("si_init_arb_table_index failed\n");
6331                 return ret;
6332         }
6333         if (eg_pi->dynamic_ac_timing) {
6334                 ret = si_populate_mc_reg_table(rdev, boot_ps);
6335                 if (ret) {
6336                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6337                         return ret;
6338                 }
6339         }
6340         ret = si_initialize_smc_cac_tables(rdev);
6341         if (ret) {
6342                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6343                 return ret;
6344         }
6345         ret = si_initialize_hardware_cac_manager(rdev);
6346         if (ret) {
6347                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6348                 return ret;
6349         }
6350         ret = si_initialize_smc_dte_tables(rdev);
6351         if (ret) {
6352                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6353                 return ret;
6354         }
6355         ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6356         if (ret) {
6357                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6358                 return ret;
6359         }
6360         ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6361         if (ret) {
6362                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6363                 return ret;
6364         }
6365         si_program_response_times(rdev);
6366         si_program_ds_registers(rdev);
6367         si_dpm_start_smc(rdev);
6368         ret = si_notify_smc_display_change(rdev, false);
6369         if (ret) {
6370                 DRM_ERROR("si_notify_smc_display_change failed\n");
6371                 return ret;
6372         }
6373         si_enable_sclk_control(rdev, true);
6374         si_start_dpm(rdev);
6375
6376         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6377
6378         si_thermal_start_thermal_controller(rdev);
6379
6380         ni_update_current_ps(rdev, boot_ps);
6381
6382         return 0;
6383 }
6384
6385 static int si_set_temperature_range(struct radeon_device *rdev)
6386 {
6387         int ret;
6388
6389         ret = si_thermal_enable_alert(rdev, false);
6390         if (ret)
6391                 return ret;
6392         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6393         if (ret)
6394                 return ret;
6395         ret = si_thermal_enable_alert(rdev, true);
6396         if (ret)
6397                 return ret;
6398
6399         return ret;
6400 }
6401
6402 int si_dpm_late_enable(struct radeon_device *rdev)
6403 {
6404         int ret;
6405
6406         ret = si_set_temperature_range(rdev);
6407         if (ret)
6408                 return ret;
6409
6410         return ret;
6411 }
6412
6413 void si_dpm_disable(struct radeon_device *rdev)
6414 {
6415         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6416         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6417
6418         if (!si_is_smc_running(rdev))
6419                 return;
6420         si_thermal_stop_thermal_controller(rdev);
6421         si_disable_ulv(rdev);
6422         si_clear_vc(rdev);
6423         if (pi->thermal_protection)
6424                 si_enable_thermal_protection(rdev, false);
6425         si_enable_power_containment(rdev, boot_ps, false);
6426         si_enable_smc_cac(rdev, boot_ps, false);
6427         si_enable_spread_spectrum(rdev, false);
6428         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6429         si_stop_dpm(rdev);
6430         si_reset_to_default(rdev);
6431         si_dpm_stop_smc(rdev);
6432         si_force_switch_to_arb_f0(rdev);
6433
6434         ni_update_current_ps(rdev, boot_ps);
6435 }
6436
6437 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6438 {
6439         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6440         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6441         struct radeon_ps *new_ps = &requested_ps;
6442
6443         ni_update_requested_ps(rdev, new_ps);
6444
6445         si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6446
6447         return 0;
6448 }
6449
6450 static int si_power_control_set_level(struct radeon_device *rdev)
6451 {
6452         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6453         int ret;
6454
6455         ret = si_restrict_performance_levels_before_switch(rdev);
6456         if (ret)
6457                 return ret;
6458         ret = si_halt_smc(rdev);
6459         if (ret)
6460                 return ret;
6461         ret = si_populate_smc_tdp_limits(rdev, new_ps);
6462         if (ret)
6463                 return ret;
6464         ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6465         if (ret)
6466                 return ret;
6467         ret = si_resume_smc(rdev);
6468         if (ret)
6469                 return ret;
6470         ret = si_set_sw_state(rdev);
6471         if (ret)
6472                 return ret;
6473         return 0;
6474 }
6475
6476 int si_dpm_set_power_state(struct radeon_device *rdev)
6477 {
6478         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6479         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6480         struct radeon_ps *old_ps = &eg_pi->current_rps;
6481         int ret;
6482
6483         ret = si_disable_ulv(rdev);
6484         if (ret) {
6485                 DRM_ERROR("si_disable_ulv failed\n");
6486                 return ret;
6487         }
6488         ret = si_restrict_performance_levels_before_switch(rdev);
6489         if (ret) {
6490                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6491                 return ret;
6492         }
6493         if (eg_pi->pcie_performance_request)
6494                 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6495         ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6496         ret = si_enable_power_containment(rdev, new_ps, false);
6497         if (ret) {
6498                 DRM_ERROR("si_enable_power_containment failed\n");
6499                 return ret;
6500         }
6501         ret = si_enable_smc_cac(rdev, new_ps, false);
6502         if (ret) {
6503                 DRM_ERROR("si_enable_smc_cac failed\n");
6504                 return ret;
6505         }
6506         ret = si_halt_smc(rdev);
6507         if (ret) {
6508                 DRM_ERROR("si_halt_smc failed\n");
6509                 return ret;
6510         }
6511         ret = si_upload_sw_state(rdev, new_ps);
6512         if (ret) {
6513                 DRM_ERROR("si_upload_sw_state failed\n");
6514                 return ret;
6515         }
6516         ret = si_upload_smc_data(rdev);
6517         if (ret) {
6518                 DRM_ERROR("si_upload_smc_data failed\n");
6519                 return ret;
6520         }
6521         ret = si_upload_ulv_state(rdev);
6522         if (ret) {
6523                 DRM_ERROR("si_upload_ulv_state failed\n");
6524                 return ret;
6525         }
6526         if (eg_pi->dynamic_ac_timing) {
6527                 ret = si_upload_mc_reg_table(rdev, new_ps);
6528                 if (ret) {
6529                         DRM_ERROR("si_upload_mc_reg_table failed\n");
6530                         return ret;
6531                 }
6532         }
6533         ret = si_program_memory_timing_parameters(rdev, new_ps);
6534         if (ret) {
6535                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6536                 return ret;
6537         }
6538         si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6539
6540         ret = si_resume_smc(rdev);
6541         if (ret) {
6542                 DRM_ERROR("si_resume_smc failed\n");
6543                 return ret;
6544         }
6545         ret = si_set_sw_state(rdev);
6546         if (ret) {
6547                 DRM_ERROR("si_set_sw_state failed\n");
6548                 return ret;
6549         }
6550         ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6551         if (eg_pi->pcie_performance_request)
6552                 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6553         ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6554         if (ret) {
6555                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6556                 return ret;
6557         }
6558         ret = si_enable_smc_cac(rdev, new_ps, true);
6559         if (ret) {
6560                 DRM_ERROR("si_enable_smc_cac failed\n");
6561                 return ret;
6562         }
6563         ret = si_enable_power_containment(rdev, new_ps, true);
6564         if (ret) {
6565                 DRM_ERROR("si_enable_power_containment failed\n");
6566                 return ret;
6567         }
6568
6569         ret = si_power_control_set_level(rdev);
6570         if (ret) {
6571                 DRM_ERROR("si_power_control_set_level failed\n");
6572                 return ret;
6573         }
6574
6575         return 0;
6576 }
6577
6578 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6579 {
6580         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6581         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6582
6583         ni_update_current_ps(rdev, new_ps);
6584 }
6585
6586 #if 0
6587 void si_dpm_reset_asic(struct radeon_device *rdev)
6588 {
6589         si_restrict_performance_levels_before_switch(rdev);
6590         si_disable_ulv(rdev);
6591         si_set_boot_state(rdev);
6592 }
6593 #endif
6594
6595 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6596 {
6597         si_program_display_gap(rdev);
6598 }
6599
6600 union power_info {
6601         struct _ATOM_POWERPLAY_INFO info;
6602         struct _ATOM_POWERPLAY_INFO_V2 info_2;
6603         struct _ATOM_POWERPLAY_INFO_V3 info_3;
6604         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6605         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6606         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6607 };
6608
6609 union pplib_clock_info {
6610         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6611         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6612         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6613         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6614         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6615 };
6616
6617 union pplib_power_state {
6618         struct _ATOM_PPLIB_STATE v1;
6619         struct _ATOM_PPLIB_STATE_V2 v2;
6620 };
6621
6622 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6623                                           struct radeon_ps *rps,
6624                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6625                                           u8 table_rev)
6626 {
6627         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6628         rps->class = le16_to_cpu(non_clock_info->usClassification);
6629         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6630
6631         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6632                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6633                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6634         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6635                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6636                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6637         } else {
6638                 rps->vclk = 0;
6639                 rps->dclk = 0;
6640         }
6641
6642         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6643                 rdev->pm.dpm.boot_ps = rps;
6644         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6645                 rdev->pm.dpm.uvd_ps = rps;
6646 }
6647
6648 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6649                                       struct radeon_ps *rps, int index,
6650                                       union pplib_clock_info *clock_info)
6651 {
6652         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6653         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6654         struct si_power_info *si_pi = si_get_pi(rdev);
6655         struct ni_ps *ps = ni_get_ps(rps);
6656         u16 leakage_voltage;
6657         struct rv7xx_pl *pl = &ps->performance_levels[index];
6658         int ret;
6659
6660         ps->performance_level_count = index + 1;
6661
6662         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6663         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6664         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6665         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6666
6667         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6668         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6669         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6670         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6671                                                  si_pi->sys_pcie_mask,
6672                                                  si_pi->boot_pcie_gen,
6673                                                  clock_info->si.ucPCIEGen);
6674
6675         /* patch up vddc if necessary */
6676         ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6677                                                         &leakage_voltage);
6678         if (ret == 0)
6679                 pl->vddc = leakage_voltage;
6680
6681         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6682                 pi->acpi_vddc = pl->vddc;
6683                 eg_pi->acpi_vddci = pl->vddci;
6684                 si_pi->acpi_pcie_gen = pl->pcie_gen;
6685         }
6686
6687         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6688             index == 0) {
6689                 /* XXX disable for A0 tahiti */
6690                 si_pi->ulv.supported = false;
6691                 si_pi->ulv.pl = *pl;
6692                 si_pi->ulv.one_pcie_lane_in_ulv = false;
6693                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6694                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6695                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6696         }
6697
6698         if (pi->min_vddc_in_table > pl->vddc)
6699                 pi->min_vddc_in_table = pl->vddc;
6700
6701         if (pi->max_vddc_in_table < pl->vddc)
6702                 pi->max_vddc_in_table = pl->vddc;
6703
6704         /* patch up boot state */
6705         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6706                 u16 vddc, vddci, mvdd;
6707                 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6708                 pl->mclk = rdev->clock.default_mclk;
6709                 pl->sclk = rdev->clock.default_sclk;
6710                 pl->vddc = vddc;
6711                 pl->vddci = vddci;
6712                 si_pi->mvdd_bootup_value = mvdd;
6713         }
6714
6715         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6716             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6717                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6718                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6719                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6720                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6721         }
6722 }
6723
6724 static int si_parse_power_table(struct radeon_device *rdev)
6725 {
6726         struct radeon_mode_info *mode_info = &rdev->mode_info;
6727         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6728         union pplib_power_state *power_state;
6729         int i, j, k, non_clock_array_index, clock_array_index;
6730         union pplib_clock_info *clock_info;
6731         struct _StateArray *state_array;
6732         struct _ClockInfoArray *clock_info_array;
6733         struct _NonClockInfoArray *non_clock_info_array;
6734         union power_info *power_info;
6735         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6736         u16 data_offset;
6737         u8 frev, crev;
6738         u8 *power_state_offset;
6739         struct ni_ps *ps;
6740
6741         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6742                                    &frev, &crev, &data_offset))
6743                 return -EINVAL;
6744         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6745
6746         state_array = (struct _StateArray *)
6747                 (mode_info->atom_context->bios + data_offset +
6748                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
6749         clock_info_array = (struct _ClockInfoArray *)
6750                 (mode_info->atom_context->bios + data_offset +
6751                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6752         non_clock_info_array = (struct _NonClockInfoArray *)
6753                 (mode_info->atom_context->bios + data_offset +
6754                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6755
6756         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6757                                   state_array->ucNumEntries, GFP_KERNEL);
6758         if (!rdev->pm.dpm.ps)
6759                 return -ENOMEM;
6760         power_state_offset = (u8 *)state_array->states;
6761         for (i = 0; i < state_array->ucNumEntries; i++) {
6762                 u8 *idx;
6763                 power_state = (union pplib_power_state *)power_state_offset;
6764                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6765                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6766                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
6767                 if (!rdev->pm.power_state[i].clock_info)
6768                         return -EINVAL;
6769                 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6770                 if (ps == NULL) {
6771                         kfree(rdev->pm.dpm.ps);
6772                         return -ENOMEM;
6773                 }
6774                 rdev->pm.dpm.ps[i].ps_priv = ps;
6775                 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6776                                               non_clock_info,
6777                                               non_clock_info_array->ucEntrySize);
6778                 k = 0;
6779                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6780                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6781                         clock_array_index = idx[j];
6782                         if (clock_array_index >= clock_info_array->ucNumEntries)
6783                                 continue;
6784                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6785                                 break;
6786                         clock_info = (union pplib_clock_info *)
6787                                 ((u8 *)&clock_info_array->clockInfo[0] +
6788                                  (clock_array_index * clock_info_array->ucEntrySize));
6789                         si_parse_pplib_clock_info(rdev,
6790                                                   &rdev->pm.dpm.ps[i], k,
6791                                                   clock_info);
6792                         k++;
6793                 }
6794                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6795         }
6796         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6797         return 0;
6798 }
6799
6800 int si_dpm_init(struct radeon_device *rdev)
6801 {
6802         struct rv7xx_power_info *pi;
6803         struct evergreen_power_info *eg_pi;
6804         struct ni_power_info *ni_pi;
6805         struct si_power_info *si_pi;
6806         struct atom_clock_dividers dividers;
6807         int ret;
6808         u32 mask;
6809
6810         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6811         if (si_pi == NULL)
6812                 return -ENOMEM;
6813         rdev->pm.dpm.priv = si_pi;
6814         ni_pi = &si_pi->ni;
6815         eg_pi = &ni_pi->eg;
6816         pi = &eg_pi->rv7xx;
6817
6818         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6819         if (ret)
6820                 si_pi->sys_pcie_mask = 0;
6821         else
6822                 si_pi->sys_pcie_mask = mask;
6823         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6824         si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6825
6826         si_set_max_cu_value(rdev);
6827
6828         rv770_get_max_vddc(rdev);
6829         si_get_leakage_vddc(rdev);
6830         si_patch_dependency_tables_based_on_leakage(rdev);
6831
6832         pi->acpi_vddc = 0;
6833         eg_pi->acpi_vddci = 0;
6834         pi->min_vddc_in_table = 0;
6835         pi->max_vddc_in_table = 0;
6836
6837         ret = r600_get_platform_caps(rdev);
6838         if (ret)
6839                 return ret;
6840
6841         ret = si_parse_power_table(rdev);
6842         if (ret)
6843                 return ret;
6844         ret = r600_parse_extended_power_table(rdev);
6845         if (ret)
6846                 return ret;
6847
6848         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6849                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6850         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6851                 r600_free_extended_power_table(rdev);
6852                 return -ENOMEM;
6853         }
6854         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6855         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6856         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6857         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6858         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6859         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6860         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6861         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6862         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6863
6864         if (rdev->pm.dpm.voltage_response_time == 0)
6865                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6866         if (rdev->pm.dpm.backbias_response_time == 0)
6867                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6868
6869         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6870                                              0, false, &dividers);
6871         if (ret)
6872                 pi->ref_div = dividers.ref_div + 1;
6873         else
6874                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6875
6876         eg_pi->smu_uvd_hs = false;
6877
6878         pi->mclk_strobe_mode_threshold = 40000;
6879         if (si_is_special_1gb_platform(rdev))
6880                 pi->mclk_stutter_mode_threshold = 0;
6881         else
6882                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6883         pi->mclk_edc_enable_threshold = 40000;
6884         eg_pi->mclk_edc_wr_enable_threshold = 40000;
6885
6886         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6887
6888         pi->voltage_control =
6889                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6890                                             VOLTAGE_OBJ_GPIO_LUT);
6891         if (!pi->voltage_control) {
6892                 si_pi->voltage_control_svi2 =
6893                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6894                                                     VOLTAGE_OBJ_SVID2);
6895                 if (si_pi->voltage_control_svi2)
6896                         radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6897                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
6898         }
6899
6900         pi->mvdd_control =
6901                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
6902                                             VOLTAGE_OBJ_GPIO_LUT);
6903
6904         eg_pi->vddci_control =
6905                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
6906                                             VOLTAGE_OBJ_GPIO_LUT);
6907         if (!eg_pi->vddci_control)
6908                 si_pi->vddci_control_svi2 =
6909                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
6910                                                     VOLTAGE_OBJ_SVID2);
6911
6912         si_pi->vddc_phase_shed_control =
6913                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6914                                             VOLTAGE_OBJ_PHASE_LUT);
6915
6916         rv770_get_engine_memory_ss(rdev);
6917
6918         pi->asi = RV770_ASI_DFLT;
6919         pi->pasi = CYPRESS_HASI_DFLT;
6920         pi->vrc = SISLANDS_VRC_DFLT;
6921
6922         pi->gfx_clock_gating = true;
6923
6924         eg_pi->sclk_deep_sleep = true;
6925         si_pi->sclk_deep_sleep_above_low = false;
6926
6927         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6928                 pi->thermal_protection = true;
6929         else
6930                 pi->thermal_protection = false;
6931
6932         eg_pi->dynamic_ac_timing = true;
6933
6934         eg_pi->light_sleep = true;
6935 #if defined(CONFIG_ACPI)
6936         eg_pi->pcie_performance_request =
6937                 radeon_acpi_is_pcie_performance_request_supported(rdev);
6938 #else
6939         eg_pi->pcie_performance_request = false;
6940 #endif
6941
6942         si_pi->sram_end = SMC_RAM_END;
6943
6944         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6945         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6946         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6947         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6948         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6949         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6950         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6951
6952         si_initialize_powertune_defaults(rdev);
6953
6954         /* make sure dc limits are valid */
6955         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6956             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6957                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6958                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6959
6960         si_pi->fan_ctrl_is_in_default_mode = true;
6961
6962         return 0;
6963 }
6964
6965 void si_dpm_fini(struct radeon_device *rdev)
6966 {
6967         int i;
6968
6969         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6970                 kfree(rdev->pm.dpm.ps[i].ps_priv);
6971         }
6972         kfree(rdev->pm.dpm.ps);
6973         kfree(rdev->pm.dpm.priv);
6974         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6975         r600_free_extended_power_table(rdev);
6976 }
6977
6978 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
6979                                                     struct seq_file *m)
6980 {
6981         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6982         struct radeon_ps *rps = &eg_pi->current_rps;
6983         struct ni_ps *ps = ni_get_ps(rps);
6984         struct rv7xx_pl *pl;
6985         u32 current_index =
6986                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
6987                 CURRENT_STATE_INDEX_SHIFT;
6988
6989         if (current_index >= ps->performance_level_count) {
6990                 seq_printf(m, "invalid dpm profile %d\n", current_index);
6991         } else {
6992                 pl = &ps->performance_levels[current_index];
6993                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6994                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6995                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
6996         }
6997 }
6998
6999 u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7000 {
7001         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7002         struct radeon_ps *rps = &eg_pi->current_rps;
7003         struct ni_ps *ps = ni_get_ps(rps);
7004         struct rv7xx_pl *pl;
7005         u32 current_index =
7006                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7007                 CURRENT_STATE_INDEX_SHIFT;
7008
7009         if (current_index >= ps->performance_level_count) {
7010                 return 0;
7011         } else {
7012                 pl = &ps->performance_levels[current_index];
7013                 return pl->sclk;
7014         }
7015 }
7016
7017 u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7018 {
7019         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7020         struct radeon_ps *rps = &eg_pi->current_rps;
7021         struct ni_ps *ps = ni_get_ps(rps);
7022         struct rv7xx_pl *pl;
7023         u32 current_index =
7024                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7025                 CURRENT_STATE_INDEX_SHIFT;
7026
7027         if (current_index >= ps->performance_level_count) {
7028                 return 0;
7029         } else {
7030                 pl = &ps->performance_levels[current_index];
7031                 return pl->mclk;
7032         }
7033 }