kernel/drivers/gpu/drm/radeon/radeon_cursor.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
  31 {
  32         struct radeon_device *rdev = crtc->dev->dev_private;
  33         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  34         uint32_t cur_lock;
  35
  36         if (ASIC_IS_DCE4(rdev)) {
  37                 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
  38                 if (lock)
  39                         cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
  40                 else
  41                         cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
  42                 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
  43         } else if (ASIC_IS_AVIVO(rdev)) {
  44                 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
  45                 if (lock)
  46                         cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
  47                 else
  48                         cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
  49                 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
  50         } else {
  51                 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
  52                 if (lock)
  53                         cur_lock |= RADEON_CUR_LOCK;
  54                 else
  55                         cur_lock &= ~RADEON_CUR_LOCK;
  56                 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
  57         }
  58 }
  59
  60 static void radeon_hide_cursor(struct drm_crtc *crtc)
  61 {
  62         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  63         struct radeon_device *rdev = crtc->dev->dev_private;
  64
  65         if (ASIC_IS_DCE4(rdev)) {
  66                 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
  67                            EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
  68                            EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
  69         } else if (ASIC_IS_AVIVO(rdev)) {
  70                 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
  71                            (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
  72         } else {
  73                 u32 reg;
  74                 switch (radeon_crtc->crtc_id) {
  75                 case 0:
  76                         reg = RADEON_CRTC_GEN_CNTL;
  77                         break;
  78                 case 1:
  79                         reg = RADEON_CRTC2_GEN_CNTL;
  80                         break;
  81                 default:
  82                         return;
  83                 }
  84                 WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN);
  85         }
  86 }
  87
  88 static void radeon_show_cursor(struct drm_crtc *crtc)
  89 {
  90         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  91         struct radeon_device *rdev = crtc->dev->dev_private;
  92
  93         if (ASIC_IS_DCE4(rdev)) {
  94                 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
  95                 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
  96                        EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
  97                        EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
  98         } else if (ASIC_IS_AVIVO(rdev)) {
  99                 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
 100                 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
 101                        (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
 102         } else {
 103                 switch (radeon_crtc->crtc_id) {
 104                 case 0:
 105                         WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
 106                         break;
 107                 case 1:
 108                         WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
 109                         break;
 110                 default:
 111                         return;
 112                 }
 113
 114                 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
 115                                           (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
 116                          ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
 117         }
 118 }
 119
 120 static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
 121 {
 122         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 123         struct radeon_device *rdev = crtc->dev->dev_private;
 124         int xorigin = 0, yorigin = 0;
 125         int w = radeon_crtc->cursor_width;
 126
 127         if (ASIC_IS_AVIVO(rdev)) {
 128                 /* avivo cursor are offset into the total surface */
 129                 x += crtc->x;
 130                 y += crtc->y;
 131         }
 132         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
 133
 134         if (x < 0) {
 135                 xorigin = min(-x, radeon_crtc->max_cursor_width - 1);
 136                 x = 0;
 137         }
 138         if (y < 0) {
 139                 yorigin = min(-y, radeon_crtc->max_cursor_height - 1);
 140                 y = 0;
 141         }
 142
 143         /* fixed on DCE6 and newer */
 144         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
 145                 int i = 0;
 146                 struct drm_crtc *crtc_p;
 147
 148                 /*
 149                  * avivo cursor image can't end on 128 pixel boundary or
 150                  * go past the end of the frame if both crtcs are enabled
 151                  *
 152                  * NOTE: It is safe to access crtc->enabled of other crtcs
 153                  * without holding either the mode_config lock or the other
 154                  * crtc's lock as long as write access to this flag _always_
 155                  * grabs all locks.
 156                  */
 157                 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
 158                         if (crtc_p->enabled)
 159                                 i++;
 160                 }
 161                 if (i > 1) {
 162                         int cursor_end, frame_end;
 163
 164                         cursor_end = x - xorigin + w;
 165                         frame_end = crtc->x + crtc->mode.crtc_hdisplay;
 166                         if (cursor_end >= frame_end) {
 167                                 w = w - (cursor_end - frame_end);
 168                                 if (!(frame_end & 0x7f))
 169                                         w--;
 170                         } else {
 171                                 if (!(cursor_end & 0x7f))
 172                                         w--;
 173                         }
 174                         if (w <= 0) {
 175                                 w = 1;
 176                                 cursor_end = x - xorigin + w;
 177                                 if (!(cursor_end & 0x7f)) {
 178                                         x--;
 179                                         WARN_ON_ONCE(x < 0);
 180                                 }
 181                         }
 182                 }
 183         }
 184
 185         if (ASIC_IS_DCE4(rdev)) {
 186                 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
 187                 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
 188                 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
 189                        ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
 190         } else if (ASIC_IS_AVIVO(rdev)) {
 191                 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
 192                 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
 193                 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
 194                        ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
 195         } else {
 196                 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
 197                         y *= 2;
 198
 199                 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
 200                        (RADEON_CUR_LOCK
 201                         | (xorigin << 16)
 202                         | yorigin));
 203                 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
 204                        (RADEON_CUR_LOCK
 205                         | (x << 16)
 206                         | y));
 207                 /* offset is from DISP(2)_BASE_ADDRESS */
 208                 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,
 209                        radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr +
 210                        yorigin * 256);
 211         }
 212
 213         radeon_crtc->cursor_x = x;
 214         radeon_crtc->cursor_y = y;
 215
 216         return 0;
 217 }
 218
 219 int radeon_crtc_cursor_move(struct drm_crtc *crtc,
 220                             int x, int y)
 221 {
 222         int ret;
 223
 224         radeon_lock_cursor(crtc, true);
 225         ret = radeon_cursor_move_locked(crtc, x, y);
 226         radeon_lock_cursor(crtc, false);
 227
 228         return ret;
 229 }
 230
 231 static void radeon_set_cursor(struct drm_crtc *crtc)
 232 {
 233         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 234         struct radeon_device *rdev = crtc->dev->dev_private;
 235
 236         if (ASIC_IS_DCE4(rdev)) {
 237                 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 238                        upper_32_bits(radeon_crtc->cursor_addr));
 239                 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 240                        lower_32_bits(radeon_crtc->cursor_addr));
 241         } else if (ASIC_IS_AVIVO(rdev)) {
 242                 if (rdev->family >= CHIP_RV770) {
 243                         if (radeon_crtc->crtc_id)
 244                                 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH,
 245                                        upper_32_bits(radeon_crtc->cursor_addr));
 246                         else
 247                                 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH,
 248                                        upper_32_bits(radeon_crtc->cursor_addr));
 249                 }
 250                 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 251                        lower_32_bits(radeon_crtc->cursor_addr));
 252         } else {
 253                 /* offset is from DISP(2)_BASE_ADDRESS */
 254                 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,
 255                        radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr);
 256         }
 257 }
 258
 259 int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
 260                             struct drm_file *file_priv,
 261                             uint32_t handle,
 262                             uint32_t width,
 263                             uint32_t height,
 264                             int32_t hot_x,
 265                             int32_t hot_y)
 266 {
 267         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 268         struct radeon_device *rdev = crtc->dev->dev_private;
 269         struct drm_gem_object *obj;
 270         struct radeon_bo *robj;
 271         int ret;
 272
 273         if (!handle) {
 274                 /* turn off cursor */
 275                 radeon_hide_cursor(crtc);
 276                 obj = NULL;
 277                 goto unpin;
 278         }
 279
 280         if ((width > radeon_crtc->max_cursor_width) ||
 281             (height > radeon_crtc->max_cursor_height)) {
 282                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
 283                 return -EINVAL;
 284         }
 285
 286         obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
 287         if (!obj) {
 288                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
 289                 return -ENOENT;
 290         }
 291
 292         robj = gem_to_radeon_bo(obj);
 293         ret = radeon_bo_reserve(robj, false);
 294         if (ret != 0) {
 295                 drm_gem_object_unreference_unlocked(obj);
 296                 return ret;
 297         }
 298         /* Only 27 bit offset for legacy cursor */
 299         ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
 300                                        ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
 301                                        &radeon_crtc->cursor_addr);
 302         radeon_bo_unreserve(robj);
 303         if (ret) {
 304                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
 305                 drm_gem_object_unreference_unlocked(obj);
 306                 return ret;
 307         }
 308
 309         radeon_crtc->cursor_width = width;
 310         radeon_crtc->cursor_height = height;
 311
 312         radeon_lock_cursor(crtc, true);
 313
 314         if (hot_x != radeon_crtc->cursor_hot_x ||
 315             hot_y != radeon_crtc->cursor_hot_y) {
 316                 int x, y;
 317
 318                 x = radeon_crtc->cursor_x + radeon_crtc->cursor_hot_x - hot_x;
 319                 y = radeon_crtc->cursor_y + radeon_crtc->cursor_hot_y - hot_y;
 320
 321                 radeon_cursor_move_locked(crtc, x, y);
 322
 323                 radeon_crtc->cursor_hot_x = hot_x;
 324                 radeon_crtc->cursor_hot_y = hot_y;
 325         }
 326
 327         radeon_set_cursor(crtc);
 328         radeon_show_cursor(crtc);
 329
 330         radeon_lock_cursor(crtc, false);
 331
 332 unpin:
 333         if (radeon_crtc->cursor_bo) {
 334                 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
 335                 ret = radeon_bo_reserve(robj, false);
 336                 if (likely(ret == 0)) {
 337                         radeon_bo_unpin(robj);
 338                         radeon_bo_unreserve(robj);
 339                 }
 340                 drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
 341         }
 342
 343         radeon_crtc->cursor_bo = obj;
 344         return 0;
 345 }
 346
 347 /**
 348  * radeon_cursor_reset - Re-set the current cursor, if any.
 349  *
 350  * @crtc: drm crtc
 351  *
 352  * If the CRTC passed in currently has a cursor assigned, this function
 353  * makes sure it's visible.
 354  */
 355 void radeon_cursor_reset(struct drm_crtc *crtc)
 356 {
 357         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 358
 359         if (radeon_crtc->cursor_bo) {
 360                 radeon_lock_cursor(crtc, true);
 361
 362                 radeon_cursor_move_locked(crtc, radeon_crtc->cursor_x,
 363                                           radeon_crtc->cursor_y);
 364
 365                 radeon_set_cursor(crtc);
 366                 radeon_show_cursor(crtc);
 367
 368                 radeon_lock_cursor(crtc, false);
 369         }
 370 }