kernel/drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 /**
  44  * radeon_invalid_rreg - dummy reg read function
  45  *
  46  * @rdev: radeon device pointer
  47  * @reg: offset of register
  48  *
  49  * Dummy register read function.  Used for register blocks
  50  * that certain asics don't have (all asics).
  51  * Returns the value in the register.
  52  */
  53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  54 {
  55         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  56         BUG_ON(1);
  57         return 0;
  58 }
  59
  60 /**
  61  * radeon_invalid_wreg - dummy reg write function
  62  *
  63  * @rdev: radeon device pointer
  64  * @reg: offset of register
  65  * @v: value to write to the register
  66  *
  67  * Dummy register read function.  Used for register blocks
  68  * that certain asics don't have (all asics).
  69  */
  70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  71 {
  72         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  73                   reg, v);
  74         BUG_ON(1);
  75 }
  76
  77 /**
  78  * radeon_register_accessor_init - sets up the register accessor callbacks
  79  *
  80  * @rdev: radeon device pointer
  81  *
  82  * Sets up the register accessor callbacks for various register
  83  * apertures.  Not all asics have all apertures (all asics).
  84  */
  85 static void radeon_register_accessor_init(struct radeon_device *rdev)
  86 {
  87         rdev->mc_rreg = &radeon_invalid_rreg;
  88         rdev->mc_wreg = &radeon_invalid_wreg;
  89         rdev->pll_rreg = &radeon_invalid_rreg;
  90         rdev->pll_wreg = &radeon_invalid_wreg;
  91         rdev->pciep_rreg = &radeon_invalid_rreg;
  92         rdev->pciep_wreg = &radeon_invalid_wreg;
  93
  94         /* Don't change order as we are overridding accessor. */
  95         if (rdev->family < CHIP_RV515) {
  96                 rdev->pcie_reg_mask = 0xff;
  97         } else {
  98                 rdev->pcie_reg_mask = 0x7ff;
  99         }
 100         /* FIXME: not sure here */
 101         if (rdev->family <= CHIP_R580) {
 102                 rdev->pll_rreg = &r100_pll_rreg;
 103                 rdev->pll_wreg = &r100_pll_wreg;
 104         }
 105         if (rdev->family >= CHIP_R420) {
 106                 rdev->mc_rreg = &r420_mc_rreg;
 107                 rdev->mc_wreg = &r420_mc_wreg;
 108         }
 109         if (rdev->family >= CHIP_RV515) {
 110                 rdev->mc_rreg = &rv515_mc_rreg;
 111                 rdev->mc_wreg = &rv515_mc_wreg;
 112         }
 113         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 114                 rdev->mc_rreg = &rs400_mc_rreg;
 115                 rdev->mc_wreg = &rs400_mc_wreg;
 116         }
 117         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 118                 rdev->mc_rreg = &rs690_mc_rreg;
 119                 rdev->mc_wreg = &rs690_mc_wreg;
 120         }
 121         if (rdev->family == CHIP_RS600) {
 122                 rdev->mc_rreg = &rs600_mc_rreg;
 123                 rdev->mc_wreg = &rs600_mc_wreg;
 124         }
 125         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 126                 rdev->mc_rreg = &rs780_mc_rreg;
 127                 rdev->mc_wreg = &rs780_mc_wreg;
 128         }
 129
 130         if (rdev->family >= CHIP_BONAIRE) {
 131                 rdev->pciep_rreg = &cik_pciep_rreg;
 132                 rdev->pciep_wreg = &cik_pciep_wreg;
 133         } else if (rdev->family >= CHIP_R600) {
 134                 rdev->pciep_rreg = &r600_pciep_rreg;
 135                 rdev->pciep_wreg = &r600_pciep_wreg;
 136         }
 137 }
 138
 139 static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev,
 140                                                     u32 reg, u32 *val)
 141 {
 142         return -EINVAL;
 143 }
 144
 145 /* helper to disable agp */
 146 /**
 147  * radeon_agp_disable - AGP disable helper function
 148  *
 149  * @rdev: radeon device pointer
 150  *
 151  * Removes AGP flags and changes the gart callbacks on AGP
 152  * cards when using the internal gart rather than AGP (all asics).
 153  */
 154 void radeon_agp_disable(struct radeon_device *rdev)
 155 {
 156         rdev->flags &= ~RADEON_IS_AGP;
 157         if (rdev->family >= CHIP_R600) {
 158                 DRM_INFO("Forcing AGP to PCIE mode\n");
 159                 rdev->flags |= RADEON_IS_PCIE;
 160         } else if (rdev->family >= CHIP_RV515 ||
 161                         rdev->family == CHIP_RV380 ||
 162                         rdev->family == CHIP_RV410 ||
 163                         rdev->family == CHIP_R423) {
 164                 DRM_INFO("Forcing AGP to PCIE mode\n");
 165                 rdev->flags |= RADEON_IS_PCIE;
 166                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 167                 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
 168                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 169         } else {
 170                 DRM_INFO("Forcing AGP to PCI mode\n");
 171                 rdev->flags |= RADEON_IS_PCI;
 172                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 173                 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
 174                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 175         }
 176         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 177 }
 178
 179 /*
 180  * ASIC
 181  */
 182
 183 static struct radeon_asic_ring r100_gfx_ring = {
 184         .ib_execute = &r100_ring_ib_execute,
 185         .emit_fence = &r100_fence_ring_emit,
 186         .emit_semaphore = &r100_semaphore_ring_emit,
 187         .cs_parse = &r100_cs_parse,
 188         .ring_start = &r100_ring_start,
 189         .ring_test = &r100_ring_test,
 190         .ib_test = &r100_ib_test,
 191         .is_lockup = &r100_gpu_is_lockup,
 192         .get_rptr = &r100_gfx_get_rptr,
 193         .get_wptr = &r100_gfx_get_wptr,
 194         .set_wptr = &r100_gfx_set_wptr,
 195 };
 196
 197 static struct radeon_asic r100_asic = {
 198         .init = &r100_init,
 199         .fini = &r100_fini,
 200         .suspend = &r100_suspend,
 201         .resume = &r100_resume,
 202         .vga_set_state = &r100_vga_set_state,
 203         .asic_reset = &r100_asic_reset,
 204         .mmio_hdp_flush = NULL,
 205         .gui_idle = &r100_gui_idle,
 206         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 207         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
 208         .gart = {
 209                 .tlb_flush = &r100_pci_gart_tlb_flush,
 210                 .get_page_entry = &r100_pci_gart_get_page_entry,
 211                 .set_page = &r100_pci_gart_set_page,
 212         },
 213         .ring = {
 214                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
 215         },
 216         .irq = {
 217                 .set = &r100_irq_set,
 218                 .process = &r100_irq_process,
 219         },
 220         .display = {
 221                 .bandwidth_update = &r100_bandwidth_update,
 222                 .get_vblank_counter = &r100_get_vblank_counter,
 223                 .wait_for_vblank = &r100_wait_for_vblank,
 224                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 225                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 226         },
 227         .copy = {
 228                 .blit = &r100_copy_blit,
 229                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 230                 .dma = NULL,
 231                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 232                 .copy = &r100_copy_blit,
 233                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 234         },
 235         .surface = {
 236                 .set_reg = r100_set_surface_reg,
 237                 .clear_reg = r100_clear_surface_reg,
 238         },
 239         .hpd = {
 240                 .init = &r100_hpd_init,
 241                 .fini = &r100_hpd_fini,
 242                 .sense = &r100_hpd_sense,
 243                 .set_polarity = &r100_hpd_set_polarity,
 244         },
 245         .pm = {
 246                 .misc = &r100_pm_misc,
 247                 .prepare = &r100_pm_prepare,
 248                 .finish = &r100_pm_finish,
 249                 .init_profile = &r100_pm_init_profile,
 250                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 251                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 252                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 253                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 254                 .set_memory_clock = NULL,
 255                 .get_pcie_lanes = NULL,
 256                 .set_pcie_lanes = NULL,
 257                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 258         },
 259         .pflip = {
 260                 .page_flip = &r100_page_flip,
 261                 .page_flip_pending = &r100_page_flip_pending,
 262         },
 263 };
 264
 265 static struct radeon_asic r200_asic = {
 266         .init = &r100_init,
 267         .fini = &r100_fini,
 268         .suspend = &r100_suspend,
 269         .resume = &r100_resume,
 270         .vga_set_state = &r100_vga_set_state,
 271         .asic_reset = &r100_asic_reset,
 272         .mmio_hdp_flush = NULL,
 273         .gui_idle = &r100_gui_idle,
 274         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 275         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
 276         .gart = {
 277                 .tlb_flush = &r100_pci_gart_tlb_flush,
 278                 .get_page_entry = &r100_pci_gart_get_page_entry,
 279                 .set_page = &r100_pci_gart_set_page,
 280         },
 281         .ring = {
 282                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
 283         },
 284         .irq = {
 285                 .set = &r100_irq_set,
 286                 .process = &r100_irq_process,
 287         },
 288         .display = {
 289                 .bandwidth_update = &r100_bandwidth_update,
 290                 .get_vblank_counter = &r100_get_vblank_counter,
 291                 .wait_for_vblank = &r100_wait_for_vblank,
 292                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 293                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 294         },
 295         .copy = {
 296                 .blit = &r100_copy_blit,
 297                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 298                 .dma = &r200_copy_dma,
 299                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 300                 .copy = &r100_copy_blit,
 301                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 302         },
 303         .surface = {
 304                 .set_reg = r100_set_surface_reg,
 305                 .clear_reg = r100_clear_surface_reg,
 306         },
 307         .hpd = {
 308                 .init = &r100_hpd_init,
 309                 .fini = &r100_hpd_fini,
 310                 .sense = &r100_hpd_sense,
 311                 .set_polarity = &r100_hpd_set_polarity,
 312         },
 313         .pm = {
 314                 .misc = &r100_pm_misc,
 315                 .prepare = &r100_pm_prepare,
 316                 .finish = &r100_pm_finish,
 317                 .init_profile = &r100_pm_init_profile,
 318                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 319                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 320                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 321                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 322                 .set_memory_clock = NULL,
 323                 .get_pcie_lanes = NULL,
 324                 .set_pcie_lanes = NULL,
 325                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 326         },
 327         .pflip = {
 328                 .page_flip = &r100_page_flip,
 329                 .page_flip_pending = &r100_page_flip_pending,
 330         },
 331 };
 332
 333 static struct radeon_asic_ring r300_gfx_ring = {
 334         .ib_execute = &r100_ring_ib_execute,
 335         .emit_fence = &r300_fence_ring_emit,
 336         .emit_semaphore = &r100_semaphore_ring_emit,
 337         .cs_parse = &r300_cs_parse,
 338         .ring_start = &r300_ring_start,
 339         .ring_test = &r100_ring_test,
 340         .ib_test = &r100_ib_test,
 341         .is_lockup = &r100_gpu_is_lockup,
 342         .get_rptr = &r100_gfx_get_rptr,
 343         .get_wptr = &r100_gfx_get_wptr,
 344         .set_wptr = &r100_gfx_set_wptr,
 345 };
 346
 347 static struct radeon_asic_ring rv515_gfx_ring = {
 348         .ib_execute = &r100_ring_ib_execute,
 349         .emit_fence = &r300_fence_ring_emit,
 350         .emit_semaphore = &r100_semaphore_ring_emit,
 351         .cs_parse = &r300_cs_parse,
 352         .ring_start = &rv515_ring_start,
 353         .ring_test = &r100_ring_test,
 354         .ib_test = &r100_ib_test,
 355         .is_lockup = &r100_gpu_is_lockup,
 356         .get_rptr = &r100_gfx_get_rptr,
 357         .get_wptr = &r100_gfx_get_wptr,
 358         .set_wptr = &r100_gfx_set_wptr,
 359 };
 360
 361 static struct radeon_asic r300_asic = {
 362         .init = &r300_init,
 363         .fini = &r300_fini,
 364         .suspend = &r300_suspend,
 365         .resume = &r300_resume,
 366         .vga_set_state = &r100_vga_set_state,
 367         .asic_reset = &r300_asic_reset,
 368         .mmio_hdp_flush = NULL,
 369         .gui_idle = &r100_gui_idle,
 370         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 371         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
 372         .gart = {
 373                 .tlb_flush = &r100_pci_gart_tlb_flush,
 374                 .get_page_entry = &r100_pci_gart_get_page_entry,
 375                 .set_page = &r100_pci_gart_set_page,
 376         },
 377         .ring = {
 378                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 379         },
 380         .irq = {
 381                 .set = &r100_irq_set,
 382                 .process = &r100_irq_process,
 383         },
 384         .display = {
 385                 .bandwidth_update = &r100_bandwidth_update,
 386                 .get_vblank_counter = &r100_get_vblank_counter,
 387                 .wait_for_vblank = &r100_wait_for_vblank,
 388                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 389                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 390         },
 391         .copy = {
 392                 .blit = &r100_copy_blit,
 393                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 394                 .dma = &r200_copy_dma,
 395                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 396                 .copy = &r100_copy_blit,
 397                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 398         },
 399         .surface = {
 400                 .set_reg = r100_set_surface_reg,
 401                 .clear_reg = r100_clear_surface_reg,
 402         },
 403         .hpd = {
 404                 .init = &r100_hpd_init,
 405                 .fini = &r100_hpd_fini,
 406                 .sense = &r100_hpd_sense,
 407                 .set_polarity = &r100_hpd_set_polarity,
 408         },
 409         .pm = {
 410                 .misc = &r100_pm_misc,
 411                 .prepare = &r100_pm_prepare,
 412                 .finish = &r100_pm_finish,
 413                 .init_profile = &r100_pm_init_profile,
 414                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 415                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 416                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 417                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 418                 .set_memory_clock = NULL,
 419                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 420                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 421                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 422         },
 423         .pflip = {
 424                 .page_flip = &r100_page_flip,
 425                 .page_flip_pending = &r100_page_flip_pending,
 426         },
 427 };
 428
 429 static struct radeon_asic r300_asic_pcie = {
 430         .init = &r300_init,
 431         .fini = &r300_fini,
 432         .suspend = &r300_suspend,
 433         .resume = &r300_resume,
 434         .vga_set_state = &r100_vga_set_state,
 435         .asic_reset = &r300_asic_reset,
 436         .mmio_hdp_flush = NULL,
 437         .gui_idle = &r100_gui_idle,
 438         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 439         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
 440         .gart = {
 441                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 442                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
 443                 .set_page = &rv370_pcie_gart_set_page,
 444         },
 445         .ring = {
 446                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 447         },
 448         .irq = {
 449                 .set = &r100_irq_set,
 450                 .process = &r100_irq_process,
 451         },
 452         .display = {
 453                 .bandwidth_update = &r100_bandwidth_update,
 454                 .get_vblank_counter = &r100_get_vblank_counter,
 455                 .wait_for_vblank = &r100_wait_for_vblank,
 456                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 457                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 458         },
 459         .copy = {
 460                 .blit = &r100_copy_blit,
 461                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 462                 .dma = &r200_copy_dma,
 463                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 464                 .copy = &r100_copy_blit,
 465                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 466         },
 467         .surface = {
 468                 .set_reg = r100_set_surface_reg,
 469                 .clear_reg = r100_clear_surface_reg,
 470         },
 471         .hpd = {
 472                 .init = &r100_hpd_init,
 473                 .fini = &r100_hpd_fini,
 474                 .sense = &r100_hpd_sense,
 475                 .set_polarity = &r100_hpd_set_polarity,
 476         },
 477         .pm = {
 478                 .misc = &r100_pm_misc,
 479                 .prepare = &r100_pm_prepare,
 480                 .finish = &r100_pm_finish,
 481                 .init_profile = &r100_pm_init_profile,
 482                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 483                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 484                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 485                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 486                 .set_memory_clock = NULL,
 487                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 488                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 489                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 490         },
 491         .pflip = {
 492                 .page_flip = &r100_page_flip,
 493                 .page_flip_pending = &r100_page_flip_pending,
 494         },
 495 };
 496
 497 static struct radeon_asic r420_asic = {
 498         .init = &r420_init,
 499         .fini = &r420_fini,
 500         .suspend = &r420_suspend,
 501         .resume = &r420_resume,
 502         .vga_set_state = &r100_vga_set_state,
 503         .asic_reset = &r300_asic_reset,
 504         .mmio_hdp_flush = NULL,
 505         .gui_idle = &r100_gui_idle,
 506         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 507         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
 508         .gart = {
 509                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 510                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
 511                 .set_page = &rv370_pcie_gart_set_page,
 512         },
 513         .ring = {
 514                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 515         },
 516         .irq = {
 517                 .set = &r100_irq_set,
 518                 .process = &r100_irq_process,
 519         },
 520         .display = {
 521                 .bandwidth_update = &r100_bandwidth_update,
 522                 .get_vblank_counter = &r100_get_vblank_counter,
 523                 .wait_for_vblank = &r100_wait_for_vblank,
 524                 .set_backlight_level = &atombios_set_backlight_level,
 525                 .get_backlight_level = &atombios_get_backlight_level,
 526         },
 527         .copy = {
 528                 .blit = &r100_copy_blit,
 529                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 530                 .dma = &r200_copy_dma,
 531                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 532                 .copy = &r100_copy_blit,
 533                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 534         },
 535         .surface = {
 536                 .set_reg = r100_set_surface_reg,
 537                 .clear_reg = r100_clear_surface_reg,
 538         },
 539         .hpd = {
 540                 .init = &r100_hpd_init,
 541                 .fini = &r100_hpd_fini,
 542                 .sense = &r100_hpd_sense,
 543                 .set_polarity = &r100_hpd_set_polarity,
 544         },
 545         .pm = {
 546                 .misc = &r100_pm_misc,
 547                 .prepare = &r100_pm_prepare,
 548                 .finish = &r100_pm_finish,
 549                 .init_profile = &r420_pm_init_profile,
 550                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 551                 .get_engine_clock = &radeon_atom_get_engine_clock,
 552                 .set_engine_clock = &radeon_atom_set_engine_clock,
 553                 .get_memory_clock = &radeon_atom_get_memory_clock,
 554                 .set_memory_clock = &radeon_atom_set_memory_clock,
 555                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 556                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 557                 .set_clock_gating = &radeon_atom_set_clock_gating,
 558         },
 559         .pflip = {
 560                 .page_flip = &r100_page_flip,
 561                 .page_flip_pending = &r100_page_flip_pending,
 562         },
 563 };
 564
 565 static struct radeon_asic rs400_asic = {
 566         .init = &rs400_init,
 567         .fini = &rs400_fini,
 568         .suspend = &rs400_suspend,
 569         .resume = &rs400_resume,
 570         .vga_set_state = &r100_vga_set_state,
 571         .asic_reset = &r300_asic_reset,
 572         .mmio_hdp_flush = NULL,
 573         .gui_idle = &r100_gui_idle,
 574         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 575         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
 576         .gart = {
 577                 .tlb_flush = &rs400_gart_tlb_flush,
 578                 .get_page_entry = &rs400_gart_get_page_entry,
 579                 .set_page = &rs400_gart_set_page,
 580         },
 581         .ring = {
 582                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 583         },
 584         .irq = {
 585                 .set = &r100_irq_set,
 586                 .process = &r100_irq_process,
 587         },
 588         .display = {
 589                 .bandwidth_update = &r100_bandwidth_update,
 590                 .get_vblank_counter = &r100_get_vblank_counter,
 591                 .wait_for_vblank = &r100_wait_for_vblank,
 592                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 593                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 594         },
 595         .copy = {
 596                 .blit = &r100_copy_blit,
 597                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 598                 .dma = &r200_copy_dma,
 599                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 600                 .copy = &r100_copy_blit,
 601                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 602         },
 603         .surface = {
 604                 .set_reg = r100_set_surface_reg,
 605                 .clear_reg = r100_clear_surface_reg,
 606         },
 607         .hpd = {
 608                 .init = &r100_hpd_init,
 609                 .fini = &r100_hpd_fini,
 610                 .sense = &r100_hpd_sense,
 611                 .set_polarity = &r100_hpd_set_polarity,
 612         },
 613         .pm = {
 614                 .misc = &r100_pm_misc,
 615                 .prepare = &r100_pm_prepare,
 616                 .finish = &r100_pm_finish,
 617                 .init_profile = &r100_pm_init_profile,
 618                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 619                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 620                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 621                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 622                 .set_memory_clock = NULL,
 623                 .get_pcie_lanes = NULL,
 624                 .set_pcie_lanes = NULL,
 625                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 626         },
 627         .pflip = {
 628                 .page_flip = &r100_page_flip,
 629                 .page_flip_pending = &r100_page_flip_pending,
 630         },
 631 };
 632
 633 static struct radeon_asic rs600_asic = {
 634         .init = &rs600_init,
 635         .fini = &rs600_fini,
 636         .suspend = &rs600_suspend,
 637         .resume = &rs600_resume,
 638         .vga_set_state = &r100_vga_set_state,
 639         .asic_reset = &rs600_asic_reset,
 640         .mmio_hdp_flush = NULL,
 641         .gui_idle = &r100_gui_idle,
 642         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 643         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
 644         .gart = {
 645                 .tlb_flush = &rs600_gart_tlb_flush,
 646                 .get_page_entry = &rs600_gart_get_page_entry,
 647                 .set_page = &rs600_gart_set_page,
 648         },
 649         .ring = {
 650                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 651         },
 652         .irq = {
 653                 .set = &rs600_irq_set,
 654                 .process = &rs600_irq_process,
 655         },
 656         .display = {
 657                 .bandwidth_update = &rs600_bandwidth_update,
 658                 .get_vblank_counter = &rs600_get_vblank_counter,
 659                 .wait_for_vblank = &avivo_wait_for_vblank,
 660                 .set_backlight_level = &atombios_set_backlight_level,
 661                 .get_backlight_level = &atombios_get_backlight_level,
 662         },
 663         .copy = {
 664                 .blit = &r100_copy_blit,
 665                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 666                 .dma = &r200_copy_dma,
 667                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 668                 .copy = &r100_copy_blit,
 669                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 670         },
 671         .surface = {
 672                 .set_reg = r100_set_surface_reg,
 673                 .clear_reg = r100_clear_surface_reg,
 674         },
 675         .hpd = {
 676                 .init = &rs600_hpd_init,
 677                 .fini = &rs600_hpd_fini,
 678                 .sense = &rs600_hpd_sense,
 679                 .set_polarity = &rs600_hpd_set_polarity,
 680         },
 681         .pm = {
 682                 .misc = &rs600_pm_misc,
 683                 .prepare = &rs600_pm_prepare,
 684                 .finish = &rs600_pm_finish,
 685                 .init_profile = &r420_pm_init_profile,
 686                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 687                 .get_engine_clock = &radeon_atom_get_engine_clock,
 688                 .set_engine_clock = &radeon_atom_set_engine_clock,
 689                 .get_memory_clock = &radeon_atom_get_memory_clock,
 690                 .set_memory_clock = &radeon_atom_set_memory_clock,
 691                 .get_pcie_lanes = NULL,
 692                 .set_pcie_lanes = NULL,
 693                 .set_clock_gating = &radeon_atom_set_clock_gating,
 694         },
 695         .pflip = {
 696                 .page_flip = &rs600_page_flip,
 697                 .page_flip_pending = &rs600_page_flip_pending,
 698         },
 699 };
 700
 701 static struct radeon_asic rs690_asic = {
 702         .init = &rs690_init,
 703         .fini = &rs690_fini,
 704         .suspend = &rs690_suspend,
 705         .resume = &rs690_resume,
 706         .vga_set_state = &r100_vga_set_state,
 707         .asic_reset = &rs600_asic_reset,
 708         .mmio_hdp_flush = NULL,
 709         .gui_idle = &r100_gui_idle,
 710         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 711         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
 712         .gart = {
 713                 .tlb_flush = &rs400_gart_tlb_flush,
 714                 .get_page_entry = &rs400_gart_get_page_entry,
 715                 .set_page = &rs400_gart_set_page,
 716         },
 717         .ring = {
 718                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 719         },
 720         .irq = {
 721                 .set = &rs600_irq_set,
 722                 .process = &rs600_irq_process,
 723         },
 724         .display = {
 725                 .get_vblank_counter = &rs600_get_vblank_counter,
 726                 .bandwidth_update = &rs690_bandwidth_update,
 727                 .wait_for_vblank = &avivo_wait_for_vblank,
 728                 .set_backlight_level = &atombios_set_backlight_level,
 729                 .get_backlight_level = &atombios_get_backlight_level,
 730         },
 731         .copy = {
 732                 .blit = &r100_copy_blit,
 733                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 734                 .dma = &r200_copy_dma,
 735                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 736                 .copy = &r200_copy_dma,
 737                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 738         },
 739         .surface = {
 740                 .set_reg = r100_set_surface_reg,
 741                 .clear_reg = r100_clear_surface_reg,
 742         },
 743         .hpd = {
 744                 .init = &rs600_hpd_init,
 745                 .fini = &rs600_hpd_fini,
 746                 .sense = &rs600_hpd_sense,
 747                 .set_polarity = &rs600_hpd_set_polarity,
 748         },
 749         .pm = {
 750                 .misc = &rs600_pm_misc,
 751                 .prepare = &rs600_pm_prepare,
 752                 .finish = &rs600_pm_finish,
 753                 .init_profile = &r420_pm_init_profile,
 754                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 755                 .get_engine_clock = &radeon_atom_get_engine_clock,
 756                 .set_engine_clock = &radeon_atom_set_engine_clock,
 757                 .get_memory_clock = &radeon_atom_get_memory_clock,
 758                 .set_memory_clock = &radeon_atom_set_memory_clock,
 759                 .get_pcie_lanes = NULL,
 760                 .set_pcie_lanes = NULL,
 761                 .set_clock_gating = &radeon_atom_set_clock_gating,
 762         },
 763         .pflip = {
 764                 .page_flip = &rs600_page_flip,
 765                 .page_flip_pending = &rs600_page_flip_pending,
 766         },
 767 };
 768
 769 static struct radeon_asic rv515_asic = {
 770         .init = &rv515_init,
 771         .fini = &rv515_fini,
 772         .suspend = &rv515_suspend,
 773         .resume = &rv515_resume,
 774         .vga_set_state = &r100_vga_set_state,
 775         .asic_reset = &rs600_asic_reset,
 776         .mmio_hdp_flush = NULL,
 777         .gui_idle = &r100_gui_idle,
 778         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 779         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
 780         .gart = {
 781                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 782                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
 783                 .set_page = &rv370_pcie_gart_set_page,
 784         },
 785         .ring = {
 786                 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
 787         },
 788         .irq = {
 789                 .set = &rs600_irq_set,
 790                 .process = &rs600_irq_process,
 791         },
 792         .display = {
 793                 .get_vblank_counter = &rs600_get_vblank_counter,
 794                 .bandwidth_update = &rv515_bandwidth_update,
 795                 .wait_for_vblank = &avivo_wait_for_vblank,
 796                 .set_backlight_level = &atombios_set_backlight_level,
 797                 .get_backlight_level = &atombios_get_backlight_level,
 798         },
 799         .copy = {
 800                 .blit = &r100_copy_blit,
 801                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 802                 .dma = &r200_copy_dma,
 803                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 804                 .copy = &r100_copy_blit,
 805                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 806         },
 807         .surface = {
 808                 .set_reg = r100_set_surface_reg,
 809                 .clear_reg = r100_clear_surface_reg,
 810         },
 811         .hpd = {
 812                 .init = &rs600_hpd_init,
 813                 .fini = &rs600_hpd_fini,
 814                 .sense = &rs600_hpd_sense,
 815                 .set_polarity = &rs600_hpd_set_polarity,
 816         },
 817         .pm = {
 818                 .misc = &rs600_pm_misc,
 819                 .prepare = &rs600_pm_prepare,
 820                 .finish = &rs600_pm_finish,
 821                 .init_profile = &r420_pm_init_profile,
 822                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 823                 .get_engine_clock = &radeon_atom_get_engine_clock,
 824                 .set_engine_clock = &radeon_atom_set_engine_clock,
 825                 .get_memory_clock = &radeon_atom_get_memory_clock,
 826                 .set_memory_clock = &radeon_atom_set_memory_clock,
 827                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 828                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 829                 .set_clock_gating = &radeon_atom_set_clock_gating,
 830         },
 831         .pflip = {
 832                 .page_flip = &rs600_page_flip,
 833                 .page_flip_pending = &rs600_page_flip_pending,
 834         },
 835 };
 836
 837 static struct radeon_asic r520_asic = {
 838         .init = &r520_init,
 839         .fini = &rv515_fini,
 840         .suspend = &rv515_suspend,
 841         .resume = &r520_resume,
 842         .vga_set_state = &r100_vga_set_state,
 843         .asic_reset = &rs600_asic_reset,
 844         .mmio_hdp_flush = NULL,
 845         .gui_idle = &r100_gui_idle,
 846         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 847         .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
 848         .gart = {
 849                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 850                 .get_page_entry = &rv370_pcie_gart_get_page_entry,
 851                 .set_page = &rv370_pcie_gart_set_page,
 852         },
 853         .ring = {
 854                 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
 855         },
 856         .irq = {
 857                 .set = &rs600_irq_set,
 858                 .process = &rs600_irq_process,
 859         },
 860         .display = {
 861                 .bandwidth_update = &rv515_bandwidth_update,
 862                 .get_vblank_counter = &rs600_get_vblank_counter,
 863                 .wait_for_vblank = &avivo_wait_for_vblank,
 864                 .set_backlight_level = &atombios_set_backlight_level,
 865                 .get_backlight_level = &atombios_get_backlight_level,
 866         },
 867         .copy = {
 868                 .blit = &r100_copy_blit,
 869                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 870                 .dma = &r200_copy_dma,
 871                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 872                 .copy = &r100_copy_blit,
 873                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 874         },
 875         .surface = {
 876                 .set_reg = r100_set_surface_reg,
 877                 .clear_reg = r100_clear_surface_reg,
 878         },
 879         .hpd = {
 880                 .init = &rs600_hpd_init,
 881                 .fini = &rs600_hpd_fini,
 882                 .sense = &rs600_hpd_sense,
 883                 .set_polarity = &rs600_hpd_set_polarity,
 884         },
 885         .pm = {
 886                 .misc = &rs600_pm_misc,
 887                 .prepare = &rs600_pm_prepare,
 888                 .finish = &rs600_pm_finish,
 889                 .init_profile = &r420_pm_init_profile,
 890                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 891                 .get_engine_clock = &radeon_atom_get_engine_clock,
 892                 .set_engine_clock = &radeon_atom_set_engine_clock,
 893                 .get_memory_clock = &radeon_atom_get_memory_clock,
 894                 .set_memory_clock = &radeon_atom_set_memory_clock,
 895                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 896                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 897                 .set_clock_gating = &radeon_atom_set_clock_gating,
 898         },
 899         .pflip = {
 900                 .page_flip = &rs600_page_flip,
 901                 .page_flip_pending = &rs600_page_flip_pending,
 902         },
 903 };
 904
 905 static struct radeon_asic_ring r600_gfx_ring = {
 906         .ib_execute = &r600_ring_ib_execute,
 907         .emit_fence = &r600_fence_ring_emit,
 908         .emit_semaphore = &r600_semaphore_ring_emit,
 909         .cs_parse = &r600_cs_parse,
 910         .ring_test = &r600_ring_test,
 911         .ib_test = &r600_ib_test,
 912         .is_lockup = &r600_gfx_is_lockup,
 913         .get_rptr = &r600_gfx_get_rptr,
 914         .get_wptr = &r600_gfx_get_wptr,
 915         .set_wptr = &r600_gfx_set_wptr,
 916 };
 917
 918 static struct radeon_asic_ring r600_dma_ring = {
 919         .ib_execute = &r600_dma_ring_ib_execute,
 920         .emit_fence = &r600_dma_fence_ring_emit,
 921         .emit_semaphore = &r600_dma_semaphore_ring_emit,
 922         .cs_parse = &r600_dma_cs_parse,
 923         .ring_test = &r600_dma_ring_test,
 924         .ib_test = &r600_dma_ib_test,
 925         .is_lockup = &r600_dma_is_lockup,
 926         .get_rptr = &r600_dma_get_rptr,
 927         .get_wptr = &r600_dma_get_wptr,
 928         .set_wptr = &r600_dma_set_wptr,
 929 };
 930
 931 static struct radeon_asic r600_asic = {
 932         .init = &r600_init,
 933         .fini = &r600_fini,
 934         .suspend = &r600_suspend,
 935         .resume = &r600_resume,
 936         .vga_set_state = &r600_vga_set_state,
 937         .asic_reset = &r600_asic_reset,
 938         .mmio_hdp_flush = r600_mmio_hdp_flush,
 939         .gui_idle = &r600_gui_idle,
 940         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 941         .get_xclk = &r600_get_xclk,
 942         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 943         .get_allowed_info_register = r600_get_allowed_info_register,
 944         .gart = {
 945                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 946                 .get_page_entry = &rs600_gart_get_page_entry,
 947                 .set_page = &rs600_gart_set_page,
 948         },
 949         .ring = {
 950                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
 951                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
 952         },
 953         .irq = {
 954                 .set = &r600_irq_set,
 955                 .process = &r600_irq_process,
 956         },
 957         .display = {
 958                 .bandwidth_update = &rv515_bandwidth_update,
 959                 .get_vblank_counter = &rs600_get_vblank_counter,
 960                 .wait_for_vblank = &avivo_wait_for_vblank,
 961                 .set_backlight_level = &atombios_set_backlight_level,
 962                 .get_backlight_level = &atombios_get_backlight_level,
 963         },
 964         .copy = {
 965                 .blit = &r600_copy_cpdma,
 966                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 967                 .dma = &r600_copy_dma,
 968                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
 969                 .copy = &r600_copy_cpdma,
 970                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 971         },
 972         .surface = {
 973                 .set_reg = r600_set_surface_reg,
 974                 .clear_reg = r600_clear_surface_reg,
 975         },
 976         .hpd = {
 977                 .init = &r600_hpd_init,
 978                 .fini = &r600_hpd_fini,
 979                 .sense = &r600_hpd_sense,
 980                 .set_polarity = &r600_hpd_set_polarity,
 981         },
 982         .pm = {
 983                 .misc = &r600_pm_misc,
 984                 .prepare = &rs600_pm_prepare,
 985                 .finish = &rs600_pm_finish,
 986                 .init_profile = &r600_pm_init_profile,
 987                 .get_dynpm_state = &r600_pm_get_dynpm_state,
 988                 .get_engine_clock = &radeon_atom_get_engine_clock,
 989                 .set_engine_clock = &radeon_atom_set_engine_clock,
 990                 .get_memory_clock = &radeon_atom_get_memory_clock,
 991                 .set_memory_clock = &radeon_atom_set_memory_clock,
 992                 .get_pcie_lanes = &r600_get_pcie_lanes,
 993                 .set_pcie_lanes = &r600_set_pcie_lanes,
 994                 .set_clock_gating = NULL,
 995                 .get_temperature = &rv6xx_get_temp,
 996         },
 997         .pflip = {
 998                 .page_flip = &rs600_page_flip,
 999                 .page_flip_pending = &rs600_page_flip_pending,
1000         },
1001 };
1002
1003 static struct radeon_asic_ring rv6xx_uvd_ring = {
1004         .ib_execute = &uvd_v1_0_ib_execute,
1005         .emit_fence = &uvd_v1_0_fence_emit,
1006         .emit_semaphore = &uvd_v1_0_semaphore_emit,
1007         .cs_parse = &radeon_uvd_cs_parse,
1008         .ring_test = &uvd_v1_0_ring_test,
1009         .ib_test = &uvd_v1_0_ib_test,
1010         .is_lockup = &radeon_ring_test_lockup,
1011         .get_rptr = &uvd_v1_0_get_rptr,
1012         .get_wptr = &uvd_v1_0_get_wptr,
1013         .set_wptr = &uvd_v1_0_set_wptr,
1014 };
1015
1016 static struct radeon_asic rv6xx_asic = {
1017         .init = &r600_init,
1018         .fini = &r600_fini,
1019         .suspend = &r600_suspend,
1020         .resume = &r600_resume,
1021         .vga_set_state = &r600_vga_set_state,
1022         .asic_reset = &r600_asic_reset,
1023         .mmio_hdp_flush = r600_mmio_hdp_flush,
1024         .gui_idle = &r600_gui_idle,
1025         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1026         .get_xclk = &r600_get_xclk,
1027         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1028         .get_allowed_info_register = r600_get_allowed_info_register,
1029         .gart = {
1030                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1031                 .get_page_entry = &rs600_gart_get_page_entry,
1032                 .set_page = &rs600_gart_set_page,
1033         },
1034         .ring = {
1035                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1036                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1037                 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1038         },
1039         .irq = {
1040                 .set = &r600_irq_set,
1041                 .process = &r600_irq_process,
1042         },
1043         .display = {
1044                 .bandwidth_update = &rv515_bandwidth_update,
1045                 .get_vblank_counter = &rs600_get_vblank_counter,
1046                 .wait_for_vblank = &avivo_wait_for_vblank,
1047                 .set_backlight_level = &atombios_set_backlight_level,
1048                 .get_backlight_level = &atombios_get_backlight_level,
1049         },
1050         .copy = {
1051                 .blit = &r600_copy_cpdma,
1052                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1053                 .dma = &r600_copy_dma,
1054                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1055                 .copy = &r600_copy_cpdma,
1056                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1057         },
1058         .surface = {
1059                 .set_reg = r600_set_surface_reg,
1060                 .clear_reg = r600_clear_surface_reg,
1061         },
1062         .hpd = {
1063                 .init = &r600_hpd_init,
1064                 .fini = &r600_hpd_fini,
1065                 .sense = &r600_hpd_sense,
1066                 .set_polarity = &r600_hpd_set_polarity,
1067         },
1068         .pm = {
1069                 .misc = &r600_pm_misc,
1070                 .prepare = &rs600_pm_prepare,
1071                 .finish = &rs600_pm_finish,
1072                 .init_profile = &r600_pm_init_profile,
1073                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1074                 .get_engine_clock = &radeon_atom_get_engine_clock,
1075                 .set_engine_clock = &radeon_atom_set_engine_clock,
1076                 .get_memory_clock = &radeon_atom_get_memory_clock,
1077                 .set_memory_clock = &radeon_atom_set_memory_clock,
1078                 .get_pcie_lanes = &r600_get_pcie_lanes,
1079                 .set_pcie_lanes = &r600_set_pcie_lanes,
1080                 .set_clock_gating = NULL,
1081                 .get_temperature = &rv6xx_get_temp,
1082                 .set_uvd_clocks = &r600_set_uvd_clocks,
1083         },
1084         .dpm = {
1085                 .init = &rv6xx_dpm_init,
1086                 .setup_asic = &rv6xx_setup_asic,
1087                 .enable = &rv6xx_dpm_enable,
1088                 .late_enable = &r600_dpm_late_enable,
1089                 .disable = &rv6xx_dpm_disable,
1090                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1091                 .set_power_state = &rv6xx_dpm_set_power_state,
1092                 .post_set_power_state = &r600_dpm_post_set_power_state,
1093                 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1094                 .fini = &rv6xx_dpm_fini,
1095                 .get_sclk = &rv6xx_dpm_get_sclk,
1096                 .get_mclk = &rv6xx_dpm_get_mclk,
1097                 .print_power_state = &rv6xx_dpm_print_power_state,
1098                 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1099                 .force_performance_level = &rv6xx_dpm_force_performance_level,
1100                 .get_current_sclk = &rv6xx_dpm_get_current_sclk,
1101                 .get_current_mclk = &rv6xx_dpm_get_current_mclk,
1102         },
1103         .pflip = {
1104                 .page_flip = &rs600_page_flip,
1105                 .page_flip_pending = &rs600_page_flip_pending,
1106         },
1107 };
1108
1109 static struct radeon_asic rs780_asic = {
1110         .init = &r600_init,
1111         .fini = &r600_fini,
1112         .suspend = &r600_suspend,
1113         .resume = &r600_resume,
1114         .vga_set_state = &r600_vga_set_state,
1115         .asic_reset = &r600_asic_reset,
1116         .mmio_hdp_flush = r600_mmio_hdp_flush,
1117         .gui_idle = &r600_gui_idle,
1118         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1119         .get_xclk = &r600_get_xclk,
1120         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1121         .get_allowed_info_register = r600_get_allowed_info_register,
1122         .gart = {
1123                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1124                 .get_page_entry = &rs600_gart_get_page_entry,
1125                 .set_page = &rs600_gart_set_page,
1126         },
1127         .ring = {
1128                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1129                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1130                 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1131         },
1132         .irq = {
1133                 .set = &r600_irq_set,
1134                 .process = &r600_irq_process,
1135         },
1136         .display = {
1137                 .bandwidth_update = &rs690_bandwidth_update,
1138                 .get_vblank_counter = &rs600_get_vblank_counter,
1139                 .wait_for_vblank = &avivo_wait_for_vblank,
1140                 .set_backlight_level = &atombios_set_backlight_level,
1141                 .get_backlight_level = &atombios_get_backlight_level,
1142         },
1143         .copy = {
1144                 .blit = &r600_copy_cpdma,
1145                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1146                 .dma = &r600_copy_dma,
1147                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1148                 .copy = &r600_copy_cpdma,
1149                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1150         },
1151         .surface = {
1152                 .set_reg = r600_set_surface_reg,
1153                 .clear_reg = r600_clear_surface_reg,
1154         },
1155         .hpd = {
1156                 .init = &r600_hpd_init,
1157                 .fini = &r600_hpd_fini,
1158                 .sense = &r600_hpd_sense,
1159                 .set_polarity = &r600_hpd_set_polarity,
1160         },
1161         .pm = {
1162                 .misc = &r600_pm_misc,
1163                 .prepare = &rs600_pm_prepare,
1164                 .finish = &rs600_pm_finish,
1165                 .init_profile = &rs780_pm_init_profile,
1166                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1167                 .get_engine_clock = &radeon_atom_get_engine_clock,
1168                 .set_engine_clock = &radeon_atom_set_engine_clock,
1169                 .get_memory_clock = NULL,
1170                 .set_memory_clock = NULL,
1171                 .get_pcie_lanes = NULL,
1172                 .set_pcie_lanes = NULL,
1173                 .set_clock_gating = NULL,
1174                 .get_temperature = &rv6xx_get_temp,
1175                 .set_uvd_clocks = &r600_set_uvd_clocks,
1176         },
1177         .dpm = {
1178                 .init = &rs780_dpm_init,
1179                 .setup_asic = &rs780_dpm_setup_asic,
1180                 .enable = &rs780_dpm_enable,
1181                 .late_enable = &r600_dpm_late_enable,
1182                 .disable = &rs780_dpm_disable,
1183                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1184                 .set_power_state = &rs780_dpm_set_power_state,
1185                 .post_set_power_state = &r600_dpm_post_set_power_state,
1186                 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1187                 .fini = &rs780_dpm_fini,
1188                 .get_sclk = &rs780_dpm_get_sclk,
1189                 .get_mclk = &rs780_dpm_get_mclk,
1190                 .print_power_state = &rs780_dpm_print_power_state,
1191                 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1192                 .force_performance_level = &rs780_dpm_force_performance_level,
1193                 .get_current_sclk = &rs780_dpm_get_current_sclk,
1194                 .get_current_mclk = &rs780_dpm_get_current_mclk,
1195         },
1196         .pflip = {
1197                 .page_flip = &rs600_page_flip,
1198                 .page_flip_pending = &rs600_page_flip_pending,
1199         },
1200 };
1201
1202 static struct radeon_asic_ring rv770_uvd_ring = {
1203         .ib_execute = &uvd_v1_0_ib_execute,
1204         .emit_fence = &uvd_v2_2_fence_emit,
1205         .emit_semaphore = &uvd_v2_2_semaphore_emit,
1206         .cs_parse = &radeon_uvd_cs_parse,
1207         .ring_test = &uvd_v1_0_ring_test,
1208         .ib_test = &uvd_v1_0_ib_test,
1209         .is_lockup = &radeon_ring_test_lockup,
1210         .get_rptr = &uvd_v1_0_get_rptr,
1211         .get_wptr = &uvd_v1_0_get_wptr,
1212         .set_wptr = &uvd_v1_0_set_wptr,
1213 };
1214
1215 static struct radeon_asic rv770_asic = {
1216         .init = &rv770_init,
1217         .fini = &rv770_fini,
1218         .suspend = &rv770_suspend,
1219         .resume = &rv770_resume,
1220         .asic_reset = &r600_asic_reset,
1221         .vga_set_state = &r600_vga_set_state,
1222         .mmio_hdp_flush = r600_mmio_hdp_flush,
1223         .gui_idle = &r600_gui_idle,
1224         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1225         .get_xclk = &rv770_get_xclk,
1226         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1227         .get_allowed_info_register = r600_get_allowed_info_register,
1228         .gart = {
1229                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1230                 .get_page_entry = &rs600_gart_get_page_entry,
1231                 .set_page = &rs600_gart_set_page,
1232         },
1233         .ring = {
1234                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1235                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1236                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1237         },
1238         .irq = {
1239                 .set = &r600_irq_set,
1240                 .process = &r600_irq_process,
1241         },
1242         .display = {
1243                 .bandwidth_update = &rv515_bandwidth_update,
1244                 .get_vblank_counter = &rs600_get_vblank_counter,
1245                 .wait_for_vblank = &avivo_wait_for_vblank,
1246                 .set_backlight_level = &atombios_set_backlight_level,
1247                 .get_backlight_level = &atombios_get_backlight_level,
1248         },
1249         .copy = {
1250                 .blit = &r600_copy_cpdma,
1251                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1252                 .dma = &rv770_copy_dma,
1253                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1254                 .copy = &rv770_copy_dma,
1255                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1256         },
1257         .surface = {
1258                 .set_reg = r600_set_surface_reg,
1259                 .clear_reg = r600_clear_surface_reg,
1260         },
1261         .hpd = {
1262                 .init = &r600_hpd_init,
1263                 .fini = &r600_hpd_fini,
1264                 .sense = &r600_hpd_sense,
1265                 .set_polarity = &r600_hpd_set_polarity,
1266         },
1267         .pm = {
1268                 .misc = &rv770_pm_misc,
1269                 .prepare = &rs600_pm_prepare,
1270                 .finish = &rs600_pm_finish,
1271                 .init_profile = &r600_pm_init_profile,
1272                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1273                 .get_engine_clock = &radeon_atom_get_engine_clock,
1274                 .set_engine_clock = &radeon_atom_set_engine_clock,
1275                 .get_memory_clock = &radeon_atom_get_memory_clock,
1276                 .set_memory_clock = &radeon_atom_set_memory_clock,
1277                 .get_pcie_lanes = &r600_get_pcie_lanes,
1278                 .set_pcie_lanes = &r600_set_pcie_lanes,
1279                 .set_clock_gating = &radeon_atom_set_clock_gating,
1280                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1281                 .get_temperature = &rv770_get_temp,
1282         },
1283         .dpm = {
1284                 .init = &rv770_dpm_init,
1285                 .setup_asic = &rv770_dpm_setup_asic,
1286                 .enable = &rv770_dpm_enable,
1287                 .late_enable = &rv770_dpm_late_enable,
1288                 .disable = &rv770_dpm_disable,
1289                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1290                 .set_power_state = &rv770_dpm_set_power_state,
1291                 .post_set_power_state = &r600_dpm_post_set_power_state,
1292                 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1293                 .fini = &rv770_dpm_fini,
1294                 .get_sclk = &rv770_dpm_get_sclk,
1295                 .get_mclk = &rv770_dpm_get_mclk,
1296                 .print_power_state = &rv770_dpm_print_power_state,
1297                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1298                 .force_performance_level = &rv770_dpm_force_performance_level,
1299                 .vblank_too_short = &rv770_dpm_vblank_too_short,
1300                 .get_current_sclk = &rv770_dpm_get_current_sclk,
1301                 .get_current_mclk = &rv770_dpm_get_current_mclk,
1302         },
1303         .pflip = {
1304                 .page_flip = &rv770_page_flip,
1305                 .page_flip_pending = &rv770_page_flip_pending,
1306         },
1307 };
1308
1309 static struct radeon_asic_ring evergreen_gfx_ring = {
1310         .ib_execute = &evergreen_ring_ib_execute,
1311         .emit_fence = &r600_fence_ring_emit,
1312         .emit_semaphore = &r600_semaphore_ring_emit,
1313         .cs_parse = &evergreen_cs_parse,
1314         .ring_test = &r600_ring_test,
1315         .ib_test = &r600_ib_test,
1316         .is_lockup = &evergreen_gfx_is_lockup,
1317         .get_rptr = &r600_gfx_get_rptr,
1318         .get_wptr = &r600_gfx_get_wptr,
1319         .set_wptr = &r600_gfx_set_wptr,
1320 };
1321
1322 static struct radeon_asic_ring evergreen_dma_ring = {
1323         .ib_execute = &evergreen_dma_ring_ib_execute,
1324         .emit_fence = &evergreen_dma_fence_ring_emit,
1325         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1326         .cs_parse = &evergreen_dma_cs_parse,
1327         .ring_test = &r600_dma_ring_test,
1328         .ib_test = &r600_dma_ib_test,
1329         .is_lockup = &evergreen_dma_is_lockup,
1330         .get_rptr = &r600_dma_get_rptr,
1331         .get_wptr = &r600_dma_get_wptr,
1332         .set_wptr = &r600_dma_set_wptr,
1333 };
1334
1335 static struct radeon_asic evergreen_asic = {
1336         .init = &evergreen_init,
1337         .fini = &evergreen_fini,
1338         .suspend = &evergreen_suspend,
1339         .resume = &evergreen_resume,
1340         .asic_reset = &evergreen_asic_reset,
1341         .vga_set_state = &r600_vga_set_state,
1342         .mmio_hdp_flush = r600_mmio_hdp_flush,
1343         .gui_idle = &r600_gui_idle,
1344         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1345         .get_xclk = &rv770_get_xclk,
1346         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1347         .get_allowed_info_register = evergreen_get_allowed_info_register,
1348         .gart = {
1349                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1350                 .get_page_entry = &rs600_gart_get_page_entry,
1351                 .set_page = &rs600_gart_set_page,
1352         },
1353         .ring = {
1354                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1355                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1356                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1357         },
1358         .irq = {
1359                 .set = &evergreen_irq_set,
1360                 .process = &evergreen_irq_process,
1361         },
1362         .display = {
1363                 .bandwidth_update = &evergreen_bandwidth_update,
1364                 .get_vblank_counter = &evergreen_get_vblank_counter,
1365                 .wait_for_vblank = &dce4_wait_for_vblank,
1366                 .set_backlight_level = &atombios_set_backlight_level,
1367                 .get_backlight_level = &atombios_get_backlight_level,
1368         },
1369         .copy = {
1370                 .blit = &r600_copy_cpdma,
1371                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1372                 .dma = &evergreen_copy_dma,
1373                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1374                 .copy = &evergreen_copy_dma,
1375                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1376         },
1377         .surface = {
1378                 .set_reg = r600_set_surface_reg,
1379                 .clear_reg = r600_clear_surface_reg,
1380         },
1381         .hpd = {
1382                 .init = &evergreen_hpd_init,
1383                 .fini = &evergreen_hpd_fini,
1384                 .sense = &evergreen_hpd_sense,
1385                 .set_polarity = &evergreen_hpd_set_polarity,
1386         },
1387         .pm = {
1388                 .misc = &evergreen_pm_misc,
1389                 .prepare = &evergreen_pm_prepare,
1390                 .finish = &evergreen_pm_finish,
1391                 .init_profile = &r600_pm_init_profile,
1392                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1393                 .get_engine_clock = &radeon_atom_get_engine_clock,
1394                 .set_engine_clock = &radeon_atom_set_engine_clock,
1395                 .get_memory_clock = &radeon_atom_get_memory_clock,
1396                 .set_memory_clock = &radeon_atom_set_memory_clock,
1397                 .get_pcie_lanes = &r600_get_pcie_lanes,
1398                 .set_pcie_lanes = &r600_set_pcie_lanes,
1399                 .set_clock_gating = NULL,
1400                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1401                 .get_temperature = &evergreen_get_temp,
1402         },
1403         .dpm = {
1404                 .init = &cypress_dpm_init,
1405                 .setup_asic = &cypress_dpm_setup_asic,
1406                 .enable = &cypress_dpm_enable,
1407                 .late_enable = &rv770_dpm_late_enable,
1408                 .disable = &cypress_dpm_disable,
1409                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1410                 .set_power_state = &cypress_dpm_set_power_state,
1411                 .post_set_power_state = &r600_dpm_post_set_power_state,
1412                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1413                 .fini = &cypress_dpm_fini,
1414                 .get_sclk = &rv770_dpm_get_sclk,
1415                 .get_mclk = &rv770_dpm_get_mclk,
1416                 .print_power_state = &rv770_dpm_print_power_state,
1417                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1418                 .force_performance_level = &rv770_dpm_force_performance_level,
1419                 .vblank_too_short = &cypress_dpm_vblank_too_short,
1420                 .get_current_sclk = &rv770_dpm_get_current_sclk,
1421                 .get_current_mclk = &rv770_dpm_get_current_mclk,
1422         },
1423         .pflip = {
1424                 .page_flip = &evergreen_page_flip,
1425                 .page_flip_pending = &evergreen_page_flip_pending,
1426         },
1427 };
1428
1429 static struct radeon_asic sumo_asic = {
1430         .init = &evergreen_init,
1431         .fini = &evergreen_fini,
1432         .suspend = &evergreen_suspend,
1433         .resume = &evergreen_resume,
1434         .asic_reset = &evergreen_asic_reset,
1435         .vga_set_state = &r600_vga_set_state,
1436         .mmio_hdp_flush = r600_mmio_hdp_flush,
1437         .gui_idle = &r600_gui_idle,
1438         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1439         .get_xclk = &r600_get_xclk,
1440         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1441         .get_allowed_info_register = evergreen_get_allowed_info_register,
1442         .gart = {
1443                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1444                 .get_page_entry = &rs600_gart_get_page_entry,
1445                 .set_page = &rs600_gart_set_page,
1446         },
1447         .ring = {
1448                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1449                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1450                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1451         },
1452         .irq = {
1453                 .set = &evergreen_irq_set,
1454                 .process = &evergreen_irq_process,
1455         },
1456         .display = {
1457                 .bandwidth_update = &evergreen_bandwidth_update,
1458                 .get_vblank_counter = &evergreen_get_vblank_counter,
1459                 .wait_for_vblank = &dce4_wait_for_vblank,
1460                 .set_backlight_level = &atombios_set_backlight_level,
1461                 .get_backlight_level = &atombios_get_backlight_level,
1462         },
1463         .copy = {
1464                 .blit = &r600_copy_cpdma,
1465                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1466                 .dma = &evergreen_copy_dma,
1467                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1468                 .copy = &evergreen_copy_dma,
1469                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1470         },
1471         .surface = {
1472                 .set_reg = r600_set_surface_reg,
1473                 .clear_reg = r600_clear_surface_reg,
1474         },
1475         .hpd = {
1476                 .init = &evergreen_hpd_init,
1477                 .fini = &evergreen_hpd_fini,
1478                 .sense = &evergreen_hpd_sense,
1479                 .set_polarity = &evergreen_hpd_set_polarity,
1480         },
1481         .pm = {
1482                 .misc = &evergreen_pm_misc,
1483                 .prepare = &evergreen_pm_prepare,
1484                 .finish = &evergreen_pm_finish,
1485                 .init_profile = &sumo_pm_init_profile,
1486                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1487                 .get_engine_clock = &radeon_atom_get_engine_clock,
1488                 .set_engine_clock = &radeon_atom_set_engine_clock,
1489                 .get_memory_clock = NULL,
1490                 .set_memory_clock = NULL,
1491                 .get_pcie_lanes = NULL,
1492                 .set_pcie_lanes = NULL,
1493                 .set_clock_gating = NULL,
1494                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1495                 .get_temperature = &sumo_get_temp,
1496         },
1497         .dpm = {
1498                 .init = &sumo_dpm_init,
1499                 .setup_asic = &sumo_dpm_setup_asic,
1500                 .enable = &sumo_dpm_enable,
1501                 .late_enable = &sumo_dpm_late_enable,
1502                 .disable = &sumo_dpm_disable,
1503                 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1504                 .set_power_state = &sumo_dpm_set_power_state,
1505                 .post_set_power_state = &sumo_dpm_post_set_power_state,
1506                 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1507                 .fini = &sumo_dpm_fini,
1508                 .get_sclk = &sumo_dpm_get_sclk,
1509                 .get_mclk = &sumo_dpm_get_mclk,
1510                 .print_power_state = &sumo_dpm_print_power_state,
1511                 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1512                 .force_performance_level = &sumo_dpm_force_performance_level,
1513                 .get_current_sclk = &sumo_dpm_get_current_sclk,
1514                 .get_current_mclk = &sumo_dpm_get_current_mclk,
1515         },
1516         .pflip = {
1517                 .page_flip = &evergreen_page_flip,
1518                 .page_flip_pending = &evergreen_page_flip_pending,
1519         },
1520 };
1521
1522 static struct radeon_asic btc_asic = {
1523         .init = &evergreen_init,
1524         .fini = &evergreen_fini,
1525         .suspend = &evergreen_suspend,
1526         .resume = &evergreen_resume,
1527         .asic_reset = &evergreen_asic_reset,
1528         .vga_set_state = &r600_vga_set_state,
1529         .mmio_hdp_flush = r600_mmio_hdp_flush,
1530         .gui_idle = &r600_gui_idle,
1531         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1532         .get_xclk = &rv770_get_xclk,
1533         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1534         .get_allowed_info_register = evergreen_get_allowed_info_register,
1535         .gart = {
1536                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1537                 .get_page_entry = &rs600_gart_get_page_entry,
1538                 .set_page = &rs600_gart_set_page,
1539         },
1540         .ring = {
1541                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1542                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1543                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1544         },
1545         .irq = {
1546                 .set = &evergreen_irq_set,
1547                 .process = &evergreen_irq_process,
1548         },
1549         .display = {
1550                 .bandwidth_update = &evergreen_bandwidth_update,
1551                 .get_vblank_counter = &evergreen_get_vblank_counter,
1552                 .wait_for_vblank = &dce4_wait_for_vblank,
1553                 .set_backlight_level = &atombios_set_backlight_level,
1554                 .get_backlight_level = &atombios_get_backlight_level,
1555         },
1556         .copy = {
1557                 .blit = &r600_copy_cpdma,
1558                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1559                 .dma = &evergreen_copy_dma,
1560                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1561                 .copy = &evergreen_copy_dma,
1562                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1563         },
1564         .surface = {
1565                 .set_reg = r600_set_surface_reg,
1566                 .clear_reg = r600_clear_surface_reg,
1567         },
1568         .hpd = {
1569                 .init = &evergreen_hpd_init,
1570                 .fini = &evergreen_hpd_fini,
1571                 .sense = &evergreen_hpd_sense,
1572                 .set_polarity = &evergreen_hpd_set_polarity,
1573         },
1574         .pm = {
1575                 .misc = &evergreen_pm_misc,
1576                 .prepare = &evergreen_pm_prepare,
1577                 .finish = &evergreen_pm_finish,
1578                 .init_profile = &btc_pm_init_profile,
1579                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1580                 .get_engine_clock = &radeon_atom_get_engine_clock,
1581                 .set_engine_clock = &radeon_atom_set_engine_clock,
1582                 .get_memory_clock = &radeon_atom_get_memory_clock,
1583                 .set_memory_clock = &radeon_atom_set_memory_clock,
1584                 .get_pcie_lanes = &r600_get_pcie_lanes,
1585                 .set_pcie_lanes = &r600_set_pcie_lanes,
1586                 .set_clock_gating = NULL,
1587                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1588                 .get_temperature = &evergreen_get_temp,
1589         },
1590         .dpm = {
1591                 .init = &btc_dpm_init,
1592                 .setup_asic = &btc_dpm_setup_asic,
1593                 .enable = &btc_dpm_enable,
1594                 .late_enable = &rv770_dpm_late_enable,
1595                 .disable = &btc_dpm_disable,
1596                 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1597                 .set_power_state = &btc_dpm_set_power_state,
1598                 .post_set_power_state = &btc_dpm_post_set_power_state,
1599                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1600                 .fini = &btc_dpm_fini,
1601                 .get_sclk = &btc_dpm_get_sclk,
1602                 .get_mclk = &btc_dpm_get_mclk,
1603                 .print_power_state = &rv770_dpm_print_power_state,
1604                 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
1605                 .force_performance_level = &rv770_dpm_force_performance_level,
1606                 .vblank_too_short = &btc_dpm_vblank_too_short,
1607                 .get_current_sclk = &btc_dpm_get_current_sclk,
1608                 .get_current_mclk = &btc_dpm_get_current_mclk,
1609         },
1610         .pflip = {
1611                 .page_flip = &evergreen_page_flip,
1612                 .page_flip_pending = &evergreen_page_flip_pending,
1613         },
1614 };
1615
1616 static struct radeon_asic_ring cayman_gfx_ring = {
1617         .ib_execute = &cayman_ring_ib_execute,
1618         .ib_parse = &evergreen_ib_parse,
1619         .emit_fence = &cayman_fence_ring_emit,
1620         .emit_semaphore = &r600_semaphore_ring_emit,
1621         .cs_parse = &evergreen_cs_parse,
1622         .ring_test = &r600_ring_test,
1623         .ib_test = &r600_ib_test,
1624         .is_lockup = &cayman_gfx_is_lockup,
1625         .vm_flush = &cayman_vm_flush,
1626         .get_rptr = &cayman_gfx_get_rptr,
1627         .get_wptr = &cayman_gfx_get_wptr,
1628         .set_wptr = &cayman_gfx_set_wptr,
1629 };
1630
1631 static struct radeon_asic_ring cayman_dma_ring = {
1632         .ib_execute = &cayman_dma_ring_ib_execute,
1633         .ib_parse = &evergreen_dma_ib_parse,
1634         .emit_fence = &evergreen_dma_fence_ring_emit,
1635         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1636         .cs_parse = &evergreen_dma_cs_parse,
1637         .ring_test = &r600_dma_ring_test,
1638         .ib_test = &r600_dma_ib_test,
1639         .is_lockup = &cayman_dma_is_lockup,
1640         .vm_flush = &cayman_dma_vm_flush,
1641         .get_rptr = &cayman_dma_get_rptr,
1642         .get_wptr = &cayman_dma_get_wptr,
1643         .set_wptr = &cayman_dma_set_wptr
1644 };
1645
1646 static struct radeon_asic_ring cayman_uvd_ring = {
1647         .ib_execute = &uvd_v1_0_ib_execute,
1648         .emit_fence = &uvd_v2_2_fence_emit,
1649         .emit_semaphore = &uvd_v3_1_semaphore_emit,
1650         .cs_parse = &radeon_uvd_cs_parse,
1651         .ring_test = &uvd_v1_0_ring_test,
1652         .ib_test = &uvd_v1_0_ib_test,
1653         .is_lockup = &radeon_ring_test_lockup,
1654         .get_rptr = &uvd_v1_0_get_rptr,
1655         .get_wptr = &uvd_v1_0_get_wptr,
1656         .set_wptr = &uvd_v1_0_set_wptr,
1657 };
1658
1659 static struct radeon_asic cayman_asic = {
1660         .init = &cayman_init,
1661         .fini = &cayman_fini,
1662         .suspend = &cayman_suspend,
1663         .resume = &cayman_resume,
1664         .asic_reset = &cayman_asic_reset,
1665         .vga_set_state = &r600_vga_set_state,
1666         .mmio_hdp_flush = r600_mmio_hdp_flush,
1667         .gui_idle = &r600_gui_idle,
1668         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1669         .get_xclk = &rv770_get_xclk,
1670         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1671         .get_allowed_info_register = cayman_get_allowed_info_register,
1672         .gart = {
1673                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1674                 .get_page_entry = &rs600_gart_get_page_entry,
1675                 .set_page = &rs600_gart_set_page,
1676         },
1677         .vm = {
1678                 .init = &cayman_vm_init,
1679                 .fini = &cayman_vm_fini,
1680                 .copy_pages = &cayman_dma_vm_copy_pages,
1681                 .write_pages = &cayman_dma_vm_write_pages,
1682                 .set_pages = &cayman_dma_vm_set_pages,
1683                 .pad_ib = &cayman_dma_vm_pad_ib,
1684         },
1685         .ring = {
1686                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1687                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1688                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1689                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1690                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1691                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1692         },
1693         .irq = {
1694                 .set = &evergreen_irq_set,
1695                 .process = &evergreen_irq_process,
1696         },
1697         .display = {
1698                 .bandwidth_update = &evergreen_bandwidth_update,
1699                 .get_vblank_counter = &evergreen_get_vblank_counter,
1700                 .wait_for_vblank = &dce4_wait_for_vblank,
1701                 .set_backlight_level = &atombios_set_backlight_level,
1702                 .get_backlight_level = &atombios_get_backlight_level,
1703         },
1704         .copy = {
1705                 .blit = &r600_copy_cpdma,
1706                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1707                 .dma = &evergreen_copy_dma,
1708                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1709                 .copy = &evergreen_copy_dma,
1710                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1711         },
1712         .surface = {
1713                 .set_reg = r600_set_surface_reg,
1714                 .clear_reg = r600_clear_surface_reg,
1715         },
1716         .hpd = {
1717                 .init = &evergreen_hpd_init,
1718                 .fini = &evergreen_hpd_fini,
1719                 .sense = &evergreen_hpd_sense,
1720                 .set_polarity = &evergreen_hpd_set_polarity,
1721         },
1722         .pm = {
1723                 .misc = &evergreen_pm_misc,
1724                 .prepare = &evergreen_pm_prepare,
1725                 .finish = &evergreen_pm_finish,
1726                 .init_profile = &btc_pm_init_profile,
1727                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1728                 .get_engine_clock = &radeon_atom_get_engine_clock,
1729                 .set_engine_clock = &radeon_atom_set_engine_clock,
1730                 .get_memory_clock = &radeon_atom_get_memory_clock,
1731                 .set_memory_clock = &radeon_atom_set_memory_clock,
1732                 .get_pcie_lanes = &r600_get_pcie_lanes,
1733                 .set_pcie_lanes = &r600_set_pcie_lanes,
1734                 .set_clock_gating = NULL,
1735                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1736                 .get_temperature = &evergreen_get_temp,
1737         },
1738         .dpm = {
1739                 .init = &ni_dpm_init,
1740                 .setup_asic = &ni_dpm_setup_asic,
1741                 .enable = &ni_dpm_enable,
1742                 .late_enable = &rv770_dpm_late_enable,
1743                 .disable = &ni_dpm_disable,
1744                 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1745                 .set_power_state = &ni_dpm_set_power_state,
1746                 .post_set_power_state = &ni_dpm_post_set_power_state,
1747                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1748                 .fini = &ni_dpm_fini,
1749                 .get_sclk = &ni_dpm_get_sclk,
1750                 .get_mclk = &ni_dpm_get_mclk,
1751                 .print_power_state = &ni_dpm_print_power_state,
1752                 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1753                 .force_performance_level = &ni_dpm_force_performance_level,
1754                 .vblank_too_short = &ni_dpm_vblank_too_short,
1755                 .get_current_sclk = &ni_dpm_get_current_sclk,
1756                 .get_current_mclk = &ni_dpm_get_current_mclk,
1757         },
1758         .pflip = {
1759                 .page_flip = &evergreen_page_flip,
1760                 .page_flip_pending = &evergreen_page_flip_pending,
1761         },
1762 };
1763
1764 static struct radeon_asic trinity_asic = {
1765         .init = &cayman_init,
1766         .fini = &cayman_fini,
1767         .suspend = &cayman_suspend,
1768         .resume = &cayman_resume,
1769         .asic_reset = &cayman_asic_reset,
1770         .vga_set_state = &r600_vga_set_state,
1771         .mmio_hdp_flush = r600_mmio_hdp_flush,
1772         .gui_idle = &r600_gui_idle,
1773         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1774         .get_xclk = &r600_get_xclk,
1775         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1776         .get_allowed_info_register = cayman_get_allowed_info_register,
1777         .gart = {
1778                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1779                 .get_page_entry = &rs600_gart_get_page_entry,
1780                 .set_page = &rs600_gart_set_page,
1781         },
1782         .vm = {
1783                 .init = &cayman_vm_init,
1784                 .fini = &cayman_vm_fini,
1785                 .copy_pages = &cayman_dma_vm_copy_pages,
1786                 .write_pages = &cayman_dma_vm_write_pages,
1787                 .set_pages = &cayman_dma_vm_set_pages,
1788                 .pad_ib = &cayman_dma_vm_pad_ib,
1789         },
1790         .ring = {
1791                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1792                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1793                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1794                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1795                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1796                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1797         },
1798         .irq = {
1799                 .set = &evergreen_irq_set,
1800                 .process = &evergreen_irq_process,
1801         },
1802         .display = {
1803                 .bandwidth_update = &dce6_bandwidth_update,
1804                 .get_vblank_counter = &evergreen_get_vblank_counter,
1805                 .wait_for_vblank = &dce4_wait_for_vblank,
1806                 .set_backlight_level = &atombios_set_backlight_level,
1807                 .get_backlight_level = &atombios_get_backlight_level,
1808         },
1809         .copy = {
1810                 .blit = &r600_copy_cpdma,
1811                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1812                 .dma = &evergreen_copy_dma,
1813                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1814                 .copy = &evergreen_copy_dma,
1815                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1816         },
1817         .surface = {
1818                 .set_reg = r600_set_surface_reg,
1819                 .clear_reg = r600_clear_surface_reg,
1820         },
1821         .hpd = {
1822                 .init = &evergreen_hpd_init,
1823                 .fini = &evergreen_hpd_fini,
1824                 .sense = &evergreen_hpd_sense,
1825                 .set_polarity = &evergreen_hpd_set_polarity,
1826         },
1827         .pm = {
1828                 .misc = &evergreen_pm_misc,
1829                 .prepare = &evergreen_pm_prepare,
1830                 .finish = &evergreen_pm_finish,
1831                 .init_profile = &sumo_pm_init_profile,
1832                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1833                 .get_engine_clock = &radeon_atom_get_engine_clock,
1834                 .set_engine_clock = &radeon_atom_set_engine_clock,
1835                 .get_memory_clock = NULL,
1836                 .set_memory_clock = NULL,
1837                 .get_pcie_lanes = NULL,
1838                 .set_pcie_lanes = NULL,
1839                 .set_clock_gating = NULL,
1840                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1841                 .get_temperature = &tn_get_temp,
1842         },
1843         .dpm = {
1844                 .init = &trinity_dpm_init,
1845                 .setup_asic = &trinity_dpm_setup_asic,
1846                 .enable = &trinity_dpm_enable,
1847                 .late_enable = &trinity_dpm_late_enable,
1848                 .disable = &trinity_dpm_disable,
1849                 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1850                 .set_power_state = &trinity_dpm_set_power_state,
1851                 .post_set_power_state = &trinity_dpm_post_set_power_state,
1852                 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1853                 .fini = &trinity_dpm_fini,
1854                 .get_sclk = &trinity_dpm_get_sclk,
1855                 .get_mclk = &trinity_dpm_get_mclk,
1856                 .print_power_state = &trinity_dpm_print_power_state,
1857                 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1858                 .force_performance_level = &trinity_dpm_force_performance_level,
1859                 .enable_bapm = &trinity_dpm_enable_bapm,
1860                 .get_current_sclk = &trinity_dpm_get_current_sclk,
1861                 .get_current_mclk = &trinity_dpm_get_current_mclk,
1862         },
1863         .pflip = {
1864                 .page_flip = &evergreen_page_flip,
1865                 .page_flip_pending = &evergreen_page_flip_pending,
1866         },
1867 };
1868
1869 static struct radeon_asic_ring si_gfx_ring = {
1870         .ib_execute = &si_ring_ib_execute,
1871         .ib_parse = &si_ib_parse,
1872         .emit_fence = &si_fence_ring_emit,
1873         .emit_semaphore = &r600_semaphore_ring_emit,
1874         .cs_parse = NULL,
1875         .ring_test = &r600_ring_test,
1876         .ib_test = &r600_ib_test,
1877         .is_lockup = &si_gfx_is_lockup,
1878         .vm_flush = &si_vm_flush,
1879         .get_rptr = &cayman_gfx_get_rptr,
1880         .get_wptr = &cayman_gfx_get_wptr,
1881         .set_wptr = &cayman_gfx_set_wptr,
1882 };
1883
1884 static struct radeon_asic_ring si_dma_ring = {
1885         .ib_execute = &cayman_dma_ring_ib_execute,
1886         .ib_parse = &evergreen_dma_ib_parse,
1887         .emit_fence = &evergreen_dma_fence_ring_emit,
1888         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1889         .cs_parse = NULL,
1890         .ring_test = &r600_dma_ring_test,
1891         .ib_test = &r600_dma_ib_test,
1892         .is_lockup = &si_dma_is_lockup,
1893         .vm_flush = &si_dma_vm_flush,
1894         .get_rptr = &cayman_dma_get_rptr,
1895         .get_wptr = &cayman_dma_get_wptr,
1896         .set_wptr = &cayman_dma_set_wptr,
1897 };
1898
1899 static struct radeon_asic si_asic = {
1900         .init = &si_init,
1901         .fini = &si_fini,
1902         .suspend = &si_suspend,
1903         .resume = &si_resume,
1904         .asic_reset = &si_asic_reset,
1905         .vga_set_state = &r600_vga_set_state,
1906         .mmio_hdp_flush = r600_mmio_hdp_flush,
1907         .gui_idle = &r600_gui_idle,
1908         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1909         .get_xclk = &si_get_xclk,
1910         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1911         .get_allowed_info_register = si_get_allowed_info_register,
1912         .gart = {
1913                 .tlb_flush = &si_pcie_gart_tlb_flush,
1914                 .get_page_entry = &rs600_gart_get_page_entry,
1915                 .set_page = &rs600_gart_set_page,
1916         },
1917         .vm = {
1918                 .init = &si_vm_init,
1919                 .fini = &si_vm_fini,
1920                 .copy_pages = &si_dma_vm_copy_pages,
1921                 .write_pages = &si_dma_vm_write_pages,
1922                 .set_pages = &si_dma_vm_set_pages,
1923                 .pad_ib = &cayman_dma_vm_pad_ib,
1924         },
1925         .ring = {
1926                 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1927                 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1928                 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1929                 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1930                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1931                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1932         },
1933         .irq = {
1934                 .set = &si_irq_set,
1935                 .process = &si_irq_process,
1936         },
1937         .display = {
1938                 .bandwidth_update = &dce6_bandwidth_update,
1939                 .get_vblank_counter = &evergreen_get_vblank_counter,
1940                 .wait_for_vblank = &dce4_wait_for_vblank,
1941                 .set_backlight_level = &atombios_set_backlight_level,
1942                 .get_backlight_level = &atombios_get_backlight_level,
1943         },
1944         .copy = {
1945                 .blit = &r600_copy_cpdma,
1946                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1947                 .dma = &si_copy_dma,
1948                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1949                 .copy = &si_copy_dma,
1950                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1951         },
1952         .surface = {
1953                 .set_reg = r600_set_surface_reg,
1954                 .clear_reg = r600_clear_surface_reg,
1955         },
1956         .hpd = {
1957                 .init = &evergreen_hpd_init,
1958                 .fini = &evergreen_hpd_fini,
1959                 .sense = &evergreen_hpd_sense,
1960                 .set_polarity = &evergreen_hpd_set_polarity,
1961         },
1962         .pm = {
1963                 .misc = &evergreen_pm_misc,
1964                 .prepare = &evergreen_pm_prepare,
1965                 .finish = &evergreen_pm_finish,
1966                 .init_profile = &sumo_pm_init_profile,
1967                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1968                 .get_engine_clock = &radeon_atom_get_engine_clock,
1969                 .set_engine_clock = &radeon_atom_set_engine_clock,
1970                 .get_memory_clock = &radeon_atom_get_memory_clock,
1971                 .set_memory_clock = &radeon_atom_set_memory_clock,
1972                 .get_pcie_lanes = &r600_get_pcie_lanes,
1973                 .set_pcie_lanes = &r600_set_pcie_lanes,
1974                 .set_clock_gating = NULL,
1975                 .set_uvd_clocks = &si_set_uvd_clocks,
1976                 .get_temperature = &si_get_temp,
1977         },
1978         .dpm = {
1979                 .init = &si_dpm_init,
1980                 .setup_asic = &si_dpm_setup_asic,
1981                 .enable = &si_dpm_enable,
1982                 .late_enable = &si_dpm_late_enable,
1983                 .disable = &si_dpm_disable,
1984                 .pre_set_power_state = &si_dpm_pre_set_power_state,
1985                 .set_power_state = &si_dpm_set_power_state,
1986                 .post_set_power_state = &si_dpm_post_set_power_state,
1987                 .display_configuration_changed = &si_dpm_display_configuration_changed,
1988                 .fini = &si_dpm_fini,
1989                 .get_sclk = &ni_dpm_get_sclk,
1990                 .get_mclk = &ni_dpm_get_mclk,
1991                 .print_power_state = &ni_dpm_print_power_state,
1992                 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1993                 .force_performance_level = &si_dpm_force_performance_level,
1994                 .vblank_too_short = &ni_dpm_vblank_too_short,
1995                 .fan_ctrl_set_mode = &si_fan_ctrl_set_mode,
1996                 .fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
1997                 .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
1998                 .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
1999                 .get_current_sclk = &si_dpm_get_current_sclk,
2000                 .get_current_mclk = &si_dpm_get_current_mclk,
2001         },
2002         .pflip = {
2003                 .page_flip = &evergreen_page_flip,
2004                 .page_flip_pending = &evergreen_page_flip_pending,
2005         },
2006 };
2007
2008 static struct radeon_asic_ring ci_gfx_ring = {
2009         .ib_execute = &cik_ring_ib_execute,
2010         .ib_parse = &cik_ib_parse,
2011         .emit_fence = &cik_fence_gfx_ring_emit,
2012         .emit_semaphore = &cik_semaphore_ring_emit,
2013         .cs_parse = NULL,
2014         .ring_test = &cik_ring_test,
2015         .ib_test = &cik_ib_test,
2016         .is_lockup = &cik_gfx_is_lockup,
2017         .vm_flush = &cik_vm_flush,
2018         .get_rptr = &cik_gfx_get_rptr,
2019         .get_wptr = &cik_gfx_get_wptr,
2020         .set_wptr = &cik_gfx_set_wptr,
2021 };
2022
2023 static struct radeon_asic_ring ci_cp_ring = {
2024         .ib_execute = &cik_ring_ib_execute,
2025         .ib_parse = &cik_ib_parse,
2026         .emit_fence = &cik_fence_compute_ring_emit,
2027         .emit_semaphore = &cik_semaphore_ring_emit,
2028         .cs_parse = NULL,
2029         .ring_test = &cik_ring_test,
2030         .ib_test = &cik_ib_test,
2031         .is_lockup = &cik_gfx_is_lockup,
2032         .vm_flush = &cik_vm_flush,
2033         .get_rptr = &cik_compute_get_rptr,
2034         .get_wptr = &cik_compute_get_wptr,
2035         .set_wptr = &cik_compute_set_wptr,
2036 };
2037
2038 static struct radeon_asic_ring ci_dma_ring = {
2039         .ib_execute = &cik_sdma_ring_ib_execute,
2040         .ib_parse = &cik_ib_parse,
2041         .emit_fence = &cik_sdma_fence_ring_emit,
2042         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2043         .cs_parse = NULL,
2044         .ring_test = &cik_sdma_ring_test,
2045         .ib_test = &cik_sdma_ib_test,
2046         .is_lockup = &cik_sdma_is_lockup,
2047         .vm_flush = &cik_dma_vm_flush,
2048         .get_rptr = &cik_sdma_get_rptr,
2049         .get_wptr = &cik_sdma_get_wptr,
2050         .set_wptr = &cik_sdma_set_wptr,
2051 };
2052
2053 static struct radeon_asic_ring ci_vce_ring = {
2054         .ib_execute = &radeon_vce_ib_execute,
2055         .emit_fence = &radeon_vce_fence_emit,
2056         .emit_semaphore = &radeon_vce_semaphore_emit,
2057         .cs_parse = &radeon_vce_cs_parse,
2058         .ring_test = &radeon_vce_ring_test,
2059         .ib_test = &radeon_vce_ib_test,
2060         .is_lockup = &radeon_ring_test_lockup,
2061         .get_rptr = &vce_v1_0_get_rptr,
2062         .get_wptr = &vce_v1_0_get_wptr,
2063         .set_wptr = &vce_v1_0_set_wptr,
2064 };
2065
2066 static struct radeon_asic ci_asic = {
2067         .init = &cik_init,
2068         .fini = &cik_fini,
2069         .suspend = &cik_suspend,
2070         .resume = &cik_resume,
2071         .asic_reset = &cik_asic_reset,
2072         .vga_set_state = &r600_vga_set_state,
2073         .mmio_hdp_flush = &r600_mmio_hdp_flush,
2074         .gui_idle = &r600_gui_idle,
2075         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2076         .get_xclk = &cik_get_xclk,
2077         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2078         .get_allowed_info_register = cik_get_allowed_info_register,
2079         .gart = {
2080                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2081                 .get_page_entry = &rs600_gart_get_page_entry,
2082                 .set_page = &rs600_gart_set_page,
2083         },
2084         .vm = {
2085                 .init = &cik_vm_init,
2086                 .fini = &cik_vm_fini,
2087                 .copy_pages = &cik_sdma_vm_copy_pages,
2088                 .write_pages = &cik_sdma_vm_write_pages,
2089                 .set_pages = &cik_sdma_vm_set_pages,
2090                 .pad_ib = &cik_sdma_vm_pad_ib,
2091         },
2092         .ring = {
2093                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2094                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2095                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2096                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2097                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2098                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2099                 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2100                 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2101         },
2102         .irq = {
2103                 .set = &cik_irq_set,
2104                 .process = &cik_irq_process,
2105         },
2106         .display = {
2107                 .bandwidth_update = &dce8_bandwidth_update,
2108                 .get_vblank_counter = &evergreen_get_vblank_counter,
2109                 .wait_for_vblank = &dce4_wait_for_vblank,
2110                 .set_backlight_level = &atombios_set_backlight_level,
2111                 .get_backlight_level = &atombios_get_backlight_level,
2112         },
2113         .copy = {
2114                 .blit = &cik_copy_cpdma,
2115                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2116                 .dma = &cik_copy_dma,
2117                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2118                 .copy = &cik_copy_dma,
2119                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2120         },
2121         .surface = {
2122                 .set_reg = r600_set_surface_reg,
2123                 .clear_reg = r600_clear_surface_reg,
2124         },
2125         .hpd = {
2126                 .init = &evergreen_hpd_init,
2127                 .fini = &evergreen_hpd_fini,
2128                 .sense = &evergreen_hpd_sense,
2129                 .set_polarity = &evergreen_hpd_set_polarity,
2130         },
2131         .pm = {
2132                 .misc = &evergreen_pm_misc,
2133                 .prepare = &evergreen_pm_prepare,
2134                 .finish = &evergreen_pm_finish,
2135                 .init_profile = &sumo_pm_init_profile,
2136                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2137                 .get_engine_clock = &radeon_atom_get_engine_clock,
2138                 .set_engine_clock = &radeon_atom_set_engine_clock,
2139                 .get_memory_clock = &radeon_atom_get_memory_clock,
2140                 .set_memory_clock = &radeon_atom_set_memory_clock,
2141                 .get_pcie_lanes = NULL,
2142                 .set_pcie_lanes = NULL,
2143                 .set_clock_gating = NULL,
2144                 .set_uvd_clocks = &cik_set_uvd_clocks,
2145                 .set_vce_clocks = &cik_set_vce_clocks,
2146                 .get_temperature = &ci_get_temp,
2147         },
2148         .dpm = {
2149                 .init = &ci_dpm_init,
2150                 .setup_asic = &ci_dpm_setup_asic,
2151                 .enable = &ci_dpm_enable,
2152                 .late_enable = &ci_dpm_late_enable,
2153                 .disable = &ci_dpm_disable,
2154                 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2155                 .set_power_state = &ci_dpm_set_power_state,
2156                 .post_set_power_state = &ci_dpm_post_set_power_state,
2157                 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2158                 .fini = &ci_dpm_fini,
2159                 .get_sclk = &ci_dpm_get_sclk,
2160                 .get_mclk = &ci_dpm_get_mclk,
2161                 .print_power_state = &ci_dpm_print_power_state,
2162                 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2163                 .force_performance_level = &ci_dpm_force_performance_level,
2164                 .vblank_too_short = &ci_dpm_vblank_too_short,
2165                 .powergate_uvd = &ci_dpm_powergate_uvd,
2166                 .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode,
2167                 .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode,
2168                 .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent,
2169                 .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent,
2170                 .get_current_sclk = &ci_dpm_get_current_sclk,
2171                 .get_current_mclk = &ci_dpm_get_current_mclk,
2172         },
2173         .pflip = {
2174                 .page_flip = &evergreen_page_flip,
2175                 .page_flip_pending = &evergreen_page_flip_pending,
2176         },
2177 };
2178
2179 static struct radeon_asic kv_asic = {
2180         .init = &cik_init,
2181         .fini = &cik_fini,
2182         .suspend = &cik_suspend,
2183         .resume = &cik_resume,
2184         .asic_reset = &cik_asic_reset,
2185         .vga_set_state = &r600_vga_set_state,
2186         .mmio_hdp_flush = &r600_mmio_hdp_flush,
2187         .gui_idle = &r600_gui_idle,
2188         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2189         .get_xclk = &cik_get_xclk,
2190         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2191         .get_allowed_info_register = cik_get_allowed_info_register,
2192         .gart = {
2193                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2194                 .get_page_entry = &rs600_gart_get_page_entry,
2195                 .set_page = &rs600_gart_set_page,
2196         },
2197         .vm = {
2198                 .init = &cik_vm_init,
2199                 .fini = &cik_vm_fini,
2200                 .copy_pages = &cik_sdma_vm_copy_pages,
2201                 .write_pages = &cik_sdma_vm_write_pages,
2202                 .set_pages = &cik_sdma_vm_set_pages,
2203                 .pad_ib = &cik_sdma_vm_pad_ib,
2204         },
2205         .ring = {
2206                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2207                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2208                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2209                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2210                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2211                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2212                 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2213                 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2214         },
2215         .irq = {
2216                 .set = &cik_irq_set,
2217                 .process = &cik_irq_process,
2218         },
2219         .display = {
2220                 .bandwidth_update = &dce8_bandwidth_update,
2221                 .get_vblank_counter = &evergreen_get_vblank_counter,
2222                 .wait_for_vblank = &dce4_wait_for_vblank,
2223                 .set_backlight_level = &atombios_set_backlight_level,
2224                 .get_backlight_level = &atombios_get_backlight_level,
2225         },
2226         .copy = {
2227                 .blit = &cik_copy_cpdma,
2228                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2229                 .dma = &cik_copy_dma,
2230                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2231                 .copy = &cik_copy_dma,
2232                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2233         },
2234         .surface = {
2235                 .set_reg = r600_set_surface_reg,
2236                 .clear_reg = r600_clear_surface_reg,
2237         },
2238         .hpd = {
2239                 .init = &evergreen_hpd_init,
2240                 .fini = &evergreen_hpd_fini,
2241                 .sense = &evergreen_hpd_sense,
2242                 .set_polarity = &evergreen_hpd_set_polarity,
2243         },
2244         .pm = {
2245                 .misc = &evergreen_pm_misc,
2246                 .prepare = &evergreen_pm_prepare,
2247                 .finish = &evergreen_pm_finish,
2248                 .init_profile = &sumo_pm_init_profile,
2249                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2250                 .get_engine_clock = &radeon_atom_get_engine_clock,
2251                 .set_engine_clock = &radeon_atom_set_engine_clock,
2252                 .get_memory_clock = &radeon_atom_get_memory_clock,
2253                 .set_memory_clock = &radeon_atom_set_memory_clock,
2254                 .get_pcie_lanes = NULL,
2255                 .set_pcie_lanes = NULL,
2256                 .set_clock_gating = NULL,
2257                 .set_uvd_clocks = &cik_set_uvd_clocks,
2258                 .set_vce_clocks = &cik_set_vce_clocks,
2259                 .get_temperature = &kv_get_temp,
2260         },
2261         .dpm = {
2262                 .init = &kv_dpm_init,
2263                 .setup_asic = &kv_dpm_setup_asic,
2264                 .enable = &kv_dpm_enable,
2265                 .late_enable = &kv_dpm_late_enable,
2266                 .disable = &kv_dpm_disable,
2267                 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2268                 .set_power_state = &kv_dpm_set_power_state,
2269                 .post_set_power_state = &kv_dpm_post_set_power_state,
2270                 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2271                 .fini = &kv_dpm_fini,
2272                 .get_sclk = &kv_dpm_get_sclk,
2273                 .get_mclk = &kv_dpm_get_mclk,
2274                 .print_power_state = &kv_dpm_print_power_state,
2275                 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2276                 .force_performance_level = &kv_dpm_force_performance_level,
2277                 .powergate_uvd = &kv_dpm_powergate_uvd,
2278                 .enable_bapm = &kv_dpm_enable_bapm,
2279                 .get_current_sclk = &kv_dpm_get_current_sclk,
2280                 .get_current_mclk = &kv_dpm_get_current_mclk,
2281         },
2282         .pflip = {
2283                 .page_flip = &evergreen_page_flip,
2284                 .page_flip_pending = &evergreen_page_flip_pending,
2285         },
2286 };
2287
2288 /**
2289  * radeon_asic_init - register asic specific callbacks
2290  *
2291  * @rdev: radeon device pointer
2292  *
2293  * Registers the appropriate asic specific callbacks for each
2294  * chip family.  Also sets other asics specific info like the number
2295  * of crtcs and the register aperture accessors (all asics).
2296  * Returns 0 for success.
2297  */
2298 int radeon_asic_init(struct radeon_device *rdev)
2299 {
2300         radeon_register_accessor_init(rdev);
2301
2302         /* set the number of crtcs */
2303         if (rdev->flags & RADEON_SINGLE_CRTC)
2304                 rdev->num_crtc = 1;
2305         else
2306                 rdev->num_crtc = 2;
2307
2308         rdev->has_uvd = false;
2309
2310         switch (rdev->family) {
2311         case CHIP_R100:
2312         case CHIP_RV100:
2313         case CHIP_RS100:
2314         case CHIP_RV200:
2315         case CHIP_RS200:
2316                 rdev->asic = &r100_asic;
2317                 break;
2318         case CHIP_R200:
2319         case CHIP_RV250:
2320         case CHIP_RS300:
2321         case CHIP_RV280:
2322                 rdev->asic = &r200_asic;
2323                 break;
2324         case CHIP_R300:
2325         case CHIP_R350:
2326         case CHIP_RV350:
2327         case CHIP_RV380:
2328                 if (rdev->flags & RADEON_IS_PCIE)
2329                         rdev->asic = &r300_asic_pcie;
2330                 else
2331                         rdev->asic = &r300_asic;
2332                 break;
2333         case CHIP_R420:
2334         case CHIP_R423:
2335         case CHIP_RV410:
2336                 rdev->asic = &r420_asic;
2337                 /* handle macs */
2338                 if (rdev->bios == NULL) {
2339                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2340                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2341                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2342                         rdev->asic->pm.set_memory_clock = NULL;
2343                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2344                 }
2345                 break;
2346         case CHIP_RS400:
2347         case CHIP_RS480:
2348                 rdev->asic = &rs400_asic;
2349                 break;
2350         case CHIP_RS600:
2351                 rdev->asic = &rs600_asic;
2352                 break;
2353         case CHIP_RS690:
2354         case CHIP_RS740:
2355                 rdev->asic = &rs690_asic;
2356                 break;
2357         case CHIP_RV515:
2358                 rdev->asic = &rv515_asic;
2359                 break;
2360         case CHIP_R520:
2361         case CHIP_RV530:
2362         case CHIP_RV560:
2363         case CHIP_RV570:
2364         case CHIP_R580:
2365                 rdev->asic = &r520_asic;
2366                 break;
2367         case CHIP_R600:
2368                 rdev->asic = &r600_asic;
2369                 break;
2370         case CHIP_RV610:
2371         case CHIP_RV630:
2372         case CHIP_RV620:
2373         case CHIP_RV635:
2374         case CHIP_RV670:
2375                 rdev->asic = &rv6xx_asic;
2376                 rdev->has_uvd = true;
2377                 break;
2378         case CHIP_RS780:
2379         case CHIP_RS880:
2380                 rdev->asic = &rs780_asic;
2381                 /* 760G/780V/880V don't have UVD */
2382                 if ((rdev->pdev->device == 0x9616)||
2383                     (rdev->pdev->device == 0x9611)||
2384                     (rdev->pdev->device == 0x9613)||
2385                     (rdev->pdev->device == 0x9711)||
2386                     (rdev->pdev->device == 0x9713))
2387                         rdev->has_uvd = false;
2388                 else
2389                         rdev->has_uvd = true;
2390                 break;
2391         case CHIP_RV770:
2392         case CHIP_RV730:
2393         case CHIP_RV710:
2394         case CHIP_RV740:
2395                 rdev->asic = &rv770_asic;
2396                 rdev->has_uvd = true;
2397                 break;
2398         case CHIP_CEDAR:
2399         case CHIP_REDWOOD:
2400         case CHIP_JUNIPER:
2401         case CHIP_CYPRESS:
2402         case CHIP_HEMLOCK:
2403                 /* set num crtcs */
2404                 if (rdev->family == CHIP_CEDAR)
2405                         rdev->num_crtc = 4;
2406                 else
2407                         rdev->num_crtc = 6;
2408                 rdev->asic = &evergreen_asic;
2409                 rdev->has_uvd = true;
2410                 break;
2411         case CHIP_PALM:
2412         case CHIP_SUMO:
2413         case CHIP_SUMO2:
2414                 rdev->asic = &sumo_asic;
2415                 rdev->has_uvd = true;
2416                 break;
2417         case CHIP_BARTS:
2418         case CHIP_TURKS:
2419         case CHIP_CAICOS:
2420                 /* set num crtcs */
2421                 if (rdev->family == CHIP_CAICOS)
2422                         rdev->num_crtc = 4;
2423                 else
2424                         rdev->num_crtc = 6;
2425                 rdev->asic = &btc_asic;
2426                 rdev->has_uvd = true;
2427                 break;
2428         case CHIP_CAYMAN:
2429                 rdev->asic = &cayman_asic;
2430                 /* set num crtcs */
2431                 rdev->num_crtc = 6;
2432                 rdev->has_uvd = true;
2433                 break;
2434         case CHIP_ARUBA:
2435                 rdev->asic = &trinity_asic;
2436                 /* set num crtcs */
2437                 rdev->num_crtc = 4;
2438                 rdev->has_uvd = true;
2439                 break;
2440         case CHIP_TAHITI:
2441         case CHIP_PITCAIRN:
2442         case CHIP_VERDE:
2443         case CHIP_OLAND:
2444         case CHIP_HAINAN:
2445                 rdev->asic = &si_asic;
2446                 /* set num crtcs */
2447                 if (rdev->family == CHIP_HAINAN)
2448                         rdev->num_crtc = 0;
2449                 else if (rdev->family == CHIP_OLAND)
2450                         rdev->num_crtc = 2;
2451                 else
2452                         rdev->num_crtc = 6;
2453                 if (rdev->family == CHIP_HAINAN)
2454                         rdev->has_uvd = false;
2455                 else
2456                         rdev->has_uvd = true;
2457                 switch (rdev->family) {
2458                 case CHIP_TAHITI:
2459                         rdev->cg_flags =
2460                                 RADEON_CG_SUPPORT_GFX_MGCG |
2461                                 RADEON_CG_SUPPORT_GFX_MGLS |
2462                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2463                                 RADEON_CG_SUPPORT_GFX_CGLS |
2464                                 RADEON_CG_SUPPORT_GFX_CGTS |
2465                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2466                                 RADEON_CG_SUPPORT_MC_MGCG |
2467                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2468                                 RADEON_CG_SUPPORT_BIF_LS |
2469                                 RADEON_CG_SUPPORT_VCE_MGCG |
2470                                 RADEON_CG_SUPPORT_UVD_MGCG |
2471                                 RADEON_CG_SUPPORT_HDP_LS |
2472                                 RADEON_CG_SUPPORT_HDP_MGCG;
2473                         rdev->pg_flags = 0;
2474                         break;
2475                 case CHIP_PITCAIRN:
2476                         rdev->cg_flags =
2477                                 RADEON_CG_SUPPORT_GFX_MGCG |
2478                                 RADEON_CG_SUPPORT_GFX_MGLS |
2479                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2480                                 RADEON_CG_SUPPORT_GFX_CGLS |
2481                                 RADEON_CG_SUPPORT_GFX_CGTS |
2482                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2483                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2484                                 RADEON_CG_SUPPORT_MC_LS |
2485                                 RADEON_CG_SUPPORT_MC_MGCG |
2486                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2487                                 RADEON_CG_SUPPORT_BIF_LS |
2488                                 RADEON_CG_SUPPORT_VCE_MGCG |
2489                                 RADEON_CG_SUPPORT_UVD_MGCG |
2490                                 RADEON_CG_SUPPORT_HDP_LS |
2491                                 RADEON_CG_SUPPORT_HDP_MGCG;
2492                         rdev->pg_flags = 0;
2493                         break;
2494                 case CHIP_VERDE:
2495                         rdev->cg_flags =
2496                                 RADEON_CG_SUPPORT_GFX_MGCG |
2497                                 RADEON_CG_SUPPORT_GFX_MGLS |
2498                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2499                                 RADEON_CG_SUPPORT_GFX_CGLS |
2500                                 RADEON_CG_SUPPORT_GFX_CGTS |
2501                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2502                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2503                                 RADEON_CG_SUPPORT_MC_LS |
2504                                 RADEON_CG_SUPPORT_MC_MGCG |
2505                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2506                                 RADEON_CG_SUPPORT_BIF_LS |
2507                                 RADEON_CG_SUPPORT_VCE_MGCG |
2508                                 RADEON_CG_SUPPORT_UVD_MGCG |
2509                                 RADEON_CG_SUPPORT_HDP_LS |
2510                                 RADEON_CG_SUPPORT_HDP_MGCG;
2511                         rdev->pg_flags = 0 |
2512                                 /*RADEON_PG_SUPPORT_GFX_PG | */
2513                                 RADEON_PG_SUPPORT_SDMA;
2514                         break;
2515                 case CHIP_OLAND:
2516                         rdev->cg_flags =
2517                                 RADEON_CG_SUPPORT_GFX_MGCG |
2518                                 RADEON_CG_SUPPORT_GFX_MGLS |
2519                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2520                                 RADEON_CG_SUPPORT_GFX_CGLS |
2521                                 RADEON_CG_SUPPORT_GFX_CGTS |
2522                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2523                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2524                                 RADEON_CG_SUPPORT_MC_LS |
2525                                 RADEON_CG_SUPPORT_MC_MGCG |
2526                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2527                                 RADEON_CG_SUPPORT_BIF_LS |
2528                                 RADEON_CG_SUPPORT_UVD_MGCG |
2529                                 RADEON_CG_SUPPORT_HDP_LS |
2530                                 RADEON_CG_SUPPORT_HDP_MGCG;
2531                         rdev->pg_flags = 0;
2532                         break;
2533                 case CHIP_HAINAN:
2534                         rdev->cg_flags =
2535                                 RADEON_CG_SUPPORT_GFX_MGCG |
2536                                 RADEON_CG_SUPPORT_GFX_MGLS |
2537                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2538                                 RADEON_CG_SUPPORT_GFX_CGLS |
2539                                 RADEON_CG_SUPPORT_GFX_CGTS |
2540                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2541                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2542                                 RADEON_CG_SUPPORT_MC_LS |
2543                                 RADEON_CG_SUPPORT_MC_MGCG |
2544                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2545                                 RADEON_CG_SUPPORT_BIF_LS |
2546                                 RADEON_CG_SUPPORT_HDP_LS |
2547                                 RADEON_CG_SUPPORT_HDP_MGCG;
2548                         rdev->pg_flags = 0;
2549                         break;
2550                 default:
2551                         rdev->cg_flags = 0;
2552                         rdev->pg_flags = 0;
2553                         break;
2554                 }
2555                 break;
2556         case CHIP_BONAIRE:
2557         case CHIP_HAWAII:
2558                 rdev->asic = &ci_asic;
2559                 rdev->num_crtc = 6;
2560                 rdev->has_uvd = true;
2561                 if (rdev->family == CHIP_BONAIRE) {
2562                         rdev->cg_flags =
2563                                 RADEON_CG_SUPPORT_GFX_MGCG |
2564                                 RADEON_CG_SUPPORT_GFX_MGLS |
2565                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2566                                 RADEON_CG_SUPPORT_GFX_CGLS |
2567                                 RADEON_CG_SUPPORT_GFX_CGTS |
2568                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2569                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2570                                 RADEON_CG_SUPPORT_MC_LS |
2571                                 RADEON_CG_SUPPORT_MC_MGCG |
2572                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2573                                 RADEON_CG_SUPPORT_SDMA_LS |
2574                                 RADEON_CG_SUPPORT_BIF_LS |
2575                                 RADEON_CG_SUPPORT_VCE_MGCG |
2576                                 RADEON_CG_SUPPORT_UVD_MGCG |
2577                                 RADEON_CG_SUPPORT_HDP_LS |
2578                                 RADEON_CG_SUPPORT_HDP_MGCG;
2579                         rdev->pg_flags = 0;
2580                 } else {
2581                         rdev->cg_flags =
2582                                 RADEON_CG_SUPPORT_GFX_MGCG |
2583                                 RADEON_CG_SUPPORT_GFX_MGLS |
2584                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2585                                 RADEON_CG_SUPPORT_GFX_CGLS |
2586                                 RADEON_CG_SUPPORT_GFX_CGTS |
2587                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2588                                 RADEON_CG_SUPPORT_MC_LS |
2589                                 RADEON_CG_SUPPORT_MC_MGCG |
2590                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2591                                 RADEON_CG_SUPPORT_SDMA_LS |
2592                                 RADEON_CG_SUPPORT_BIF_LS |
2593                                 RADEON_CG_SUPPORT_VCE_MGCG |
2594                                 RADEON_CG_SUPPORT_UVD_MGCG |
2595                                 RADEON_CG_SUPPORT_HDP_LS |
2596                                 RADEON_CG_SUPPORT_HDP_MGCG;
2597                         rdev->pg_flags = 0;
2598                 }
2599                 break;
2600         case CHIP_KAVERI:
2601         case CHIP_KABINI:
2602         case CHIP_MULLINS:
2603                 rdev->asic = &kv_asic;
2604                 /* set num crtcs */
2605                 if (rdev->family == CHIP_KAVERI) {
2606                         rdev->num_crtc = 4;
2607                         rdev->cg_flags =
2608                                 RADEON_CG_SUPPORT_GFX_MGCG |
2609                                 RADEON_CG_SUPPORT_GFX_MGLS |
2610                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2611                                 RADEON_CG_SUPPORT_GFX_CGLS |
2612                                 RADEON_CG_SUPPORT_GFX_CGTS |
2613                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2614                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2615                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2616                                 RADEON_CG_SUPPORT_SDMA_LS |
2617                                 RADEON_CG_SUPPORT_BIF_LS |
2618                                 RADEON_CG_SUPPORT_VCE_MGCG |
2619                                 RADEON_CG_SUPPORT_UVD_MGCG |
2620                                 RADEON_CG_SUPPORT_HDP_LS |
2621                                 RADEON_CG_SUPPORT_HDP_MGCG;
2622                         rdev->pg_flags = 0;
2623                                 /*RADEON_PG_SUPPORT_GFX_PG |
2624                                 RADEON_PG_SUPPORT_GFX_SMG |
2625                                 RADEON_PG_SUPPORT_GFX_DMG |
2626                                 RADEON_PG_SUPPORT_UVD |
2627                                 RADEON_PG_SUPPORT_VCE |
2628                                 RADEON_PG_SUPPORT_CP |
2629                                 RADEON_PG_SUPPORT_GDS |
2630                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2631                                 RADEON_PG_SUPPORT_ACP |
2632                                 RADEON_PG_SUPPORT_SAMU;*/
2633                 } else {
2634                         rdev->num_crtc = 2;
2635                         rdev->cg_flags =
2636                                 RADEON_CG_SUPPORT_GFX_MGCG |
2637                                 RADEON_CG_SUPPORT_GFX_MGLS |
2638                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2639                                 RADEON_CG_SUPPORT_GFX_CGLS |
2640                                 RADEON_CG_SUPPORT_GFX_CGTS |
2641                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2642                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2643                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2644                                 RADEON_CG_SUPPORT_SDMA_LS |
2645                                 RADEON_CG_SUPPORT_BIF_LS |
2646                                 RADEON_CG_SUPPORT_VCE_MGCG |
2647                                 RADEON_CG_SUPPORT_UVD_MGCG |
2648                                 RADEON_CG_SUPPORT_HDP_LS |
2649                                 RADEON_CG_SUPPORT_HDP_MGCG;
2650                         rdev->pg_flags = 0;
2651                                 /*RADEON_PG_SUPPORT_GFX_PG |
2652                                 RADEON_PG_SUPPORT_GFX_SMG |
2653                                 RADEON_PG_SUPPORT_UVD |
2654                                 RADEON_PG_SUPPORT_VCE |
2655                                 RADEON_PG_SUPPORT_CP |
2656                                 RADEON_PG_SUPPORT_GDS |
2657                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2658                                 RADEON_PG_SUPPORT_SAMU;*/
2659                 }
2660                 rdev->has_uvd = true;
2661                 break;
2662         default:
2663                 /* FIXME: not supported yet */
2664                 return -EINVAL;
2665         }
2666
2667         if (rdev->flags & RADEON_IS_IGP) {
2668                 rdev->asic->pm.get_memory_clock = NULL;
2669                 rdev->asic->pm.set_memory_clock = NULL;
2670         }
2671
2672         return 0;
2673 }
2674