kernel/drivers/gpu/drm/radeon/dce6_afmt.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/hdmi.h>
  24 #include <drm/drmP.h>
  25 #include "radeon.h"
  26 #include "radeon_audio.h"
  27 #include "sid.h"
  28
  29 #define DCE8_DCCG_AUDIO_DTO1_PHASE      0x05b8
  30 #define DCE8_DCCG_AUDIO_DTO1_MODULE     0x05bc
  31
  32 u32 dce6_endpoint_rreg(struct radeon_device *rdev,
  33                               u32 block_offset, u32 reg)
  34 {
  35         unsigned long flags;
  36         u32 r;
  37
  38         spin_lock_irqsave(&rdev->end_idx_lock, flags);
  39         WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
  40         r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
  41         spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
  42
  43         return r;
  44 }
  45
  46 void dce6_endpoint_wreg(struct radeon_device *rdev,
  47                                u32 block_offset, u32 reg, u32 v)
  48 {
  49         unsigned long flags;
  50
  51         spin_lock_irqsave(&rdev->end_idx_lock, flags);
  52         if (ASIC_IS_DCE8(rdev))
  53                 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
  54         else
  55                 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
  56                        AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
  57         WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
  58         spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
  59 }
  60
  61 static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
  62 {
  63         int i;
  64         u32 offset, tmp;
  65
  66         for (i = 0; i < rdev->audio.num_pins; i++) {
  67                 offset = rdev->audio.pin[i].offset;
  68                 tmp = RREG32_ENDPOINT(offset,
  69                                       AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
  70                 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
  71                         rdev->audio.pin[i].connected = false;
  72                 else
  73                         rdev->audio.pin[i].connected = true;
  74         }
  75 }
  76
  77 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev)
  78 {
  79         int i;
  80
  81         dce6_afmt_get_connected_pins(rdev);
  82
  83         for (i = 0; i < rdev->audio.num_pins; i++) {
  84                 if (rdev->audio.pin[i].connected)
  85                         return &rdev->audio.pin[i];
  86         }
  87         DRM_ERROR("No connected audio pins found!\n");
  88         return NULL;
  89 }
  90
  91 void dce6_afmt_select_pin(struct drm_encoder *encoder)
  92 {
  93         struct radeon_device *rdev = encoder->dev->dev_private;
  94         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  95         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  96         u32 offset;
  97
  98         if (!dig || !dig->afmt || !dig->afmt->pin)
  99                 return;
 100
 101         offset = dig->afmt->offset;
 102
 103         WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
 104                AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
 105 }
 106
 107 void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
 108                 struct drm_connector *connector, struct drm_display_mode *mode)
 109 {
 110         struct radeon_device *rdev = encoder->dev->dev_private;
 111         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 112         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 113         u32 tmp = 0, offset;
 114
 115         if (!dig || !dig->afmt || !dig->afmt->pin)
 116                 return;
 117
 118         offset = dig->afmt->pin->offset;
 119
 120         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 121                 if (connector->latency_present[1])
 122                         tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
 123                                 AUDIO_LIPSYNC(connector->audio_latency[1]);
 124                 else
 125                         tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
 126         } else {
 127                 if (connector->latency_present[0])
 128                         tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
 129                                 AUDIO_LIPSYNC(connector->audio_latency[0]);
 130                 else
 131                         tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
 132         }
 133         WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
 134 }
 135
 136 void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
 137         u8 *sadb, int sad_count)
 138 {
 139         struct radeon_device *rdev = encoder->dev->dev_private;
 140         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 141         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 142         u32 offset, tmp;
 143
 144         if (!dig || !dig->afmt || !dig->afmt->pin)
 145                 return;
 146
 147         offset = dig->afmt->pin->offset;
 148
 149         /* program the speaker allocation */
 150         tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
 151         tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
 152         /* set HDMI mode */
 153         tmp |= HDMI_CONNECTION;
 154         if (sad_count)
 155                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
 156         else
 157                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
 158         WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
 159 }
 160
 161 void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
 162         u8 *sadb, int sad_count)
 163 {
 164         struct radeon_device *rdev = encoder->dev->dev_private;
 165         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 166         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 167         u32 offset, tmp;
 168
 169         if (!dig || !dig->afmt || !dig->afmt->pin)
 170                 return;
 171
 172         offset = dig->afmt->pin->offset;
 173
 174         /* program the speaker allocation */
 175         tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
 176         tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
 177         /* set DP mode */
 178         tmp |= DP_CONNECTION;
 179         if (sad_count)
 180                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
 181         else
 182                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
 183         WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
 184 }
 185
 186 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
 187         struct cea_sad *sads, int sad_count)
 188 {
 189         u32 offset;
 190         int i;
 191         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 192         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 193         struct radeon_device *rdev = encoder->dev->dev_private;
 194         static const u16 eld_reg_to_type[][2] = {
 195                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
 196                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
 197                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
 198                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
 199                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
 200                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
 201                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
 202                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
 203                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
 204                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
 205                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
 206                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
 207         };
 208
 209         if (!dig || !dig->afmt || !dig->afmt->pin)
 210                 return;
 211
 212         offset = dig->afmt->pin->offset;
 213
 214         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
 215                 u32 value = 0;
 216                 u8 stereo_freqs = 0;
 217                 int max_channels = -1;
 218                 int j;
 219
 220                 for (j = 0; j < sad_count; j++) {
 221                         struct cea_sad *sad = &sads[j];
 222
 223                         if (sad->format == eld_reg_to_type[i][1]) {
 224                                 if (sad->channels > max_channels) {
 225                                         value = MAX_CHANNELS(sad->channels) |
 226                                                 DESCRIPTOR_BYTE_2(sad->byte2) |
 227                                                 SUPPORTED_FREQUENCIES(sad->freq);
 228                                         max_channels = sad->channels;
 229                                 }
 230
 231                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
 232                                         stereo_freqs |= sad->freq;
 233                                 else
 234                                         break;
 235                         }
 236                 }
 237
 238                 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
 239
 240                 WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);
 241         }
 242 }
 243
 244 void dce6_audio_enable(struct radeon_device *rdev,
 245                        struct r600_audio_pin *pin,
 246                        u8 enable_mask)
 247 {
 248         if (!pin)
 249                 return;
 250
 251         WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 252                         enable_mask ? AUDIO_ENABLED : 0);
 253 }
 254
 255 void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
 256         struct radeon_crtc *crtc, unsigned int clock)
 257 {
 258         /* Two dtos; generally use dto0 for HDMI */
 259         u32 value = 0;
 260
 261         if (crtc)
 262                 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
 263
 264         WREG32(DCCG_AUDIO_DTO_SOURCE, value);
 265
 266         /* Express [24MHz / target pixel clock] as an exact rational
 267          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
 268          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
 269          */
 270         WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
 271         WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
 272 }
 273
 274 void dce6_dp_audio_set_dto(struct radeon_device *rdev,
 275         struct radeon_crtc *crtc, unsigned int clock)
 276 {
 277         /* Two dtos; generally use dto1 for DP */
 278         u32 value = 0;
 279         value |= DCCG_AUDIO_DTO_SEL;
 280
 281         if (crtc)
 282                 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
 283
 284         WREG32(DCCG_AUDIO_DTO_SOURCE, value);
 285
 286         /* Express [24MHz / target pixel clock] as an exact rational
 287          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
 288          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
 289          */
 290         if (ASIC_IS_DCE8(rdev)) {
 291                 WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
 292                 WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
 293         } else {
 294                 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
 295                 WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
 296         }
 297 }