kernel/drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.ucCRTC = radeon_crtc->crtc_id;
  48
  49         switch (radeon_crtc->rmx_type) {
  50         case RMX_CENTER:
  51                 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  52                 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  53                 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  54                 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  55                 break;
  56         case RMX_ASPECT:
  57                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  58                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  59
  60                 if (a1 > a2) {
  61                         args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  62                         args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  63                 } else if (a2 > a1) {
  64                         args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  65                         args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  66                 }
  67                 break;
  68         case RMX_FULL:
  69         default:
  70                 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
  71                 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
  72                 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
  73                 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
  74                 break;
  75         }
  76         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  77 }
  78
  79 static void atombios_scaler_setup(struct drm_crtc *crtc)
  80 {
  81         struct drm_device *dev = crtc->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  84         ENABLE_SCALER_PS_ALLOCATION args;
  85         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  86         struct radeon_encoder *radeon_encoder =
  87                 to_radeon_encoder(radeon_crtc->encoder);
  88         /* fixme - fill in enc_priv for atom dac */
  89         enum radeon_tv_std tv_std = TV_STD_NTSC;
  90         bool is_tv = false, is_cv = false;
  91
  92         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  93                 return;
  94
  95         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
  96                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
  97                 tv_std = tv_dac->tv_std;
  98                 is_tv = true;
  99         }
 100
 101         memset(&args, 0, sizeof(args));
 102
 103         args.ucScaler = radeon_crtc->crtc_id;
 104
 105         if (is_tv) {
 106                 switch (tv_std) {
 107                 case TV_STD_NTSC:
 108                 default:
 109                         args.ucTVStandard = ATOM_TV_NTSC;
 110                         break;
 111                 case TV_STD_PAL:
 112                         args.ucTVStandard = ATOM_TV_PAL;
 113                         break;
 114                 case TV_STD_PAL_M:
 115                         args.ucTVStandard = ATOM_TV_PALM;
 116                         break;
 117                 case TV_STD_PAL_60:
 118                         args.ucTVStandard = ATOM_TV_PAL60;
 119                         break;
 120                 case TV_STD_NTSC_J:
 121                         args.ucTVStandard = ATOM_TV_NTSCJ;
 122                         break;
 123                 case TV_STD_SCART_PAL:
 124                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 125                         break;
 126                 case TV_STD_SECAM:
 127                         args.ucTVStandard = ATOM_TV_SECAM;
 128                         break;
 129                 case TV_STD_PAL_CN:
 130                         args.ucTVStandard = ATOM_TV_PALCN;
 131                         break;
 132                 }
 133                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 134         } else if (is_cv) {
 135                 args.ucTVStandard = ATOM_TV_CV;
 136                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 137         } else {
 138                 switch (radeon_crtc->rmx_type) {
 139                 case RMX_FULL:
 140                         args.ucEnable = ATOM_SCALER_EXPANSION;
 141                         break;
 142                 case RMX_CENTER:
 143                         args.ucEnable = ATOM_SCALER_CENTER;
 144                         break;
 145                 case RMX_ASPECT:
 146                         args.ucEnable = ATOM_SCALER_EXPANSION;
 147                         break;
 148                 default:
 149                         if (ASIC_IS_AVIVO(rdev))
 150                                 args.ucEnable = ATOM_SCALER_DISABLE;
 151                         else
 152                                 args.ucEnable = ATOM_SCALER_CENTER;
 153                         break;
 154                 }
 155         }
 156         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 157         if ((is_tv || is_cv)
 158             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 159                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 160         }
 161 }
 162
 163 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 164 {
 165         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 166         struct drm_device *dev = crtc->dev;
 167         struct radeon_device *rdev = dev->dev_private;
 168         int index =
 169             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 170         ENABLE_CRTC_PS_ALLOCATION args;
 171
 172         memset(&args, 0, sizeof(args));
 173
 174         args.ucCRTC = radeon_crtc->crtc_id;
 175         args.ucEnable = lock;
 176
 177         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 178 }
 179
 180 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 181 {
 182         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 183         struct drm_device *dev = crtc->dev;
 184         struct radeon_device *rdev = dev->dev_private;
 185         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 186         ENABLE_CRTC_PS_ALLOCATION args;
 187
 188         memset(&args, 0, sizeof(args));
 189
 190         args.ucCRTC = radeon_crtc->crtc_id;
 191         args.ucEnable = state;
 192
 193         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 194 }
 195
 196 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 197 {
 198         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 199         struct drm_device *dev = crtc->dev;
 200         struct radeon_device *rdev = dev->dev_private;
 201         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 202         ENABLE_CRTC_PS_ALLOCATION args;
 203
 204         memset(&args, 0, sizeof(args));
 205
 206         args.ucCRTC = radeon_crtc->crtc_id;
 207         args.ucEnable = state;
 208
 209         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 210 }
 211
 212 static const u32 vga_control_regs[6] =
 213 {
 214         AVIVO_D1VGA_CONTROL,
 215         AVIVO_D2VGA_CONTROL,
 216         EVERGREEN_D3VGA_CONTROL,
 217         EVERGREEN_D4VGA_CONTROL,
 218         EVERGREEN_D5VGA_CONTROL,
 219         EVERGREEN_D6VGA_CONTROL,
 220 };
 221
 222 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 223 {
 224         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 225         struct drm_device *dev = crtc->dev;
 226         struct radeon_device *rdev = dev->dev_private;
 227         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 228         BLANK_CRTC_PS_ALLOCATION args;
 229         u32 vga_control = 0;
 230
 231         memset(&args, 0, sizeof(args));
 232
 233         if (ASIC_IS_DCE8(rdev)) {
 234                 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
 235                 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
 236         }
 237
 238         args.ucCRTC = radeon_crtc->crtc_id;
 239         args.ucBlanking = state;
 240
 241         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 242
 243         if (ASIC_IS_DCE8(rdev)) {
 244                 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
 245         }
 246 }
 247
 248 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
 249 {
 250         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 251         struct drm_device *dev = crtc->dev;
 252         struct radeon_device *rdev = dev->dev_private;
 253         int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
 254         ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
 255
 256         memset(&args, 0, sizeof(args));
 257
 258         args.ucDispPipeId = radeon_crtc->crtc_id;
 259         args.ucEnable = state;
 260
 261         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 262 }
 263
 264 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 265 {
 266         struct drm_device *dev = crtc->dev;
 267         struct radeon_device *rdev = dev->dev_private;
 268         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 269
 270         switch (mode) {
 271         case DRM_MODE_DPMS_ON:
 272                 radeon_crtc->enabled = true;
 273                 atombios_enable_crtc(crtc, ATOM_ENABLE);
 274                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 275                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 276                 atombios_blank_crtc(crtc, ATOM_DISABLE);
 277                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 278                 radeon_crtc_load_lut(crtc);
 279                 break;
 280         case DRM_MODE_DPMS_STANDBY:
 281         case DRM_MODE_DPMS_SUSPEND:
 282         case DRM_MODE_DPMS_OFF:
 283                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 284                 if (radeon_crtc->enabled)
 285                         atombios_blank_crtc(crtc, ATOM_ENABLE);
 286                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 287                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 288                 atombios_enable_crtc(crtc, ATOM_DISABLE);
 289                 radeon_crtc->enabled = false;
 290                 break;
 291         }
 292         /* adjust pm to dpms */
 293         radeon_pm_compute_clocks(rdev);
 294 }
 295
 296 static void
 297 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 298                              struct drm_display_mode *mode)
 299 {
 300         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 301         struct drm_device *dev = crtc->dev;
 302         struct radeon_device *rdev = dev->dev_private;
 303         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 304         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 305         u16 misc = 0;
 306
 307         memset(&args, 0, sizeof(args));
 308         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
 309         args.usH_Blanking_Time =
 310                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
 311         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
 312         args.usV_Blanking_Time =
 313                 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
 314         args.usH_SyncOffset =
 315                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
 316         args.usH_SyncWidth =
 317                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 318         args.usV_SyncOffset =
 319                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
 320         args.usV_SyncWidth =
 321                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 322         args.ucH_Border = radeon_crtc->h_border;
 323         args.ucV_Border = radeon_crtc->v_border;
 324
 325         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 326                 misc |= ATOM_VSYNC_POLARITY;
 327         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 328                 misc |= ATOM_HSYNC_POLARITY;
 329         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 330                 misc |= ATOM_COMPOSITESYNC;
 331         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 332                 misc |= ATOM_INTERLACE;
 333         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 334                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 335         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 336                 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
 337
 338         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 339         args.ucCRTC = radeon_crtc->crtc_id;
 340
 341         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 342 }
 343
 344 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 345                                      struct drm_display_mode *mode)
 346 {
 347         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 348         struct drm_device *dev = crtc->dev;
 349         struct radeon_device *rdev = dev->dev_private;
 350         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 351         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 352         u16 misc = 0;
 353
 354         memset(&args, 0, sizeof(args));
 355         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 356         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 357         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 358         args.usH_SyncWidth =
 359                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 360         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 361         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 362         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 363         args.usV_SyncWidth =
 364                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 365
 366         args.ucOverscanRight = radeon_crtc->h_border;
 367         args.ucOverscanLeft = radeon_crtc->h_border;
 368         args.ucOverscanBottom = radeon_crtc->v_border;
 369         args.ucOverscanTop = radeon_crtc->v_border;
 370
 371         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 372                 misc |= ATOM_VSYNC_POLARITY;
 373         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 374                 misc |= ATOM_HSYNC_POLARITY;
 375         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 376                 misc |= ATOM_COMPOSITESYNC;
 377         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 378                 misc |= ATOM_INTERLACE;
 379         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 380                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 381         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 382                 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
 383
 384         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 385         args.ucCRTC = radeon_crtc->crtc_id;
 386
 387         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 388 }
 389
 390 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
 391 {
 392         u32 ss_cntl;
 393
 394         if (ASIC_IS_DCE4(rdev)) {
 395                 switch (pll_id) {
 396                 case ATOM_PPLL1:
 397                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 398                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 399                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 400                         break;
 401                 case ATOM_PPLL2:
 402                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 403                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 404                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 405                         break;
 406                 case ATOM_DCPLL:
 407                 case ATOM_PPLL_INVALID:
 408                         return;
 409                 }
 410         } else if (ASIC_IS_AVIVO(rdev)) {
 411                 switch (pll_id) {
 412                 case ATOM_PPLL1:
 413                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 414                         ss_cntl &= ~1;
 415                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 416                         break;
 417                 case ATOM_PPLL2:
 418                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 419                         ss_cntl &= ~1;
 420                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 421                         break;
 422                 case ATOM_DCPLL:
 423                 case ATOM_PPLL_INVALID:
 424                         return;
 425                 }
 426         }
 427 }
 428
 429
 430 union atom_enable_ss {
 431         ENABLE_LVDS_SS_PARAMETERS lvds_ss;
 432         ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
 433         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 434         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
 435         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
 436 };
 437
 438 static void atombios_crtc_program_ss(struct radeon_device *rdev,
 439                                      int enable,
 440                                      int pll_id,
 441                                      int crtc_id,
 442                                      struct radeon_atom_ss *ss)
 443 {
 444         unsigned i;
 445         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 446         union atom_enable_ss args;
 447
 448         if (enable) {
 449                 /* Don't mess with SS if percentage is 0 or external ss.
 450                  * SS is already disabled previously, and disabling it
 451                  * again can cause display problems if the pll is already
 452                  * programmed.
 453                  */
 454                 if (ss->percentage == 0)
 455                         return;
 456                 if (ss->type & ATOM_EXTERNAL_SS_MASK)
 457                         return;
 458         } else {
 459                 for (i = 0; i < rdev->num_crtc; i++) {
 460                         if (rdev->mode_info.crtcs[i] &&
 461                             rdev->mode_info.crtcs[i]->enabled &&
 462                             i != crtc_id &&
 463                             pll_id == rdev->mode_info.crtcs[i]->pll_id) {
 464                                 /* one other crtc is using this pll don't turn
 465                                  * off spread spectrum as it might turn off
 466                                  * display on active crtc
 467                                  */
 468                                 return;
 469                         }
 470                 }
 471         }
 472
 473         memset(&args, 0, sizeof(args));
 474
 475         if (ASIC_IS_DCE5(rdev)) {
 476                 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
 477                 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 478                 switch (pll_id) {
 479                 case ATOM_PPLL1:
 480                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
 481                         break;
 482                 case ATOM_PPLL2:
 483                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
 484                         break;
 485                 case ATOM_DCPLL:
 486                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
 487                         break;
 488                 case ATOM_PPLL_INVALID:
 489                         return;
 490                 }
 491                 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 492                 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 493                 args.v3.ucEnable = enable;
 494         } else if (ASIC_IS_DCE4(rdev)) {
 495                 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 496                 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 497                 switch (pll_id) {
 498                 case ATOM_PPLL1:
 499                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
 500                         break;
 501                 case ATOM_PPLL2:
 502                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
 503                         break;
 504                 case ATOM_DCPLL:
 505                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
 506                         break;
 507                 case ATOM_PPLL_INVALID:
 508                         return;
 509                 }
 510                 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 511                 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 512                 args.v2.ucEnable = enable;
 513         } else if (ASIC_IS_DCE3(rdev)) {
 514                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 515                 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 516                 args.v1.ucSpreadSpectrumStep = ss->step;
 517                 args.v1.ucSpreadSpectrumDelay = ss->delay;
 518                 args.v1.ucSpreadSpectrumRange = ss->range;
 519                 args.v1.ucPpll = pll_id;
 520                 args.v1.ucEnable = enable;
 521         } else if (ASIC_IS_AVIVO(rdev)) {
 522                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 523                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
 524                         atombios_disable_ss(rdev, pll_id);
 525                         return;
 526                 }
 527                 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 528                 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 529                 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
 530                 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
 531                 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
 532                 args.lvds_ss_2.ucEnable = enable;
 533         } else {
 534                 if (enable == ATOM_DISABLE) {
 535                         atombios_disable_ss(rdev, pll_id);
 536                         return;
 537                 }
 538                 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 539                 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 540                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
 541                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
 542                 args.lvds_ss.ucEnable = enable;
 543         }
 544         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 545 }
 546
 547 union adjust_pixel_clock {
 548         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 549         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 550 };
 551
 552 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 553                                struct drm_display_mode *mode)
 554 {
 555         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 556         struct drm_device *dev = crtc->dev;
 557         struct radeon_device *rdev = dev->dev_private;
 558         struct drm_encoder *encoder = radeon_crtc->encoder;
 559         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 560         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 561         u32 adjusted_clock = mode->clock;
 562         int encoder_mode = atombios_get_encoder_mode(encoder);
 563         u32 dp_clock = mode->clock;
 564         u32 clock = mode->clock;
 565         int bpc = radeon_crtc->bpc;
 566         bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
 567
 568         /* reset the pll flags */
 569         radeon_crtc->pll_flags = 0;
 570
 571         if (ASIC_IS_AVIVO(rdev)) {
 572                 if ((rdev->family == CHIP_RS600) ||
 573                     (rdev->family == CHIP_RS690) ||
 574                     (rdev->family == CHIP_RS740))
 575                         radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
 576                                 RADEON_PLL_PREFER_CLOSEST_LOWER);
 577
 578                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 579                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 580                 else
 581                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 582
 583                 if (rdev->family < CHIP_RV770)
 584                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
 585                 /* use frac fb div on APUs */
 586                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
 587                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 588                 /* use frac fb div on RS780/RS880 */
 589                 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
 590                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 591                 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
 592                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 593         } else {
 594                 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
 595
 596                 if (mode->clock > 200000)       /* range limits??? */
 597                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 598                 else
 599                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 600         }
 601
 602         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 603             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
 604                 if (connector) {
 605                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 606                         struct radeon_connector_atom_dig *dig_connector =
 607                                 radeon_connector->con_priv;
 608
 609                         dp_clock = dig_connector->dp_clock;
 610                 }
 611         }
 612
 613         if (radeon_encoder->is_mst_encoder) {
 614                 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
 615                 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
 616
 617                 dp_clock = dig_connector->dp_clock;
 618         }
 619
 620         /* use recommended ref_div for ss */
 621         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 622                 if (radeon_crtc->ss_enabled) {
 623                         if (radeon_crtc->ss.refdiv) {
 624                                 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 625                                 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
 626                                 if (ASIC_IS_AVIVO(rdev))
 627                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 628                         }
 629                 }
 630         }
 631
 632         if (ASIC_IS_AVIVO(rdev)) {
 633                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 634                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 635                         adjusted_clock = mode->clock * 2;
 636                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 637                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
 638                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 639                         radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
 640         } else {
 641                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 642                         radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 643                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 644                         radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 645         }
 646
 647         /* adjust pll for deep color modes */
 648         if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
 649                 switch (bpc) {
 650                 case 8:
 651                 default:
 652                         break;
 653                 case 10:
 654                         clock = (clock * 5) / 4;
 655                         break;
 656                 case 12:
 657                         clock = (clock * 3) / 2;
 658                         break;
 659                 case 16:
 660                         clock = clock * 2;
 661                         break;
 662                 }
 663         }
 664
 665         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 666          * accordingly based on the encoder/transmitter to work around
 667          * special hw requirements.
 668          */
 669         if (ASIC_IS_DCE3(rdev)) {
 670                 union adjust_pixel_clock args;
 671                 u8 frev, crev;
 672                 int index;
 673
 674                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 675                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 676                                            &crev))
 677                         return adjusted_clock;
 678
 679                 memset(&args, 0, sizeof(args));
 680
 681                 switch (frev) {
 682                 case 1:
 683                         switch (crev) {
 684                         case 1:
 685                         case 2:
 686                                 args.v1.usPixelClock = cpu_to_le16(clock / 10);
 687                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 688                                 args.v1.ucEncodeMode = encoder_mode;
 689                                 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
 690                                         args.v1.ucConfig |=
 691                                                 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 692
 693                                 atom_execute_table(rdev->mode_info.atom_context,
 694                                                    index, (uint32_t *)&args);
 695                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 696                                 break;
 697                         case 3:
 698                                 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
 699                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 700                                 args.v3.sInput.ucEncodeMode = encoder_mode;
 701                                 args.v3.sInput.ucDispPllConfig = 0;
 702                                 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
 703                                         args.v3.sInput.ucDispPllConfig |=
 704                                                 DISPPLL_CONFIG_SS_ENABLE;
 705                                 if (ENCODER_MODE_IS_DP(encoder_mode)) {
 706                                         args.v3.sInput.ucDispPllConfig |=
 707                                                 DISPPLL_CONFIG_COHERENT_MODE;
 708                                         /* 16200 or 27000 */
 709                                         args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 710                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 711                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 712                                         if (dig->coherent_mode)
 713                                                 args.v3.sInput.ucDispPllConfig |=
 714                                                         DISPPLL_CONFIG_COHERENT_MODE;
 715                                         if (is_duallink)
 716                                                 args.v3.sInput.ucDispPllConfig |=
 717                                                         DISPPLL_CONFIG_DUAL_LINK;
 718                                 }
 719                                 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
 720                                     ENCODER_OBJECT_ID_NONE)
 721                                         args.v3.sInput.ucExtTransmitterID =
 722                                                 radeon_encoder_get_dp_bridge_encoder_id(encoder);
 723                                 else
 724                                         args.v3.sInput.ucExtTransmitterID = 0;
 725
 726                                 atom_execute_table(rdev->mode_info.atom_context,
 727                                                    index, (uint32_t *)&args);
 728                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 729                                 if (args.v3.sOutput.ucRefDiv) {
 730                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 731                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 732                                         radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
 733                                 }
 734                                 if (args.v3.sOutput.ucPostDiv) {
 735                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 736                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
 737                                         radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
 738                                 }
 739                                 break;
 740                         default:
 741                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 742                                 return adjusted_clock;
 743                         }
 744                         break;
 745                 default:
 746                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 747                         return adjusted_clock;
 748                 }
 749         }
 750         return adjusted_clock;
 751 }
 752
 753 union set_pixel_clock {
 754         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 755         PIXEL_CLOCK_PARAMETERS v1;
 756         PIXEL_CLOCK_PARAMETERS_V2 v2;
 757         PIXEL_CLOCK_PARAMETERS_V3 v3;
 758         PIXEL_CLOCK_PARAMETERS_V5 v5;
 759         PIXEL_CLOCK_PARAMETERS_V6 v6;
 760 };
 761
 762 /* on DCE5, make sure the voltage is high enough to support the
 763  * required disp clk.
 764  */
 765 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
 766                                     u32 dispclk)
 767 {
 768         u8 frev, crev;
 769         int index;
 770         union set_pixel_clock args;
 771
 772         memset(&args, 0, sizeof(args));
 773
 774         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 775         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 776                                    &crev))
 777                 return;
 778
 779         switch (frev) {
 780         case 1:
 781                 switch (crev) {
 782                 case 5:
 783                         /* if the default dcpll clock is specified,
 784                          * SetPixelClock provides the dividers
 785                          */
 786                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 787                         args.v5.usPixelClock = cpu_to_le16(dispclk);
 788                         args.v5.ucPpll = ATOM_DCPLL;
 789                         break;
 790                 case 6:
 791                         /* if the default dcpll clock is specified,
 792                          * SetPixelClock provides the dividers
 793                          */
 794                         args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
 795                         if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
 796                                 args.v6.ucPpll = ATOM_EXT_PLL1;
 797                         else if (ASIC_IS_DCE6(rdev))
 798                                 args.v6.ucPpll = ATOM_PPLL0;
 799                         else
 800                                 args.v6.ucPpll = ATOM_DCPLL;
 801                         break;
 802                 default:
 803                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 804                         return;
 805                 }
 806                 break;
 807         default:
 808                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 809                 return;
 810         }
 811         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 812 }
 813
 814 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
 815                                       u32 crtc_id,
 816                                       int pll_id,
 817                                       u32 encoder_mode,
 818                                       u32 encoder_id,
 819                                       u32 clock,
 820                                       u32 ref_div,
 821                                       u32 fb_div,
 822                                       u32 frac_fb_div,
 823                                       u32 post_div,
 824                                       int bpc,
 825                                       bool ss_enabled,
 826                                       struct radeon_atom_ss *ss)
 827 {
 828         struct drm_device *dev = crtc->dev;
 829         struct radeon_device *rdev = dev->dev_private;
 830         u8 frev, crev;
 831         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 832         union set_pixel_clock args;
 833
 834         memset(&args, 0, sizeof(args));
 835
 836         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 837                                    &crev))
 838                 return;
 839
 840         switch (frev) {
 841         case 1:
 842                 switch (crev) {
 843                 case 1:
 844                         if (clock == ATOM_DISABLE)
 845                                 return;
 846                         args.v1.usPixelClock = cpu_to_le16(clock / 10);
 847                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 848                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 849                         args.v1.ucFracFbDiv = frac_fb_div;
 850                         args.v1.ucPostDiv = post_div;
 851                         args.v1.ucPpll = pll_id;
 852                         args.v1.ucCRTC = crtc_id;
 853                         args.v1.ucRefDivSrc = 1;
 854                         break;
 855                 case 2:
 856                         args.v2.usPixelClock = cpu_to_le16(clock / 10);
 857                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 858                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 859                         args.v2.ucFracFbDiv = frac_fb_div;
 860                         args.v2.ucPostDiv = post_div;
 861                         args.v2.ucPpll = pll_id;
 862                         args.v2.ucCRTC = crtc_id;
 863                         args.v2.ucRefDivSrc = 1;
 864                         break;
 865                 case 3:
 866                         args.v3.usPixelClock = cpu_to_le16(clock / 10);
 867                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 868                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 869                         args.v3.ucFracFbDiv = frac_fb_div;
 870                         args.v3.ucPostDiv = post_div;
 871                         args.v3.ucPpll = pll_id;
 872                         if (crtc_id == ATOM_CRTC2)
 873                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
 874                         else
 875                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
 876                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 877                                 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
 878                         args.v3.ucTransmitterId = encoder_id;
 879                         args.v3.ucEncoderMode = encoder_mode;
 880                         break;
 881                 case 5:
 882                         args.v5.ucCRTC = crtc_id;
 883                         args.v5.usPixelClock = cpu_to_le16(clock / 10);
 884                         args.v5.ucRefDiv = ref_div;
 885                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 886                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 887                         args.v5.ucPostDiv = post_div;
 888                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 889                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 890                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
 891                         if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
 892                                 switch (bpc) {
 893                                 case 8:
 894                                 default:
 895                                         args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
 896                                         break;
 897                                 case 10:
 898                                         /* yes this is correct, the atom define is wrong */
 899                                         args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
 900                                         break;
 901                                 case 12:
 902                                         /* yes this is correct, the atom define is wrong */
 903                                         args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
 904                                         break;
 905                                 }
 906                         }
 907                         args.v5.ucTransmitterID = encoder_id;
 908                         args.v5.ucEncoderMode = encoder_mode;
 909                         args.v5.ucPpll = pll_id;
 910                         break;
 911                 case 6:
 912                         args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
 913                         args.v6.ucRefDiv = ref_div;
 914                         args.v6.usFbDiv = cpu_to_le16(fb_div);
 915                         args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 916                         args.v6.ucPostDiv = post_div;
 917                         args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
 918                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 919                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
 920                         if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
 921                                 switch (bpc) {
 922                                 case 8:
 923                                 default:
 924                                         args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
 925                                         break;
 926                                 case 10:
 927                                         args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
 928                                         break;
 929                                 case 12:
 930                                         args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
 931                                         break;
 932                                 case 16:
 933                                         args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
 934                                         break;
 935                                 }
 936                         }
 937                         args.v6.ucTransmitterID = encoder_id;
 938                         args.v6.ucEncoderMode = encoder_mode;
 939                         args.v6.ucPpll = pll_id;
 940                         break;
 941                 default:
 942                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 943                         return;
 944                 }
 945                 break;
 946         default:
 947                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 948                 return;
 949         }
 950
 951         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 952 }
 953
 954 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 955 {
 956         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 957         struct drm_device *dev = crtc->dev;
 958         struct radeon_device *rdev = dev->dev_private;
 959         struct radeon_encoder *radeon_encoder =
 960                 to_radeon_encoder(radeon_crtc->encoder);
 961         int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
 962
 963         radeon_crtc->bpc = 8;
 964         radeon_crtc->ss_enabled = false;
 965
 966         if (radeon_encoder->is_mst_encoder) {
 967                 radeon_dp_mst_prepare_pll(crtc, mode);
 968         } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 969             (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
 970                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 971                 struct drm_connector *connector =
 972                         radeon_get_connector_for_encoder(radeon_crtc->encoder);
 973                 struct radeon_connector *radeon_connector =
 974                         to_radeon_connector(connector);
 975                 struct radeon_connector_atom_dig *dig_connector =
 976                         radeon_connector->con_priv;
 977                 int dp_clock;
 978
 979                 /* Assign mode clock for hdmi deep color max clock limit check */
 980                 radeon_connector->pixelclock_for_modeset = mode->clock;
 981                 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
 982
 983                 switch (encoder_mode) {
 984                 case ATOM_ENCODER_MODE_DP_MST:
 985                 case ATOM_ENCODER_MODE_DP:
 986                         /* DP/eDP */
 987                         dp_clock = dig_connector->dp_clock / 10;
 988                         if (ASIC_IS_DCE4(rdev))
 989                                 radeon_crtc->ss_enabled =
 990                                         radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
 991                                                                          ASIC_INTERNAL_SS_ON_DP,
 992                                                                          dp_clock);
 993                         else {
 994                                 if (dp_clock == 16200) {
 995                                         radeon_crtc->ss_enabled =
 996                                                 radeon_atombios_get_ppll_ss_info(rdev,
 997                                                                                  &radeon_crtc->ss,
 998                                                                                  ATOM_DP_SS_ID2);
 999                                         if (!radeon_crtc->ss_enabled)
1000                                                 radeon_crtc->ss_enabled =
1001                                                         radeon_atombios_get_ppll_ss_info(rdev,
1002                                                                                          &radeon_crtc->ss,
1003                                                                                          ATOM_DP_SS_ID1);
1004                                 } else {
1005                                         radeon_crtc->ss_enabled =
1006                                                 radeon_atombios_get_ppll_ss_info(rdev,
1007                                                                                  &radeon_crtc->ss,
1008                                                                                  ATOM_DP_SS_ID1);
1009                                 }
1010                                 /* disable spread spectrum on DCE3 DP */
1011                                 radeon_crtc->ss_enabled = false;
1012                         }
1013                         break;
1014                 case ATOM_ENCODER_MODE_LVDS:
1015                         if (ASIC_IS_DCE4(rdev))
1016                                 radeon_crtc->ss_enabled =
1017                                         radeon_atombios_get_asic_ss_info(rdev,
1018                                                                          &radeon_crtc->ss,
1019                                                                          dig->lcd_ss_id,
1020                                                                          mode->clock / 10);
1021                         else
1022                                 radeon_crtc->ss_enabled =
1023                                         radeon_atombios_get_ppll_ss_info(rdev,
1024                                                                          &radeon_crtc->ss,
1025                                                                          dig->lcd_ss_id);
1026                         break;
1027                 case ATOM_ENCODER_MODE_DVI:
1028                         if (ASIC_IS_DCE4(rdev))
1029                                 radeon_crtc->ss_enabled =
1030                                         radeon_atombios_get_asic_ss_info(rdev,
1031                                                                          &radeon_crtc->ss,
1032                                                                          ASIC_INTERNAL_SS_ON_TMDS,
1033                                                                          mode->clock / 10);
1034                         break;
1035                 case ATOM_ENCODER_MODE_HDMI:
1036                         if (ASIC_IS_DCE4(rdev))
1037                                 radeon_crtc->ss_enabled =
1038                                         radeon_atombios_get_asic_ss_info(rdev,
1039                                                                          &radeon_crtc->ss,
1040                                                                          ASIC_INTERNAL_SS_ON_HDMI,
1041                                                                          mode->clock / 10);
1042                         break;
1043                 default:
1044                         break;
1045                 }
1046         }
1047
1048         /* adjust pixel clock as needed */
1049         radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1050
1051         return true;
1052 }
1053
1054 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1055 {
1056         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1057         struct drm_device *dev = crtc->dev;
1058         struct radeon_device *rdev = dev->dev_private;
1059         struct radeon_encoder *radeon_encoder =
1060                 to_radeon_encoder(radeon_crtc->encoder);
1061         u32 pll_clock = mode->clock;
1062         u32 clock = mode->clock;
1063         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1064         struct radeon_pll *pll;
1065         int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1066
1067         /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
1068         if (ASIC_IS_DCE5(rdev) &&
1069             (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
1070             (radeon_crtc->bpc > 8))
1071                 clock = radeon_crtc->adjusted_clock;
1072
1073         switch (radeon_crtc->pll_id) {
1074         case ATOM_PPLL1:
1075                 pll = &rdev->clock.p1pll;
1076                 break;
1077         case ATOM_PPLL2:
1078                 pll = &rdev->clock.p2pll;
1079                 break;
1080         case ATOM_DCPLL:
1081         case ATOM_PPLL_INVALID:
1082         default:
1083                 pll = &rdev->clock.dcpll;
1084                 break;
1085         }
1086
1087         /* update pll params */
1088         pll->flags = radeon_crtc->pll_flags;
1089         pll->reference_div = radeon_crtc->pll_reference_div;
1090         pll->post_div = radeon_crtc->pll_post_div;
1091
1092         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1093                 /* TV seems to prefer the legacy algo on some boards */
1094                 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1095                                           &fb_div, &frac_fb_div, &ref_div, &post_div);
1096         else if (ASIC_IS_AVIVO(rdev))
1097                 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1098                                          &fb_div, &frac_fb_div, &ref_div, &post_div);
1099         else
1100                 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1101                                           &fb_div, &frac_fb_div, &ref_div, &post_div);
1102
1103         atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1104                                  radeon_crtc->crtc_id, &radeon_crtc->ss);
1105
1106         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1107                                   encoder_mode, radeon_encoder->encoder_id, clock,
1108                                   ref_div, fb_div, frac_fb_div, post_div,
1109                                   radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1110
1111         if (radeon_crtc->ss_enabled) {
1112                 /* calculate ss amount and step size */
1113                 if (ASIC_IS_DCE4(rdev)) {
1114                         u32 step_size;
1115                         u32 amount = (((fb_div * 10) + frac_fb_div) *
1116                                       (u32)radeon_crtc->ss.percentage) /
1117                                 (100 * (u32)radeon_crtc->ss.percentage_divider);
1118                         radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1119                         radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1120                                 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1121                         if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1122                                 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1123                                         (125 * 25 * pll->reference_freq / 100);
1124                         else
1125                                 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1126                                         (125 * 25 * pll->reference_freq / 100);
1127                         radeon_crtc->ss.step = step_size;
1128                 }
1129
1130                 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1131                                          radeon_crtc->crtc_id, &radeon_crtc->ss);
1132         }
1133 }
1134
1135 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1136                                  struct drm_framebuffer *fb,
1137                                  int x, int y, int atomic)
1138 {
1139         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1140         struct drm_device *dev = crtc->dev;
1141         struct radeon_device *rdev = dev->dev_private;
1142         struct radeon_framebuffer *radeon_fb;
1143         struct drm_framebuffer *target_fb;
1144         struct drm_gem_object *obj;
1145         struct radeon_bo *rbo;
1146         uint64_t fb_location;
1147         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1148         unsigned bankw, bankh, mtaspect, tile_split;
1149         u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1150         u32 tmp, viewport_w, viewport_h;
1151         int r;
1152         bool bypass_lut = false;
1153
1154         /* no fb bound */
1155         if (!atomic && !crtc->primary->fb) {
1156                 DRM_DEBUG_KMS("No FB bound\n");
1157                 return 0;
1158         }
1159
1160         if (atomic) {
1161                 radeon_fb = to_radeon_framebuffer(fb);
1162                 target_fb = fb;
1163         }
1164         else {
1165                 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1166                 target_fb = crtc->primary->fb;
1167         }
1168
1169         /* If atomic, assume fb object is pinned & idle & fenced and
1170          * just update base pointers
1171          */
1172         obj = radeon_fb->obj;
1173         rbo = gem_to_radeon_bo(obj);
1174         r = radeon_bo_reserve(rbo, false);
1175         if (unlikely(r != 0))
1176                 return r;
1177
1178         if (atomic)
1179                 fb_location = radeon_bo_gpu_offset(rbo);
1180         else {
1181                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1182                 if (unlikely(r != 0)) {
1183                         radeon_bo_unreserve(rbo);
1184                         return -EINVAL;
1185                 }
1186         }
1187
1188         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1189         radeon_bo_unreserve(rbo);
1190
1191         switch (target_fb->pixel_format) {
1192         case DRM_FORMAT_C8:
1193                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1194                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1195                 break;
1196         case DRM_FORMAT_XRGB4444:
1197         case DRM_FORMAT_ARGB4444:
1198                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1199                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1200 #ifdef __BIG_ENDIAN
1201                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1202 #endif
1203                 break;
1204         case DRM_FORMAT_XRGB1555:
1205         case DRM_FORMAT_ARGB1555:
1206                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1207                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1208 #ifdef __BIG_ENDIAN
1209                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1210 #endif
1211                 break;
1212         case DRM_FORMAT_BGRX5551:
1213         case DRM_FORMAT_BGRA5551:
1214                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1215                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1216 #ifdef __BIG_ENDIAN
1217                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1218 #endif
1219                 break;
1220         case DRM_FORMAT_RGB565:
1221                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1222                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1223 #ifdef __BIG_ENDIAN
1224                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1225 #endif
1226                 break;
1227         case DRM_FORMAT_XRGB8888:
1228         case DRM_FORMAT_ARGB8888:
1229                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1230                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1231 #ifdef __BIG_ENDIAN
1232                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1233 #endif
1234                 break;
1235         case DRM_FORMAT_XRGB2101010:
1236         case DRM_FORMAT_ARGB2101010:
1237                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1238                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1239 #ifdef __BIG_ENDIAN
1240                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1241 #endif
1242                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1243                 bypass_lut = true;
1244                 break;
1245         case DRM_FORMAT_BGRX1010102:
1246         case DRM_FORMAT_BGRA1010102:
1247                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1248                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1249 #ifdef __BIG_ENDIAN
1250                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1251 #endif
1252                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1253                 bypass_lut = true;
1254                 break;
1255         default:
1256                 DRM_ERROR("Unsupported screen format %s\n",
1257                           drm_get_format_name(target_fb->pixel_format));
1258                 return -EINVAL;
1259         }
1260
1261         if (tiling_flags & RADEON_TILING_MACRO) {
1262                 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1263
1264                 /* Set NUM_BANKS. */
1265                 if (rdev->family >= CHIP_TAHITI) {
1266                         unsigned index, num_banks;
1267
1268                         if (rdev->family >= CHIP_BONAIRE) {
1269                                 unsigned tileb, tile_split_bytes;
1270
1271                                 /* Calculate the macrotile mode index. */
1272                                 tile_split_bytes = 64 << tile_split;
1273                                 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1274                                 tileb = min(tile_split_bytes, tileb);
1275
1276                                 for (index = 0; tileb > 64; index++)
1277                                         tileb >>= 1;
1278
1279                                 if (index >= 16) {
1280                                         DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1281                                                   target_fb->bits_per_pixel, tile_split);
1282                                         return -EINVAL;
1283                                 }
1284
1285                                 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1286                         } else {
1287                                 switch (target_fb->bits_per_pixel) {
1288                                 case 8:
1289                                         index = 10;
1290                                         break;
1291                                 case 16:
1292                                         index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1293                                         break;
1294                                 default:
1295                                 case 32:
1296                                         index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1297                                         break;
1298                                 }
1299
1300                                 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1301                         }
1302
1303                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1304                 } else {
1305                         /* NI and older. */
1306                         if (rdev->family >= CHIP_CAYMAN)
1307                                 tmp = rdev->config.cayman.tile_config;
1308                         else
1309                                 tmp = rdev->config.evergreen.tile_config;
1310
1311                         switch ((tmp & 0xf0) >> 4) {
1312                         case 0: /* 4 banks */
1313                                 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1314                                 break;
1315                         case 1: /* 8 banks */
1316                         default:
1317                                 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1318                                 break;
1319                         case 2: /* 16 banks */
1320                                 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1321                                 break;
1322                         }
1323                 }
1324
1325                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1326                 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1327                 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1328                 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1329                 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1330                 if (rdev->family >= CHIP_BONAIRE) {
1331                         /* XXX need to know more about the surface tiling mode */
1332                         fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1333                 }
1334         } else if (tiling_flags & RADEON_TILING_MICRO)
1335                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1336
1337         if (rdev->family >= CHIP_BONAIRE) {
1338                 /* Read the pipe config from the 2D TILED SCANOUT mode.
1339                  * It should be the same for the other modes too, but not all
1340                  * modes set the pipe config field. */
1341                 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1342
1343                 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1344         } else if ((rdev->family == CHIP_TAHITI) ||
1345                    (rdev->family == CHIP_PITCAIRN))
1346                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1347         else if ((rdev->family == CHIP_VERDE) ||
1348                  (rdev->family == CHIP_OLAND) ||
1349                  (rdev->family == CHIP_HAINAN)) /* for completeness.  HAINAN has no display hw */
1350                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1351
1352         switch (radeon_crtc->crtc_id) {
1353         case 0:
1354                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1355                 break;
1356         case 1:
1357                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1358                 break;
1359         case 2:
1360                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1361                 break;
1362         case 3:
1363                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1364                 break;
1365         case 4:
1366                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1367                 break;
1368         case 5:
1369                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1370                 break;
1371         default:
1372                 break;
1373         }
1374
1375         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1376                upper_32_bits(fb_location));
1377         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1378                upper_32_bits(fb_location));
1379         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1380                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1381         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1382                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1383         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1384         WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1385
1386         /*
1387          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1388          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1389          * retain the full precision throughout the pipeline.
1390          */
1391         WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1392                  (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1393                  ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1394
1395         if (bypass_lut)
1396                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1397
1398         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1399         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1400         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1401         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1402         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1403         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1404
1405         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1406         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1407         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1408
1409         if (rdev->family >= CHIP_BONAIRE)
1410                 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1411                        target_fb->height);
1412         else
1413                 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1414                        target_fb->height);
1415         x &= ~3;
1416         y &= ~1;
1417         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1418                (x << 16) | y);
1419         viewport_w = crtc->mode.hdisplay;
1420         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1421         if ((rdev->family >= CHIP_BONAIRE) &&
1422             (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
1423                 viewport_h *= 2;
1424         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1425                (viewport_w << 16) | viewport_h);
1426
1427         /* pageflip setup */
1428         /* make sure flip is at vb rather than hb */
1429         tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1430         tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1431         WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1432
1433         /* set pageflip to happen only at start of vblank interval (front porch) */
1434         WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1435
1436         if (!atomic && fb && fb != crtc->primary->fb) {
1437                 radeon_fb = to_radeon_framebuffer(fb);
1438                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1439                 r = radeon_bo_reserve(rbo, false);
1440                 if (unlikely(r != 0))
1441                         return r;
1442                 radeon_bo_unpin(rbo);
1443                 radeon_bo_unreserve(rbo);
1444         }
1445
1446         /* Bytes per pixel may have changed */
1447         radeon_bandwidth_update(rdev);
1448
1449         return 0;
1450 }
1451
1452 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1453                                   struct drm_framebuffer *fb,
1454                                   int x, int y, int atomic)
1455 {
1456         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1457         struct drm_device *dev = crtc->dev;
1458         struct radeon_device *rdev = dev->dev_private;
1459         struct radeon_framebuffer *radeon_fb;
1460         struct drm_gem_object *obj;
1461         struct radeon_bo *rbo;
1462         struct drm_framebuffer *target_fb;
1463         uint64_t fb_location;
1464         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1465         u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1466         u32 tmp, viewport_w, viewport_h;
1467         int r;
1468         bool bypass_lut = false;
1469
1470         /* no fb bound */
1471         if (!atomic && !crtc->primary->fb) {
1472                 DRM_DEBUG_KMS("No FB bound\n");
1473                 return 0;
1474         }
1475
1476         if (atomic) {
1477                 radeon_fb = to_radeon_framebuffer(fb);
1478                 target_fb = fb;
1479         }
1480         else {
1481                 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1482                 target_fb = crtc->primary->fb;
1483         }
1484
1485         obj = radeon_fb->obj;
1486         rbo = gem_to_radeon_bo(obj);
1487         r = radeon_bo_reserve(rbo, false);
1488         if (unlikely(r != 0))
1489                 return r;
1490
1491         /* If atomic, assume fb object is pinned & idle & fenced and
1492          * just update base pointers
1493          */
1494         if (atomic)
1495                 fb_location = radeon_bo_gpu_offset(rbo);
1496         else {
1497                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1498                 if (unlikely(r != 0)) {
1499                         radeon_bo_unreserve(rbo);
1500                         return -EINVAL;
1501                 }
1502         }
1503         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1504         radeon_bo_unreserve(rbo);
1505
1506         switch (target_fb->pixel_format) {
1507         case DRM_FORMAT_C8:
1508                 fb_format =
1509                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1510                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1511                 break;
1512         case DRM_FORMAT_XRGB4444:
1513         case DRM_FORMAT_ARGB4444:
1514                 fb_format =
1515                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1516                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
1517 #ifdef __BIG_ENDIAN
1518                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1519 #endif
1520                 break;
1521         case DRM_FORMAT_XRGB1555:
1522                 fb_format =
1523                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1524                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1525 #ifdef __BIG_ENDIAN
1526                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1527 #endif
1528                 break;
1529         case DRM_FORMAT_RGB565:
1530                 fb_format =
1531                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1532                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1533 #ifdef __BIG_ENDIAN
1534                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1535 #endif
1536                 break;
1537         case DRM_FORMAT_XRGB8888:
1538         case DRM_FORMAT_ARGB8888:
1539                 fb_format =
1540                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1541                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1542 #ifdef __BIG_ENDIAN
1543                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1544 #endif
1545                 break;
1546         case DRM_FORMAT_XRGB2101010:
1547         case DRM_FORMAT_ARGB2101010:
1548                 fb_format =
1549                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1550                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
1551 #ifdef __BIG_ENDIAN
1552                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1553 #endif
1554                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1555                 bypass_lut = true;
1556                 break;
1557         default:
1558                 DRM_ERROR("Unsupported screen format %s\n",
1559                           drm_get_format_name(target_fb->pixel_format));
1560                 return -EINVAL;
1561         }
1562
1563         if (rdev->family >= CHIP_R600) {
1564                 if (tiling_flags & RADEON_TILING_MACRO)
1565                         fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1566                 else if (tiling_flags & RADEON_TILING_MICRO)
1567                         fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1568         } else {
1569                 if (tiling_flags & RADEON_TILING_MACRO)
1570                         fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1571
1572                 if (tiling_flags & RADEON_TILING_MICRO)
1573                         fb_format |= AVIVO_D1GRPH_TILED;
1574         }
1575
1576         if (radeon_crtc->crtc_id == 0)
1577                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1578         else
1579                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1580
1581         if (rdev->family >= CHIP_RV770) {
1582                 if (radeon_crtc->crtc_id) {
1583                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1584                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1585                 } else {
1586                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1587                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1588                 }
1589         }
1590         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1591                (u32) fb_location);
1592         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1593                radeon_crtc->crtc_offset, (u32) fb_location);
1594         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1595         if (rdev->family >= CHIP_R600)
1596                 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1597
1598         /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
1599         WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
1600                  (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
1601
1602         if (bypass_lut)
1603                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1604
1605         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1606         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1607         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1608         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1609         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1610         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1611
1612         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1613         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1614         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1615
1616         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1617                target_fb->height);
1618         x &= ~3;
1619         y &= ~1;
1620         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1621                (x << 16) | y);
1622         viewport_w = crtc->mode.hdisplay;
1623         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1624         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1625                (viewport_w << 16) | viewport_h);
1626
1627         /* pageflip setup */
1628         /* make sure flip is at vb rather than hb */
1629         tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1630         tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1631         WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1632
1633         /* set pageflip to happen only at start of vblank interval (front porch) */
1634         WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1635
1636         if (!atomic && fb && fb != crtc->primary->fb) {
1637                 radeon_fb = to_radeon_framebuffer(fb);
1638                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1639                 r = radeon_bo_reserve(rbo, false);
1640                 if (unlikely(r != 0))
1641                         return r;
1642                 radeon_bo_unpin(rbo);
1643                 radeon_bo_unreserve(rbo);
1644         }
1645
1646         /* Bytes per pixel may have changed */
1647         radeon_bandwidth_update(rdev);
1648
1649         return 0;
1650 }
1651
1652 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1653                            struct drm_framebuffer *old_fb)
1654 {
1655         struct drm_device *dev = crtc->dev;
1656         struct radeon_device *rdev = dev->dev_private;
1657
1658         if (ASIC_IS_DCE4(rdev))
1659                 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1660         else if (ASIC_IS_AVIVO(rdev))
1661                 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1662         else
1663                 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1664 }
1665
1666 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1667                                   struct drm_framebuffer *fb,
1668                                   int x, int y, enum mode_set_atomic state)
1669 {
1670        struct drm_device *dev = crtc->dev;
1671        struct radeon_device *rdev = dev->dev_private;
1672
1673         if (ASIC_IS_DCE4(rdev))
1674                 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1675         else if (ASIC_IS_AVIVO(rdev))
1676                 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1677         else
1678                 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1679 }
1680
1681 /* properly set additional regs when using atombios */
1682 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1683 {
1684         struct drm_device *dev = crtc->dev;
1685         struct radeon_device *rdev = dev->dev_private;
1686         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1687         u32 disp_merge_cntl;
1688
1689         switch (radeon_crtc->crtc_id) {
1690         case 0:
1691                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1692                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1693                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1694                 break;
1695         case 1:
1696                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1697                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1698                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1699                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1700                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1701                 break;
1702         }
1703 }
1704
1705 /**
1706  * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1707  *
1708  * @crtc: drm crtc
1709  *
1710  * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1711  */
1712 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1713 {
1714         struct drm_device *dev = crtc->dev;
1715         struct drm_crtc *test_crtc;
1716         struct radeon_crtc *test_radeon_crtc;
1717         u32 pll_in_use = 0;
1718
1719         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1720                 if (crtc == test_crtc)
1721                         continue;
1722
1723                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1724                 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1725                         pll_in_use |= (1 << test_radeon_crtc->pll_id);
1726         }
1727         return pll_in_use;
1728 }
1729
1730 /**
1731  * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1732  *
1733  * @crtc: drm crtc
1734  *
1735  * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1736  * also in DP mode.  For DP, a single PPLL can be used for all DP
1737  * crtcs/encoders.
1738  */
1739 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1740 {
1741         struct drm_device *dev = crtc->dev;
1742         struct drm_crtc *test_crtc;
1743         struct radeon_crtc *test_radeon_crtc;
1744
1745         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1746                 if (crtc == test_crtc)
1747                         continue;
1748                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1749                 if (test_radeon_crtc->encoder &&
1750                     ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1751                         /* for DP use the same PLL for all */
1752                         if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1753                                 return test_radeon_crtc->pll_id;
1754                 }
1755         }
1756         return ATOM_PPLL_INVALID;
1757 }
1758
1759 /**
1760  * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1761  *
1762  * @crtc: drm crtc
1763  * @encoder: drm encoder
1764  *
1765  * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1766  * be shared (i.e., same clock).
1767  */
1768 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1769 {
1770         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1771         struct drm_device *dev = crtc->dev;
1772         struct drm_crtc *test_crtc;
1773         struct radeon_crtc *test_radeon_crtc;
1774         u32 adjusted_clock, test_adjusted_clock;
1775
1776         adjusted_clock = radeon_crtc->adjusted_clock;
1777
1778         if (adjusted_clock == 0)
1779                 return ATOM_PPLL_INVALID;
1780
1781         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1782                 if (crtc == test_crtc)
1783                         continue;
1784                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1785                 if (test_radeon_crtc->encoder &&
1786                     !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1787                         /* check if we are already driving this connector with another crtc */
1788                         if (test_radeon_crtc->connector == radeon_crtc->connector) {
1789                                 /* if we are, return that pll */
1790                                 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1791                                         return test_radeon_crtc->pll_id;
1792                         }
1793                         /* for non-DP check the clock */
1794                         test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1795                         if ((crtc->mode.clock == test_crtc->mode.clock) &&
1796                             (adjusted_clock == test_adjusted_clock) &&
1797                             (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1798                             (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1799                                 return test_radeon_crtc->pll_id;
1800                 }
1801         }
1802         return ATOM_PPLL_INVALID;
1803 }
1804
1805 /**
1806  * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1807  *
1808  * @crtc: drm crtc
1809  *
1810  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
1811  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
1812  * monitors a dedicated PPLL must be used.  If a particular board has
1813  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1814  * as there is no need to program the PLL itself.  If we are not able to
1815  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1816  * avoid messing up an existing monitor.
1817  *
1818  * Asic specific PLL information
1819  *
1820  * DCE 8.x
1821  * KB/KV
1822  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1823  * CI
1824  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1825  *
1826  * DCE 6.1
1827  * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1828  * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1829  *
1830  * DCE 6.0
1831  * - PPLL0 is available to all UNIPHY (DP only)
1832  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1833  *
1834  * DCE 5.0
1835  * - DCPLL is available to all UNIPHY (DP only)
1836  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1837  *
1838  * DCE 3.0/4.0/4.1
1839  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1840  *
1841  */
1842 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1843 {
1844         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1845         struct drm_device *dev = crtc->dev;
1846         struct radeon_device *rdev = dev->dev_private;
1847         struct radeon_encoder *radeon_encoder =
1848                 to_radeon_encoder(radeon_crtc->encoder);
1849         u32 pll_in_use;
1850         int pll;
1851
1852         if (ASIC_IS_DCE8(rdev)) {
1853                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1854                         if (rdev->clock.dp_extclk)
1855                                 /* skip PPLL programming if using ext clock */
1856                                 return ATOM_PPLL_INVALID;
1857                         else {
1858                                 /* use the same PPLL for all DP monitors */
1859                                 pll = radeon_get_shared_dp_ppll(crtc);
1860                                 if (pll != ATOM_PPLL_INVALID)
1861                                         return pll;
1862                         }
1863                 } else {
1864                         /* use the same PPLL for all monitors with the same clock */
1865                         pll = radeon_get_shared_nondp_ppll(crtc);
1866                         if (pll != ATOM_PPLL_INVALID)
1867                                 return pll;
1868                 }
1869                 /* otherwise, pick one of the plls */
1870                 if ((rdev->family == CHIP_KABINI) ||
1871                     (rdev->family == CHIP_MULLINS)) {
1872                         /* KB/ML has PPLL1 and PPLL2 */
1873                         pll_in_use = radeon_get_pll_use_mask(crtc);
1874                         if (!(pll_in_use & (1 << ATOM_PPLL2)))
1875                                 return ATOM_PPLL2;
1876                         if (!(pll_in_use & (1 << ATOM_PPLL1)))
1877                                 return ATOM_PPLL1;
1878                         DRM_ERROR("unable to allocate a PPLL\n");
1879                         return ATOM_PPLL_INVALID;
1880                 } else {
1881                         /* CI/KV has PPLL0, PPLL1, and PPLL2 */
1882                         pll_in_use = radeon_get_pll_use_mask(crtc);
1883                         if (!(pll_in_use & (1 << ATOM_PPLL2)))
1884                                 return ATOM_PPLL2;
1885                         if (!(pll_in_use & (1 << ATOM_PPLL1)))
1886                                 return ATOM_PPLL1;
1887                         if (!(pll_in_use & (1 << ATOM_PPLL0)))
1888                                 return ATOM_PPLL0;
1889                         DRM_ERROR("unable to allocate a PPLL\n");
1890                         return ATOM_PPLL_INVALID;
1891                 }
1892         } else if (ASIC_IS_DCE61(rdev)) {
1893                 struct radeon_encoder_atom_dig *dig =
1894                         radeon_encoder->enc_priv;
1895
1896                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1897                     (dig->linkb == false))
1898                         /* UNIPHY A uses PPLL2 */
1899                         return ATOM_PPLL2;
1900                 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1901                         /* UNIPHY B/C/D/E/F */
1902                         if (rdev->clock.dp_extclk)
1903                                 /* skip PPLL programming if using ext clock */
1904                                 return ATOM_PPLL_INVALID;
1905                         else {
1906                                 /* use the same PPLL for all DP monitors */
1907                                 pll = radeon_get_shared_dp_ppll(crtc);
1908                                 if (pll != ATOM_PPLL_INVALID)
1909                                         return pll;
1910                         }
1911                 } else {
1912                         /* use the same PPLL for all monitors with the same clock */
1913                         pll = radeon_get_shared_nondp_ppll(crtc);
1914                         if (pll != ATOM_PPLL_INVALID)
1915                                 return pll;
1916                 }
1917                 /* UNIPHY B/C/D/E/F */
1918                 pll_in_use = radeon_get_pll_use_mask(crtc);
1919                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1920                         return ATOM_PPLL0;
1921                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1922                         return ATOM_PPLL1;
1923                 DRM_ERROR("unable to allocate a PPLL\n");
1924                 return ATOM_PPLL_INVALID;
1925         } else if (ASIC_IS_DCE41(rdev)) {
1926                 /* Don't share PLLs on DCE4.1 chips */
1927                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1928                         if (rdev->clock.dp_extclk)
1929                                 /* skip PPLL programming if using ext clock */
1930                                 return ATOM_PPLL_INVALID;
1931                 }
1932                 pll_in_use = radeon_get_pll_use_mask(crtc);
1933                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1934                         return ATOM_PPLL1;
1935                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1936                         return ATOM_PPLL2;
1937                 DRM_ERROR("unable to allocate a PPLL\n");
1938                 return ATOM_PPLL_INVALID;
1939         } else if (ASIC_IS_DCE4(rdev)) {
1940                 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1941                  * depending on the asic:
1942                  * DCE4: PPLL or ext clock
1943                  * DCE5: PPLL, DCPLL, or ext clock
1944                  * DCE6: PPLL, PPLL0, or ext clock
1945                  *
1946                  * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1947                  * PPLL/DCPLL programming and only program the DP DTO for the
1948                  * crtc virtual pixel clock.
1949                  */
1950                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1951                         if (rdev->clock.dp_extclk)
1952                                 /* skip PPLL programming if using ext clock */
1953                                 return ATOM_PPLL_INVALID;
1954                         else if (ASIC_IS_DCE6(rdev))
1955                                 /* use PPLL0 for all DP */
1956                                 return ATOM_PPLL0;
1957                         else if (ASIC_IS_DCE5(rdev))
1958                                 /* use DCPLL for all DP */
1959                                 return ATOM_DCPLL;
1960                         else {
1961                                 /* use the same PPLL for all DP monitors */
1962                                 pll = radeon_get_shared_dp_ppll(crtc);
1963                                 if (pll != ATOM_PPLL_INVALID)
1964                                         return pll;
1965                         }
1966                 } else {
1967                         /* use the same PPLL for all monitors with the same clock */
1968                         pll = radeon_get_shared_nondp_ppll(crtc);
1969                         if (pll != ATOM_PPLL_INVALID)
1970                                 return pll;
1971                 }
1972                 /* all other cases */
1973                 pll_in_use = radeon_get_pll_use_mask(crtc);
1974                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1975                         return ATOM_PPLL1;
1976                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1977                         return ATOM_PPLL2;
1978                 DRM_ERROR("unable to allocate a PPLL\n");
1979                 return ATOM_PPLL_INVALID;
1980         } else {
1981                 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1982                 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1983                  * the matching btw pll and crtc is done through
1984                  * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1985                  * pll (1 or 2) to select which register to write. ie if using
1986                  * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1987                  * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1988                  * choose which value to write. Which is reverse order from
1989                  * register logic. So only case that works is when pllid is
1990                  * same as crtcid or when both pll and crtc are enabled and
1991                  * both use same clock.
1992                  *
1993                  * So just return crtc id as if crtc and pll were hard linked
1994                  * together even if they aren't
1995                  */
1996                 return radeon_crtc->crtc_id;
1997         }
1998 }
1999
2000 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
2001 {
2002         /* always set DCPLL */
2003         if (ASIC_IS_DCE6(rdev))
2004                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2005         else if (ASIC_IS_DCE4(rdev)) {
2006                 struct radeon_atom_ss ss;
2007                 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
2008                                                                    ASIC_INTERNAL_SS_ON_DCPLL,
2009                                                                    rdev->clock.default_dispclk);
2010                 if (ss_enabled)
2011                         atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
2012                 /* XXX: DCE5, make sure voltage, dispclk is high enough */
2013                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2014                 if (ss_enabled)
2015                         atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
2016         }
2017
2018 }
2019
2020 int atombios_crtc_mode_set(struct drm_crtc *crtc,
2021                            struct drm_display_mode *mode,
2022                            struct drm_display_mode *adjusted_mode,
2023                            int x, int y, struct drm_framebuffer *old_fb)
2024 {
2025         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2026         struct drm_device *dev = crtc->dev;
2027         struct radeon_device *rdev = dev->dev_private;
2028         struct radeon_encoder *radeon_encoder =
2029                 to_radeon_encoder(radeon_crtc->encoder);
2030         bool is_tvcv = false;
2031
2032         if (radeon_encoder->active_device &
2033             (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2034                 is_tvcv = true;
2035
2036         if (!radeon_crtc->adjusted_clock)
2037                 return -EINVAL;
2038
2039         atombios_crtc_set_pll(crtc, adjusted_mode);
2040
2041         if (ASIC_IS_DCE4(rdev))
2042                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2043         else if (ASIC_IS_AVIVO(rdev)) {
2044                 if (is_tvcv)
2045                         atombios_crtc_set_timing(crtc, adjusted_mode);
2046                 else
2047                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2048         } else {
2049                 atombios_crtc_set_timing(crtc, adjusted_mode);
2050                 if (radeon_crtc->crtc_id == 0)
2051                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2052                 radeon_legacy_atom_fixup(crtc);
2053         }
2054         atombios_crtc_set_base(crtc, x, y, old_fb);
2055         atombios_overscan_setup(crtc, mode, adjusted_mode);
2056         atombios_scaler_setup(crtc);
2057         radeon_cursor_reset(crtc);
2058         /* update the hw version fpr dpm */
2059         radeon_crtc->hw_mode = *adjusted_mode;
2060
2061         return 0;
2062 }
2063
2064 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
2065                                      const struct drm_display_mode *mode,
2066                                      struct drm_display_mode *adjusted_mode)
2067 {
2068         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2069         struct drm_device *dev = crtc->dev;
2070         struct drm_encoder *encoder;
2071
2072         /* assign the encoder to the radeon crtc to avoid repeated lookups later */
2073         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2074                 if (encoder->crtc == crtc) {
2075                         radeon_crtc->encoder = encoder;
2076                         radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
2077                         break;
2078                 }
2079         }
2080         if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
2081                 radeon_crtc->encoder = NULL;
2082                 radeon_crtc->connector = NULL;
2083                 return false;
2084         }
2085         if (radeon_crtc->encoder) {
2086                 struct radeon_encoder *radeon_encoder =
2087                         to_radeon_encoder(radeon_crtc->encoder);
2088
2089                 radeon_crtc->output_csc = radeon_encoder->output_csc;
2090         }
2091         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2092                 return false;
2093         if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
2094                 return false;
2095         /* pick pll */
2096         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
2097         /* if we can't get a PPLL for a non-DP encoder, fail */
2098         if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
2099             !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
2100                 return false;
2101
2102         return true;
2103 }
2104
2105 static void atombios_crtc_prepare(struct drm_crtc *crtc)
2106 {
2107         struct drm_device *dev = crtc->dev;
2108         struct radeon_device *rdev = dev->dev_private;
2109
2110         /* disable crtc pair power gating before programming */
2111         if (ASIC_IS_DCE6(rdev))
2112                 atombios_powergate_crtc(crtc, ATOM_DISABLE);
2113
2114         atombios_lock_crtc(crtc, ATOM_ENABLE);
2115         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2116 }
2117
2118 static void atombios_crtc_commit(struct drm_crtc *crtc)
2119 {
2120         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2121         atombios_lock_crtc(crtc, ATOM_DISABLE);
2122 }
2123
2124 static void atombios_crtc_disable(struct drm_crtc *crtc)
2125 {
2126         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2127         struct drm_device *dev = crtc->dev;
2128         struct radeon_device *rdev = dev->dev_private;
2129         struct radeon_atom_ss ss;
2130         int i;
2131
2132         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2133         if (crtc->primary->fb) {
2134                 int r;
2135                 struct radeon_framebuffer *radeon_fb;
2136                 struct radeon_bo *rbo;
2137
2138                 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
2139                 rbo = gem_to_radeon_bo(radeon_fb->obj);
2140                 r = radeon_bo_reserve(rbo, false);
2141                 if (unlikely(r))
2142                         DRM_ERROR("failed to reserve rbo before unpin\n");
2143                 else {
2144                         radeon_bo_unpin(rbo);
2145                         radeon_bo_unreserve(rbo);
2146                 }
2147         }
2148         /* disable the GRPH */
2149         if (ASIC_IS_DCE4(rdev))
2150                 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2151         else if (ASIC_IS_AVIVO(rdev))
2152                 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2153
2154         if (ASIC_IS_DCE6(rdev))
2155                 atombios_powergate_crtc(crtc, ATOM_ENABLE);
2156
2157         for (i = 0; i < rdev->num_crtc; i++) {
2158                 if (rdev->mode_info.crtcs[i] &&
2159                     rdev->mode_info.crtcs[i]->enabled &&
2160                     i != radeon_crtc->crtc_id &&
2161                     radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2162                         /* one other crtc is using this pll don't turn
2163                          * off the pll
2164                          */
2165                         goto done;
2166                 }
2167         }
2168
2169         switch (radeon_crtc->pll_id) {
2170         case ATOM_PPLL1:
2171         case ATOM_PPLL2:
2172                 /* disable the ppll */
2173                 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2174                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2175                 break;
2176         case ATOM_PPLL0:
2177                 /* disable the ppll */
2178                 if ((rdev->family == CHIP_ARUBA) ||
2179                     (rdev->family == CHIP_KAVERI) ||
2180                     (rdev->family == CHIP_BONAIRE) ||
2181                     (rdev->family == CHIP_HAWAII))
2182                         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2183                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2184                 break;
2185         default:
2186                 break;
2187         }
2188 done:
2189         radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2190         radeon_crtc->adjusted_clock = 0;
2191         radeon_crtc->encoder = NULL;
2192         radeon_crtc->connector = NULL;
2193 }
2194
2195 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2196         .dpms = atombios_crtc_dpms,
2197         .mode_fixup = atombios_crtc_mode_fixup,
2198         .mode_set = atombios_crtc_mode_set,
2199         .mode_set_base = atombios_crtc_set_base,
2200         .mode_set_base_atomic = atombios_crtc_set_base_atomic,
2201         .prepare = atombios_crtc_prepare,
2202         .commit = atombios_crtc_commit,
2203         .load_lut = radeon_crtc_load_lut,
2204         .disable = atombios_crtc_disable,
2205 };
2206
2207 void radeon_atombios_init_crtc(struct drm_device *dev,
2208                                struct radeon_crtc *radeon_crtc)
2209 {
2210         struct radeon_device *rdev = dev->dev_private;
2211
2212         if (ASIC_IS_DCE4(rdev)) {
2213                 switch (radeon_crtc->crtc_id) {
2214                 case 0:
2215                 default:
2216                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2217                         break;
2218                 case 1:
2219                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2220                         break;
2221                 case 2:
2222                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2223                         break;
2224                 case 3:
2225                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2226                         break;
2227                 case 4:
2228                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2229                         break;
2230                 case 5:
2231                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2232                         break;
2233                 }
2234         } else {
2235                 if (radeon_crtc->crtc_id == 1)
2236                         radeon_crtc->crtc_offset =
2237                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2238                 else
2239                         radeon_crtc->crtc_offset = 0;
2240         }
2241         radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2242         radeon_crtc->adjusted_clock = 0;
2243         radeon_crtc->encoder = NULL;
2244         radeon_crtc->connector = NULL;
2245         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2246 }