kernel/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

   1 /*
   2  * DMM IOMMU driver support functions for TI OMAP processors.
   3  *
   4  * Author: Rob Clark <rob@ti.com>
   5  *         Andy Gross <andy.gross@ti.com>
   6  *
   7  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation version 2.
  12  *
  13  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  14  * kind, whether express or implied; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h> /* platform_device() */
  21 #include <linux/errno.h>
  22 #include <linux/sched.h>
  23 #include <linux/wait.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/delay.h>
  29 #include <linux/mm.h>
  30 #include <linux/time.h>
  31 #include <linux/list.h>
  32 #include <linux/completion.h>
  33
  34 #include "omap_dmm_tiler.h"
  35 #include "omap_dmm_priv.h"
  36
  37 #define DMM_DRIVER_NAME "dmm"
  38
  39 /* mappings for associating views to luts */
  40 static struct tcm *containers[TILFMT_NFORMATS];
  41 static struct dmm *omap_dmm;
  42
  43 #if defined(CONFIG_OF)
  44 static const struct of_device_id dmm_of_match[];
  45 #endif
  46
  47 /* global spinlock for protecting lists */
  48 static DEFINE_SPINLOCK(list_lock);
  49
  50 /* Geometry table */
  51 #define GEOM(xshift, yshift, bytes_per_pixel) { \
  52                 .x_shft = (xshift), \
  53                 .y_shft = (yshift), \
  54                 .cpp    = (bytes_per_pixel), \
  55                 .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \
  56                 .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \
  57         }
  58
  59 static const struct {
  60         uint32_t x_shft;        /* unused X-bits (as part of bpp) */
  61         uint32_t y_shft;        /* unused Y-bits (as part of bpp) */
  62         uint32_t cpp;           /* bytes/chars per pixel */
  63         uint32_t slot_w;        /* width of each slot (in pixels) */
  64         uint32_t slot_h;        /* height of each slot (in pixels) */
  65 } geom[TILFMT_NFORMATS] = {
  66         [TILFMT_8BIT]  = GEOM(0, 0, 1),
  67         [TILFMT_16BIT] = GEOM(0, 1, 2),
  68         [TILFMT_32BIT] = GEOM(1, 1, 4),
  69         [TILFMT_PAGE]  = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1),
  70 };
  71
  72
  73 /* lookup table for registers w/ per-engine instances */
  74 static const uint32_t reg[][4] = {
  75         [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1,
  76                         DMM_PAT_STATUS__2, DMM_PAT_STATUS__3},
  77         [PAT_DESCR]  = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1,
  78                         DMM_PAT_DESCR__2, DMM_PAT_DESCR__3},
  79 };
  80
  81 /* simple allocator to grab next 16 byte aligned memory from txn */
  82 static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa)
  83 {
  84         void *ptr;
  85         struct refill_engine *engine = txn->engine_handle;
  86
  87         /* dmm programming requires 16 byte aligned addresses */
  88         txn->current_pa = round_up(txn->current_pa, 16);
  89         txn->current_va = (void *)round_up((long)txn->current_va, 16);
  90
  91         ptr = txn->current_va;
  92         *pa = txn->current_pa;
  93
  94         txn->current_pa += sz;
  95         txn->current_va += sz;
  96
  97         BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE);
  98
  99         return ptr;
 100 }
 101
 102 /* check status and spin until wait_mask comes true */
 103 static int wait_status(struct refill_engine *engine, uint32_t wait_mask)
 104 {
 105         struct dmm *dmm = engine->dmm;
 106         uint32_t r = 0, err, i;
 107
 108         i = DMM_FIXED_RETRY_COUNT;
 109         while (true) {
 110                 r = readl(dmm->base + reg[PAT_STATUS][engine->id]);
 111                 err = r & DMM_PATSTATUS_ERR;
 112                 if (err)
 113                         return -EFAULT;
 114
 115                 if ((r & wait_mask) == wait_mask)
 116                         break;
 117
 118                 if (--i == 0)
 119                         return -ETIMEDOUT;
 120
 121                 udelay(1);
 122         }
 123
 124         return 0;
 125 }
 126
 127 static void release_engine(struct refill_engine *engine)
 128 {
 129         unsigned long flags;
 130
 131         spin_lock_irqsave(&list_lock, flags);
 132         list_add(&engine->idle_node, &omap_dmm->idle_head);
 133         spin_unlock_irqrestore(&list_lock, flags);
 134
 135         atomic_inc(&omap_dmm->engine_counter);
 136         wake_up_interruptible(&omap_dmm->engine_queue);
 137 }
 138
 139 static irqreturn_t omap_dmm_irq_handler(int irq, void *arg)
 140 {
 141         struct dmm *dmm = arg;
 142         uint32_t status = readl(dmm->base + DMM_PAT_IRQSTATUS);
 143         int i;
 144
 145         /* ack IRQ */
 146         writel(status, dmm->base + DMM_PAT_IRQSTATUS);
 147
 148         for (i = 0; i < dmm->num_engines; i++) {
 149                 if (status & DMM_IRQSTAT_LST) {
 150                         if (dmm->engines[i].async)
 151                                 release_engine(&dmm->engines[i]);
 152
 153                         complete(&dmm->engines[i].compl);
 154                 }
 155
 156                 status >>= 8;
 157         }
 158
 159         return IRQ_HANDLED;
 160 }
 161
 162 /**
 163  * Get a handle for a DMM transaction
 164  */
 165 static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm)
 166 {
 167         struct dmm_txn *txn = NULL;
 168         struct refill_engine *engine = NULL;
 169         int ret;
 170         unsigned long flags;
 171
 172
 173         /* wait until an engine is available */
 174         ret = wait_event_interruptible(omap_dmm->engine_queue,
 175                 atomic_add_unless(&omap_dmm->engine_counter, -1, 0));
 176         if (ret)
 177                 return ERR_PTR(ret);
 178
 179         /* grab an idle engine */
 180         spin_lock_irqsave(&list_lock, flags);
 181         if (!list_empty(&dmm->idle_head)) {
 182                 engine = list_entry(dmm->idle_head.next, struct refill_engine,
 183                                         idle_node);
 184                 list_del(&engine->idle_node);
 185         }
 186         spin_unlock_irqrestore(&list_lock, flags);
 187
 188         BUG_ON(!engine);
 189
 190         txn = &engine->txn;
 191         engine->tcm = tcm;
 192         txn->engine_handle = engine;
 193         txn->last_pat = NULL;
 194         txn->current_va = engine->refill_va;
 195         txn->current_pa = engine->refill_pa;
 196
 197         return txn;
 198 }
 199
 200 /**
 201  * Add region to DMM transaction.  If pages or pages[i] is NULL, then the
 202  * corresponding slot is cleared (ie. dummy_pa is programmed)
 203  */
 204 static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area,
 205                 struct page **pages, uint32_t npages, uint32_t roll)
 206 {
 207         dma_addr_t pat_pa = 0, data_pa = 0;
 208         uint32_t *data;
 209         struct pat *pat;
 210         struct refill_engine *engine = txn->engine_handle;
 211         int columns = (1 + area->x1 - area->x0);
 212         int rows = (1 + area->y1 - area->y0);
 213         int i = columns*rows;
 214
 215         pat = alloc_dma(txn, sizeof(struct pat), &pat_pa);
 216
 217         if (txn->last_pat)
 218                 txn->last_pat->next_pa = (uint32_t)pat_pa;
 219
 220         pat->area = *area;
 221
 222         /* adjust Y coordinates based off of container parameters */
 223         pat->area.y0 += engine->tcm->y_offset;
 224         pat->area.y1 += engine->tcm->y_offset;
 225
 226         pat->ctrl = (struct pat_ctrl){
 227                         .start = 1,
 228                         .lut_id = engine->tcm->lut_id,
 229                 };
 230
 231         data = alloc_dma(txn, 4*i, &data_pa);
 232         /* FIXME: what if data_pa is more than 32-bit ? */
 233         pat->data_pa = data_pa;
 234
 235         while (i--) {
 236                 int n = i + roll;
 237                 if (n >= npages)
 238                         n -= npages;
 239                 data[i] = (pages && pages[n]) ?
 240                         page_to_phys(pages[n]) : engine->dmm->dummy_pa;
 241         }
 242
 243         txn->last_pat = pat;
 244
 245         return;
 246 }
 247
 248 /**
 249  * Commit the DMM transaction.
 250  */
 251 static int dmm_txn_commit(struct dmm_txn *txn, bool wait)
 252 {
 253         int ret = 0;
 254         struct refill_engine *engine = txn->engine_handle;
 255         struct dmm *dmm = engine->dmm;
 256
 257         if (!txn->last_pat) {
 258                 dev_err(engine->dmm->dev, "need at least one txn\n");
 259                 ret = -EINVAL;
 260                 goto cleanup;
 261         }
 262
 263         txn->last_pat->next_pa = 0;
 264
 265         /* write to PAT_DESCR to clear out any pending transaction */
 266         writel(0x0, dmm->base + reg[PAT_DESCR][engine->id]);
 267
 268         /* wait for engine ready: */
 269         ret = wait_status(engine, DMM_PATSTATUS_READY);
 270         if (ret) {
 271                 ret = -EFAULT;
 272                 goto cleanup;
 273         }
 274
 275         /* mark whether it is async to denote list management in IRQ handler */
 276         engine->async = wait ? false : true;
 277         reinit_completion(&engine->compl);
 278         /* verify that the irq handler sees the 'async' and completion value */
 279         smp_mb();
 280
 281         /* kick reload */
 282         writel(engine->refill_pa,
 283                 dmm->base + reg[PAT_DESCR][engine->id]);
 284
 285         if (wait) {
 286                 if (!wait_for_completion_timeout(&engine->compl,
 287                                 msecs_to_jiffies(1))) {
 288                         dev_err(dmm->dev, "timed out waiting for done\n");
 289                         ret = -ETIMEDOUT;
 290                 }
 291         }
 292
 293 cleanup:
 294         /* only place engine back on list if we are done with it */
 295         if (ret || wait)
 296                 release_engine(engine);
 297
 298         return ret;
 299 }
 300
 301 /*
 302  * DMM programming
 303  */
 304 static int fill(struct tcm_area *area, struct page **pages,
 305                 uint32_t npages, uint32_t roll, bool wait)
 306 {
 307         int ret = 0;
 308         struct tcm_area slice, area_s;
 309         struct dmm_txn *txn;
 310
 311         txn = dmm_txn_init(omap_dmm, area->tcm);
 312         if (IS_ERR_OR_NULL(txn))
 313                 return -ENOMEM;
 314
 315         tcm_for_each_slice(slice, *area, area_s) {
 316                 struct pat_area p_area = {
 317                                 .x0 = slice.p0.x,  .y0 = slice.p0.y,
 318                                 .x1 = slice.p1.x,  .y1 = slice.p1.y,
 319                 };
 320
 321                 dmm_txn_append(txn, &p_area, pages, npages, roll);
 322
 323                 roll += tcm_sizeof(slice);
 324         }
 325
 326         ret = dmm_txn_commit(txn, wait);
 327
 328         return ret;
 329 }
 330
 331 /*
 332  * Pin/unpin
 333  */
 334
 335 /* note: slots for which pages[i] == NULL are filled w/ dummy page
 336  */
 337 int tiler_pin(struct tiler_block *block, struct page **pages,
 338                 uint32_t npages, uint32_t roll, bool wait)
 339 {
 340         int ret;
 341
 342         ret = fill(&block->area, pages, npages, roll, wait);
 343
 344         if (ret)
 345                 tiler_unpin(block);
 346
 347         return ret;
 348 }
 349
 350 int tiler_unpin(struct tiler_block *block)
 351 {
 352         return fill(&block->area, NULL, 0, 0, false);
 353 }
 354
 355 /*
 356  * Reserve/release
 357  */
 358 struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w,
 359                 uint16_t h, uint16_t align)
 360 {
 361         struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
 362         u32 min_align = 128;
 363         int ret;
 364         unsigned long flags;
 365
 366         BUG_ON(!validfmt(fmt));
 367
 368         /* convert width/height to slots */
 369         w = DIV_ROUND_UP(w, geom[fmt].slot_w);
 370         h = DIV_ROUND_UP(h, geom[fmt].slot_h);
 371
 372         /* convert alignment to slots */
 373         min_align = max(min_align, (geom[fmt].slot_w * geom[fmt].cpp));
 374         align = ALIGN(align, min_align);
 375         align /= geom[fmt].slot_w * geom[fmt].cpp;
 376
 377         block->fmt = fmt;
 378
 379         ret = tcm_reserve_2d(containers[fmt], w, h, align, &block->area);
 380         if (ret) {
 381                 kfree(block);
 382                 return ERR_PTR(-ENOMEM);
 383         }
 384
 385         /* add to allocation list */
 386         spin_lock_irqsave(&list_lock, flags);
 387         list_add(&block->alloc_node, &omap_dmm->alloc_head);
 388         spin_unlock_irqrestore(&list_lock, flags);
 389
 390         return block;
 391 }
 392
 393 struct tiler_block *tiler_reserve_1d(size_t size)
 394 {
 395         struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
 396         int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 397         unsigned long flags;
 398
 399         if (!block)
 400                 return ERR_PTR(-ENOMEM);
 401
 402         block->fmt = TILFMT_PAGE;
 403
 404         if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages,
 405                                 &block->area)) {
 406                 kfree(block);
 407                 return ERR_PTR(-ENOMEM);
 408         }
 409
 410         spin_lock_irqsave(&list_lock, flags);
 411         list_add(&block->alloc_node, &omap_dmm->alloc_head);
 412         spin_unlock_irqrestore(&list_lock, flags);
 413
 414         return block;
 415 }
 416
 417 /* note: if you have pin'd pages, you should have already unpin'd first! */
 418 int tiler_release(struct tiler_block *block)
 419 {
 420         int ret = tcm_free(&block->area);
 421         unsigned long flags;
 422
 423         if (block->area.tcm)
 424                 dev_err(omap_dmm->dev, "failed to release block\n");
 425
 426         spin_lock_irqsave(&list_lock, flags);
 427         list_del(&block->alloc_node);
 428         spin_unlock_irqrestore(&list_lock, flags);
 429
 430         kfree(block);
 431         return ret;
 432 }
 433
 434 /*
 435  * Utils
 436  */
 437
 438 /* calculate the tiler space address of a pixel in a view orientation...
 439  * below description copied from the display subsystem section of TRM:
 440  *
 441  * When the TILER is addressed, the bits:
 442  *   [28:27] = 0x0 for 8-bit tiled
 443  *             0x1 for 16-bit tiled
 444  *             0x2 for 32-bit tiled
 445  *             0x3 for page mode
 446  *   [31:29] = 0x0 for 0-degree view
 447  *             0x1 for 180-degree view + mirroring
 448  *             0x2 for 0-degree view + mirroring
 449  *             0x3 for 180-degree view
 450  *             0x4 for 270-degree view + mirroring
 451  *             0x5 for 270-degree view
 452  *             0x6 for 90-degree view
 453  *             0x7 for 90-degree view + mirroring
 454  * Otherwise the bits indicated the corresponding bit address to access
 455  * the SDRAM.
 456  */
 457 static u32 tiler_get_address(enum tiler_fmt fmt, u32 orient, u32 x, u32 y)
 458 {
 459         u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment;
 460
 461         x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft;
 462         y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft;
 463         alignment = geom[fmt].x_shft + geom[fmt].y_shft;
 464
 465         /* validate coordinate */
 466         x_mask = MASK(x_bits);
 467         y_mask = MASK(y_bits);
 468
 469         if (x < 0 || x > x_mask || y < 0 || y > y_mask) {
 470                 DBG("invalid coords: %u < 0 || %u > %u || %u < 0 || %u > %u",
 471                                 x, x, x_mask, y, y, y_mask);
 472                 return 0;
 473         }
 474
 475         /* account for mirroring */
 476         if (orient & MASK_X_INVERT)
 477                 x ^= x_mask;
 478         if (orient & MASK_Y_INVERT)
 479                 y ^= y_mask;
 480
 481         /* get coordinate address */
 482         if (orient & MASK_XY_FLIP)
 483                 tmp = ((x << y_bits) + y);
 484         else
 485                 tmp = ((y << x_bits) + x);
 486
 487         return TIL_ADDR((tmp << alignment), orient, fmt);
 488 }
 489
 490 dma_addr_t tiler_ssptr(struct tiler_block *block)
 491 {
 492         BUG_ON(!validfmt(block->fmt));
 493
 494         return TILVIEW_8BIT + tiler_get_address(block->fmt, 0,
 495                         block->area.p0.x * geom[block->fmt].slot_w,
 496                         block->area.p0.y * geom[block->fmt].slot_h);
 497 }
 498
 499 dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient,
 500                 uint32_t x, uint32_t y)
 501 {
 502         struct tcm_pt *p = &block->area.p0;
 503         BUG_ON(!validfmt(block->fmt));
 504
 505         return tiler_get_address(block->fmt, orient,
 506                         (p->x * geom[block->fmt].slot_w) + x,
 507                         (p->y * geom[block->fmt].slot_h) + y);
 508 }
 509
 510 void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h)
 511 {
 512         BUG_ON(!validfmt(fmt));
 513         *w = round_up(*w, geom[fmt].slot_w);
 514         *h = round_up(*h, geom[fmt].slot_h);
 515 }
 516
 517 uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient)
 518 {
 519         BUG_ON(!validfmt(fmt));
 520
 521         if (orient & MASK_XY_FLIP)
 522                 return 1 << (CONT_HEIGHT_BITS + geom[fmt].x_shft);
 523         else
 524                 return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft);
 525 }
 526
 527 size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h)
 528 {
 529         tiler_align(fmt, &w, &h);
 530         return geom[fmt].cpp * w * h;
 531 }
 532
 533 size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h)
 534 {
 535         BUG_ON(!validfmt(fmt));
 536         return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h;
 537 }
 538
 539 uint32_t tiler_get_cpu_cache_flags(void)
 540 {
 541         return omap_dmm->plat_data->cpu_cache_flags;
 542 }
 543
 544 bool dmm_is_available(void)
 545 {
 546         return omap_dmm ? true : false;
 547 }
 548
 549 static int omap_dmm_remove(struct platform_device *dev)
 550 {
 551         struct tiler_block *block, *_block;
 552         int i;
 553         unsigned long flags;
 554
 555         if (omap_dmm) {
 556                 /* free all area regions */
 557                 spin_lock_irqsave(&list_lock, flags);
 558                 list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head,
 559                                         alloc_node) {
 560                         list_del(&block->alloc_node);
 561                         kfree(block);
 562                 }
 563                 spin_unlock_irqrestore(&list_lock, flags);
 564
 565                 for (i = 0; i < omap_dmm->num_lut; i++)
 566                         if (omap_dmm->tcm && omap_dmm->tcm[i])
 567                                 omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]);
 568                 kfree(omap_dmm->tcm);
 569
 570                 kfree(omap_dmm->engines);
 571                 if (omap_dmm->refill_va)
 572                         dma_free_writecombine(omap_dmm->dev,
 573                                 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
 574                                 omap_dmm->refill_va,
 575                                 omap_dmm->refill_pa);
 576                 if (omap_dmm->dummy_page)
 577                         __free_page(omap_dmm->dummy_page);
 578
 579                 if (omap_dmm->irq > 0)
 580                         free_irq(omap_dmm->irq, omap_dmm);
 581
 582                 iounmap(omap_dmm->base);
 583                 kfree(omap_dmm);
 584                 omap_dmm = NULL;
 585         }
 586
 587         return 0;
 588 }
 589
 590 static int omap_dmm_probe(struct platform_device *dev)
 591 {
 592         int ret = -EFAULT, i;
 593         struct tcm_area area = {0};
 594         u32 hwinfo, pat_geom;
 595         struct resource *mem;
 596
 597         omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL);
 598         if (!omap_dmm)
 599                 goto fail;
 600
 601         /* initialize lists */
 602         INIT_LIST_HEAD(&omap_dmm->alloc_head);
 603         INIT_LIST_HEAD(&omap_dmm->idle_head);
 604
 605         init_waitqueue_head(&omap_dmm->engine_queue);
 606
 607         if (dev->dev.of_node) {
 608                 const struct of_device_id *match;
 609
 610                 match = of_match_node(dmm_of_match, dev->dev.of_node);
 611                 if (!match) {
 612                         dev_err(&dev->dev, "failed to find matching device node\n");
 613                         return -ENODEV;
 614                 }
 615
 616                 omap_dmm->plat_data = match->data;
 617         }
 618
 619         /* lookup hwmod data - base address and irq */
 620         mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
 621         if (!mem) {
 622                 dev_err(&dev->dev, "failed to get base address resource\n");
 623                 goto fail;
 624         }
 625
 626         omap_dmm->base = ioremap(mem->start, SZ_2K);
 627
 628         if (!omap_dmm->base) {
 629                 dev_err(&dev->dev, "failed to get dmm base address\n");
 630                 goto fail;
 631         }
 632
 633         omap_dmm->irq = platform_get_irq(dev, 0);
 634         if (omap_dmm->irq < 0) {
 635                 dev_err(&dev->dev, "failed to get IRQ resource\n");
 636                 goto fail;
 637         }
 638
 639         omap_dmm->dev = &dev->dev;
 640
 641         hwinfo = readl(omap_dmm->base + DMM_PAT_HWINFO);
 642         omap_dmm->num_engines = (hwinfo >> 24) & 0x1F;
 643         omap_dmm->num_lut = (hwinfo >> 16) & 0x1F;
 644         omap_dmm->container_width = 256;
 645         omap_dmm->container_height = 128;
 646
 647         atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines);
 648
 649         /* read out actual LUT width and height */
 650         pat_geom = readl(omap_dmm->base + DMM_PAT_GEOMETRY);
 651         omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5;
 652         omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5;
 653
 654         /* increment LUT by one if on OMAP5 */
 655         /* LUT has twice the height, and is split into a separate container */
 656         if (omap_dmm->lut_height != omap_dmm->container_height)
 657                 omap_dmm->num_lut++;
 658
 659         /* initialize DMM registers */
 660         writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__0);
 661         writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__1);
 662         writel(0x80808080, omap_dmm->base + DMM_PAT_VIEW_MAP__0);
 663         writel(0x80000000, omap_dmm->base + DMM_PAT_VIEW_MAP_BASE);
 664         writel(0x88888888, omap_dmm->base + DMM_TILER_OR__0);
 665         writel(0x88888888, omap_dmm->base + DMM_TILER_OR__1);
 666
 667         ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED,
 668                                 "omap_dmm_irq_handler", omap_dmm);
 669
 670         if (ret) {
 671                 dev_err(&dev->dev, "couldn't register IRQ %d, error %d\n",
 672                         omap_dmm->irq, ret);
 673                 omap_dmm->irq = -1;
 674                 goto fail;
 675         }
 676
 677         /* Enable all interrupts for each refill engine except
 678          * ERR_LUT_MISS<n> (which is just advisory, and we don't care
 679          * about because we want to be able to refill live scanout
 680          * buffers for accelerated pan/scroll) and FILL_DSC<n> which
 681          * we just generally don't care about.
 682          */
 683         writel(0x7e7e7e7e, omap_dmm->base + DMM_PAT_IRQENABLE_SET);
 684
 685         omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32);
 686         if (!omap_dmm->dummy_page) {
 687                 dev_err(&dev->dev, "could not allocate dummy page\n");
 688                 ret = -ENOMEM;
 689                 goto fail;
 690         }
 691
 692         /* set dma mask for device */
 693         ret = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
 694         if (ret)
 695                 goto fail;
 696
 697         omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page);
 698
 699         /* alloc refill memory */
 700         omap_dmm->refill_va = dma_alloc_writecombine(&dev->dev,
 701                                 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
 702                                 &omap_dmm->refill_pa, GFP_KERNEL);
 703         if (!omap_dmm->refill_va) {
 704                 dev_err(&dev->dev, "could not allocate refill memory\n");
 705                 goto fail;
 706         }
 707
 708         /* alloc engines */
 709         omap_dmm->engines = kcalloc(omap_dmm->num_engines,
 710                                     sizeof(struct refill_engine), GFP_KERNEL);
 711         if (!omap_dmm->engines) {
 712                 ret = -ENOMEM;
 713                 goto fail;
 714         }
 715
 716         for (i = 0; i < omap_dmm->num_engines; i++) {
 717                 omap_dmm->engines[i].id = i;
 718                 omap_dmm->engines[i].dmm = omap_dmm;
 719                 omap_dmm->engines[i].refill_va = omap_dmm->refill_va +
 720                                                 (REFILL_BUFFER_SIZE * i);
 721                 omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa +
 722                                                 (REFILL_BUFFER_SIZE * i);
 723                 init_completion(&omap_dmm->engines[i].compl);
 724
 725                 list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head);
 726         }
 727
 728         omap_dmm->tcm = kcalloc(omap_dmm->num_lut, sizeof(*omap_dmm->tcm),
 729                                 GFP_KERNEL);
 730         if (!omap_dmm->tcm) {
 731                 ret = -ENOMEM;
 732                 goto fail;
 733         }
 734
 735         /* init containers */
 736         /* Each LUT is associated with a TCM (container manager).  We use the
 737            lut_id to denote the lut_id used to identify the correct LUT for
 738            programming during reill operations */
 739         for (i = 0; i < omap_dmm->num_lut; i++) {
 740                 omap_dmm->tcm[i] = sita_init(omap_dmm->container_width,
 741                                                 omap_dmm->container_height,
 742                                                 NULL);
 743
 744                 if (!omap_dmm->tcm[i]) {
 745                         dev_err(&dev->dev, "failed to allocate container\n");
 746                         ret = -ENOMEM;
 747                         goto fail;
 748                 }
 749
 750                 omap_dmm->tcm[i]->lut_id = i;
 751         }
 752
 753         /* assign access mode containers to applicable tcm container */
 754         /* OMAP 4 has 1 container for all 4 views */
 755         /* OMAP 5 has 2 containers, 1 for 2D and 1 for 1D */
 756         containers[TILFMT_8BIT] = omap_dmm->tcm[0];
 757         containers[TILFMT_16BIT] = omap_dmm->tcm[0];
 758         containers[TILFMT_32BIT] = omap_dmm->tcm[0];
 759
 760         if (omap_dmm->container_height != omap_dmm->lut_height) {
 761                 /* second LUT is used for PAGE mode.  Programming must use
 762                    y offset that is added to all y coordinates.  LUT id is still
 763                    0, because it is the same LUT, just the upper 128 lines */
 764                 containers[TILFMT_PAGE] = omap_dmm->tcm[1];
 765                 omap_dmm->tcm[1]->y_offset = OMAP5_LUT_OFFSET;
 766                 omap_dmm->tcm[1]->lut_id = 0;
 767         } else {
 768                 containers[TILFMT_PAGE] = omap_dmm->tcm[0];
 769         }
 770
 771         area = (struct tcm_area) {
 772                 .tcm = NULL,
 773                 .p1.x = omap_dmm->container_width - 1,
 774                 .p1.y = omap_dmm->container_height - 1,
 775         };
 776
 777         /* initialize all LUTs to dummy page entries */
 778         for (i = 0; i < omap_dmm->num_lut; i++) {
 779                 area.tcm = omap_dmm->tcm[i];
 780                 if (fill(&area, NULL, 0, 0, true))
 781                         dev_err(omap_dmm->dev, "refill failed");
 782         }
 783
 784         dev_info(omap_dmm->dev, "initialized all PAT entries\n");
 785
 786         return 0;
 787
 788 fail:
 789         if (omap_dmm_remove(dev))
 790                 dev_err(&dev->dev, "cleanup failed\n");
 791         return ret;
 792 }
 793
 794 /*
 795  * debugfs support
 796  */
 797
 798 #ifdef CONFIG_DEBUG_FS
 799
 800 static const char *alphabet = "abcdefghijklmnopqrstuvwxyz"
 801                                 "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
 802 static const char *special = ".,:;'\"`~!^-+";
 803
 804 static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a,
 805                                                         char c, bool ovw)
 806 {
 807         int x, y;
 808         for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++)
 809                 for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++)
 810                         if (map[y][x] == ' ' || ovw)
 811                                 map[y][x] = c;
 812 }
 813
 814 static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p,
 815                                                                         char c)
 816 {
 817         map[p->y / ydiv][p->x / xdiv] = c;
 818 }
 819
 820 static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p)
 821 {
 822         return map[p->y / ydiv][p->x / xdiv];
 823 }
 824
 825 static int map_width(int xdiv, int x0, int x1)
 826 {
 827         return (x1 / xdiv) - (x0 / xdiv) + 1;
 828 }
 829
 830 static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1)
 831 {
 832         char *p = map[yd] + (x0 / xdiv);
 833         int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2;
 834         if (w >= 0) {
 835                 p += w;
 836                 while (*nice)
 837                         *p++ = *nice++;
 838         }
 839 }
 840
 841 static void map_1d_info(char **map, int xdiv, int ydiv, char *nice,
 842                                                         struct tcm_area *a)
 843 {
 844         sprintf(nice, "%dK", tcm_sizeof(*a) * 4);
 845         if (a->p0.y + 1 < a->p1.y) {
 846                 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0,
 847                                                         256 - 1);
 848         } else if (a->p0.y < a->p1.y) {
 849                 if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1))
 850                         text_map(map, xdiv, nice, a->p0.y / ydiv,
 851                                         a->p0.x + xdiv, 256 - 1);
 852                 else if (strlen(nice) < map_width(xdiv, 0, a->p1.x))
 853                         text_map(map, xdiv, nice, a->p1.y / ydiv,
 854                                         0, a->p1.y - xdiv);
 855         } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) {
 856                 text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x);
 857         }
 858 }
 859
 860 static void map_2d_info(char **map, int xdiv, int ydiv, char *nice,
 861                                                         struct tcm_area *a)
 862 {
 863         sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a));
 864         if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x))
 865                 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv,
 866                                                         a->p0.x, a->p1.x);
 867 }
 868
 869 int tiler_map_show(struct seq_file *s, void *arg)
 870 {
 871         int xdiv = 2, ydiv = 1;
 872         char **map = NULL, *global_map;
 873         struct tiler_block *block;
 874         struct tcm_area a, p;
 875         int i;
 876         const char *m2d = alphabet;
 877         const char *a2d = special;
 878         const char *m2dp = m2d, *a2dp = a2d;
 879         char nice[128];
 880         int h_adj;
 881         int w_adj;
 882         unsigned long flags;
 883         int lut_idx;
 884
 885
 886         if (!omap_dmm) {
 887                 /* early return if dmm/tiler device is not initialized */
 888                 return 0;
 889         }
 890
 891         h_adj = omap_dmm->container_height / ydiv;
 892         w_adj = omap_dmm->container_width / xdiv;
 893
 894         map = kmalloc(h_adj * sizeof(*map), GFP_KERNEL);
 895         global_map = kmalloc((w_adj + 1) * h_adj, GFP_KERNEL);
 896
 897         if (!map || !global_map)
 898                 goto error;
 899
 900         for (lut_idx = 0; lut_idx < omap_dmm->num_lut; lut_idx++) {
 901                 memset(map, 0, h_adj * sizeof(*map));
 902                 memset(global_map, ' ', (w_adj + 1) * h_adj);
 903
 904                 for (i = 0; i < omap_dmm->container_height; i++) {
 905                         map[i] = global_map + i * (w_adj + 1);
 906                         map[i][w_adj] = 0;
 907                 }
 908
 909                 spin_lock_irqsave(&list_lock, flags);
 910
 911                 list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) {
 912                         if (block->area.tcm == omap_dmm->tcm[lut_idx]) {
 913                                 if (block->fmt != TILFMT_PAGE) {
 914                                         fill_map(map, xdiv, ydiv, &block->area,
 915                                                 *m2dp, true);
 916                                         if (!*++a2dp)
 917                                                 a2dp = a2d;
 918                                         if (!*++m2dp)
 919                                                 m2dp = m2d;
 920                                         map_2d_info(map, xdiv, ydiv, nice,
 921                                                         &block->area);
 922                                 } else {
 923                                         bool start = read_map_pt(map, xdiv,
 924                                                 ydiv, &block->area.p0) == ' ';
 925                                         bool end = read_map_pt(map, xdiv, ydiv,
 926                                                         &block->area.p1) == ' ';
 927
 928                                         tcm_for_each_slice(a, block->area, p)
 929                                                 fill_map(map, xdiv, ydiv, &a,
 930                                                         '=', true);
 931                                         fill_map_pt(map, xdiv, ydiv,
 932                                                         &block->area.p0,
 933                                                         start ? '<' : 'X');
 934                                         fill_map_pt(map, xdiv, ydiv,
 935                                                         &block->area.p1,
 936                                                         end ? '>' : 'X');
 937                                         map_1d_info(map, xdiv, ydiv, nice,
 938                                                         &block->area);
 939                                 }
 940                         }
 941                 }
 942
 943                 spin_unlock_irqrestore(&list_lock, flags);
 944
 945                 if (s) {
 946                         seq_printf(s, "CONTAINER %d DUMP BEGIN\n", lut_idx);
 947                         for (i = 0; i < 128; i++)
 948                                 seq_printf(s, "%03d:%s\n", i, map[i]);
 949                         seq_printf(s, "CONTAINER %d DUMP END\n", lut_idx);
 950                 } else {
 951                         dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP BEGIN\n",
 952                                 lut_idx);
 953                         for (i = 0; i < 128; i++)
 954                                 dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]);
 955                         dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP END\n",
 956                                 lut_idx);
 957                 }
 958         }
 959
 960 error:
 961         kfree(map);
 962         kfree(global_map);
 963
 964         return 0;
 965 }
 966 #endif
 967
 968 #ifdef CONFIG_PM_SLEEP
 969 static int omap_dmm_resume(struct device *dev)
 970 {
 971         struct tcm_area area;
 972         int i;
 973
 974         if (!omap_dmm)
 975                 return -ENODEV;
 976
 977         area = (struct tcm_area) {
 978                 .tcm = NULL,
 979                 .p1.x = omap_dmm->container_width - 1,
 980                 .p1.y = omap_dmm->container_height - 1,
 981         };
 982
 983         /* initialize all LUTs to dummy page entries */
 984         for (i = 0; i < omap_dmm->num_lut; i++) {
 985                 area.tcm = omap_dmm->tcm[i];
 986                 if (fill(&area, NULL, 0, 0, true))
 987                         dev_err(dev, "refill failed");
 988         }
 989
 990         return 0;
 991 }
 992 #endif
 993
 994 static SIMPLE_DEV_PM_OPS(omap_dmm_pm_ops, NULL, omap_dmm_resume);
 995
 996 #if defined(CONFIG_OF)
 997 static const struct dmm_platform_data dmm_omap4_platform_data = {
 998         .cpu_cache_flags = OMAP_BO_WC,
 999 };
1000
1001 static const struct dmm_platform_data dmm_omap5_platform_data = {
1002         .cpu_cache_flags = OMAP_BO_UNCACHED,
1003 };
1004
1005 static const struct of_device_id dmm_of_match[] = {
1006         {
1007                 .compatible = "ti,omap4-dmm",
1008                 .data = &dmm_omap4_platform_data,
1009         },
1010         {
1011                 .compatible = "ti,omap5-dmm",
1012                 .data = &dmm_omap5_platform_data,
1013         },
1014         {},
1015 };
1016 #endif
1017
1018 struct platform_driver omap_dmm_driver = {
1019         .probe = omap_dmm_probe,
1020         .remove = omap_dmm_remove,
1021         .driver = {
1022                 .owner = THIS_MODULE,
1023                 .name = DMM_DRIVER_NAME,
1024                 .of_match_table = of_match_ptr(dmm_of_match),
1025                 .pm = &omap_dmm_pm_ops,
1026         },
1027 };
1028
1029 MODULE_LICENSE("GPL v2");
1030 MODULE_AUTHOR("Andy Gross <andy.gross@ti.com>");
1031 MODULE_DESCRIPTION("OMAP DMM/Tiler Driver");
1032 MODULE_ALIAS("platform:" DMM_DRIVER_NAME);