kernel/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *          Martin Peres
  24  */
  25 #include "priv.h"
  26
  27 #include <core/device.h>
  28
  29 struct nv50_therm_priv {
  30         struct nvkm_therm_priv base;
  31 };
  32
  33 static int
  34 pwm_info(struct nvkm_therm *therm, int *line, int *ctrl, int *indx)
  35 {
  36         if (*line == 0x04) {
  37                 *ctrl = 0x00e100;
  38                 *line = 4;
  39                 *indx = 0;
  40         } else
  41         if (*line == 0x09) {
  42                 *ctrl = 0x00e100;
  43                 *line = 9;
  44                 *indx = 1;
  45         } else
  46         if (*line == 0x10) {
  47                 *ctrl = 0x00e28c;
  48                 *line = 0;
  49                 *indx = 0;
  50         } else {
  51                 nv_error(therm, "unknown pwm ctrl for gpio %d\n", *line);
  52                 return -ENODEV;
  53         }
  54
  55         return 0;
  56 }
  57
  58 int
  59 nv50_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable)
  60 {
  61         u32 data = enable ? 0x00000001 : 0x00000000;
  62         int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id);
  63         if (ret == 0)
  64                 nv_mask(therm, ctrl, 0x00010001 << line, data << line);
  65         return ret;
  66 }
  67
  68 int
  69 nv50_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty)
  70 {
  71         int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id);
  72         if (ret)
  73                 return ret;
  74
  75         if (nv_rd32(therm, ctrl) & (1 << line)) {
  76                 *divs = nv_rd32(therm, 0x00e114 + (id * 8));
  77                 *duty = nv_rd32(therm, 0x00e118 + (id * 8));
  78                 return 0;
  79         }
  80
  81         return -EINVAL;
  82 }
  83
  84 int
  85 nv50_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty)
  86 {
  87         int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id);
  88         if (ret)
  89                 return ret;
  90
  91         nv_wr32(therm, 0x00e114 + (id * 8), divs);
  92         nv_wr32(therm, 0x00e118 + (id * 8), duty | 0x80000000);
  93         return 0;
  94 }
  95
  96 int
  97 nv50_fan_pwm_clock(struct nvkm_therm *therm, int line)
  98 {
  99         int chipset = nv_device(therm)->chipset;
 100         int crystal = nv_device(therm)->crystal;
 101         int pwm_clock;
 102
 103         /* determine the PWM source clock */
 104         if (chipset > 0x50 && chipset < 0x94) {
 105                 u8 pwm_div = nv_rd32(therm, 0x410c);
 106                 if (nv_rd32(therm, 0xc040) & 0x800000) {
 107                         /* Use the HOST clock (100 MHz)
 108                         * Where does this constant(2.4) comes from? */
 109                         pwm_clock = (100000000 >> pwm_div) * 10 / 24;
 110                 } else {
 111                         /* Where does this constant(20) comes from? */
 112                         pwm_clock = (crystal * 1000) >> pwm_div;
 113                         pwm_clock /= 20;
 114                 }
 115         } else {
 116                 pwm_clock = (crystal * 1000) / 20;
 117         }
 118
 119         return pwm_clock;
 120 }
 121
 122 static void
 123 nv50_sensor_setup(struct nvkm_therm *therm)
 124 {
 125         nv_mask(therm, 0x20010, 0x40000000, 0x0);
 126         mdelay(20); /* wait for the temperature to stabilize */
 127 }
 128
 129 static int
 130 nv50_temp_get(struct nvkm_therm *therm)
 131 {
 132         struct nvkm_therm_priv *priv = (void *)therm;
 133         struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
 134         int core_temp;
 135
 136         core_temp = nv_rd32(therm, 0x20014) & 0x3fff;
 137
 138         /* if the slope or the offset is unset, do no use the sensor */
 139         if (!sensor->slope_div || !sensor->slope_mult ||
 140             !sensor->offset_num || !sensor->offset_den)
 141             return -ENODEV;
 142
 143         core_temp = core_temp * sensor->slope_mult / sensor->slope_div;
 144         core_temp = core_temp + sensor->offset_num / sensor->offset_den;
 145         core_temp = core_temp + sensor->offset_constant - 8;
 146
 147         /* reserve negative temperatures for errors */
 148         if (core_temp < 0)
 149                 core_temp = 0;
 150
 151         return core_temp;
 152 }
 153
 154 static int
 155 nv50_therm_ctor(struct nvkm_object *parent,
 156                 struct nvkm_object *engine,
 157                 struct nvkm_oclass *oclass, void *data, u32 size,
 158                 struct nvkm_object **pobject)
 159 {
 160         struct nv50_therm_priv *priv;
 161         int ret;
 162
 163         ret = nvkm_therm_create(parent, engine, oclass, &priv);
 164         *pobject = nv_object(priv);
 165         if (ret)
 166                 return ret;
 167
 168         priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl;
 169         priv->base.base.pwm_get = nv50_fan_pwm_get;
 170         priv->base.base.pwm_set = nv50_fan_pwm_set;
 171         priv->base.base.pwm_clock = nv50_fan_pwm_clock;
 172         priv->base.base.temp_get = nv50_temp_get;
 173         priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling;
 174         nv_subdev(priv)->intr = nv40_therm_intr;
 175
 176         return nvkm_therm_preinit(&priv->base.base);
 177 }
 178
 179 static int
 180 nv50_therm_init(struct nvkm_object *object)
 181 {
 182         struct nvkm_therm *therm = (void *)object;
 183
 184         nv50_sensor_setup(therm);
 185
 186         return _nvkm_therm_init(object);
 187 }
 188
 189 struct nvkm_oclass
 190 nv50_therm_oclass = {
 191         .handle = NV_SUBDEV(THERM, 0x50),
 192         .ofuncs = &(struct nvkm_ofuncs) {
 193                 .ctor = nv50_therm_ctor,
 194                 .dtor = _nvkm_therm_dtor,
 195                 .init = nv50_therm_init,
 196                 .fini = _nvkm_therm_fini,
 197         },
 198 };