kernel/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c

   1 /*
   2  * Copyright 2014 Martin Peres
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Martin Peres
  23  */
  24 #include "priv.h"
  25
  26 #include <core/device.h>
  27
  28 struct gm107_therm_priv {
  29         struct nvkm_therm_priv base;
  30 };
  31
  32 static int
  33 gm107_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable)
  34 {
  35         /* nothing to do, it seems hardwired */
  36         return 0;
  37 }
  38
  39 static int
  40 gm107_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty)
  41 {
  42         *divs = nv_rd32(therm, 0x10eb20) & 0x1fff;
  43         *duty = nv_rd32(therm, 0x10eb24) & 0x1fff;
  44         return 0;
  45 }
  46
  47 static int
  48 gm107_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty)
  49 {
  50         nv_mask(therm, 0x10eb10, 0x1fff, divs); /* keep the high bits */
  51         nv_wr32(therm, 0x10eb14, duty | 0x80000000);
  52         return 0;
  53 }
  54
  55 static int
  56 gm107_fan_pwm_clock(struct nvkm_therm *therm, int line)
  57 {
  58         return nv_device(therm)->crystal * 1000;
  59 }
  60
  61 static int
  62 gm107_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  63                  struct nvkm_oclass *oclass, void *data, u32 size,
  64                  struct nvkm_object **pobject)
  65 {
  66         struct gm107_therm_priv *priv;
  67         int ret;
  68
  69         ret = nvkm_therm_create(parent, engine, oclass, &priv);
  70         *pobject = nv_object(priv);
  71         if (ret)
  72                 return ret;
  73
  74         priv->base.base.pwm_ctrl = gm107_fan_pwm_ctrl;
  75         priv->base.base.pwm_get = gm107_fan_pwm_get;
  76         priv->base.base.pwm_set = gm107_fan_pwm_set;
  77         priv->base.base.pwm_clock = gm107_fan_pwm_clock;
  78         priv->base.base.temp_get = g84_temp_get;
  79         priv->base.base.fan_sense = gt215_therm_fan_sense;
  80         priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling;
  81         return nvkm_therm_preinit(&priv->base.base);
  82 }
  83
  84 struct nvkm_oclass
  85 gm107_therm_oclass = {
  86         .handle = NV_SUBDEV(THERM, 0x117),
  87         .ofuncs = &(struct nvkm_ofuncs) {
  88                 .ctor = gm107_therm_ctor,
  89                 .dtor = _nvkm_therm_dtor,
  90                 .init = gf110_therm_init,
  91                 .fini = g84_therm_fini,
  92         },
  93 };