kernel/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "priv.h"
  25
  26 #include <core/device.h>
  27
  28 struct gf110_therm_priv {
  29         struct nvkm_therm_priv base;
  30 };
  31
  32 static int
  33 pwm_info(struct nvkm_therm *therm, int line)
  34 {
  35         u32 gpio = nv_rd32(therm, 0x00d610 + (line * 0x04));
  36
  37         switch (gpio & 0x000000c0) {
  38         case 0x00000000: /* normal mode, possibly pwm forced off by us */
  39         case 0x00000040: /* nvio special */
  40                 switch (gpio & 0x0000001f) {
  41                 case 0x00: return 2;
  42                 case 0x19: return 1;
  43                 case 0x1c: return 0;
  44                 case 0x1e: return 2;
  45                 default:
  46                         break;
  47                 }
  48         default:
  49                 break;
  50         }
  51
  52         nv_error(therm, "GPIO %d unknown PWM: 0x%08x\n", line, gpio);
  53         return -ENODEV;
  54 }
  55
  56 static int
  57 gf110_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable)
  58 {
  59         u32 data = enable ? 0x00000040 : 0x00000000;
  60         int indx = pwm_info(therm, line);
  61         if (indx < 0)
  62                 return indx;
  63         else if (indx < 2)
  64                 nv_mask(therm, 0x00d610 + (line * 0x04), 0x000000c0, data);
  65         /* nothing to do for indx == 2, it seems hardwired to PTHERM */
  66         return 0;
  67 }
  68
  69 static int
  70 gf110_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty)
  71 {
  72         int indx = pwm_info(therm, line);
  73         if (indx < 0)
  74                 return indx;
  75         else if (indx < 2) {
  76                 if (nv_rd32(therm, 0x00d610 + (line * 0x04)) & 0x00000040) {
  77                         *divs = nv_rd32(therm, 0x00e114 + (indx * 8));
  78                         *duty = nv_rd32(therm, 0x00e118 + (indx * 8));
  79                         return 0;
  80                 }
  81         } else if (indx == 2) {
  82                 *divs = nv_rd32(therm, 0x0200d8) & 0x1fff;
  83                 *duty = nv_rd32(therm, 0x0200dc) & 0x1fff;
  84                 return 0;
  85         }
  86
  87         return -EINVAL;
  88 }
  89
  90 static int
  91 gf110_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty)
  92 {
  93         int indx = pwm_info(therm, line);
  94         if (indx < 0)
  95                 return indx;
  96         else if (indx < 2) {
  97                 nv_wr32(therm, 0x00e114 + (indx * 8), divs);
  98                 nv_wr32(therm, 0x00e118 + (indx * 8), duty | 0x80000000);
  99         } else if (indx == 2) {
 100                 nv_mask(therm, 0x0200d8, 0x1fff, divs); /* keep the high bits */
 101                 nv_wr32(therm, 0x0200dc, duty | 0x40000000);
 102         }
 103         return 0;
 104 }
 105
 106 static int
 107 gf110_fan_pwm_clock(struct nvkm_therm *therm, int line)
 108 {
 109         int indx = pwm_info(therm, line);
 110         if (indx < 0)
 111                 return 0;
 112         else if (indx < 2)
 113                 return (nv_device(therm)->crystal * 1000) / 20;
 114         else
 115                 return nv_device(therm)->crystal * 1000 / 10;
 116 }
 117
 118 int
 119 gf110_therm_init(struct nvkm_object *object)
 120 {
 121         struct gf110_therm_priv *priv = (void *)object;
 122         int ret;
 123
 124         ret = nvkm_therm_init(&priv->base.base);
 125         if (ret)
 126                 return ret;
 127
 128         /* enable fan tach, count revolutions per-second */
 129         nv_mask(priv, 0x00e720, 0x00000003, 0x00000002);
 130         if (priv->base.fan->tach.func != DCB_GPIO_UNUSED) {
 131                 nv_mask(priv, 0x00d79c, 0x000000ff, priv->base.fan->tach.line);
 132                 nv_wr32(priv, 0x00e724, nv_device(priv)->crystal * 1000);
 133                 nv_mask(priv, 0x00e720, 0x00000001, 0x00000001);
 134         }
 135         nv_mask(priv, 0x00e720, 0x00000002, 0x00000000);
 136
 137         return 0;
 138 }
 139
 140 static int
 141 gf110_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 142                  struct nvkm_oclass *oclass, void *data, u32 size,
 143                  struct nvkm_object **pobject)
 144 {
 145         struct gf110_therm_priv *priv;
 146         int ret;
 147
 148         ret = nvkm_therm_create(parent, engine, oclass, &priv);
 149         *pobject = nv_object(priv);
 150         if (ret)
 151                 return ret;
 152
 153         g84_sensor_setup(&priv->base.base);
 154
 155         priv->base.base.pwm_ctrl = gf110_fan_pwm_ctrl;
 156         priv->base.base.pwm_get = gf110_fan_pwm_get;
 157         priv->base.base.pwm_set = gf110_fan_pwm_set;
 158         priv->base.base.pwm_clock = gf110_fan_pwm_clock;
 159         priv->base.base.temp_get = g84_temp_get;
 160         priv->base.base.fan_sense = gt215_therm_fan_sense;
 161         priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling;
 162         return nvkm_therm_preinit(&priv->base.base);
 163 }
 164
 165 struct nvkm_oclass
 166 gf110_therm_oclass = {
 167         .handle = NV_SUBDEV(THERM, 0xd0),
 168         .ofuncs = &(struct nvkm_ofuncs) {
 169                 .ctor = gf110_therm_ctor,
 170                 .dtor = _nvkm_therm_dtor,
 171                 .init = gf110_therm_init,
 172                 .fini = g84_therm_fini,
 173         },
 174 };