kernel/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *          Martin Peres
  24  */
  25 #include "priv.h"
  26
  27 #include <subdev/fuse.h>
  28
  29 struct g84_therm_priv {
  30         struct nvkm_therm_priv base;
  31 };
  32
  33 int
  34 g84_temp_get(struct nvkm_therm *therm)
  35 {
  36         struct nvkm_fuse *fuse = nvkm_fuse(therm);
  37
  38         if (nv_ro32(fuse, 0x1a8) == 1)
  39                 return nv_rd32(therm, 0x20400);
  40         else
  41                 return -ENODEV;
  42 }
  43
  44 void
  45 g84_sensor_setup(struct nvkm_therm *therm)
  46 {
  47         struct nvkm_fuse *fuse = nvkm_fuse(therm);
  48
  49         /* enable temperature reading for cards with insane defaults */
  50         if (nv_ro32(fuse, 0x1a8) == 1) {
  51                 nv_mask(therm, 0x20008, 0x80008000, 0x80000000);
  52                 nv_mask(therm, 0x2000c, 0x80000003, 0x00000000);
  53                 mdelay(20); /* wait for the temperature to stabilize */
  54         }
  55 }
  56
  57 static void
  58 g84_therm_program_alarms(struct nvkm_therm *therm)
  59 {
  60         struct nvkm_therm_priv *priv = (void *)therm;
  61         struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
  62         unsigned long flags;
  63
  64         spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);
  65
  66         /* enable RISING and FALLING IRQs for shutdown, THRS 0, 1, 2 and 4 */
  67         nv_wr32(therm, 0x20000, 0x000003ff);
  68
  69         /* shutdown: The computer should be shutdown when reached */
  70         nv_wr32(therm, 0x20484, sensor->thrs_shutdown.hysteresis);
  71         nv_wr32(therm, 0x20480, sensor->thrs_shutdown.temp);
  72
  73         /* THRS_1 : fan boost*/
  74         nv_wr32(therm, 0x204c4, sensor->thrs_fan_boost.temp);
  75
  76         /* THRS_2 : critical */
  77         nv_wr32(therm, 0x204c0, sensor->thrs_critical.temp);
  78
  79         /* THRS_4 : down clock */
  80         nv_wr32(therm, 0x20414, sensor->thrs_down_clock.temp);
  81         spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);
  82
  83         nv_debug(therm,
  84                  "Programmed thresholds [ %d(%d), %d(%d), %d(%d), %d(%d) ]\n",
  85                  sensor->thrs_fan_boost.temp, sensor->thrs_fan_boost.hysteresis,
  86                  sensor->thrs_down_clock.temp,
  87                  sensor->thrs_down_clock.hysteresis,
  88                  sensor->thrs_critical.temp, sensor->thrs_critical.hysteresis,
  89                  sensor->thrs_shutdown.temp, sensor->thrs_shutdown.hysteresis);
  90
  91 }
  92
  93 /* must be called with alarm_program_lock taken ! */
  94 static void
  95 g84_therm_threshold_hyst_emulation(struct nvkm_therm *therm,
  96                                    uint32_t thrs_reg, u8 status_bit,
  97                                    const struct nvbios_therm_threshold *thrs,
  98                                    enum nvkm_therm_thrs thrs_name)
  99 {
 100         enum nvkm_therm_thrs_direction direction;
 101         enum nvkm_therm_thrs_state prev_state, new_state;
 102         int temp, cur;
 103
 104         prev_state = nvkm_therm_sensor_get_threshold_state(therm, thrs_name);
 105         temp = nv_rd32(therm, thrs_reg);
 106
 107         /* program the next threshold */
 108         if (temp == thrs->temp) {
 109                 nv_wr32(therm, thrs_reg, thrs->temp - thrs->hysteresis);
 110                 new_state = NVKM_THERM_THRS_HIGHER;
 111         } else {
 112                 nv_wr32(therm, thrs_reg, thrs->temp);
 113                 new_state = NVKM_THERM_THRS_LOWER;
 114         }
 115
 116         /* fix the state (in case someone reprogrammed the alarms) */
 117         cur = therm->temp_get(therm);
 118         if (new_state == NVKM_THERM_THRS_LOWER && cur > thrs->temp)
 119                 new_state = NVKM_THERM_THRS_HIGHER;
 120         else if (new_state == NVKM_THERM_THRS_HIGHER &&
 121                 cur < thrs->temp - thrs->hysteresis)
 122                 new_state = NVKM_THERM_THRS_LOWER;
 123         nvkm_therm_sensor_set_threshold_state(therm, thrs_name, new_state);
 124
 125         /* find the direction */
 126         if (prev_state < new_state)
 127                 direction = NVKM_THERM_THRS_RISING;
 128         else if (prev_state > new_state)
 129                 direction = NVKM_THERM_THRS_FALLING;
 130         else
 131                 return;
 132
 133         /* advertise a change in direction */
 134         nvkm_therm_sensor_event(therm, thrs_name, direction);
 135 }
 136
 137 static void
 138 g84_therm_intr(struct nvkm_subdev *subdev)
 139 {
 140         struct nvkm_therm *therm = nvkm_therm(subdev);
 141         struct nvkm_therm_priv *priv = (void *)therm;
 142         struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
 143         unsigned long flags;
 144         uint32_t intr;
 145
 146         spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);
 147
 148         intr = nv_rd32(therm, 0x20100) & 0x3ff;
 149
 150         /* THRS_4: downclock */
 151         if (intr & 0x002) {
 152                 g84_therm_threshold_hyst_emulation(therm, 0x20414, 24,
 153                                                    &sensor->thrs_down_clock,
 154                                                    NVKM_THERM_THRS_DOWNCLOCK);
 155                 intr &= ~0x002;
 156         }
 157
 158         /* shutdown */
 159         if (intr & 0x004) {
 160                 g84_therm_threshold_hyst_emulation(therm, 0x20480, 20,
 161                                                    &sensor->thrs_shutdown,
 162                                                    NVKM_THERM_THRS_SHUTDOWN);
 163                 intr &= ~0x004;
 164         }
 165
 166         /* THRS_1 : fan boost */
 167         if (intr & 0x008) {
 168                 g84_therm_threshold_hyst_emulation(therm, 0x204c4, 21,
 169                                                    &sensor->thrs_fan_boost,
 170                                                    NVKM_THERM_THRS_FANBOOST);
 171                 intr &= ~0x008;
 172         }
 173
 174         /* THRS_2 : critical */
 175         if (intr & 0x010) {
 176                 g84_therm_threshold_hyst_emulation(therm, 0x204c0, 22,
 177                                                    &sensor->thrs_critical,
 178                                                    NVKM_THERM_THRS_CRITICAL);
 179                 intr &= ~0x010;
 180         }
 181
 182         if (intr)
 183                 nv_error(therm, "unhandled intr 0x%08x\n", intr);
 184
 185         /* ACK everything */
 186         nv_wr32(therm, 0x20100, 0xffffffff);
 187         nv_wr32(therm, 0x1100, 0x10000); /* PBUS */
 188
 189         spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);
 190 }
 191
 192 static int
 193 g84_therm_init(struct nvkm_object *object)
 194 {
 195         struct g84_therm_priv *priv = (void *)object;
 196         int ret;
 197
 198         ret = nvkm_therm_init(&priv->base.base);
 199         if (ret)
 200                 return ret;
 201
 202         g84_sensor_setup(&priv->base.base);
 203         return 0;
 204 }
 205
 206 static int
 207 g84_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 208                struct nvkm_oclass *oclass, void *data, u32 size,
 209                struct nvkm_object **pobject)
 210 {
 211         struct g84_therm_priv *priv;
 212         int ret;
 213
 214         ret = nvkm_therm_create(parent, engine, oclass, &priv);
 215         *pobject = nv_object(priv);
 216         if (ret)
 217                 return ret;
 218
 219         priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl;
 220         priv->base.base.pwm_get = nv50_fan_pwm_get;
 221         priv->base.base.pwm_set = nv50_fan_pwm_set;
 222         priv->base.base.pwm_clock = nv50_fan_pwm_clock;
 223         priv->base.base.temp_get = g84_temp_get;
 224         priv->base.sensor.program_alarms = g84_therm_program_alarms;
 225         nv_subdev(priv)->intr = g84_therm_intr;
 226
 227         /* init the thresholds */
 228         nvkm_therm_sensor_set_threshold_state(&priv->base.base,
 229                                               NVKM_THERM_THRS_SHUTDOWN,
 230                                               NVKM_THERM_THRS_LOWER);
 231         nvkm_therm_sensor_set_threshold_state(&priv->base.base,
 232                                               NVKM_THERM_THRS_FANBOOST,
 233                                               NVKM_THERM_THRS_LOWER);
 234         nvkm_therm_sensor_set_threshold_state(&priv->base.base,
 235                                               NVKM_THERM_THRS_CRITICAL,
 236                                               NVKM_THERM_THRS_LOWER);
 237         nvkm_therm_sensor_set_threshold_state(&priv->base.base,
 238                                               NVKM_THERM_THRS_DOWNCLOCK,
 239                                               NVKM_THERM_THRS_LOWER);
 240
 241         return nvkm_therm_preinit(&priv->base.base);
 242 }
 243
 244 int
 245 g84_therm_fini(struct nvkm_object *object, bool suspend)
 246 {
 247         /* Disable PTherm IRQs */
 248         nv_wr32(object, 0x20000, 0x00000000);
 249
 250         /* ACK all PTherm IRQs */
 251         nv_wr32(object, 0x20100, 0xffffffff);
 252         nv_wr32(object, 0x1100, 0x10000); /* PBUS */
 253
 254         return _nvkm_therm_fini(object, suspend);
 255 }
 256
 257 struct nvkm_oclass
 258 g84_therm_oclass = {
 259         .handle = NV_SUBDEV(THERM, 0x84),
 260         .ofuncs = &(struct nvkm_ofuncs) {
 261                 .ctor = g84_therm_ctor,
 262                 .dtor = _nvkm_therm_dtor,
 263                 .init = g84_therm_init,
 264                 .fini = g84_therm_fini,
 265         },
 266 };