2 * Copyright 2012 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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26 #include <core/ramht.h>
28 /******************************************************************************
29 * instmem object implementation
30 *****************************************************************************/
33 nv04_instobj_rd32(struct nvkm_object *object, u64 addr)
35 struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object);
36 struct nv04_instobj_priv *node = (void *)object;
37 return nv_ro32(priv, node->mem->offset + addr);
41 nv04_instobj_wr32(struct nvkm_object *object, u64 addr, u32 data)
43 struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object);
44 struct nv04_instobj_priv *node = (void *)object;
45 nv_wo32(priv, node->mem->offset + addr, data);
49 nv04_instobj_dtor(struct nvkm_object *object)
51 struct nv04_instmem_priv *priv = (void *)nvkm_instmem(object);
52 struct nv04_instobj_priv *node = (void *)object;
53 struct nvkm_subdev *subdev = (void *)priv;
55 mutex_lock(&subdev->mutex);
56 nvkm_mm_free(&priv->heap, &node->mem);
57 mutex_unlock(&subdev->mutex);
59 nvkm_instobj_destroy(&node->base);
63 nv04_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
64 struct nvkm_oclass *oclass, void *data, u32 size,
65 struct nvkm_object **pobject)
67 struct nv04_instmem_priv *priv = (void *)nvkm_instmem(parent);
68 struct nv04_instobj_priv *node;
69 struct nvkm_instobj_args *args = data;
70 struct nvkm_subdev *subdev = (void *)priv;
76 ret = nvkm_instobj_create(parent, engine, oclass, &node);
77 *pobject = nv_object(node);
81 mutex_lock(&subdev->mutex);
82 ret = nvkm_mm_head(&priv->heap, 0, 1, args->size, args->size,
83 args->align, &node->mem);
84 mutex_unlock(&subdev->mutex);
88 node->base.addr = node->mem->offset;
89 node->base.size = node->mem->length;
93 struct nvkm_instobj_impl
94 nv04_instobj_oclass = {
95 .base.ofuncs = &(struct nvkm_ofuncs) {
96 .ctor = nv04_instobj_ctor,
97 .dtor = nv04_instobj_dtor,
98 .init = _nvkm_instobj_init,
99 .fini = _nvkm_instobj_fini,
100 .rd32 = nv04_instobj_rd32,
101 .wr32 = nv04_instobj_wr32,
105 /******************************************************************************
106 * instmem subdev implementation
107 *****************************************************************************/
110 nv04_instmem_rd32(struct nvkm_object *object, u64 addr)
112 return nv_rd32(object, 0x700000 + addr);
116 nv04_instmem_wr32(struct nvkm_object *object, u64 addr, u32 data)
118 return nv_wr32(object, 0x700000 + addr, data);
122 nv04_instmem_dtor(struct nvkm_object *object)
124 struct nv04_instmem_priv *priv = (void *)object;
125 nvkm_gpuobj_ref(NULL, &priv->ramfc);
126 nvkm_gpuobj_ref(NULL, &priv->ramro);
127 nvkm_ramht_ref(NULL, &priv->ramht);
128 nvkm_gpuobj_ref(NULL, &priv->vbios);
129 nvkm_mm_fini(&priv->heap);
131 iounmap(priv->iomem);
132 nvkm_instmem_destroy(&priv->base);
136 nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
137 struct nvkm_oclass *oclass, void *data, u32 size,
138 struct nvkm_object **pobject)
140 struct nv04_instmem_priv *priv;
143 ret = nvkm_instmem_create(parent, engine, oclass, &priv);
144 *pobject = nv_object(priv);
148 /* PRAMIN aperture maps over the end of VRAM, reserve it */
149 priv->base.reserved = 512 * 1024;
151 ret = nvkm_mm_init(&priv->heap, 0, priv->base.reserved, 1);
155 /* 0x00000-0x10000: reserve for probable vbios image */
156 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0,
161 /* 0x10000-0x18000: reserve for RAMHT */
162 ret = nvkm_ramht_new(nv_object(priv), NULL, 0x08000, 0, &priv->ramht);
166 /* 0x18000-0x18800: reserve for RAMFC (enough for 32 nv30 channels) */
167 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x00800, 0,
168 NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc);
172 /* 0x18800-0x18a00: reserve for RAMRO */
173 ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x00200, 0, 0,
182 nv04_instmem_oclass = &(struct nvkm_instmem_impl) {
183 .base.handle = NV_SUBDEV(INSTMEM, 0x04),
184 .base.ofuncs = &(struct nvkm_ofuncs) {
185 .ctor = nv04_instmem_ctor,
186 .dtor = nv04_instmem_dtor,
187 .init = _nvkm_instmem_init,
188 .fini = _nvkm_instmem_fini,
189 .rd32 = nv04_instmem_rd32,
190 .wr32 = nv04_instmem_wr32,
192 .instobj = &nv04_instobj_oclass.base,