kernel/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv50.h"
  25
  26 void
  27 nv50_i2c_drive_scl(struct nvkm_i2c_port *base, int state)
  28 {
  29         struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
  30         struct nv50_i2c_port *port = (void *)base;
  31         if (state) port->state |= 0x01;
  32         else       port->state &= 0xfe;
  33         nv_wr32(priv, port->addr, port->state);
  34 }
  35
  36 void
  37 nv50_i2c_drive_sda(struct nvkm_i2c_port *base, int state)
  38 {
  39         struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
  40         struct nv50_i2c_port *port = (void *)base;
  41         if (state) port->state |= 0x02;
  42         else       port->state &= 0xfd;
  43         nv_wr32(priv, port->addr, port->state);
  44 }
  45
  46 int
  47 nv50_i2c_sense_scl(struct nvkm_i2c_port *base)
  48 {
  49         struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
  50         struct nv50_i2c_port *port = (void *)base;
  51         return !!(nv_rd32(priv, port->addr) & 0x00000001);
  52 }
  53
  54 int
  55 nv50_i2c_sense_sda(struct nvkm_i2c_port *base)
  56 {
  57         struct nv50_i2c_priv *priv = (void *)nvkm_i2c(base);
  58         struct nv50_i2c_port *port = (void *)base;
  59         return !!(nv_rd32(priv, port->addr) & 0x00000002);
  60 }
  61
  62 static const struct nvkm_i2c_func
  63 nv50_i2c_func = {
  64         .drive_scl = nv50_i2c_drive_scl,
  65         .drive_sda = nv50_i2c_drive_sda,
  66         .sense_scl = nv50_i2c_sense_scl,
  67         .sense_sda = nv50_i2c_sense_sda,
  68 };
  69
  70 const u32 nv50_i2c_addr[] = {
  71         0x00e138, 0x00e150, 0x00e168, 0x00e180,
  72         0x00e254, 0x00e274, 0x00e764, 0x00e780,
  73         0x00e79c, 0x00e7b8
  74 };
  75 const int nv50_i2c_addr_nr = ARRAY_SIZE(nv50_i2c_addr);
  76
  77 static int
  78 nv50_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  79                    struct nvkm_oclass *oclass, void *data, u32 index,
  80                    struct nvkm_object **pobject)
  81 {
  82         struct dcb_i2c_entry *info = data;
  83         struct nv50_i2c_port *port;
  84         int ret;
  85
  86         ret = nvkm_i2c_port_create(parent, engine, oclass, index,
  87                                    &nvkm_i2c_bit_algo, &nv50_i2c_func, &port);
  88         *pobject = nv_object(port);
  89         if (ret)
  90                 return ret;
  91
  92         if (info->drive >= nv50_i2c_addr_nr)
  93                 return -EINVAL;
  94
  95         port->state = 0x00000007;
  96         port->addr = nv50_i2c_addr[info->drive];
  97         return 0;
  98 }
  99
 100 int
 101 nv50_i2c_port_init(struct nvkm_object *object)
 102 {
 103         struct nv50_i2c_priv *priv = (void *)nvkm_i2c(object);
 104         struct nv50_i2c_port *port = (void *)object;
 105         nv_wr32(priv, port->addr, port->state);
 106         return nvkm_i2c_port_init(&port->base);
 107 }
 108
 109 static struct nvkm_oclass
 110 nv50_i2c_sclass[] = {
 111         { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT),
 112           .ofuncs = &(struct nvkm_ofuncs) {
 113                   .ctor = nv50_i2c_port_ctor,
 114                   .dtor = _nvkm_i2c_port_dtor,
 115                   .init = nv50_i2c_port_init,
 116                   .fini = _nvkm_i2c_port_fini,
 117           },
 118         },
 119         {}
 120 };
 121
 122 struct nvkm_oclass *
 123 nv50_i2c_oclass = &(struct nvkm_i2c_impl) {
 124         .base.handle = NV_SUBDEV(I2C, 0x50),
 125         .base.ofuncs = &(struct nvkm_ofuncs) {
 126                 .ctor = _nvkm_i2c_ctor,
 127                 .dtor = _nvkm_i2c_dtor,
 128                 .init = _nvkm_i2c_init,
 129                 .fini = _nvkm_i2c_fini,
 130         },
 131         .sclass = nv50_i2c_sclass,
 132         .pad_x = &nv04_i2c_pad_oclass,
 133 }.base;