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26 #define AUX_DBG(fmt, args...) nv_debug(aux, "AUXCH(%d): " fmt, ch, ##args)
27 #define AUX_ERR(fmt, args...) nv_error(aux, "AUXCH(%d): " fmt, ch, ##args)
30 auxch_fini(struct nvkm_i2c *aux, int ch)
32 nv_mask(aux, 0x00d954 + (ch * 0x50), 0x00310000, 0x00000000);
36 auxch_init(struct nvkm_i2c *aux, int ch)
38 const u32 unksel = 1; /* nfi which to use, or if it matters.. */
39 const u32 ureq = unksel ? 0x00100000 : 0x00200000;
40 const u32 urep = unksel ? 0x01000000 : 0x02000000;
43 /* wait up to 1ms for any previous transaction to be done... */
46 ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50));
49 AUX_ERR("begin idle timeout 0x%08x\n", ctrl);
52 } while (ctrl & 0x03010000);
54 /* set some magic, and wait up to 1ms for it to appear */
55 nv_mask(aux, 0x00d954 + (ch * 0x50), 0x00300000, ureq);
58 ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50));
61 AUX_ERR("magic wait 0x%08x\n", ctrl);
65 } while ((ctrl & 0x03000000) != urep);
71 gm204_aux(struct nvkm_i2c_port *base, bool retry,
72 u8 type, u32 addr, u8 *data, u8 size)
74 struct nvkm_i2c *aux = nvkm_i2c(base);
75 struct nv50_i2c_port *port = (void *)base;
76 u32 ctrl, stat, timeout, retries;
81 AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
83 ret = auxch_init(aux, ch);
87 stat = nv_rd32(aux, 0x00d958 + (ch * 0x50));
88 if (!(stat & 0x10000000)) {
89 AUX_DBG("sink not detected\n");
95 memcpy(xbuf, data, size);
96 for (i = 0; i < 16; i += 4) {
97 AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
98 nv_wr32(aux, 0x00d930 + (ch * 0x50) + i, xbuf[i / 4]);
102 ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50));
106 nv_wr32(aux, 0x00d950 + (ch * 0x50), addr);
108 /* (maybe) retry transaction a number of times on failure... */
109 for (retries = 0; !ret && retries < 32; retries++) {
110 /* reset, and delay a while if this is a retry */
111 nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x80000000 | ctrl);
112 nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x00000000 | ctrl);
116 /* transaction request, wait up to 1ms for it to complete */
117 nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x00010000 | ctrl);
121 ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50));
124 AUX_ERR("tx req timeout 0x%08x\n", ctrl);
128 } while (ctrl & 0x00010000);
131 /* read status, and check if transaction completed ok */
132 stat = nv_mask(aux, 0x00d958 + (ch * 0x50), 0, 0);
133 if ((stat & 0x000f0000) == 0x00080000 ||
134 (stat & 0x000f0000) == 0x00020000)
136 if ((stat & 0x00000100))
138 if ((stat & 0x00000e00))
141 AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
145 for (i = 0; i < 16; i += 4) {
146 xbuf[i / 4] = nv_rd32(aux, 0x00d940 + (ch * 0x50) + i);
147 AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
149 memcpy(data, xbuf, size);
154 return ret < 0 ? ret : (stat & 0x000f0000) >> 16;
157 static const struct nvkm_i2c_func
163 gm204_aux_port_ctor(struct nvkm_object *parent,
164 struct nvkm_object *engine,
165 struct nvkm_oclass *oclass, void *data, u32 index,
166 struct nvkm_object **pobject)
168 struct dcb_i2c_entry *info = data;
169 struct nv50_i2c_port *port;
172 ret = nvkm_i2c_port_create(parent, engine, oclass, index,
173 &nvkm_i2c_aux_algo, &gm204_aux_func, &port);
174 *pobject = nv_object(port);
178 port->base.aux = info->auxch;
179 port->addr = info->auxch;
184 gm204_i2c_sclass[] = {
185 { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT),
186 .ofuncs = &(struct nvkm_ofuncs) {
187 .ctor = gf110_i2c_port_ctor,
188 .dtor = _nvkm_i2c_port_dtor,
189 .init = nv50_i2c_port_init,
190 .fini = _nvkm_i2c_port_fini,
193 { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX),
194 .ofuncs = &(struct nvkm_ofuncs) {
195 .ctor = gm204_aux_port_ctor,
196 .dtor = _nvkm_i2c_port_dtor,
197 .init = _nvkm_i2c_port_init,
198 .fini = _nvkm_i2c_port_fini,
205 gm204_i2c_oclass = &(struct nvkm_i2c_impl) {
206 .base.handle = NV_SUBDEV(I2C, 0x24),
207 .base.ofuncs = &(struct nvkm_ofuncs) {
208 .ctor = _nvkm_i2c_ctor,
209 .dtor = _nvkm_i2c_dtor,
210 .init = _nvkm_i2c_init,
211 .fini = _nvkm_i2c_fini,
213 .sclass = gm204_i2c_sclass,
214 .pad_x = &nv04_i2c_pad_oclass,
215 .pad_s = &gm204_i2c_pad_oclass,
217 .aux_stat = gk104_aux_stat,
218 .aux_mask = gk104_aux_mask,