2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <subdev/clk.h>
27 #include <core/device.h>
28 #include <subdev/bios.h>
29 #include <subdev/bios/pll.h>
31 struct nv40_clk_priv {
39 static struct nvkm_domain
41 { nv_clk_src_crystal, 0xff },
42 { nv_clk_src_href , 0xff },
43 { nv_clk_src_core , 0xff, 0, "core", 1000 },
44 { nv_clk_src_shader , 0xff, 0, "shader", 1000 },
45 { nv_clk_src_mem , 0xff, 0, "memory", 1000 },
50 read_pll_1(struct nv40_clk_priv *priv, u32 reg)
52 u32 ctrl = nv_rd32(priv, reg + 0x00);
53 int P = (ctrl & 0x00070000) >> 16;
54 int N = (ctrl & 0x0000ff00) >> 8;
55 int M = (ctrl & 0x000000ff) >> 0;
56 u32 ref = 27000, clk = 0;
58 if (ctrl & 0x80000000)
65 read_pll_2(struct nv40_clk_priv *priv, u32 reg)
67 u32 ctrl = nv_rd32(priv, reg + 0x00);
68 u32 coef = nv_rd32(priv, reg + 0x04);
69 int N2 = (coef & 0xff000000) >> 24;
70 int M2 = (coef & 0x00ff0000) >> 16;
71 int N1 = (coef & 0x0000ff00) >> 8;
72 int M1 = (coef & 0x000000ff) >> 0;
73 int P = (ctrl & 0x00070000) >> 16;
74 u32 ref = 27000, clk = 0;
76 if ((ctrl & 0x80000000) && M1) {
78 if ((ctrl & 0x40000100) == 0x40000000) {
90 read_clk(struct nv40_clk_priv *priv, u32 src)
94 return read_pll_2(priv, 0x004000);
96 return read_pll_1(priv, 0x004008);
105 nv40_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
107 struct nv40_clk_priv *priv = (void *)clk;
108 u32 mast = nv_rd32(priv, 0x00c040);
111 case nv_clk_src_crystal:
112 return nv_device(priv)->crystal;
113 case nv_clk_src_href:
114 return 100000; /*XXX: PCIE/AGP differ*/
115 case nv_clk_src_core:
116 return read_clk(priv, (mast & 0x00000003) >> 0);
117 case nv_clk_src_shader:
118 return read_clk(priv, (mast & 0x00000030) >> 4);
120 return read_pll_2(priv, 0x4020);
125 nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
130 nv40_clk_calc_pll(struct nv40_clk_priv *priv, u32 reg, u32 clk,
131 int *N1, int *M1, int *N2, int *M2, int *log2P)
133 struct nvkm_bios *bios = nvkm_bios(priv);
134 struct nvbios_pll pll;
137 ret = nvbios_pll_parse(bios, reg, &pll);
141 if (clk < pll.vco1.max_freq)
142 pll.vco2.max_freq = 0;
144 ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P);
152 nv40_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
154 struct nv40_clk_priv *priv = (void *)clk;
155 int gclk = cstate->domain[nv_clk_src_core];
156 int sclk = cstate->domain[nv_clk_src_shader];
157 int N1, M1, N2, M2, log2P;
160 /* core/geometric clock */
161 ret = nv40_clk_calc_pll(priv, 0x004000, gclk,
162 &N1, &M1, &N2, &M2, &log2P);
167 priv->npll_ctrl = 0x80000100 | (log2P << 16);
168 priv->npll_coef = (N1 << 8) | M1;
170 priv->npll_ctrl = 0xc0000000 | (log2P << 16);
171 priv->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
174 /* use the second pll for shader/rop clock, if it differs from core */
175 if (sclk && sclk != gclk) {
176 ret = nv40_clk_calc_pll(priv, 0x004008, sclk,
177 &N1, &M1, NULL, NULL, &log2P);
181 priv->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
182 priv->ctrl = 0x00000223;
184 priv->spll = 0x00000000;
185 priv->ctrl = 0x00000333;
192 nv40_clk_prog(struct nvkm_clk *clk)
194 struct nv40_clk_priv *priv = (void *)clk;
195 nv_mask(priv, 0x00c040, 0x00000333, 0x00000000);
196 nv_wr32(priv, 0x004004, priv->npll_coef);
197 nv_mask(priv, 0x004000, 0xc0070100, priv->npll_ctrl);
198 nv_mask(priv, 0x004008, 0xc007ffff, priv->spll);
200 nv_mask(priv, 0x00c040, 0x00000333, priv->ctrl);
205 nv40_clk_tidy(struct nvkm_clk *clk)
210 nv40_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
211 struct nvkm_oclass *oclass, void *data, u32 size,
212 struct nvkm_object **pobject)
214 struct nv40_clk_priv *priv;
217 ret = nvkm_clk_create(parent, engine, oclass, nv40_domain,
218 NULL, 0, true, &priv);
219 *pobject = nv_object(priv);
223 priv->base.pll_calc = nv04_clk_pll_calc;
224 priv->base.pll_prog = nv04_clk_pll_prog;
225 priv->base.read = nv40_clk_read;
226 priv->base.calc = nv40_clk_calc;
227 priv->base.prog = nv40_clk_prog;
228 priv->base.tidy = nv40_clk_tidy;
234 .handle = NV_SUBDEV(CLK, 0x40),
235 .ofuncs = &(struct nvkm_ofuncs) {
236 .ctor = nv40_clk_ctor,
237 .dtor = _nvkm_clk_dtor,
238 .init = _nvkm_clk_init,
239 .fini = _nvkm_clk_fini,