kernel/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include <subdev/clk.h>
  25 #include <subdev/bios.h>
  26 #include <subdev/bios/boost.h>
  27 #include <subdev/bios/cstep.h>
  28 #include <subdev/bios/perf.h>
  29 #include <subdev/fb.h>
  30 #include <subdev/therm.h>
  31 #include <subdev/volt.h>
  32
  33 #include <core/device.h>
  34 #include <core/option.h>
  35
  36 /******************************************************************************
  37  * misc
  38  *****************************************************************************/
  39 static u32
  40 nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust,
  41                 u8 pstate, u8 domain, u32 input)
  42 {
  43         struct nvkm_bios *bios = nvkm_bios(clk);
  44         struct nvbios_boostE boostE;
  45         u8  ver, hdr, cnt, len;
  46         u16 data;
  47
  48         data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);
  49         if (data) {
  50                 struct nvbios_boostS boostS;
  51                 u8  idx = 0, sver, shdr;
  52                 u16 subd;
  53
  54                 input = max(boostE.min, input);
  55                 input = min(boostE.max, input);
  56                 do {
  57                         sver = ver;
  58                         shdr = hdr;
  59                         subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr,
  60                                               cnt, len, &boostS);
  61                         if (subd && boostS.domain == domain) {
  62                                 if (adjust)
  63                                         input = input * boostS.percent / 100;
  64                                 input = max(boostS.min, input);
  65                                 input = min(boostS.max, input);
  66                                 break;
  67                         }
  68                 } while (subd);
  69         }
  70
  71         return input;
  72 }
  73
  74 /******************************************************************************
  75  * C-States
  76  *****************************************************************************/
  77 static int
  78 nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
  79 {
  80         struct nvkm_therm *ptherm = nvkm_therm(clk);
  81         struct nvkm_volt *volt = nvkm_volt(clk);
  82         struct nvkm_cstate *cstate;
  83         int ret;
  84
  85         if (!list_empty(&pstate->list)) {
  86                 cstate = list_entry(pstate->list.prev, typeof(*cstate), head);
  87         } else {
  88                 cstate = &pstate->base;
  89         }
  90
  91         if (ptherm) {
  92                 ret = nvkm_therm_cstate(ptherm, pstate->fanspeed, +1);
  93                 if (ret && ret != -ENODEV) {
  94                         nv_error(clk, "failed to raise fan speed: %d\n", ret);
  95                         return ret;
  96                 }
  97         }
  98
  99         if (volt) {
 100                 ret = volt->set_id(volt, cstate->voltage, +1);
 101                 if (ret && ret != -ENODEV) {
 102                         nv_error(clk, "failed to raise voltage: %d\n", ret);
 103                         return ret;
 104                 }
 105         }
 106
 107         ret = clk->calc(clk, cstate);
 108         if (ret == 0) {
 109                 ret = clk->prog(clk);
 110                 clk->tidy(clk);
 111         }
 112
 113         if (volt) {
 114                 ret = volt->set_id(volt, cstate->voltage, -1);
 115                 if (ret && ret != -ENODEV)
 116                         nv_error(clk, "failed to lower voltage: %d\n", ret);
 117         }
 118
 119         if (ptherm) {
 120                 ret = nvkm_therm_cstate(ptherm, pstate->fanspeed, -1);
 121                 if (ret && ret != -ENODEV)
 122                         nv_error(clk, "failed to lower fan speed: %d\n", ret);
 123         }
 124
 125         return 0;
 126 }
 127
 128 static void
 129 nvkm_cstate_del(struct nvkm_cstate *cstate)
 130 {
 131         list_del(&cstate->head);
 132         kfree(cstate);
 133 }
 134
 135 static int
 136 nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate)
 137 {
 138         struct nvkm_bios *bios = nvkm_bios(clk);
 139         struct nvkm_domain *domain = clk->domains;
 140         struct nvkm_cstate *cstate = NULL;
 141         struct nvbios_cstepX cstepX;
 142         u8  ver, hdr;
 143         u16 data;
 144
 145         data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX);
 146         if (!data)
 147                 return -ENOENT;
 148
 149         cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
 150         if (!cstate)
 151                 return -ENOMEM;
 152
 153         *cstate = pstate->base;
 154         cstate->voltage = cstepX.voltage;
 155
 156         while (domain && domain->name != nv_clk_src_max) {
 157                 if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
 158                         u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate,
 159                                                    domain->bios, cstepX.freq);
 160                         cstate->domain[domain->name] = freq;
 161                 }
 162                 domain++;
 163         }
 164
 165         list_add(&cstate->head, &pstate->list);
 166         return 0;
 167 }
 168
 169 /******************************************************************************
 170  * P-States
 171  *****************************************************************************/
 172 static int
 173 nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
 174 {
 175         struct nvkm_fb *pfb = nvkm_fb(clk);
 176         struct nvkm_pstate *pstate;
 177         int ret, idx = 0;
 178
 179         list_for_each_entry(pstate, &clk->states, head) {
 180                 if (idx++ == pstatei)
 181                         break;
 182         }
 183
 184         nv_debug(clk, "setting performance state %d\n", pstatei);
 185         clk->pstate = pstatei;
 186
 187         if (pfb->ram && pfb->ram->calc) {
 188                 int khz = pstate->base.domain[nv_clk_src_mem];
 189                 do {
 190                         ret = pfb->ram->calc(pfb, khz);
 191                         if (ret == 0)
 192                                 ret = pfb->ram->prog(pfb);
 193                 } while (ret > 0);
 194                 pfb->ram->tidy(pfb);
 195         }
 196
 197         return nvkm_cstate_prog(clk, pstate, 0);
 198 }
 199
 200 static void
 201 nvkm_pstate_work(struct work_struct *work)
 202 {
 203         struct nvkm_clk *clk = container_of(work, typeof(*clk), work);
 204         int pstate;
 205
 206         if (!atomic_xchg(&clk->waiting, 0))
 207                 return;
 208         clk->pwrsrc = power_supply_is_system_supplied();
 209
 210         nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n",
 211                  clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
 212                  clk->astate, clk->tstate, clk->dstate);
 213
 214         pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc;
 215         if (clk->state_nr && pstate != -1) {
 216                 pstate = (pstate < 0) ? clk->astate : pstate;
 217                 pstate = min(pstate, clk->state_nr - 1 - clk->tstate);
 218                 pstate = max(pstate, clk->dstate);
 219         } else {
 220                 pstate = clk->pstate = -1;
 221         }
 222
 223         nv_trace(clk, "-> %d\n", pstate);
 224         if (pstate != clk->pstate) {
 225                 int ret = nvkm_pstate_prog(clk, pstate);
 226                 if (ret) {
 227                         nv_error(clk, "error setting pstate %d: %d\n",
 228                                  pstate, ret);
 229                 }
 230         }
 231
 232         wake_up_all(&clk->wait);
 233         nvkm_notify_get(&clk->pwrsrc_ntfy);
 234 }
 235
 236 static int
 237 nvkm_pstate_calc(struct nvkm_clk *clk, bool wait)
 238 {
 239         atomic_set(&clk->waiting, 1);
 240         schedule_work(&clk->work);
 241         if (wait)
 242                 wait_event(clk->wait, !atomic_read(&clk->waiting));
 243         return 0;
 244 }
 245
 246 static void
 247 nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate)
 248 {
 249         struct nvkm_domain *clock = clk->domains - 1;
 250         struct nvkm_cstate *cstate;
 251         char info[3][32] = { "", "", "" };
 252         char name[4] = "--";
 253         int i = -1;
 254
 255         if (pstate->pstate != 0xff)
 256                 snprintf(name, sizeof(name), "%02x", pstate->pstate);
 257
 258         while ((++clock)->name != nv_clk_src_max) {
 259                 u32 lo = pstate->base.domain[clock->name];
 260                 u32 hi = lo;
 261                 if (hi == 0)
 262                         continue;
 263
 264                 nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo);
 265                 list_for_each_entry(cstate, &pstate->list, head) {
 266                         u32 freq = cstate->domain[clock->name];
 267                         lo = min(lo, freq);
 268                         hi = max(hi, freq);
 269                         nv_debug(clk, "%10d KHz\n", freq);
 270                 }
 271
 272                 if (clock->mname && ++i < ARRAY_SIZE(info)) {
 273                         lo /= clock->mdiv;
 274                         hi /= clock->mdiv;
 275                         if (lo == hi) {
 276                                 snprintf(info[i], sizeof(info[i]), "%s %d MHz",
 277                                          clock->mname, lo);
 278                         } else {
 279                                 snprintf(info[i], sizeof(info[i]),
 280                                          "%s %d-%d MHz", clock->mname, lo, hi);
 281                         }
 282                 }
 283         }
 284
 285         nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
 286 }
 287
 288 static void
 289 nvkm_pstate_del(struct nvkm_pstate *pstate)
 290 {
 291         struct nvkm_cstate *cstate, *temp;
 292
 293         list_for_each_entry_safe(cstate, temp, &pstate->list, head) {
 294                 nvkm_cstate_del(cstate);
 295         }
 296
 297         list_del(&pstate->head);
 298         kfree(pstate);
 299 }
 300
 301 static int
 302 nvkm_pstate_new(struct nvkm_clk *clk, int idx)
 303 {
 304         struct nvkm_bios *bios = nvkm_bios(clk);
 305         struct nvkm_domain *domain = clk->domains - 1;
 306         struct nvkm_pstate *pstate;
 307         struct nvkm_cstate *cstate;
 308         struct nvbios_cstepE cstepE;
 309         struct nvbios_perfE perfE;
 310         u8  ver, hdr, cnt, len;
 311         u16 data;
 312
 313         data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE);
 314         if (!data)
 315                 return -EINVAL;
 316         if (perfE.pstate == 0xff)
 317                 return 0;
 318
 319         pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
 320         cstate = &pstate->base;
 321         if (!pstate)
 322                 return -ENOMEM;
 323
 324         INIT_LIST_HEAD(&pstate->list);
 325
 326         pstate->pstate = perfE.pstate;
 327         pstate->fanspeed = perfE.fanspeed;
 328         cstate->voltage = perfE.voltage;
 329         cstate->domain[nv_clk_src_core] = perfE.core;
 330         cstate->domain[nv_clk_src_shader] = perfE.shader;
 331         cstate->domain[nv_clk_src_mem] = perfE.memory;
 332         cstate->domain[nv_clk_src_vdec] = perfE.vdec;
 333         cstate->domain[nv_clk_src_dom6] = perfE.disp;
 334
 335         while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) {
 336                 struct nvbios_perfS perfS;
 337                 u8  sver = ver, shdr = hdr;
 338                 u32 perfSe = nvbios_perfSp(bios, data, domain->bios,
 339                                           &sver, &shdr, cnt, len, &perfS);
 340                 if (perfSe == 0 || sver != 0x40)
 341                         continue;
 342
 343                 if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
 344                         perfS.v40.freq = nvkm_clk_adjust(clk, false,
 345                                                          pstate->pstate,
 346                                                          domain->bios,
 347                                                          perfS.v40.freq);
 348                 }
 349
 350                 cstate->domain[domain->name] = perfS.v40.freq;
 351         }
 352
 353         data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE);
 354         if (data) {
 355                 int idx = cstepE.index;
 356                 do {
 357                         nvkm_cstate_new(clk, idx, pstate);
 358                 } while(idx--);
 359         }
 360
 361         nvkm_pstate_info(clk, pstate);
 362         list_add_tail(&pstate->head, &clk->states);
 363         clk->state_nr++;
 364         return 0;
 365 }
 366
 367 /******************************************************************************
 368  * Adjustment triggers
 369  *****************************************************************************/
 370 static int
 371 nvkm_clk_ustate_update(struct nvkm_clk *clk, int req)
 372 {
 373         struct nvkm_pstate *pstate;
 374         int i = 0;
 375
 376         if (!clk->allow_reclock)
 377                 return -ENOSYS;
 378
 379         if (req != -1 && req != -2) {
 380                 list_for_each_entry(pstate, &clk->states, head) {
 381                         if (pstate->pstate == req)
 382                                 break;
 383                         i++;
 384                 }
 385
 386                 if (pstate->pstate != req)
 387                         return -EINVAL;
 388                 req = i;
 389         }
 390
 391         return req + 2;
 392 }
 393
 394 static int
 395 nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen)
 396 {
 397         int ret = 1;
 398
 399         if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen))
 400                 return -2;
 401
 402         if (strncasecmpz(mode, "disabled", arglen)) {
 403                 char save = mode[arglen];
 404                 long v;
 405
 406                 ((char *)mode)[arglen] = '\0';
 407                 if (!kstrtol(mode, 0, &v)) {
 408                         ret = nvkm_clk_ustate_update(clk, v);
 409                         if (ret < 0)
 410                                 ret = 1;
 411                 }
 412                 ((char *)mode)[arglen] = save;
 413         }
 414
 415         return ret - 2;
 416 }
 417
 418 int
 419 nvkm_clk_ustate(struct nvkm_clk *clk, int req, int pwr)
 420 {
 421         int ret = nvkm_clk_ustate_update(clk, req);
 422         if (ret >= 0) {
 423                 if (ret -= 2, pwr) clk->ustate_ac = ret;
 424                 else               clk->ustate_dc = ret;
 425                 return nvkm_pstate_calc(clk, true);
 426         }
 427         return ret;
 428 }
 429
 430 int
 431 nvkm_clk_astate(struct nvkm_clk *clk, int req, int rel, bool wait)
 432 {
 433         if (!rel) clk->astate  = req;
 434         if ( rel) clk->astate += rel;
 435         clk->astate = min(clk->astate, clk->state_nr - 1);
 436         clk->astate = max(clk->astate, 0);
 437         return nvkm_pstate_calc(clk, wait);
 438 }
 439
 440 int
 441 nvkm_clk_tstate(struct nvkm_clk *clk, int req, int rel)
 442 {
 443         if (!rel) clk->tstate  = req;
 444         if ( rel) clk->tstate += rel;
 445         clk->tstate = min(clk->tstate, 0);
 446         clk->tstate = max(clk->tstate, -(clk->state_nr - 1));
 447         return nvkm_pstate_calc(clk, true);
 448 }
 449
 450 int
 451 nvkm_clk_dstate(struct nvkm_clk *clk, int req, int rel)
 452 {
 453         if (!rel) clk->dstate  = req;
 454         if ( rel) clk->dstate += rel;
 455         clk->dstate = min(clk->dstate, clk->state_nr - 1);
 456         clk->dstate = max(clk->dstate, 0);
 457         return nvkm_pstate_calc(clk, true);
 458 }
 459
 460 static int
 461 nvkm_clk_pwrsrc(struct nvkm_notify *notify)
 462 {
 463         struct nvkm_clk *clk =
 464                 container_of(notify, typeof(*clk), pwrsrc_ntfy);
 465         nvkm_pstate_calc(clk, false);
 466         return NVKM_NOTIFY_DROP;
 467 }
 468
 469 /******************************************************************************
 470  * subdev base class implementation
 471  *****************************************************************************/
 472
 473 int
 474 _nvkm_clk_fini(struct nvkm_object *object, bool suspend)
 475 {
 476         struct nvkm_clk *clk = (void *)object;
 477         nvkm_notify_put(&clk->pwrsrc_ntfy);
 478         return nvkm_subdev_fini(&clk->base, suspend);
 479 }
 480
 481 int
 482 _nvkm_clk_init(struct nvkm_object *object)
 483 {
 484         struct nvkm_clk *clk = (void *)object;
 485         struct nvkm_domain *clock = clk->domains;
 486         int ret;
 487
 488         ret = nvkm_subdev_init(&clk->base);
 489         if (ret)
 490                 return ret;
 491
 492         memset(&clk->bstate, 0x00, sizeof(clk->bstate));
 493         INIT_LIST_HEAD(&clk->bstate.list);
 494         clk->bstate.pstate = 0xff;
 495
 496         while (clock->name != nv_clk_src_max) {
 497                 ret = clk->read(clk, clock->name);
 498                 if (ret < 0) {
 499                         nv_error(clk, "%02x freq unknown\n", clock->name);
 500                         return ret;
 501                 }
 502                 clk->bstate.base.domain[clock->name] = ret;
 503                 clock++;
 504         }
 505
 506         nvkm_pstate_info(clk, &clk->bstate);
 507
 508         clk->astate = clk->state_nr - 1;
 509         clk->tstate = 0;
 510         clk->dstate = 0;
 511         clk->pstate = -1;
 512         nvkm_pstate_calc(clk, true);
 513         return 0;
 514 }
 515
 516 void
 517 _nvkm_clk_dtor(struct nvkm_object *object)
 518 {
 519         struct nvkm_clk *clk = (void *)object;
 520         struct nvkm_pstate *pstate, *temp;
 521
 522         nvkm_notify_fini(&clk->pwrsrc_ntfy);
 523
 524         list_for_each_entry_safe(pstate, temp, &clk->states, head) {
 525                 nvkm_pstate_del(pstate);
 526         }
 527
 528         nvkm_subdev_destroy(&clk->base);
 529 }
 530
 531 int
 532 nvkm_clk_create_(struct nvkm_object *parent, struct nvkm_object *engine,
 533                  struct nvkm_oclass *oclass, struct nvkm_domain *clocks,
 534                  struct nvkm_pstate *pstates, int nb_pstates,
 535                  bool allow_reclock, int length, void **object)
 536 {
 537         struct nvkm_device *device = nv_device(parent);
 538         struct nvkm_clk *clk;
 539         int ret, idx, arglen;
 540         const char *mode;
 541
 542         ret = nvkm_subdev_create_(parent, engine, oclass, 0, "CLK",
 543                                   "clock", length, object);
 544         clk = *object;
 545         if (ret)
 546                 return ret;
 547
 548         INIT_LIST_HEAD(&clk->states);
 549         clk->domains = clocks;
 550         clk->ustate_ac = -1;
 551         clk->ustate_dc = -1;
 552
 553         INIT_WORK(&clk->work, nvkm_pstate_work);
 554         init_waitqueue_head(&clk->wait);
 555         atomic_set(&clk->waiting, 0);
 556
 557         /* If no pstates are provided, try and fetch them from the BIOS */
 558         if (!pstates) {
 559                 idx = 0;
 560                 do {
 561                         ret = nvkm_pstate_new(clk, idx++);
 562                 } while (ret == 0);
 563         } else {
 564                 for (idx = 0; idx < nb_pstates; idx++)
 565                         list_add_tail(&pstates[idx].head, &clk->states);
 566                 clk->state_nr = nb_pstates;
 567         }
 568
 569         clk->allow_reclock = allow_reclock;
 570
 571         ret = nvkm_notify_init(NULL, &device->event, nvkm_clk_pwrsrc, true,
 572                                NULL, 0, 0, &clk->pwrsrc_ntfy);
 573         if (ret)
 574                 return ret;
 575
 576         mode = nvkm_stropt(device->cfgopt, "NvClkMode", &arglen);
 577         if (mode) {
 578                 clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen);
 579                 clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen);
 580         }
 581
 582         mode = nvkm_stropt(device->cfgopt, "NvClkModeAC", &arglen);
 583         if (mode)
 584                 clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen);
 585
 586         mode = nvkm_stropt(device->cfgopt, "NvClkModeDC", &arglen);
 587         if (mode)
 588                 clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen);
 589
 590         return 0;
 591 }