2 * Copyright 2012 Nouveau Community
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Martin Peres <martin.peres@labri.fr>
27 #include <subdev/timer.h>
30 nv50_bus_hwsq_exec(struct nvkm_bus *pbus, u32 *data, u32 size)
32 struct nv50_bus_priv *priv = (void *)pbus;
35 nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
36 nv_wr32(pbus, 0x001304, 0x00000000);
37 for (i = 0; i < size; i++)
38 nv_wr32(priv, 0x001400 + (i * 4), data[i]);
39 nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
40 nv_wr32(pbus, 0x00130c, 0x00000003);
42 return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
46 nv50_bus_intr(struct nvkm_subdev *subdev)
48 struct nvkm_bus *pbus = nvkm_bus(subdev);
49 u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
51 if (stat & 0x00000008) {
52 u32 addr = nv_rd32(pbus, 0x009084);
53 u32 data = nv_rd32(pbus, 0x009088);
55 nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
56 (addr & 0x00000002) ? "write" : "read", data,
60 nv_wr32(pbus, 0x001100, 0x00000008);
63 if (stat & 0x00010000) {
64 subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_THERM);
65 if (subdev && subdev->intr)
68 nv_wr32(pbus, 0x001100, 0x00010000);
72 nv_error(pbus, "unknown intr 0x%08x\n", stat);
73 nv_mask(pbus, 0x001140, stat, 0);
78 nv50_bus_init(struct nvkm_object *object)
80 struct nv04_bus_priv *priv = (void *)object;
83 ret = nvkm_bus_init(&priv->base);
87 nv_wr32(priv, 0x001100, 0xffffffff);
88 nv_wr32(priv, 0x001140, 0x00010008);
93 nv50_bus_oclass = &(struct nv04_bus_impl) {
94 .base.handle = NV_SUBDEV(BUS, 0x50),
95 .base.ofuncs = &(struct nvkm_ofuncs) {
96 .ctor = nv04_bus_ctor,
97 .dtor = _nvkm_bus_dtor,
98 .init = nv50_bus_init,
99 .fini = _nvkm_bus_fini,
101 .intr = nv50_bus_intr,
102 .hwsq_exec = nv50_bus_hwsq_exec,