2 * Copyright 2012 Nouveau Community
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Martin Peres
24 #include <subdev/bios.h>
25 #include <subdev/bios/bit.h>
26 #include <subdev/bios/perf.h>
28 #include <core/device.h>
31 nvbios_perf_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr,
32 u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
34 struct bit_entry bit_P;
37 if (!bit_entry(bios, 'P', &bit_P)) {
38 if (bit_P.version <= 2) {
39 perf = nv_ro16(bios, bit_P.offset + 0);
41 *ver = nv_ro08(bios, perf + 0);
42 *hdr = nv_ro08(bios, perf + 1);
43 if (*ver >= 0x40 && *ver < 0x41) {
44 *cnt = nv_ro08(bios, perf + 5);
45 *len = nv_ro08(bios, perf + 2);
46 *snr = nv_ro08(bios, perf + 4);
47 *ssz = nv_ro08(bios, perf + 3);
50 if (*ver >= 0x20 && *ver < 0x40) {
51 *cnt = nv_ro08(bios, perf + 2);
52 *len = nv_ro08(bios, perf + 3);
53 *snr = nv_ro08(bios, perf + 4);
54 *ssz = nv_ro08(bios, perf + 5);
61 if (bios->bmp_offset) {
62 if (nv_ro08(bios, bios->bmp_offset + 6) >= 0x25) {
63 perf = nv_ro16(bios, bios->bmp_offset + 0x94);
65 *hdr = nv_ro08(bios, perf + 0);
66 *ver = nv_ro08(bios, perf + 1);
67 *cnt = nv_ro08(bios, perf + 2);
68 *len = nv_ro08(bios, perf + 3);
80 nvbios_perf_entry(struct nvkm_bios *bios, int idx,
81 u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
84 u16 perf = nvbios_perf_table(bios, ver, hdr, cnt, len, &snr, &ssz);
85 if (perf && idx < *cnt) {
86 perf = perf + *hdr + (idx * (*len + (snr * ssz)));
96 nvbios_perfEp(struct nvkm_bios *bios, int idx,
97 u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *info)
99 u16 perf = nvbios_perf_entry(bios, idx, ver, hdr, cnt, len);
100 memset(info, 0x00, sizeof(*info));
101 info->pstate = nv_ro08(bios, perf + 0x00);
102 switch (!!perf * *ver) {
106 info->core = nv_ro32(bios, perf + 0x01) * 10;
107 info->memory = nv_ro32(bios, perf + 0x05) * 20;
108 info->fanspeed = nv_ro08(bios, perf + 0x37);
110 info->voltage = nv_ro08(bios, perf + 0x38);
115 info->fanspeed = nv_ro08(bios, perf + 0x04);
116 info->voltage = nv_ro08(bios, perf + 0x05);
117 info->shader = nv_ro16(bios, perf + 0x06) * 1000;
118 info->core = info->shader + (signed char)
119 nv_ro08(bios, perf + 0x08) * 1000;
120 switch (nv_device(bios)->chipset) {
123 info->memory = nv_ro16(bios, perf + 0x0b) * 1000;
126 info->memory = nv_ro16(bios, perf + 0x0b) * 2000;
131 info->fanspeed = nv_ro08(bios, perf + 0x04);
132 info->voltage = nv_ro08(bios, perf + 0x05);
133 info->core = nv_ro16(bios, perf + 0x06) * 1000;
134 info->shader = nv_ro16(bios, perf + 0x0a) * 1000;
135 info->memory = nv_ro16(bios, perf + 0x0c) * 1000;
138 info->script = nv_ro16(bios, perf + 0x02);
140 info->fanspeed = nv_ro08(bios, perf + 0x06);
141 info->voltage = nv_ro08(bios, perf + 0x07);
142 info->core = nv_ro16(bios, perf + 0x08) * 1000;
143 info->shader = nv_ro16(bios, perf + 0x0a) * 1000;
144 info->memory = nv_ro16(bios, perf + 0x0c) * 1000;
145 info->vdec = nv_ro16(bios, perf + 0x10) * 1000;
146 info->disp = nv_ro16(bios, perf + 0x14) * 1000;
149 info->voltage = nv_ro08(bios, perf + 0x02);
158 nvbios_perfSe(struct nvkm_bios *bios, u32 perfE, int idx,
159 u8 *ver, u8 *hdr, u8 cnt, u8 len)
161 u32 data = 0x00000000;
163 data = perfE + *hdr + (idx * len);
170 nvbios_perfSp(struct nvkm_bios *bios, u32 perfE, int idx,
171 u8 *ver, u8 *hdr, u8 cnt, u8 len,
172 struct nvbios_perfS *info)
174 u32 data = nvbios_perfSe(bios, perfE, idx, ver, hdr, cnt, len);
175 memset(info, 0x00, sizeof(*info));
176 switch (!!data * *ver) {
178 info->v40.freq = (nv_ro16(bios, data + 0x00) & 0x3fff) * 1000;
187 nvbios_perf_fan_parse(struct nvkm_bios *bios,
188 struct nvbios_perf_fan *fan)
190 u8 ver, hdr, cnt, len, snr, ssz;
191 u16 perf = nvbios_perf_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
195 if (ver >= 0x20 && ver < 0x40 && hdr > 6)
196 fan->pwm_divisor = nv_ro16(bios, perf + 6);
198 fan->pwm_divisor = 0;