kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include <engine/sw.h>
  25 #include <engine/fifo.h>
  26
  27 struct nv04_sw_priv {
  28         struct nvkm_sw base;
  29 };
  30
  31 struct nv04_sw_chan {
  32         struct nvkm_sw_chan base;
  33 };
  34
  35 /*******************************************************************************
  36  * software object classes
  37  ******************************************************************************/
  38
  39 static int
  40 nv04_sw_set_ref(struct nvkm_object *object, u32 mthd, void *data, u32 size)
  41 {
  42         struct nvkm_object *channel = (void *)nv_engctx(object->parent);
  43         struct nvkm_fifo_chan *fifo = (void *)channel->parent;
  44         atomic_set(&fifo->refcnt, *(u32*)data);
  45         return 0;
  46 }
  47
  48 static int
  49 nv04_sw_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size)
  50 {
  51         struct nv04_sw_chan *chan = (void *)nv_engctx(object->parent);
  52         if (chan->base.flip)
  53                 return chan->base.flip(chan->base.flip_data);
  54         return -EINVAL;
  55 }
  56
  57 static struct nvkm_omthds
  58 nv04_sw_omthds[] = {
  59         { 0x0150, 0x0150, nv04_sw_set_ref },
  60         { 0x0500, 0x0500, nv04_sw_flip },
  61         {}
  62 };
  63
  64 static struct nvkm_oclass
  65 nv04_sw_sclass[] = {
  66         { 0x006e, &nvkm_object_ofuncs, nv04_sw_omthds },
  67         {}
  68 };
  69
  70 /*******************************************************************************
  71  * software context
  72  ******************************************************************************/
  73
  74 static int
  75 nv04_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  76                      struct nvkm_oclass *oclass, void *data, u32 size,
  77                      struct nvkm_object **pobject)
  78 {
  79         struct nv04_sw_chan *chan;
  80         int ret;
  81
  82         ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
  83         *pobject = nv_object(chan);
  84         if (ret)
  85                 return ret;
  86
  87         return 0;
  88 }
  89
  90 static struct nvkm_oclass
  91 nv04_sw_cclass = {
  92         .handle = NV_ENGCTX(SW, 0x04),
  93         .ofuncs = &(struct nvkm_ofuncs) {
  94                 .ctor = nv04_sw_context_ctor,
  95                 .dtor = _nvkm_sw_context_dtor,
  96                 .init = _nvkm_sw_context_init,
  97                 .fini = _nvkm_sw_context_fini,
  98         },
  99 };
 100
 101 /*******************************************************************************
 102  * software engine/subdev functions
 103  ******************************************************************************/
 104
 105 void
 106 nv04_sw_intr(struct nvkm_subdev *subdev)
 107 {
 108         nv_mask(subdev, 0x000100, 0x80000000, 0x00000000);
 109 }
 110
 111 static int
 112 nv04_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 113              struct nvkm_oclass *oclass, void *data, u32 size,
 114              struct nvkm_object **pobject)
 115 {
 116         struct nv04_sw_priv *priv;
 117         int ret;
 118
 119         ret = nvkm_sw_create(parent, engine, oclass, &priv);
 120         *pobject = nv_object(priv);
 121         if (ret)
 122                 return ret;
 123
 124         nv_engine(priv)->cclass = &nv04_sw_cclass;
 125         nv_engine(priv)->sclass = nv04_sw_sclass;
 126         nv_subdev(priv)->intr = nv04_sw_intr;
 127         return 0;
 128 }
 129
 130 struct nvkm_oclass *
 131 nv04_sw_oclass = &(struct nvkm_oclass) {
 132         .handle = NV_ENGINE(SW, 0x04),
 133         .ofuncs = &(struct nvkm_ofuncs) {
 134                 .ctor = nv04_sw_ctor,
 135                 .dtor = _nvkm_sw_dtor,
 136                 .init = _nvkm_sw_init,
 137                 .fini = _nvkm_sw_fini,
 138         },
 139 };