kernel/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

   1 #include "nv20.h"
   2 #include "regs.h"
   3
   4 #include <core/client.h>
   5 #include <core/gpuobj.h>
   6 #include <engine/fifo.h>
   7 #include <engine/fifo/chan.h>
   8 #include <subdev/fb.h>
   9 #include <subdev/timer.h>
  10
  11 /*******************************************************************************
  12  * PGRAPH context
  13  ******************************************************************************/
  14
  15 int
  16 nv20_gr_chan_init(struct nvkm_object *object)
  17 {
  18         struct nv20_gr_chan *chan = nv20_gr_chan(object);
  19         struct nv20_gr *gr = chan->gr;
  20         u32 inst = nvkm_memory_addr(chan->inst);
  21
  22         nvkm_kmap(gr->ctxtab);
  23         nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4);
  24         nvkm_done(gr->ctxtab);
  25         return 0;
  26 }
  27
  28 int
  29 nv20_gr_chan_fini(struct nvkm_object *object, bool suspend)
  30 {
  31         struct nv20_gr_chan *chan = nv20_gr_chan(object);
  32         struct nv20_gr *gr = chan->gr;
  33         struct nvkm_device *device = gr->base.engine.subdev.device;
  34         u32 inst = nvkm_memory_addr(chan->inst);
  35         int chid = -1;
  36
  37         nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
  38         if (nvkm_rd32(device, 0x400144) & 0x00010000)
  39                 chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
  40         if (chan->chid == chid) {
  41                 nvkm_wr32(device, 0x400784, inst >> 4);
  42                 nvkm_wr32(device, 0x400788, 0x00000002);
  43                 nvkm_msec(device, 2000,
  44                         if (!nvkm_rd32(device, 0x400700))
  45                                 break;
  46                 );
  47                 nvkm_wr32(device, 0x400144, 0x10000000);
  48                 nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);
  49         }
  50         nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);
  51
  52         nvkm_kmap(gr->ctxtab);
  53         nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
  54         nvkm_done(gr->ctxtab);
  55         return 0;
  56 }
  57
  58 void *
  59 nv20_gr_chan_dtor(struct nvkm_object *object)
  60 {
  61         struct nv20_gr_chan *chan = nv20_gr_chan(object);
  62         nvkm_memory_del(&chan->inst);
  63         return chan;
  64 }
  65
  66 static const struct nvkm_object_func
  67 nv20_gr_chan = {
  68         .dtor = nv20_gr_chan_dtor,
  69         .init = nv20_gr_chan_init,
  70         .fini = nv20_gr_chan_fini,
  71 };
  72
  73 static int
  74 nv20_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
  75                  const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
  76 {
  77         struct nv20_gr *gr = nv20_gr(base);
  78         struct nv20_gr_chan *chan;
  79         int ret, i;
  80
  81         if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
  82                 return -ENOMEM;
  83         nvkm_object_ctor(&nv20_gr_chan, oclass, &chan->object);
  84         chan->gr = gr;
  85         chan->chid = fifoch->chid;
  86         *pobject = &chan->object;
  87
  88         ret = nvkm_memory_new(gr->base.engine.subdev.device,
  89                               NVKM_MEM_TARGET_INST, 0x37f0, 16, true,
  90                               &chan->inst);
  91         if (ret)
  92                 return ret;
  93
  94         nvkm_kmap(chan->inst);
  95         nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
  96         nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
  97         nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
  98         nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
  99         nvkm_wo32(chan->inst, 0x047c, 0x00000101);
 100         nvkm_wo32(chan->inst, 0x0490, 0x00000111);
 101         nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
 102         for (i = 0x04d4; i <= 0x04e0; i += 4)
 103                 nvkm_wo32(chan->inst, i, 0x00030303);
 104         for (i = 0x04f4; i <= 0x0500; i += 4)
 105                 nvkm_wo32(chan->inst, i, 0x00080000);
 106         for (i = 0x050c; i <= 0x0518; i += 4)
 107                 nvkm_wo32(chan->inst, i, 0x01012000);
 108         for (i = 0x051c; i <= 0x0528; i += 4)
 109                 nvkm_wo32(chan->inst, i, 0x000105b8);
 110         for (i = 0x052c; i <= 0x0538; i += 4)
 111                 nvkm_wo32(chan->inst, i, 0x00080008);
 112         for (i = 0x055c; i <= 0x0598; i += 4)
 113                 nvkm_wo32(chan->inst, i, 0x07ff0000);
 114         nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);
 115         nvkm_wo32(chan->inst, 0x05fc, 0x00000001);
 116         nvkm_wo32(chan->inst, 0x0604, 0x00004000);
 117         nvkm_wo32(chan->inst, 0x0610, 0x00000001);
 118         nvkm_wo32(chan->inst, 0x0618, 0x00040000);
 119         nvkm_wo32(chan->inst, 0x061c, 0x00010000);
 120         for (i = 0x1c1c; i <= 0x248c; i += 16) {
 121                 nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
 122                 nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
 123                 nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
 124         }
 125         nvkm_wo32(chan->inst, 0x281c, 0x3f800000);
 126         nvkm_wo32(chan->inst, 0x2830, 0x3f800000);
 127         nvkm_wo32(chan->inst, 0x285c, 0x40000000);
 128         nvkm_wo32(chan->inst, 0x2860, 0x3f800000);
 129         nvkm_wo32(chan->inst, 0x2864, 0x3f000000);
 130         nvkm_wo32(chan->inst, 0x286c, 0x40000000);
 131         nvkm_wo32(chan->inst, 0x2870, 0x3f800000);
 132         nvkm_wo32(chan->inst, 0x2878, 0xbf800000);
 133         nvkm_wo32(chan->inst, 0x2880, 0xbf800000);
 134         nvkm_wo32(chan->inst, 0x34a4, 0x000fe000);
 135         nvkm_wo32(chan->inst, 0x3530, 0x000003f8);
 136         nvkm_wo32(chan->inst, 0x3540, 0x002fe000);
 137         for (i = 0x355c; i <= 0x3578; i += 4)
 138                 nvkm_wo32(chan->inst, i, 0x001c527c);
 139         nvkm_done(chan->inst);
 140         return 0;
 141 }
 142
 143 /*******************************************************************************
 144  * PGRAPH engine/subdev functions
 145  ******************************************************************************/
 146
 147 void
 148 nv20_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
 149 {
 150         struct nv20_gr *gr = nv20_gr(base);
 151         struct nvkm_device *device = gr->base.engine.subdev.device;
 152         struct nvkm_fifo *fifo = device->fifo;
 153         unsigned long flags;
 154
 155         nvkm_fifo_pause(fifo, &flags);
 156         nv04_gr_idle(&gr->base);
 157
 158         nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
 159         nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
 160         nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
 161
 162         nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
 163         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
 164         nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
 165         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
 166         nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
 167         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);
 168
 169         if (device->chipset != 0x34) {
 170                 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
 171                 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
 172                 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
 173         }
 174
 175         nvkm_fifo_start(fifo, &flags);
 176 }
 177
 178 void
 179 nv20_gr_intr(struct nvkm_gr *base)
 180 {
 181         struct nv20_gr *gr = nv20_gr(base);
 182         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
 183         struct nvkm_device *device = subdev->device;
 184         struct nvkm_fifo_chan *chan;
 185         u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
 186         u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
 187         u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
 188         u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
 189         u32 chid = (addr & 0x01f00000) >> 20;
 190         u32 subc = (addr & 0x00070000) >> 16;
 191         u32 mthd = (addr & 0x00001ffc);
 192         u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
 193         u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
 194         u32 show = stat;
 195         char msg[128], src[128], sta[128];
 196         unsigned long flags;
 197
 198         chan = nvkm_fifo_chan_chid(device->fifo, chid, &flags);
 199
 200         nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
 201         nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
 202
 203         if (show) {
 204                 nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
 205                 nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
 206                 nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
 207                 nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
 208                                    "nstatus %08x [%s] ch %d [%s] subc %d "
 209                                    "class %04x mthd %04x data %08x\n",
 210                            show, msg, nsource, src, nstatus, sta, chid,
 211                            chan ? chan->object.client->name : "unknown",
 212                            subc, class, mthd, data);
 213         }
 214
 215         nvkm_fifo_chan_put(device->fifo, flags, &chan);
 216 }
 217
 218 int
 219 nv20_gr_oneinit(struct nvkm_gr *base)
 220 {
 221         struct nv20_gr *gr = nv20_gr(base);
 222         return nvkm_memory_new(gr->base.engine.subdev.device,
 223                                NVKM_MEM_TARGET_INST, 32 * 4, 16,
 224                                true, &gr->ctxtab);
 225 }
 226
 227 int
 228 nv20_gr_init(struct nvkm_gr *base)
 229 {
 230         struct nv20_gr *gr = nv20_gr(base);
 231         struct nvkm_device *device = gr->base.engine.subdev.device;
 232         u32 tmp, vramsz;
 233         int i;
 234
 235         nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE,
 236                           nvkm_memory_addr(gr->ctxtab) >> 4);
 237
 238         if (device->chipset == 0x20) {
 239                 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
 240                 for (i = 0; i < 15; i++)
 241                         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
 242                 nvkm_msec(device, 2000,
 243                         if (!nvkm_rd32(device, 0x400700))
 244                                 break;
 245                 );
 246         } else {
 247                 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
 248                 for (i = 0; i < 32; i++)
 249                         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
 250                 nvkm_msec(device, 2000,
 251                         if (!nvkm_rd32(device, 0x400700))
 252                                 break;
 253                 );
 254         }
 255
 256         nvkm_wr32(device, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
 257         nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
 258
 259         nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
 260         nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
 261         nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
 262         nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
 263         nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
 264         nvkm_wr32(device, 0x40009C           , 0x00000040);
 265
 266         if (device->chipset >= 0x25) {
 267                 nvkm_wr32(device, 0x400890, 0x00a8cfff);
 268                 nvkm_wr32(device, 0x400610, 0x304B1FB6);
 269                 nvkm_wr32(device, 0x400B80, 0x1cbd3883);
 270                 nvkm_wr32(device, 0x400B84, 0x44000000);
 271                 nvkm_wr32(device, 0x400098, 0x40000080);
 272                 nvkm_wr32(device, 0x400B88, 0x000000ff);
 273
 274         } else {
 275                 nvkm_wr32(device, 0x400880, 0x0008c7df);
 276                 nvkm_wr32(device, 0x400094, 0x00000005);
 277                 nvkm_wr32(device, 0x400B80, 0x45eae20e);
 278                 nvkm_wr32(device, 0x400B84, 0x24000000);
 279                 nvkm_wr32(device, 0x400098, 0x00000040);
 280                 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
 281                 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
 282                 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
 283                 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
 284         }
 285
 286         nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));
 287         nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
 288         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));
 289
 290         nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
 291         nvkm_wr32(device, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 292
 293         tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;
 294         nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
 295         tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100;
 296         nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
 297
 298         /* begin RAM config */
 299         vramsz = device->func->resource_size(device, 1) - 1;
 300         nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
 301         nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
 302         nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
 303         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));
 304         nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
 305         nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));
 306         nvkm_wr32(device, 0x400820, 0);
 307         nvkm_wr32(device, 0x400824, 0);
 308         nvkm_wr32(device, 0x400864, vramsz - 1);
 309         nvkm_wr32(device, 0x400868, vramsz - 1);
 310
 311         /* interesting.. the below overwrites some of the tile setup above.. */
 312         nvkm_wr32(device, 0x400B20, 0x00000000);
 313         nvkm_wr32(device, 0x400B04, 0xFFFFFFFF);
 314
 315         nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
 316         nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
 317         nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
 318         nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
 319         return 0;
 320 }
 321
 322 void *
 323 nv20_gr_dtor(struct nvkm_gr *base)
 324 {
 325         struct nv20_gr *gr = nv20_gr(base);
 326         nvkm_memory_del(&gr->ctxtab);
 327         return gr;
 328 }
 329
 330 int
 331 nv20_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
 332              int index, struct nvkm_gr **pgr)
 333 {
 334         struct nv20_gr *gr;
 335
 336         if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
 337                 return -ENOMEM;
 338         *pgr = &gr->base;
 339
 340         return nvkm_gr_ctor(func, device, index, 0x00001000, true, &gr->base);
 341 }
 342
 343 static const struct nvkm_gr_func
 344 nv20_gr = {
 345         .dtor = nv20_gr_dtor,
 346         .oneinit = nv20_gr_oneinit,
 347         .init = nv20_gr_init,
 348         .intr = nv20_gr_intr,
 349         .tile = nv20_gr_tile,
 350         .chan_new = nv20_gr_chan_new,
 351         .sclass = {
 352                 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
 353                 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */
 354                 { -1, -1, 0x0030, &nv04_gr_object }, /* null */
 355                 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
 356                 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */
 357                 { -1, -1, 0x0044, &nv04_gr_object }, /* patt */
 358                 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
 359                 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
 360                 { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
 361                 { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
 362                 { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
 363                 { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
 364                 { -1, -1, 0x0097, &nv04_gr_object }, /* kelvin */
 365                 { -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */
 366                 { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
 367                 {}
 368         }
 369 };
 370
 371 int
 372 nv20_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
 373 {
 374         return nv20_gr_new_(&nv20_gr, device, index, pgr);
 375 }