kernel/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c

   1 #include "nv20.h"
   2 #include "regs.h"
   3
   4 #include <core/client.h>
   5 #include <core/device.h>
   6 #include <core/handle.h>
   7 #include <engine/fifo.h>
   8 #include <subdev/fb.h>
   9 #include <subdev/timer.h>
  10
  11 /*******************************************************************************
  12  * Graphics object classes
  13  ******************************************************************************/
  14
  15 static struct nvkm_oclass
  16 nv20_gr_sclass[] = {
  17         { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
  18         { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
  19         { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
  20         { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
  21         { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
  22         { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
  23         { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
  24         { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
  25         { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
  26         { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
  27         { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
  28         { 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */
  29         { 0x0097, &nv04_gr_ofuncs, NULL }, /* kelvin */
  30         { 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */
  31         { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
  32         {},
  33 };
  34
  35 /*******************************************************************************
  36  * PGRAPH context
  37  ******************************************************************************/
  38
  39 static int
  40 nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  41                      struct nvkm_oclass *oclass, void *data, u32 size,
  42                      struct nvkm_object **pobject)
  43 {
  44         struct nv20_gr_chan *chan;
  45         int ret, i;
  46
  47         ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0,
  48                                      16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
  49         *pobject = nv_object(chan);
  50         if (ret)
  51                 return ret;
  52
  53         chan->chid = nvkm_fifo_chan(parent)->chid;
  54
  55         nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
  56         nv_wo32(chan, 0x033c, 0xffff0000);
  57         nv_wo32(chan, 0x03a0, 0x0fff0000);
  58         nv_wo32(chan, 0x03a4, 0x0fff0000);
  59         nv_wo32(chan, 0x047c, 0x00000101);
  60         nv_wo32(chan, 0x0490, 0x00000111);
  61         nv_wo32(chan, 0x04a8, 0x44400000);
  62         for (i = 0x04d4; i <= 0x04e0; i += 4)
  63                 nv_wo32(chan, i, 0x00030303);
  64         for (i = 0x04f4; i <= 0x0500; i += 4)
  65                 nv_wo32(chan, i, 0x00080000);
  66         for (i = 0x050c; i <= 0x0518; i += 4)
  67                 nv_wo32(chan, i, 0x01012000);
  68         for (i = 0x051c; i <= 0x0528; i += 4)
  69                 nv_wo32(chan, i, 0x000105b8);
  70         for (i = 0x052c; i <= 0x0538; i += 4)
  71                 nv_wo32(chan, i, 0x00080008);
  72         for (i = 0x055c; i <= 0x0598; i += 4)
  73                 nv_wo32(chan, i, 0x07ff0000);
  74         nv_wo32(chan, 0x05a4, 0x4b7fffff);
  75         nv_wo32(chan, 0x05fc, 0x00000001);
  76         nv_wo32(chan, 0x0604, 0x00004000);
  77         nv_wo32(chan, 0x0610, 0x00000001);
  78         nv_wo32(chan, 0x0618, 0x00040000);
  79         nv_wo32(chan, 0x061c, 0x00010000);
  80         for (i = 0x1c1c; i <= 0x248c; i += 16) {
  81                 nv_wo32(chan, (i + 0), 0x10700ff9);
  82                 nv_wo32(chan, (i + 4), 0x0436086c);
  83                 nv_wo32(chan, (i + 8), 0x000c001b);
  84         }
  85         nv_wo32(chan, 0x281c, 0x3f800000);
  86         nv_wo32(chan, 0x2830, 0x3f800000);
  87         nv_wo32(chan, 0x285c, 0x40000000);
  88         nv_wo32(chan, 0x2860, 0x3f800000);
  89         nv_wo32(chan, 0x2864, 0x3f000000);
  90         nv_wo32(chan, 0x286c, 0x40000000);
  91         nv_wo32(chan, 0x2870, 0x3f800000);
  92         nv_wo32(chan, 0x2878, 0xbf800000);
  93         nv_wo32(chan, 0x2880, 0xbf800000);
  94         nv_wo32(chan, 0x34a4, 0x000fe000);
  95         nv_wo32(chan, 0x3530, 0x000003f8);
  96         nv_wo32(chan, 0x3540, 0x002fe000);
  97         for (i = 0x355c; i <= 0x3578; i += 4)
  98                 nv_wo32(chan, i, 0x001c527c);
  99         return 0;
 100 }
 101
 102 int
 103 nv20_gr_context_init(struct nvkm_object *object)
 104 {
 105         struct nv20_gr_priv *priv = (void *)object->engine;
 106         struct nv20_gr_chan *chan = (void *)object;
 107         int ret;
 108
 109         ret = nvkm_gr_context_init(&chan->base);
 110         if (ret)
 111                 return ret;
 112
 113         nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
 114         return 0;
 115 }
 116
 117 int
 118 nv20_gr_context_fini(struct nvkm_object *object, bool suspend)
 119 {
 120         struct nv20_gr_priv *priv = (void *)object->engine;
 121         struct nv20_gr_chan *chan = (void *)object;
 122         int chid = -1;
 123
 124         nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
 125         if (nv_rd32(priv, 0x400144) & 0x00010000)
 126                 chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24;
 127         if (chan->chid == chid) {
 128                 nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4);
 129                 nv_wr32(priv, 0x400788, 0x00000002);
 130                 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
 131                 nv_wr32(priv, 0x400144, 0x10000000);
 132                 nv_mask(priv, 0x400148, 0xff000000, 0x1f000000);
 133         }
 134         nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
 135
 136         nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
 137         return nvkm_gr_context_fini(&chan->base, suspend);
 138 }
 139
 140 static struct nvkm_oclass
 141 nv20_gr_cclass = {
 142         .handle = NV_ENGCTX(GR, 0x20),
 143         .ofuncs = &(struct nvkm_ofuncs) {
 144                 .ctor = nv20_gr_context_ctor,
 145                 .dtor = _nvkm_gr_context_dtor,
 146                 .init = nv20_gr_context_init,
 147                 .fini = nv20_gr_context_fini,
 148                 .rd32 = _nvkm_gr_context_rd32,
 149                 .wr32 = _nvkm_gr_context_wr32,
 150         },
 151 };
 152
 153 /*******************************************************************************
 154  * PGRAPH engine/subdev functions
 155  ******************************************************************************/
 156
 157 void
 158 nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
 159 {
 160         struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
 161         struct nvkm_fifo *pfifo = nvkm_fifo(engine);
 162         struct nv20_gr_priv *priv = (void *)engine;
 163         unsigned long flags;
 164
 165         pfifo->pause(pfifo, &flags);
 166         nv04_gr_idle(priv);
 167
 168         nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
 169         nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
 170         nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
 171
 172         nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
 173         nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit);
 174         nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
 175         nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch);
 176         nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
 177         nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr);
 178
 179         if (nv_device(engine)->chipset != 0x34) {
 180                 nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
 181                 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
 182                 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp);
 183         }
 184
 185         pfifo->start(pfifo, &flags);
 186 }
 187
 188 void
 189 nv20_gr_intr(struct nvkm_subdev *subdev)
 190 {
 191         struct nvkm_engine *engine = nv_engine(subdev);
 192         struct nvkm_object *engctx;
 193         struct nvkm_handle *handle;
 194         struct nv20_gr_priv *priv = (void *)subdev;
 195         u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
 196         u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
 197         u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
 198         u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
 199         u32 chid = (addr & 0x01f00000) >> 20;
 200         u32 subc = (addr & 0x00070000) >> 16;
 201         u32 mthd = (addr & 0x00001ffc);
 202         u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
 203         u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
 204         u32 show = stat;
 205
 206         engctx = nvkm_engctx_get(engine, chid);
 207         if (stat & NV_PGRAPH_INTR_ERROR) {
 208                 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
 209                         handle = nvkm_handle_get_class(engctx, class);
 210                         if (handle && !nv_call(handle->object, mthd, data))
 211                                 show &= ~NV_PGRAPH_INTR_ERROR;
 212                         nvkm_handle_put(handle);
 213                 }
 214         }
 215
 216         nv_wr32(priv, NV03_PGRAPH_INTR, stat);
 217         nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
 218
 219         if (show) {
 220                 nv_error(priv, "%s", "");
 221                 nvkm_bitfield_print(nv10_gr_intr_name, show);
 222                 pr_cont(" nsource:");
 223                 nvkm_bitfield_print(nv04_gr_nsource, nsource);
 224                 pr_cont(" nstatus:");
 225                 nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
 226                 pr_cont("\n");
 227                 nv_error(priv,
 228                          "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
 229                          chid, nvkm_client_name(engctx), subc, class, mthd,
 230                          data);
 231         }
 232
 233         nvkm_engctx_put(engctx);
 234 }
 235
 236 static int
 237 nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 238              struct nvkm_oclass *oclass, void *data, u32 size,
 239              struct nvkm_object **pobject)
 240 {
 241         struct nv20_gr_priv *priv;
 242         int ret;
 243
 244         ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
 245         *pobject = nv_object(priv);
 246         if (ret)
 247                 return ret;
 248
 249         ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
 250                               NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
 251         if (ret)
 252                 return ret;
 253
 254         nv_subdev(priv)->unit = 0x00001000;
 255         nv_subdev(priv)->intr = nv20_gr_intr;
 256         nv_engine(priv)->cclass = &nv20_gr_cclass;
 257         nv_engine(priv)->sclass = nv20_gr_sclass;
 258         nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
 259         return 0;
 260 }
 261
 262 void
 263 nv20_gr_dtor(struct nvkm_object *object)
 264 {
 265         struct nv20_gr_priv *priv = (void *)object;
 266         nvkm_gpuobj_ref(NULL, &priv->ctxtab);
 267         nvkm_gr_destroy(&priv->base);
 268 }
 269
 270 int
 271 nv20_gr_init(struct nvkm_object *object)
 272 {
 273         struct nvkm_engine *engine = nv_engine(object);
 274         struct nv20_gr_priv *priv = (void *)engine;
 275         struct nvkm_fb *pfb = nvkm_fb(object);
 276         u32 tmp, vramsz;
 277         int ret, i;
 278
 279         ret = nvkm_gr_init(&priv->base);
 280         if (ret)
 281                 return ret;
 282
 283         nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);
 284
 285         if (nv_device(priv)->chipset == 0x20) {
 286                 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
 287                 for (i = 0; i < 15; i++)
 288                         nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
 289                 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
 290         } else {
 291                 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
 292                 for (i = 0; i < 32; i++)
 293                         nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
 294                 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
 295         }
 296
 297         nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
 298         nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
 299
 300         nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
 301         nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
 302         nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700);
 303         nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
 304         nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000);
 305         nv_wr32(priv, 0x40009C           , 0x00000040);
 306
 307         if (nv_device(priv)->chipset >= 0x25) {
 308                 nv_wr32(priv, 0x400890, 0x00a8cfff);
 309                 nv_wr32(priv, 0x400610, 0x304B1FB6);
 310                 nv_wr32(priv, 0x400B80, 0x1cbd3883);
 311                 nv_wr32(priv, 0x400B84, 0x44000000);
 312                 nv_wr32(priv, 0x400098, 0x40000080);
 313                 nv_wr32(priv, 0x400B88, 0x000000ff);
 314
 315         } else {
 316                 nv_wr32(priv, 0x400880, 0x0008c7df);
 317                 nv_wr32(priv, 0x400094, 0x00000005);
 318                 nv_wr32(priv, 0x400B80, 0x45eae20e);
 319                 nv_wr32(priv, 0x400B84, 0x24000000);
 320                 nv_wr32(priv, 0x400098, 0x00000040);
 321                 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
 322                 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
 323                 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
 324                 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
 325         }
 326
 327         /* Turn all the tiling regions off. */
 328         for (i = 0; i < pfb->tile.regions; i++)
 329                 engine->tile_prog(engine, i);
 330
 331         nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324));
 332         nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
 333         nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324));
 334
 335         nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
 336         nv_wr32(priv, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 337
 338         tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00;
 339         nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
 340         tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) | 0x00020100;
 341         nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
 342
 343         /* begin RAM config */
 344         vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
 345         nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
 346         nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
 347         nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
 348         nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200));
 349         nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
 350         nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204));
 351         nv_wr32(priv, 0x400820, 0);
 352         nv_wr32(priv, 0x400824, 0);
 353         nv_wr32(priv, 0x400864, vramsz - 1);
 354         nv_wr32(priv, 0x400868, vramsz - 1);
 355
 356         /* interesting.. the below overwrites some of the tile setup above.. */
 357         nv_wr32(priv, 0x400B20, 0x00000000);
 358         nv_wr32(priv, 0x400B04, 0xFFFFFFFF);
 359
 360         nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
 361         nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
 362         nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
 363         nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
 364         return 0;
 365 }
 366
 367 struct nvkm_oclass
 368 nv20_gr_oclass = {
 369         .handle = NV_ENGINE(GR, 0x20),
 370         .ofuncs = &(struct nvkm_ofuncs) {
 371                 .ctor = nv20_gr_ctor,
 372                 .dtor = nv20_gr_dtor,
 373                 .init = nv20_gr_init,
 374                 .fini = _nvkm_gr_fini,
 375         },
 376 };