kernel/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv04.h"
  25
  26 #include <core/client.h>
  27 #include <core/engctx.h>
  28 #include <core/ramht.h>
  29 #include <subdev/instmem/nv04.h>
  30
  31 #include <nvif/class.h>
  32 #include <nvif/unpack.h>
  33
  34 static struct ramfc_desc
  35 nv10_ramfc[] = {
  36         { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
  37         { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
  38         { 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
  39         { 16,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
  40         { 16, 16, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
  41         { 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_STATE },
  42         { 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
  43         { 32,  0, 0x18,  0, NV04_PFIFO_CACHE1_ENGINE },
  44         { 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_PULL1 },
  45         {}
  46 };
  47
  48 /*******************************************************************************
  49  * FIFO channel objects
  50  ******************************************************************************/
  51
  52 static int
  53 nv10_fifo_chan_ctor(struct nvkm_object *parent,
  54                     struct nvkm_object *engine,
  55                     struct nvkm_oclass *oclass, void *data, u32 size,
  56                     struct nvkm_object **pobject)
  57 {
  58         union {
  59                 struct nv03_channel_dma_v0 v0;
  60         } *args = data;
  61         struct nv04_fifo_priv *priv = (void *)engine;
  62         struct nv04_fifo_chan *chan;
  63         int ret;
  64
  65         nv_ioctl(parent, "create channel dma size %d\n", size);
  66         if (nvif_unpack(args->v0, 0, 0, false)) {
  67                 nv_ioctl(parent, "create channel dma vers %d pushbuf %08x "
  68                                  "offset %016llx\n", args->v0.version,
  69                          args->v0.pushbuf, args->v0.offset);
  70         } else
  71                 return ret;
  72
  73         ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
  74                                        0x10000, args->v0.pushbuf,
  75                                        (1ULL << NVDEV_ENGINE_DMAOBJ) |
  76                                        (1ULL << NVDEV_ENGINE_SW) |
  77                                        (1ULL << NVDEV_ENGINE_GR), &chan);
  78         *pobject = nv_object(chan);
  79         if (ret)
  80                 return ret;
  81
  82         args->v0.chid = chan->base.chid;
  83
  84         nv_parent(chan)->object_attach = nv04_fifo_object_attach;
  85         nv_parent(chan)->object_detach = nv04_fifo_object_detach;
  86         nv_parent(chan)->context_attach = nv04_fifo_context_attach;
  87         chan->ramfc = chan->base.chid * 32;
  88
  89         nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset);
  90         nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset);
  91         nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
  92         nv_wo32(priv->ramfc, chan->ramfc + 0x14,
  93                              NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
  94                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
  95 #ifdef __BIG_ENDIAN
  96                              NV_PFIFO_CACHE1_BIG_ENDIAN |
  97 #endif
  98                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
  99         return 0;
 100 }
 101
 102 static struct nvkm_ofuncs
 103 nv10_fifo_ofuncs = {
 104         .ctor = nv10_fifo_chan_ctor,
 105         .dtor = nv04_fifo_chan_dtor,
 106         .init = nv04_fifo_chan_init,
 107         .fini = nv04_fifo_chan_fini,
 108         .map  = _nvkm_fifo_channel_map,
 109         .rd32 = _nvkm_fifo_channel_rd32,
 110         .wr32 = _nvkm_fifo_channel_wr32,
 111         .ntfy = _nvkm_fifo_channel_ntfy
 112 };
 113
 114 static struct nvkm_oclass
 115 nv10_fifo_sclass[] = {
 116         { NV10_CHANNEL_DMA, &nv10_fifo_ofuncs },
 117         {}
 118 };
 119
 120 /*******************************************************************************
 121  * FIFO context - basically just the instmem reserved for the channel
 122  ******************************************************************************/
 123
 124 static struct nvkm_oclass
 125 nv10_fifo_cclass = {
 126         .handle = NV_ENGCTX(FIFO, 0x10),
 127         .ofuncs = &(struct nvkm_ofuncs) {
 128                 .ctor = nv04_fifo_context_ctor,
 129                 .dtor = _nvkm_fifo_context_dtor,
 130                 .init = _nvkm_fifo_context_init,
 131                 .fini = _nvkm_fifo_context_fini,
 132                 .rd32 = _nvkm_fifo_context_rd32,
 133                 .wr32 = _nvkm_fifo_context_wr32,
 134         },
 135 };
 136
 137 /*******************************************************************************
 138  * PFIFO engine
 139  ******************************************************************************/
 140
 141 static int
 142 nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 143                struct nvkm_oclass *oclass, void *data, u32 size,
 144                struct nvkm_object **pobject)
 145 {
 146         struct nv04_instmem_priv *imem = nv04_instmem(parent);
 147         struct nv04_fifo_priv *priv;
 148         int ret;
 149
 150         ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv);
 151         *pobject = nv_object(priv);
 152         if (ret)
 153                 return ret;
 154
 155         nvkm_ramht_ref(imem->ramht, &priv->ramht);
 156         nvkm_gpuobj_ref(imem->ramro, &priv->ramro);
 157         nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc);
 158
 159         nv_subdev(priv)->unit = 0x00000100;
 160         nv_subdev(priv)->intr = nv04_fifo_intr;
 161         nv_engine(priv)->cclass = &nv10_fifo_cclass;
 162         nv_engine(priv)->sclass = nv10_fifo_sclass;
 163         priv->base.pause = nv04_fifo_pause;
 164         priv->base.start = nv04_fifo_start;
 165         priv->ramfc_desc = nv10_ramfc;
 166         return 0;
 167 }
 168
 169 struct nvkm_oclass *
 170 nv10_fifo_oclass = &(struct nvkm_oclass) {
 171         .handle = NV_ENGINE(FIFO, 0x10),
 172         .ofuncs = &(struct nvkm_ofuncs) {
 173                 .ctor = nv10_fifo_ctor,
 174                 .dtor = nv04_fifo_dtor,
 175                 .init = nv04_fifo_init,
 176                 .fini = _nvkm_fifo_fini,
 177         },
 178 };