kernel/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "changk104.h"
  25
  26 #include <core/client.h>
  27 #include <core/gpuobj.h>
  28 #include <subdev/fb.h>
  29 #include <subdev/mmu.h>
  30 #include <subdev/timer.h>
  31
  32 #include <nvif/class.h>
  33 #include <nvif/unpack.h>
  34
  35 static int
  36 gk104_fifo_gpfifo_kick(struct gk104_fifo_chan *chan)
  37 {
  38         struct gk104_fifo *fifo = chan->fifo;
  39         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
  40         struct nvkm_device *device = subdev->device;
  41         struct nvkm_client *client = chan->base.object.client;
  42         int ret = 0;
  43
  44         mutex_lock(&subdev->mutex);
  45         nvkm_wr32(device, 0x002634, chan->base.chid);
  46         if (nvkm_msec(device, 2000,
  47                 if (!(nvkm_rd32(device, 0x002634) & 0x00100000))
  48                         break;
  49         ) < 0) {
  50                 nvkm_error(subdev, "channel %d [%s] kick timeout\n",
  51                            chan->base.chid, client->name);
  52                 ret = -ETIMEDOUT;
  53         }
  54         mutex_unlock(&subdev->mutex);
  55         return ret;
  56 }
  57
  58 static u32
  59 gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
  60 {
  61         switch (engine->subdev.index) {
  62         case NVKM_ENGINE_SW    :
  63         case NVKM_ENGINE_CE0   :
  64         case NVKM_ENGINE_CE1   :
  65         case NVKM_ENGINE_CE2   : return 0x0000;
  66         case NVKM_ENGINE_GR    : return 0x0210;
  67         case NVKM_ENGINE_MSPDEC: return 0x0250;
  68         case NVKM_ENGINE_MSPPP : return 0x0260;
  69         case NVKM_ENGINE_MSVLD : return 0x0270;
  70         default:
  71                 WARN_ON(1);
  72                 return 0;
  73         }
  74 }
  75
  76 static int
  77 gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
  78                               struct nvkm_engine *engine, bool suspend)
  79 {
  80         const u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
  81         struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
  82         struct nvkm_gpuobj *inst = chan->base.inst;
  83         int ret;
  84
  85         ret = gk104_fifo_gpfifo_kick(chan);
  86         if (ret && suspend)
  87                 return ret;
  88
  89         if (offset) {
  90                 nvkm_kmap(inst);
  91                 nvkm_wo32(inst, offset + 0x00, 0x00000000);
  92                 nvkm_wo32(inst, offset + 0x04, 0x00000000);
  93                 nvkm_done(inst);
  94         }
  95
  96         return ret;
  97 }
  98
  99 static int
 100 gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
 101                               struct nvkm_engine *engine)
 102 {
 103         const u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
 104         struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
 105         struct nvkm_gpuobj *inst = chan->base.inst;
 106
 107         if (offset) {
 108                 u64 addr = chan->engn[engine->subdev.index].vma.offset;
 109                 nvkm_kmap(inst);
 110                 nvkm_wo32(inst, offset + 0x00, lower_32_bits(addr) | 4);
 111                 nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr));
 112                 nvkm_done(inst);
 113         }
 114
 115         return 0;
 116 }
 117
 118 static void
 119 gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base,
 120                               struct nvkm_engine *engine)
 121 {
 122         struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
 123         nvkm_gpuobj_unmap(&chan->engn[engine->subdev.index].vma);
 124         nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst);
 125 }
 126
 127 static int
 128 gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base,
 129                               struct nvkm_engine *engine,
 130                               struct nvkm_object *object)
 131 {
 132         struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
 133         int engn = engine->subdev.index;
 134         int ret;
 135
 136         if (!gk104_fifo_gpfifo_engine_addr(engine))
 137                 return 0;
 138
 139         ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst);
 140         if (ret)
 141                 return ret;
 142
 143         return nvkm_gpuobj_map(chan->engn[engn].inst, chan->vm,
 144                                NV_MEM_ACCESS_RW, &chan->engn[engn].vma);
 145 }
 146
 147 static void
 148 gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *base)
 149 {
 150         struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
 151         struct gk104_fifo *fifo = chan->fifo;
 152         struct nvkm_device *device = fifo->base.engine.subdev.device;
 153         u32 coff = chan->base.chid * 8;
 154
 155         if (!list_empty(&chan->head)) {
 156                 list_del_init(&chan->head);
 157                 nvkm_mask(device, 0x800004 + coff, 0x00000800, 0x00000800);
 158                 gk104_fifo_runlist_update(fifo, chan->engine);
 159         }
 160
 161         nvkm_wr32(device, 0x800000 + coff, 0x00000000);
 162 }
 163
 164 static void
 165 gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base)
 166 {
 167         struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
 168         struct gk104_fifo *fifo = chan->fifo;
 169         struct nvkm_device *device = fifo->base.engine.subdev.device;
 170         u32 addr = chan->base.inst->addr >> 12;
 171         u32 coff = chan->base.chid * 8;
 172
 173         nvkm_mask(device, 0x800004 + coff, 0x000f0000, chan->engine << 16);
 174         nvkm_wr32(device, 0x800000 + coff, 0x80000000 | addr);
 175
 176         if (list_empty(&chan->head) && !chan->killed) {
 177                 list_add_tail(&chan->head, &fifo->engine[chan->engine].chan);
 178                 nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400);
 179                 gk104_fifo_runlist_update(fifo, chan->engine);
 180                 nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400);
 181         }
 182 }
 183
 184 static void *
 185 gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base)
 186 {
 187         struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
 188         nvkm_vm_ref(NULL, &chan->vm, chan->pgd);
 189         nvkm_gpuobj_del(&chan->pgd);
 190         return chan;
 191 }
 192
 193 static const struct nvkm_fifo_chan_func
 194 gk104_fifo_gpfifo_func = {
 195         .dtor = gk104_fifo_gpfifo_dtor,
 196         .init = gk104_fifo_gpfifo_init,
 197         .fini = gk104_fifo_gpfifo_fini,
 198         .ntfy = g84_fifo_chan_ntfy,
 199         .engine_ctor = gk104_fifo_gpfifo_engine_ctor,
 200         .engine_dtor = gk104_fifo_gpfifo_engine_dtor,
 201         .engine_init = gk104_fifo_gpfifo_engine_init,
 202         .engine_fini = gk104_fifo_gpfifo_engine_fini,
 203 };
 204
 205 int
 206 gk104_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
 207                       void *data, u32 size, struct nvkm_object **pobject)
 208 {
 209         union {
 210                 struct kepler_channel_gpfifo_a_v0 v0;
 211         } *args = data;
 212         struct gk104_fifo *fifo = gk104_fifo(base);
 213         struct nvkm_device *device = fifo->base.engine.subdev.device;
 214         struct nvkm_object *parent = oclass->parent;
 215         struct gk104_fifo_chan *chan;
 216         u64 usermem, ioffset, ilength;
 217         u32 engines;
 218         int ret, i;
 219
 220         nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
 221         if (nvif_unpack(args->v0, 0, 0, false)) {
 222                 nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx "
 223                                    "ioffset %016llx ilength %08x engine %08x\n",
 224                            args->v0.version, args->v0.vm, args->v0.ioffset,
 225                            args->v0.ilength, args->v0.engine);
 226         } else
 227                 return ret;
 228
 229         /* determine which downstream engines are present */
 230         for (i = 0, engines = 0; i < ARRAY_SIZE(fifo->engine); i++) {
 231                 u64 subdevs = gk104_fifo_engine_subdev(i);
 232                 if (!nvkm_device_engine(device, __ffs64(subdevs)))
 233                         continue;
 234                 engines |= (1 << i);
 235         }
 236
 237         /* if this is an engine mask query, we're done */
 238         if (!args->v0.engine) {
 239                 args->v0.engine = engines;
 240                 return nvkm_object_new(oclass, NULL, 0, pobject);
 241         }
 242
 243         /* check that we support a requested engine - note that the user
 244          * argument is a mask in order to allow the user to request (for
 245          * example) *any* copy engine, but doesn't matter which.
 246          */
 247         args->v0.engine &= engines;
 248         if (!args->v0.engine) {
 249                 nvif_ioctl(parent, "no supported engine\n");
 250                 return -ENODEV;
 251         }
 252
 253         /* allocate the channel */
 254         if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
 255                 return -ENOMEM;
 256         *pobject = &chan->base.object;
 257         chan->fifo = fifo;
 258         chan->engine = __ffs(args->v0.engine);
 259         INIT_LIST_HEAD(&chan->head);
 260
 261         ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base,
 262                                   0x1000, 0x1000, true, args->v0.vm, 0,
 263                                   gk104_fifo_engine_subdev(chan->engine),
 264                                   1, fifo->user.bar.offset, 0x200,
 265                                   oclass, &chan->base);
 266         if (ret)
 267                 return ret;
 268
 269         args->v0.chid = chan->base.chid;
 270
 271         /* page directory */
 272         ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &chan->pgd);
 273         if (ret)
 274                 return ret;
 275
 276         nvkm_kmap(chan->base.inst);
 277         nvkm_wo32(chan->base.inst, 0x0200, lower_32_bits(chan->pgd->addr));
 278         nvkm_wo32(chan->base.inst, 0x0204, upper_32_bits(chan->pgd->addr));
 279         nvkm_wo32(chan->base.inst, 0x0208, 0xffffffff);
 280         nvkm_wo32(chan->base.inst, 0x020c, 0x000000ff);
 281         nvkm_done(chan->base.inst);
 282
 283         ret = nvkm_vm_ref(chan->base.vm, &chan->vm, chan->pgd);
 284         if (ret)
 285                 return ret;
 286
 287         /* clear channel control registers */
 288         usermem = chan->base.chid * 0x200;
 289         ioffset = args->v0.ioffset;
 290         ilength = order_base_2(args->v0.ilength / 8);
 291
 292         nvkm_kmap(fifo->user.mem);
 293         for (i = 0; i < 0x200; i += 4)
 294                 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
 295         nvkm_done(fifo->user.mem);
 296         usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
 297
 298         /* RAMFC */
 299         nvkm_kmap(chan->base.inst);
 300         nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem));
 301         nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem));
 302         nvkm_wo32(chan->base.inst, 0x10, 0x0000face);
 303         nvkm_wo32(chan->base.inst, 0x30, 0xfffff902);
 304         nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset));
 305         nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) |
 306                                          (ilength << 16));
 307         nvkm_wo32(chan->base.inst, 0x84, 0x20400000);
 308         nvkm_wo32(chan->base.inst, 0x94, 0x30000001);
 309         nvkm_wo32(chan->base.inst, 0x9c, 0x00000100);
 310         nvkm_wo32(chan->base.inst, 0xac, 0x0000001f);
 311         nvkm_wo32(chan->base.inst, 0xe8, chan->base.chid);
 312         nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000);
 313         nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */
 314         nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */
 315         nvkm_done(chan->base.inst);
 316         return 0;
 317 }
 318
 319 const struct nvkm_fifo_chan_oclass
 320 gk104_fifo_gpfifo_oclass = {
 321         .base.oclass = KEPLER_CHANNEL_GPFIFO_A,
 322         .base.minver = 0,
 323         .base.maxver = 0,
 324         .ctor = gk104_fifo_gpfifo_new,
 325 };