kernel/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "changf100.h"
  25
  26 #include <core/client.h>
  27 #include <core/gpuobj.h>
  28 #include <subdev/fb.h>
  29 #include <subdev/timer.h>
  30
  31 #include <nvif/class.h>
  32 #include <nvif/unpack.h>
  33
  34 static u32
  35 gf100_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
  36 {
  37         switch (engine->subdev.index) {
  38         case NVKM_ENGINE_SW    : return 0;
  39         case NVKM_ENGINE_GR    : return 0x0210;
  40         case NVKM_ENGINE_CE0   : return 0x0230;
  41         case NVKM_ENGINE_CE1   : return 0x0240;
  42         case NVKM_ENGINE_MSPDEC: return 0x0250;
  43         case NVKM_ENGINE_MSPPP : return 0x0260;
  44         case NVKM_ENGINE_MSVLD : return 0x0270;
  45         default:
  46                 WARN_ON(1);
  47                 return 0;
  48         }
  49 }
  50
  51 static int
  52 gf100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
  53                               struct nvkm_engine *engine, bool suspend)
  54 {
  55         const u32 offset = gf100_fifo_gpfifo_engine_addr(engine);
  56         struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
  57         struct nvkm_subdev *subdev = &chan->fifo->base.engine.subdev;
  58         struct nvkm_device *device = subdev->device;
  59         struct nvkm_gpuobj *inst = chan->base.inst;
  60         int ret = 0;
  61
  62         mutex_lock(&subdev->mutex);
  63         nvkm_wr32(device, 0x002634, chan->base.chid);
  64         if (nvkm_msec(device, 2000,
  65                 if (nvkm_rd32(device, 0x002634) == chan->base.chid)
  66                         break;
  67         ) < 0) {
  68                 nvkm_error(subdev, "channel %d [%s] kick timeout\n",
  69                            chan->base.chid, chan->base.object.client->name);
  70                 ret = -ETIMEDOUT;
  71         }
  72         mutex_unlock(&subdev->mutex);
  73
  74         if (ret && suspend)
  75                 return ret;
  76
  77         if (offset) {
  78                 nvkm_kmap(inst);
  79                 nvkm_wo32(inst, offset + 0x00, 0x00000000);
  80                 nvkm_wo32(inst, offset + 0x04, 0x00000000);
  81                 nvkm_done(inst);
  82         }
  83
  84         return ret;
  85 }
  86
  87 static int
  88 gf100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
  89                               struct nvkm_engine *engine)
  90 {
  91         const u32 offset = gf100_fifo_gpfifo_engine_addr(engine);
  92         struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
  93         struct nvkm_gpuobj *inst = chan->base.inst;
  94
  95         if (offset) {
  96                 u64 addr = chan->engn[engine->subdev.index].vma.offset;
  97                 nvkm_kmap(inst);
  98                 nvkm_wo32(inst, offset + 0x00, lower_32_bits(addr) | 4);
  99                 nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr));
 100                 nvkm_done(inst);
 101         }
 102
 103         return 0;
 104 }
 105
 106 static void
 107 gf100_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base,
 108                               struct nvkm_engine *engine)
 109 {
 110         struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
 111         nvkm_gpuobj_unmap(&chan->engn[engine->subdev.index].vma);
 112         nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst);
 113 }
 114
 115 static int
 116 gf100_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base,
 117                               struct nvkm_engine *engine,
 118                               struct nvkm_object *object)
 119 {
 120         struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
 121         int engn = engine->subdev.index;
 122         int ret;
 123
 124         if (!gf100_fifo_gpfifo_engine_addr(engine))
 125                 return 0;
 126
 127         ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst);
 128         if (ret)
 129                 return ret;
 130
 131         return nvkm_gpuobj_map(chan->engn[engn].inst, chan->vm,
 132                                NV_MEM_ACCESS_RW, &chan->engn[engn].vma);
 133 }
 134
 135 static void
 136 gf100_fifo_gpfifo_fini(struct nvkm_fifo_chan *base)
 137 {
 138         struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
 139         struct gf100_fifo *fifo = chan->fifo;
 140         struct nvkm_device *device = fifo->base.engine.subdev.device;
 141         u32 coff = chan->base.chid * 8;
 142
 143         if (!list_empty(&chan->head) && !chan->killed) {
 144                 list_del_init(&chan->head);
 145                 nvkm_mask(device, 0x003004 + coff, 0x00000001, 0x00000000);
 146                 gf100_fifo_runlist_update(fifo);
 147         }
 148
 149         gf100_fifo_intr_engine(fifo);
 150
 151         nvkm_wr32(device, 0x003000 + coff, 0x00000000);
 152 }
 153
 154 static void
 155 gf100_fifo_gpfifo_init(struct nvkm_fifo_chan *base)
 156 {
 157         struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
 158         struct gf100_fifo *fifo = chan->fifo;
 159         struct nvkm_device *device = fifo->base.engine.subdev.device;
 160         u32 addr = chan->base.inst->addr >> 12;
 161         u32 coff = chan->base.chid * 8;
 162
 163         nvkm_wr32(device, 0x003000 + coff, 0xc0000000 | addr);
 164
 165         if (list_empty(&chan->head) && !chan->killed) {
 166                 list_add_tail(&chan->head, &fifo->chan);
 167                 nvkm_wr32(device, 0x003004 + coff, 0x001f0001);
 168                 gf100_fifo_runlist_update(fifo);
 169         }
 170 }
 171
 172 static void *
 173 gf100_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base)
 174 {
 175         struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
 176         nvkm_vm_ref(NULL, &chan->vm, chan->pgd);
 177         nvkm_gpuobj_del(&chan->pgd);
 178         return chan;
 179 }
 180
 181 static const struct nvkm_fifo_chan_func
 182 gf100_fifo_gpfifo_func = {
 183         .dtor = gf100_fifo_gpfifo_dtor,
 184         .init = gf100_fifo_gpfifo_init,
 185         .fini = gf100_fifo_gpfifo_fini,
 186         .ntfy = g84_fifo_chan_ntfy,
 187         .engine_ctor = gf100_fifo_gpfifo_engine_ctor,
 188         .engine_dtor = gf100_fifo_gpfifo_engine_dtor,
 189         .engine_init = gf100_fifo_gpfifo_engine_init,
 190         .engine_fini = gf100_fifo_gpfifo_engine_fini,
 191 };
 192
 193 static int
 194 gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
 195                       void *data, u32 size, struct nvkm_object **pobject)
 196 {
 197         union {
 198                 struct fermi_channel_gpfifo_v0 v0;
 199         } *args = data;
 200         struct gf100_fifo *fifo = gf100_fifo(base);
 201         struct nvkm_device *device = fifo->base.engine.subdev.device;
 202         struct nvkm_object *parent = oclass->parent;
 203         struct gf100_fifo_chan *chan;
 204         u64 usermem, ioffset, ilength;
 205         int ret, i;
 206
 207         nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
 208         if (nvif_unpack(args->v0, 0, 0, false)) {
 209                 nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx "
 210                                    "ioffset %016llx ilength %08x\n",
 211                            args->v0.version, args->v0.vm, args->v0.ioffset,
 212                            args->v0.ilength);
 213         } else
 214                 return ret;
 215
 216         /* allocate channel */
 217         if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
 218                 return -ENOMEM;
 219         *pobject = &chan->base.object;
 220         chan->fifo = fifo;
 221         INIT_LIST_HEAD(&chan->head);
 222
 223         ret = nvkm_fifo_chan_ctor(&gf100_fifo_gpfifo_func, &fifo->base,
 224                                   0x1000, 0x1000, true, args->v0.vm, 0,
 225                                   (1ULL << NVKM_ENGINE_CE0) |
 226                                   (1ULL << NVKM_ENGINE_CE1) |
 227                                   (1ULL << NVKM_ENGINE_GR) |
 228                                   (1ULL << NVKM_ENGINE_MSPDEC) |
 229                                   (1ULL << NVKM_ENGINE_MSPPP) |
 230                                   (1ULL << NVKM_ENGINE_MSVLD) |
 231                                   (1ULL << NVKM_ENGINE_SW),
 232                                   1, fifo->user.bar.offset, 0x1000,
 233                                   oclass, &chan->base);
 234         if (ret)
 235                 return ret;
 236
 237         args->v0.chid = chan->base.chid;
 238
 239         /* page directory */
 240         ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &chan->pgd);
 241         if (ret)
 242                 return ret;
 243
 244         nvkm_kmap(chan->base.inst);
 245         nvkm_wo32(chan->base.inst, 0x0200, lower_32_bits(chan->pgd->addr));
 246         nvkm_wo32(chan->base.inst, 0x0204, upper_32_bits(chan->pgd->addr));
 247         nvkm_wo32(chan->base.inst, 0x0208, 0xffffffff);
 248         nvkm_wo32(chan->base.inst, 0x020c, 0x000000ff);
 249         nvkm_done(chan->base.inst);
 250
 251         ret = nvkm_vm_ref(chan->base.vm, &chan->vm, chan->pgd);
 252         if (ret)
 253                 return ret;
 254
 255         /* clear channel control registers */
 256
 257         usermem = chan->base.chid * 0x1000;
 258         ioffset = args->v0.ioffset;
 259         ilength = order_base_2(args->v0.ilength / 8);
 260
 261         nvkm_kmap(fifo->user.mem);
 262         for (i = 0; i < 0x1000; i += 4)
 263                 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
 264         nvkm_done(fifo->user.mem);
 265         usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
 266
 267         /* RAMFC */
 268         nvkm_kmap(chan->base.inst);
 269         nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem));
 270         nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem));
 271         nvkm_wo32(chan->base.inst, 0x10, 0x0000face);
 272         nvkm_wo32(chan->base.inst, 0x30, 0xfffff902);
 273         nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset));
 274         nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) |
 275                                          (ilength << 16));
 276         nvkm_wo32(chan->base.inst, 0x54, 0x00000002);
 277         nvkm_wo32(chan->base.inst, 0x84, 0x20400000);
 278         nvkm_wo32(chan->base.inst, 0x94, 0x30000001);
 279         nvkm_wo32(chan->base.inst, 0x9c, 0x00000100);
 280         nvkm_wo32(chan->base.inst, 0xa4, 0x1f1f1f1f);
 281         nvkm_wo32(chan->base.inst, 0xa8, 0x1f1f1f1f);
 282         nvkm_wo32(chan->base.inst, 0xac, 0x0000001f);
 283         nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000);
 284         nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */
 285         nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */
 286         nvkm_done(chan->base.inst);
 287         return 0;
 288 }
 289
 290 const struct nvkm_fifo_chan_oclass
 291 gf100_fifo_gpfifo_oclass = {
 292         .base.oclass = FERMI_CHANNEL_GPFIFO,
 293         .base.minver = 0,
 294         .base.maxver = 0,
 295         .ctor = gf100_fifo_gpfifo_new,
 296 };