kernel/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "channv04.h"
  25 #include "regsnv04.h"
  26
  27 #include <core/client.h>
  28 #include <core/ramht.h>
  29 #include <subdev/instmem.h>
  30
  31 #include <nvif/class.h>
  32 #include <nvif/unpack.h>
  33
  34 void
  35 nv04_fifo_dma_object_dtor(struct nvkm_fifo_chan *base, int cookie)
  36 {
  37         struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
  38         struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;
  39
  40         mutex_lock(&chan->fifo->base.engine.subdev.mutex);
  41         nvkm_ramht_remove(imem->ramht, cookie);
  42         mutex_unlock(&chan->fifo->base.engine.subdev.mutex);
  43 }
  44
  45 static int
  46 nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base,
  47                           struct nvkm_object *object)
  48 {
  49         struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
  50         struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;
  51         u32 context = 0x80000000 | chan->base.chid << 24;
  52         u32 handle  = object->handle;
  53         int hash;
  54
  55         switch (object->engine->subdev.index) {
  56         case NVKM_ENGINE_DMAOBJ:
  57         case NVKM_ENGINE_SW    : context |= 0x00000000; break;
  58         case NVKM_ENGINE_GR    : context |= 0x00010000; break;
  59         case NVKM_ENGINE_MPEG  : context |= 0x00020000; break;
  60         default:
  61                 WARN_ON(1);
  62                 return -EINVAL;
  63         }
  64
  65         mutex_lock(&chan->fifo->base.engine.subdev.mutex);
  66         hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4,
  67                                  handle, context);
  68         mutex_unlock(&chan->fifo->base.engine.subdev.mutex);
  69         return hash;
  70 }
  71
  72 void
  73 nv04_fifo_dma_fini(struct nvkm_fifo_chan *base)
  74 {
  75         struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
  76         struct nv04_fifo *fifo = chan->fifo;
  77         struct nvkm_device *device = fifo->base.engine.subdev.device;
  78         struct nvkm_memory *fctx = device->imem->ramfc;
  79         const struct nv04_fifo_ramfc *c;
  80         unsigned long flags;
  81         u32 mask = fifo->base.nr - 1;
  82         u32 data = chan->ramfc;
  83         u32 chid;
  84
  85         /* prevent fifo context switches */
  86         spin_lock_irqsave(&fifo->base.lock, flags);
  87         nvkm_wr32(device, NV03_PFIFO_CACHES, 0);
  88
  89         /* if this channel is active, replace it with a null context */
  90         chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & mask;
  91         if (chid == chan->base.chid) {
  92                 nvkm_mask(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0);
  93                 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0);
  94                 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0);
  95
  96                 c = fifo->ramfc;
  97                 do {
  98                         u32 rm = ((1ULL << c->bits) - 1) << c->regs;
  99                         u32 cm = ((1ULL << c->bits) - 1) << c->ctxs;
 100                         u32 rv = (nvkm_rd32(device, c->regp) &  rm) >> c->regs;
 101                         u32 cv = (nvkm_ro32(fctx, c->ctxp + data) & ~cm);
 102                         nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs));
 103                 } while ((++c)->bits);
 104
 105                 c = fifo->ramfc;
 106                 do {
 107                         nvkm_wr32(device, c->regp, 0x00000000);
 108                 } while ((++c)->bits);
 109
 110                 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, 0);
 111                 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUT, 0);
 112                 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, mask);
 113                 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
 114                 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
 115         }
 116
 117         /* restore normal operation, after disabling dma mode */
 118         nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0);
 119         nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
 120         spin_unlock_irqrestore(&fifo->base.lock, flags);
 121 }
 122
 123 void
 124 nv04_fifo_dma_init(struct nvkm_fifo_chan *base)
 125 {
 126         struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
 127         struct nv04_fifo *fifo = chan->fifo;
 128         struct nvkm_device *device = fifo->base.engine.subdev.device;
 129         u32 mask = 1 << chan->base.chid;
 130         unsigned long flags;
 131         spin_lock_irqsave(&fifo->base.lock, flags);
 132         nvkm_mask(device, NV04_PFIFO_MODE, mask, mask);
 133         spin_unlock_irqrestore(&fifo->base.lock, flags);
 134 }
 135
 136 void *
 137 nv04_fifo_dma_dtor(struct nvkm_fifo_chan *base)
 138 {
 139         struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
 140         struct nv04_fifo *fifo = chan->fifo;
 141         struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem;
 142         const struct nv04_fifo_ramfc *c = fifo->ramfc;
 143
 144         nvkm_kmap(imem->ramfc);
 145         do {
 146                 nvkm_wo32(imem->ramfc, chan->ramfc + c->ctxp, 0x00000000);
 147         } while ((++c)->bits);
 148         nvkm_done(imem->ramfc);
 149         return chan;
 150 }
 151
 152 const struct nvkm_fifo_chan_func
 153 nv04_fifo_dma_func = {
 154         .dtor = nv04_fifo_dma_dtor,
 155         .init = nv04_fifo_dma_init,
 156         .fini = nv04_fifo_dma_fini,
 157         .object_ctor = nv04_fifo_dma_object_ctor,
 158         .object_dtor = nv04_fifo_dma_object_dtor,
 159 };
 160
 161 static int
 162 nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
 163                   void *data, u32 size, struct nvkm_object **pobject)
 164 {
 165         struct nvkm_object *parent = oclass->parent;
 166         union {
 167                 struct nv03_channel_dma_v0 v0;
 168         } *args = data;
 169         struct nv04_fifo *fifo = nv04_fifo(base);
 170         struct nv04_fifo_chan *chan = NULL;
 171         struct nvkm_device *device = fifo->base.engine.subdev.device;
 172         struct nvkm_instmem *imem = device->imem;
 173         int ret;
 174
 175         nvif_ioctl(parent, "create channel dma size %d\n", size);
 176         if (nvif_unpack(args->v0, 0, 0, false)) {
 177                 nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx "
 178                                    "offset %08x\n", args->v0.version,
 179                            args->v0.pushbuf, args->v0.offset);
 180                 if (!args->v0.pushbuf)
 181                         return -EINVAL;
 182         } else
 183                 return ret;
 184
 185         if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
 186                 return -ENOMEM;
 187         *pobject = &chan->base.object;
 188
 189         ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base,
 190                                   0x1000, 0x1000, false, 0, args->v0.pushbuf,
 191                                   (1ULL << NVKM_ENGINE_DMAOBJ) |
 192                                   (1ULL << NVKM_ENGINE_GR) |
 193                                   (1ULL << NVKM_ENGINE_SW),
 194                                   0, 0x800000, 0x10000, oclass, &chan->base);
 195         chan->fifo = fifo;
 196         if (ret)
 197                 return ret;
 198
 199         args->v0.chid = chan->base.chid;
 200         chan->ramfc = chan->base.chid * 32;
 201
 202         nvkm_kmap(imem->ramfc);
 203         nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
 204         nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
 205         nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.push->addr >> 4);
 206         nvkm_wo32(imem->ramfc, chan->ramfc + 0x10,
 207                                NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 208                                NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 209 #ifdef __BIG_ENDIAN
 210                                NV_PFIFO_CACHE1_BIG_ENDIAN |
 211 #endif
 212                                NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
 213         nvkm_done(imem->ramfc);
 214         return 0;
 215 }
 216
 217 const struct nvkm_fifo_chan_oclass
 218 nv04_fifo_dma_oclass = {
 219         .base.oclass = NV03_CHANNEL_DMA,
 220         .base.minver = 0,
 221         .base.maxver = 0,
 222         .ctor = nv04_fifo_dma_new,
 223 };