kernel/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #define gf100_dmaobj(p) container_of((p), struct gf100_dmaobj, base)
  25 #include "user.h"
  26
  27 #include <core/client.h>
  28 #include <core/gpuobj.h>
  29 #include <subdev/fb.h>
  30
  31 #include <nvif/class.h>
  32 #include <nvif/unpack.h>
  33
  34 struct gf100_dmaobj {
  35         struct nvkm_dmaobj base;
  36         u32 flags0;
  37         u32 flags5;
  38 };
  39
  40 static int
  41 gf100_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent,
  42                   int align, struct nvkm_gpuobj **pgpuobj)
  43 {
  44         struct gf100_dmaobj *dmaobj = gf100_dmaobj(base);
  45         struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
  46         int ret;
  47
  48         ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj);
  49         if (ret == 0) {
  50                 nvkm_kmap(*pgpuobj);
  51                 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
  52                 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
  53                 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
  54                 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
  55                                           upper_32_bits(dmaobj->base.start));
  56                 nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
  57                 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);
  58                 nvkm_done(*pgpuobj);
  59         }
  60
  61         return ret;
  62 }
  63
  64 static const struct nvkm_dmaobj_func
  65 gf100_dmaobj_func = {
  66         .bind = gf100_dmaobj_bind,
  67 };
  68
  69 int
  70 gf100_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
  71                  void *data, u32 size, struct nvkm_dmaobj **pdmaobj)
  72 {
  73         union {
  74                 struct gf100_dma_v0 v0;
  75         } *args;
  76         struct nvkm_object *parent = oclass->parent;
  77         struct gf100_dmaobj *dmaobj;
  78         u32 kind, user, unkn;
  79         int ret;
  80
  81         if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
  82                 return -ENOMEM;
  83         *pdmaobj = &dmaobj->base;
  84
  85         ret = nvkm_dmaobj_ctor(&gf100_dmaobj_func, dma, oclass,
  86                                &data, &size, &dmaobj->base);
  87         if (ret)
  88                 return ret;
  89
  90         args = data;
  91
  92         nvif_ioctl(parent, "create gf100 dma size %d\n", size);
  93         if (nvif_unpack(args->v0, 0, 0, false)) {
  94                 nvif_ioctl(parent,
  95                            "create gf100 dma vers %d priv %d kind %02x\n",
  96                            args->v0.version, args->v0.priv, args->v0.kind);
  97                 kind = args->v0.kind;
  98                 user = args->v0.priv;
  99                 unkn = 0;
 100         } else
 101         if (size == 0) {
 102                 if (dmaobj->base.target != NV_MEM_TARGET_VM) {
 103                         kind = GF100_DMA_V0_KIND_PITCH;
 104                         user = GF100_DMA_V0_PRIV_US;
 105                         unkn = 2;
 106                 } else {
 107                         kind = GF100_DMA_V0_KIND_VM;
 108                         user = GF100_DMA_V0_PRIV_VM;
 109                         unkn = 0;
 110                 }
 111         } else
 112                 return ret;
 113
 114         if (user > 2)
 115                 return -EINVAL;
 116         dmaobj->flags0 |= (kind << 22) | (user << 20) | oclass->base.oclass;
 117         dmaobj->flags5 |= (unkn << 16);
 118
 119         switch (dmaobj->base.target) {
 120         case NV_MEM_TARGET_VM:
 121                 dmaobj->flags0 |= 0x00000000;
 122                 break;
 123         case NV_MEM_TARGET_VRAM:
 124                 dmaobj->flags0 |= 0x00010000;
 125                 break;
 126         case NV_MEM_TARGET_PCI:
 127                 dmaobj->flags0 |= 0x00020000;
 128                 break;
 129         case NV_MEM_TARGET_PCI_NOSNOOP:
 130                 dmaobj->flags0 |= 0x00030000;
 131                 break;
 132         default:
 133                 return -EINVAL;
 134         }
 135
 136         switch (dmaobj->base.access) {
 137         case NV_MEM_ACCESS_VM:
 138                 break;
 139         case NV_MEM_ACCESS_RO:
 140                 dmaobj->flags0 |= 0x00040000;
 141                 break;
 142         case NV_MEM_ACCESS_WO:
 143         case NV_MEM_ACCESS_RW:
 144                 dmaobj->flags0 |= 0x00080000;
 145                 break;
 146         }
 147
 148         return 0;
 149 }