kernel/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv50.h"
  25 #include "outpdp.h"
  26
  27 #include <nvif/class.h>
  28
  29 /*******************************************************************************
  30  * EVO master channel object
  31  ******************************************************************************/
  32
  33 const struct nv50_disp_mthd_list
  34 g94_disp_core_mthd_sor = {
  35         .mthd = 0x0040,
  36         .addr = 0x000008,
  37         .data = {
  38                 { 0x0600, 0x610794 },
  39                 {}
  40         }
  41 };
  42
  43 const struct nv50_disp_mthd_chan
  44 g94_disp_core_mthd_chan = {
  45         .name = "Core",
  46         .addr = 0x000000,
  47         .data = {
  48                 { "Global", 1, &nv50_disp_core_mthd_base },
  49                 {    "DAC", 3, &g84_disp_core_mthd_dac  },
  50                 {    "SOR", 4, &g94_disp_core_mthd_sor  },
  51                 {   "PIOR", 3, &nv50_disp_core_mthd_pior },
  52                 {   "HEAD", 2, &g84_disp_core_mthd_head },
  53                 {}
  54         }
  55 };
  56
  57 /*******************************************************************************
  58  * Base display object
  59  ******************************************************************************/
  60
  61 static struct nvkm_oclass
  62 g94_disp_sclass[] = {
  63         { GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
  64         { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
  65         { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
  66         { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
  67         { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
  68         {}
  69 };
  70
  71 static struct nvkm_oclass
  72 g94_disp_main_oclass[] = {
  73         { GT206_DISP, &nv50_disp_main_ofuncs },
  74         {}
  75 };
  76
  77 /*******************************************************************************
  78  * Display engine implementation
  79  ******************************************************************************/
  80
  81 static int
  82 g94_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  83               struct nvkm_oclass *oclass, void *data, u32 size,
  84               struct nvkm_object **pobject)
  85 {
  86         struct nv50_disp_priv *priv;
  87         int ret;
  88
  89         ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
  90                                "display", &priv);
  91         *pobject = nv_object(priv);
  92         if (ret)
  93                 return ret;
  94
  95         ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
  96         if (ret)
  97                 return ret;
  98
  99         nv_engine(priv)->sclass = g94_disp_main_oclass;
 100         nv_engine(priv)->cclass = &nv50_disp_cclass;
 101         nv_subdev(priv)->intr = nv50_disp_intr;
 102         INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
 103         priv->sclass = g94_disp_sclass;
 104         priv->head.nr = 2;
 105         priv->dac.nr = 3;
 106         priv->sor.nr = 4;
 107         priv->pior.nr = 3;
 108         priv->dac.power = nv50_dac_power;
 109         priv->dac.sense = nv50_dac_sense;
 110         priv->sor.power = nv50_sor_power;
 111         priv->sor.hdmi = g84_hdmi_ctrl;
 112         priv->pior.power = nv50_pior_power;
 113         return 0;
 114 }
 115
 116 struct nvkm_oclass *
 117 g94_disp_outp_sclass[] = {
 118         &nv50_pior_dp_impl.base.base,
 119         &g94_sor_dp_impl.base.base,
 120         NULL
 121 };
 122
 123 struct nvkm_oclass *
 124 g94_disp_oclass = &(struct nv50_disp_impl) {
 125         .base.base.handle = NV_ENGINE(DISP, 0x88),
 126         .base.base.ofuncs = &(struct nvkm_ofuncs) {
 127                 .ctor = g94_disp_ctor,
 128                 .dtor = _nvkm_disp_dtor,
 129                 .init = _nvkm_disp_init,
 130                 .fini = _nvkm_disp_fini,
 131         },
 132         .base.vblank = &nv50_disp_vblank_func,
 133         .base.outp =  g94_disp_outp_sclass,
 134         .mthd.core = &g94_disp_core_mthd_chan,
 135         .mthd.base = &g84_disp_base_mthd_chan,
 136         .mthd.ovly = &g84_disp_ovly_mthd_chan,
 137         .mthd.prev = 0x000004,
 138         .head.scanoutpos = nv50_disp_main_scanoutpos,
 139 }.base.base;