kernel/drivers/gpu/drm/msm/edp/edp.xml.h

   1 #ifndef EDP_XML
   2 #define EDP_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
  12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
  13 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
  14 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
  15 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
  16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
  17 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
  18 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
  19 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
  20 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
  21 - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
  22
  23 Copyright (C) 2013-2014 by the following authors:
  24 - Rob Clark <robdclark@gmail.com> (robclark)
  25
  26 Permission is hereby granted, free of charge, to any person obtaining
  27 a copy of this software and associated documentation files (the
  28 "Software"), to deal in the Software without restriction, including
  29 without limitation the rights to use, copy, modify, merge, publish,
  30 distribute, sublicense, and/or sell copies of the Software, and to
  31 permit persons to whom the Software is furnished to do so, subject to
  32 the following conditions:
  33
  34 The above copyright notice and this permission notice (including the
  35 next paragraph) shall be included in all copies or substantial
  36 portions of the Software.
  37
  38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  40 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  41 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  42 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  43 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  44 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  45 */
  46
  47
  48 enum edp_color_depth {
  49         EDP_6BIT = 0,
  50         EDP_8BIT = 1,
  51         EDP_10BIT = 2,
  52         EDP_12BIT = 3,
  53         EDP_16BIT = 4,
  54 };
  55
  56 enum edp_component_format {
  57         EDP_RGB = 0,
  58         EDP_YUV422 = 1,
  59         EDP_YUV444 = 2,
  60 };
  61
  62 #define REG_EDP_MAINLINK_CTRL                                   0x00000004
  63 #define EDP_MAINLINK_CTRL_ENABLE                                0x00000001
  64 #define EDP_MAINLINK_CTRL_RESET                                 0x00000002
  65
  66 #define REG_EDP_STATE_CTRL                                      0x00000008
  67 #define EDP_STATE_CTRL_TRAIN_PATTERN_1                          0x00000001
  68 #define EDP_STATE_CTRL_TRAIN_PATTERN_2                          0x00000002
  69 #define EDP_STATE_CTRL_TRAIN_PATTERN_3                          0x00000004
  70 #define EDP_STATE_CTRL_SYMBOL_ERR_RATE_MEAS                     0x00000008
  71 #define EDP_STATE_CTRL_PRBS7                                    0x00000010
  72 #define EDP_STATE_CTRL_CUSTOM_80_BIT_PATTERN                    0x00000020
  73 #define EDP_STATE_CTRL_SEND_VIDEO                               0x00000040
  74 #define EDP_STATE_CTRL_PUSH_IDLE                                0x00000080
  75
  76 #define REG_EDP_CONFIGURATION_CTRL                              0x0000000c
  77 #define EDP_CONFIGURATION_CTRL_SYNC_CLK                         0x00000001
  78 #define EDP_CONFIGURATION_CTRL_STATIC_MVID                      0x00000002
  79 #define EDP_CONFIGURATION_CTRL_PROGRESSIVE                      0x00000004
  80 #define EDP_CONFIGURATION_CTRL_LANES__MASK                      0x00000030
  81 #define EDP_CONFIGURATION_CTRL_LANES__SHIFT                     4
  82 static inline uint32_t EDP_CONFIGURATION_CTRL_LANES(uint32_t val)
  83 {
  84         return ((val) << EDP_CONFIGURATION_CTRL_LANES__SHIFT) & EDP_CONFIGURATION_CTRL_LANES__MASK;
  85 }
  86 #define EDP_CONFIGURATION_CTRL_ENHANCED_FRAMING                 0x00000040
  87 #define EDP_CONFIGURATION_CTRL_COLOR__MASK                      0x00000100
  88 #define EDP_CONFIGURATION_CTRL_COLOR__SHIFT                     8
  89 static inline uint32_t EDP_CONFIGURATION_CTRL_COLOR(enum edp_color_depth val)
  90 {
  91         return ((val) << EDP_CONFIGURATION_CTRL_COLOR__SHIFT) & EDP_CONFIGURATION_CTRL_COLOR__MASK;
  92 }
  93
  94 #define REG_EDP_SOFTWARE_MVID                                   0x00000014
  95
  96 #define REG_EDP_SOFTWARE_NVID                                   0x00000018
  97
  98 #define REG_EDP_TOTAL_HOR_VER                                   0x0000001c
  99 #define EDP_TOTAL_HOR_VER_HORIZ__MASK                           0x0000ffff
 100 #define EDP_TOTAL_HOR_VER_HORIZ__SHIFT                          0
 101 static inline uint32_t EDP_TOTAL_HOR_VER_HORIZ(uint32_t val)
 102 {
 103         return ((val) << EDP_TOTAL_HOR_VER_HORIZ__SHIFT) & EDP_TOTAL_HOR_VER_HORIZ__MASK;
 104 }
 105 #define EDP_TOTAL_HOR_VER_VERT__MASK                            0xffff0000
 106 #define EDP_TOTAL_HOR_VER_VERT__SHIFT                           16
 107 static inline uint32_t EDP_TOTAL_HOR_VER_VERT(uint32_t val)
 108 {
 109         return ((val) << EDP_TOTAL_HOR_VER_VERT__SHIFT) & EDP_TOTAL_HOR_VER_VERT__MASK;
 110 }
 111
 112 #define REG_EDP_START_HOR_VER_FROM_SYNC                         0x00000020
 113 #define EDP_START_HOR_VER_FROM_SYNC_HORIZ__MASK                 0x0000ffff
 114 #define EDP_START_HOR_VER_FROM_SYNC_HORIZ__SHIFT                0
 115 static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_HORIZ(uint32_t val)
 116 {
 117         return ((val) << EDP_START_HOR_VER_FROM_SYNC_HORIZ__SHIFT) & EDP_START_HOR_VER_FROM_SYNC_HORIZ__MASK;
 118 }
 119 #define EDP_START_HOR_VER_FROM_SYNC_VERT__MASK                  0xffff0000
 120 #define EDP_START_HOR_VER_FROM_SYNC_VERT__SHIFT                 16
 121 static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_VERT(uint32_t val)
 122 {
 123         return ((val) << EDP_START_HOR_VER_FROM_SYNC_VERT__SHIFT) & EDP_START_HOR_VER_FROM_SYNC_VERT__MASK;
 124 }
 125
 126 #define REG_EDP_HSYNC_VSYNC_WIDTH_POLARITY                      0x00000024
 127 #define EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__MASK              0x00007fff
 128 #define EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__SHIFT             0
 129 static inline uint32_t EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ(uint32_t val)
 130 {
 131         return ((val) << EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__SHIFT) & EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__MASK;
 132 }
 133 #define EDP_HSYNC_VSYNC_WIDTH_POLARITY_NHSYNC                   0x00008000
 134 #define EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__MASK               0x7fff0000
 135 #define EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__SHIFT              16
 136 static inline uint32_t EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT(uint32_t val)
 137 {
 138         return ((val) << EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__SHIFT) & EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__MASK;
 139 }
 140 #define EDP_HSYNC_VSYNC_WIDTH_POLARITY_NVSYNC                   0x80000000
 141
 142 #define REG_EDP_ACTIVE_HOR_VER                                  0x00000028
 143 #define EDP_ACTIVE_HOR_VER_HORIZ__MASK                          0x0000ffff
 144 #define EDP_ACTIVE_HOR_VER_HORIZ__SHIFT                         0
 145 static inline uint32_t EDP_ACTIVE_HOR_VER_HORIZ(uint32_t val)
 146 {
 147         return ((val) << EDP_ACTIVE_HOR_VER_HORIZ__SHIFT) & EDP_ACTIVE_HOR_VER_HORIZ__MASK;
 148 }
 149 #define EDP_ACTIVE_HOR_VER_VERT__MASK                           0xffff0000
 150 #define EDP_ACTIVE_HOR_VER_VERT__SHIFT                          16
 151 static inline uint32_t EDP_ACTIVE_HOR_VER_VERT(uint32_t val)
 152 {
 153         return ((val) << EDP_ACTIVE_HOR_VER_VERT__SHIFT) & EDP_ACTIVE_HOR_VER_VERT__MASK;
 154 }
 155
 156 #define REG_EDP_MISC1_MISC0                                     0x0000002c
 157 #define EDP_MISC1_MISC0_MISC0__MASK                             0x000000ff
 158 #define EDP_MISC1_MISC0_MISC0__SHIFT                            0
 159 static inline uint32_t EDP_MISC1_MISC0_MISC0(uint32_t val)
 160 {
 161         return ((val) << EDP_MISC1_MISC0_MISC0__SHIFT) & EDP_MISC1_MISC0_MISC0__MASK;
 162 }
 163 #define EDP_MISC1_MISC0_SYNC                                    0x00000001
 164 #define EDP_MISC1_MISC0_COMPONENT_FORMAT__MASK                  0x00000006
 165 #define EDP_MISC1_MISC0_COMPONENT_FORMAT__SHIFT                 1
 166 static inline uint32_t EDP_MISC1_MISC0_COMPONENT_FORMAT(enum edp_component_format val)
 167 {
 168         return ((val) << EDP_MISC1_MISC0_COMPONENT_FORMAT__SHIFT) & EDP_MISC1_MISC0_COMPONENT_FORMAT__MASK;
 169 }
 170 #define EDP_MISC1_MISC0_CEA                                     0x00000008
 171 #define EDP_MISC1_MISC0_BT709_5                                 0x00000010
 172 #define EDP_MISC1_MISC0_COLOR__MASK                             0x000000e0
 173 #define EDP_MISC1_MISC0_COLOR__SHIFT                            5
 174 static inline uint32_t EDP_MISC1_MISC0_COLOR(enum edp_color_depth val)
 175 {
 176         return ((val) << EDP_MISC1_MISC0_COLOR__SHIFT) & EDP_MISC1_MISC0_COLOR__MASK;
 177 }
 178 #define EDP_MISC1_MISC0_MISC1__MASK                             0x0000ff00
 179 #define EDP_MISC1_MISC0_MISC1__SHIFT                            8
 180 static inline uint32_t EDP_MISC1_MISC0_MISC1(uint32_t val)
 181 {
 182         return ((val) << EDP_MISC1_MISC0_MISC1__SHIFT) & EDP_MISC1_MISC0_MISC1__MASK;
 183 }
 184 #define EDP_MISC1_MISC0_INTERLACED_ODD                          0x00000100
 185 #define EDP_MISC1_MISC0_STEREO__MASK                            0x00000600
 186 #define EDP_MISC1_MISC0_STEREO__SHIFT                           9
 187 static inline uint32_t EDP_MISC1_MISC0_STEREO(uint32_t val)
 188 {
 189         return ((val) << EDP_MISC1_MISC0_STEREO__SHIFT) & EDP_MISC1_MISC0_STEREO__MASK;
 190 }
 191
 192 #define REG_EDP_PHY_CTRL                                        0x00000074
 193 #define EDP_PHY_CTRL_SW_RESET_PLL                               0x00000001
 194 #define EDP_PHY_CTRL_SW_RESET                                   0x00000004
 195
 196 #define REG_EDP_MAINLINK_READY                                  0x00000084
 197 #define EDP_MAINLINK_READY_TRAIN_PATTERN_1_READY                0x00000008
 198 #define EDP_MAINLINK_READY_TRAIN_PATTERN_2_READY                0x00000010
 199 #define EDP_MAINLINK_READY_TRAIN_PATTERN_3_READY                0x00000020
 200
 201 #define REG_EDP_AUX_CTRL                                        0x00000300
 202 #define EDP_AUX_CTRL_ENABLE                                     0x00000001
 203 #define EDP_AUX_CTRL_RESET                                      0x00000002
 204
 205 #define REG_EDP_INTERRUPT_REG_1                                 0x00000308
 206 #define EDP_INTERRUPT_REG_1_HPD                                 0x00000001
 207 #define EDP_INTERRUPT_REG_1_HPD_ACK                             0x00000002
 208 #define EDP_INTERRUPT_REG_1_HPD_EN                              0x00000004
 209 #define EDP_INTERRUPT_REG_1_AUX_I2C_DONE                        0x00000008
 210 #define EDP_INTERRUPT_REG_1_AUX_I2C_DONE_ACK                    0x00000010
 211 #define EDP_INTERRUPT_REG_1_AUX_I2C_DONE_EN                     0x00000020
 212 #define EDP_INTERRUPT_REG_1_WRONG_ADDR                          0x00000040
 213 #define EDP_INTERRUPT_REG_1_WRONG_ADDR_ACK                      0x00000080
 214 #define EDP_INTERRUPT_REG_1_WRONG_ADDR_EN                       0x00000100
 215 #define EDP_INTERRUPT_REG_1_TIMEOUT                             0x00000200
 216 #define EDP_INTERRUPT_REG_1_TIMEOUT_ACK                         0x00000400
 217 #define EDP_INTERRUPT_REG_1_TIMEOUT_EN                          0x00000800
 218 #define EDP_INTERRUPT_REG_1_NACK_DEFER                          0x00001000
 219 #define EDP_INTERRUPT_REG_1_NACK_DEFER_ACK                      0x00002000
 220 #define EDP_INTERRUPT_REG_1_NACK_DEFER_EN                       0x00004000
 221 #define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT                      0x00008000
 222 #define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT_ACK                  0x00010000
 223 #define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT_EN                   0x00020000
 224 #define EDP_INTERRUPT_REG_1_I2C_NACK                            0x00040000
 225 #define EDP_INTERRUPT_REG_1_I2C_NACK_ACK                        0x00080000
 226 #define EDP_INTERRUPT_REG_1_I2C_NACK_EN                         0x00100000
 227 #define EDP_INTERRUPT_REG_1_I2C_DEFER                           0x00200000
 228 #define EDP_INTERRUPT_REG_1_I2C_DEFER_ACK                       0x00400000
 229 #define EDP_INTERRUPT_REG_1_I2C_DEFER_EN                        0x00800000
 230 #define EDP_INTERRUPT_REG_1_PLL_UNLOCK                          0x01000000
 231 #define EDP_INTERRUPT_REG_1_PLL_UNLOCK_ACK                      0x02000000
 232 #define EDP_INTERRUPT_REG_1_PLL_UNLOCK_EN                       0x04000000
 233 #define EDP_INTERRUPT_REG_1_AUX_ERROR                           0x08000000
 234 #define EDP_INTERRUPT_REG_1_AUX_ERROR_ACK                       0x10000000
 235 #define EDP_INTERRUPT_REG_1_AUX_ERROR_EN                        0x20000000
 236
 237 #define REG_EDP_INTERRUPT_REG_2                                 0x0000030c
 238 #define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO                     0x00000001
 239 #define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO_ACK                 0x00000002
 240 #define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO_EN                  0x00000004
 241 #define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT                  0x00000008
 242 #define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT_ACK              0x00000010
 243 #define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT_EN               0x00000020
 244 #define EDP_INTERRUPT_REG_2_FRAME_END                           0x00000200
 245 #define EDP_INTERRUPT_REG_2_FRAME_END_ACK                       0x00000080
 246 #define EDP_INTERRUPT_REG_2_FRAME_END_EN                        0x00000100
 247 #define EDP_INTERRUPT_REG_2_CRC_UPDATED                         0x00000200
 248 #define EDP_INTERRUPT_REG_2_CRC_UPDATED_ACK                     0x00000400
 249 #define EDP_INTERRUPT_REG_2_CRC_UPDATED_EN                      0x00000800
 250
 251 #define REG_EDP_INTERRUPT_TRANS_NUM                             0x00000310
 252
 253 #define REG_EDP_AUX_DATA                                        0x00000314
 254 #define EDP_AUX_DATA_READ                                       0x00000001
 255 #define EDP_AUX_DATA_DATA__MASK                                 0x0000ff00
 256 #define EDP_AUX_DATA_DATA__SHIFT                                8
 257 static inline uint32_t EDP_AUX_DATA_DATA(uint32_t val)
 258 {
 259         return ((val) << EDP_AUX_DATA_DATA__SHIFT) & EDP_AUX_DATA_DATA__MASK;
 260 }
 261 #define EDP_AUX_DATA_INDEX__MASK                                0x00ff0000
 262 #define EDP_AUX_DATA_INDEX__SHIFT                               16
 263 static inline uint32_t EDP_AUX_DATA_INDEX(uint32_t val)
 264 {
 265         return ((val) << EDP_AUX_DATA_INDEX__SHIFT) & EDP_AUX_DATA_INDEX__MASK;
 266 }
 267 #define EDP_AUX_DATA_INDEX_WRITE                                0x80000000
 268
 269 #define REG_EDP_AUX_TRANS_CTRL                                  0x00000318
 270 #define EDP_AUX_TRANS_CTRL_I2C                                  0x00000100
 271 #define EDP_AUX_TRANS_CTRL_GO                                   0x00000200
 272
 273 #define REG_EDP_AUX_STATUS                                      0x00000324
 274
 275 static inline uint32_t REG_EDP_PHY_LN(uint32_t i0) { return 0x00000400 + 0x40*i0; }
 276
 277 static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + 0x40*i0; }
 278
 279 #define REG_EDP_PHY_GLB_VM_CFG0                                 0x00000510
 280
 281 #define REG_EDP_PHY_GLB_VM_CFG1                                 0x00000514
 282
 283 #define REG_EDP_PHY_GLB_MISC9                                   0x00000518
 284
 285 #define REG_EDP_PHY_GLB_CFG                                     0x00000528
 286
 287 #define REG_EDP_PHY_GLB_PD_CTL                                  0x0000052c
 288
 289 #define REG_EDP_PHY_GLB_PHY_STATUS                              0x00000598
 290
 291
 292 #endif /* EDP_XML */