4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /usr2/hali/local/envytools/envytools/rnndb/dsi/dsi.xml ( 18681 bytes, from 2015-03-04 23:08:31)
12 - /usr2/hali/local/envytools/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-01-28 21:43:22)
14 Copyright (C) 2013-2015 by the following authors:
15 - Rob Clark <robdclark@gmail.com> (robclark)
17 Permission is hereby granted, free of charge, to any person obtaining
18 a copy of this software and associated documentation files (the
19 "Software"), to deal in the Software without restriction, including
20 without limitation the rights to use, copy, modify, merge, publish,
21 distribute, sublicense, and/or sell copies of the Software, and to
22 permit persons to whom the Software is furnished to do so, subject to
23 the following conditions:
25 The above copyright notice and this permission notice (including the
26 next paragraph) shall be included in all copies or substantial
27 portions of the Software.
29 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
30 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
31 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
32 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
33 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
34 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
35 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
39 enum dsi_traffic_mode {
40 NON_BURST_SYNCH_PULSE = 0,
41 NON_BURST_SYNCH_EVENT = 1,
45 enum dsi_vid_dst_format {
46 VID_DST_FORMAT_RGB565 = 0,
47 VID_DST_FORMAT_RGB666 = 1,
48 VID_DST_FORMAT_RGB666_LOOSE = 2,
49 VID_DST_FORMAT_RGB888 = 3,
61 enum dsi_cmd_trigger {
70 enum dsi_cmd_dst_format {
71 CMD_DST_FORMAT_RGB111 = 0,
72 CMD_DST_FORMAT_RGB332 = 3,
73 CMD_DST_FORMAT_RGB444 = 4,
74 CMD_DST_FORMAT_RGB565 = 6,
75 CMD_DST_FORMAT_RGB666 = 7,
76 CMD_DST_FORMAT_RGB888 = 8,
90 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
91 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
92 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
93 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
94 #define DSI_IRQ_VIDEO_DONE 0x00010000
95 #define DSI_IRQ_MASK_VIDEO_DONE 0x00020000
96 #define DSI_IRQ_BTA_DONE 0x00100000
97 #define DSI_IRQ_MASK_BTA_DONE 0x00200000
98 #define DSI_IRQ_ERROR 0x01000000
99 #define DSI_IRQ_MASK_ERROR 0x02000000
100 #define REG_DSI_6G_HW_VERSION 0x00000000
101 #define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000
102 #define DSI_6G_HW_VERSION_MAJOR__SHIFT 28
103 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val)
105 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK;
107 #define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000
108 #define DSI_6G_HW_VERSION_MINOR__SHIFT 16
109 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val)
111 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK;
113 #define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff
114 #define DSI_6G_HW_VERSION_STEP__SHIFT 0
115 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)
117 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK;
120 #define REG_DSI_CTRL 0x00000000
121 #define DSI_CTRL_ENABLE 0x00000001
122 #define DSI_CTRL_VID_MODE_EN 0x00000002
123 #define DSI_CTRL_CMD_MODE_EN 0x00000004
124 #define DSI_CTRL_LANE0 0x00000010
125 #define DSI_CTRL_LANE1 0x00000020
126 #define DSI_CTRL_LANE2 0x00000040
127 #define DSI_CTRL_LANE3 0x00000080
128 #define DSI_CTRL_CLK_EN 0x00000100
129 #define DSI_CTRL_ECC_CHECK 0x00100000
130 #define DSI_CTRL_CRC_CHECK 0x01000000
132 #define REG_DSI_STATUS0 0x00000004
133 #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001
134 #define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002
135 #define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004
136 #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008
137 #define DSI_STATUS0_DSI_BUSY 0x00000010
138 #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000
140 #define REG_DSI_FIFO_STATUS 0x00000008
141 #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080
143 #define REG_DSI_VID_CFG0 0x0000000c
144 #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
145 #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0
146 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)
148 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK;
150 #define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030
151 #define DSI_VID_CFG0_DST_FORMAT__SHIFT 4
152 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val)
154 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK;
156 #define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300
157 #define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8
158 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)
160 return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK;
162 #define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000
163 #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000
164 #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000
165 #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000
166 #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000
167 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000
169 #define REG_DSI_VID_CFG1 0x0000001c
170 #define DSI_VID_CFG1_R_SEL 0x00000001
171 #define DSI_VID_CFG1_G_SEL 0x00000010
172 #define DSI_VID_CFG1_B_SEL 0x00000100
173 #define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000
174 #define DSI_VID_CFG1_RGB_SWAP__SHIFT 12
175 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)
177 return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK;
180 #define REG_DSI_ACTIVE_H 0x00000020
181 #define DSI_ACTIVE_H_START__MASK 0x00000fff
182 #define DSI_ACTIVE_H_START__SHIFT 0
183 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)
185 return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK;
187 #define DSI_ACTIVE_H_END__MASK 0x0fff0000
188 #define DSI_ACTIVE_H_END__SHIFT 16
189 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)
191 return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK;
194 #define REG_DSI_ACTIVE_V 0x00000024
195 #define DSI_ACTIVE_V_START__MASK 0x00000fff
196 #define DSI_ACTIVE_V_START__SHIFT 0
197 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)
199 return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK;
201 #define DSI_ACTIVE_V_END__MASK 0x0fff0000
202 #define DSI_ACTIVE_V_END__SHIFT 16
203 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)
205 return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK;
208 #define REG_DSI_TOTAL 0x00000028
209 #define DSI_TOTAL_H_TOTAL__MASK 0x00000fff
210 #define DSI_TOTAL_H_TOTAL__SHIFT 0
211 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)
213 return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK;
215 #define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000
216 #define DSI_TOTAL_V_TOTAL__SHIFT 16
217 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val)
219 return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK;
222 #define REG_DSI_ACTIVE_HSYNC 0x0000002c
223 #define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff
224 #define DSI_ACTIVE_HSYNC_START__SHIFT 0
225 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val)
227 return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK;
229 #define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000
230 #define DSI_ACTIVE_HSYNC_END__SHIFT 16
231 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val)
233 return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK;
236 #define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030
237 #define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff
238 #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0
239 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val)
241 return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK;
243 #define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000
244 #define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16
245 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val)
247 return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK;
250 #define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034
251 #define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff
252 #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0
253 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val)
255 return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK;
257 #define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000
258 #define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16
259 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val)
261 return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK;
264 #define REG_DSI_CMD_DMA_CTRL 0x00000038
265 #define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000
266 #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000
267 #define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000
269 #define REG_DSI_CMD_CFG0 0x0000003c
270 #define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f
271 #define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0
272 static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val)
274 return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK;
276 #define DSI_CMD_CFG0_R_SEL 0x00000010
277 #define DSI_CMD_CFG0_G_SEL 0x00000100
278 #define DSI_CMD_CFG0_B_SEL 0x00001000
279 #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000
280 #define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20
281 static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val)
283 return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK;
285 #define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000
286 #define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16
287 static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val)
289 return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK;
292 #define REG_DSI_CMD_CFG1 0x00000040
293 #define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff
294 #define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0
295 static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val)
297 return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK;
299 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00
300 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8
301 static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)
303 return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK;
305 #define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000
307 #define REG_DSI_DMA_BASE 0x00000044
309 #define REG_DSI_DMA_LEN 0x00000048
311 #define REG_DSI_CMD_MDP_STREAM_CTRL 0x00000054
312 #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK 0x0000003f
313 #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT 0
314 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val)
316 return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK;
318 #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
319 #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT 8
320 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val)
322 return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK;
324 #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK 0xffff0000
325 #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT 16
326 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val)
328 return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK;
331 #define REG_DSI_CMD_MDP_STREAM_TOTAL 0x00000058
332 #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK 0x00000fff
333 #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT 0
334 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val)
336 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK;
338 #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK 0x0fff0000
339 #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT 16
340 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val)
342 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK;
345 #define REG_DSI_ACK_ERR_STATUS 0x00000064
347 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }
349 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }
351 #define REG_DSI_TRIG_CTRL 0x00000080
352 #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007
353 #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0
354 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val)
356 return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK;
358 #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070
359 #define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4
360 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val)
362 return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK;
364 #define DSI_TRIG_CTRL_STREAM__MASK 0x00000300
365 #define DSI_TRIG_CTRL_STREAM__SHIFT 8
366 static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)
368 return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK;
370 #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000
371 #define DSI_TRIG_CTRL_TE 0x80000000
373 #define REG_DSI_TRIG_DMA 0x0000008c
375 #define REG_DSI_DLN0_PHY_ERR 0x000000b0
377 #define REG_DSI_TIMEOUT_STATUS 0x000000bc
379 #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0
380 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f
381 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0
382 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val)
384 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK;
386 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00
387 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8
388 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
390 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK;
393 #define REG_DSI_EOT_PACKET_CTRL 0x000000c8
394 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
395 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
397 #define REG_DSI_LANE_SWAP_CTRL 0x000000ac
398 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007
399 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0
400 static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
402 return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK;
405 #define REG_DSI_ERR_INT_MASK0 0x00000108
407 #define REG_DSI_INTR_CTRL 0x0000010c
409 #define REG_DSI_RESET 0x00000114
411 #define REG_DSI_CLK_CTRL 0x00000118
412 #define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001
413 #define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002
414 #define DSI_CLK_CTRL_PCLK_ON 0x00000004
415 #define DSI_CLK_CTRL_DSICLK_ON 0x00000008
416 #define DSI_CLK_CTRL_BYTECLK_ON 0x00000010
417 #define DSI_CLK_CTRL_ESCCLK_ON 0x00000020
418 #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200
420 #define REG_DSI_CLK_STATUS 0x0000011c
421 #define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000
423 #define REG_DSI_PHY_RESET 0x00000128
424 #define DSI_PHY_RESET_RESET 0x00000001
426 #define REG_DSI_RDBK_DATA_CTRL 0x000001d0
427 #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000
428 #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16
429 static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val)
431 return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK;
433 #define DSI_RDBK_DATA_CTRL_CLR 0x00000001
435 #define REG_DSI_VERSION 0x000001f0
436 #define DSI_VERSION_MAJOR__MASK 0xff000000
437 #define DSI_VERSION_MAJOR__SHIFT 24
438 static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
440 return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK;
443 #define REG_DSI_PHY_PLL_CTRL_0 0x00000200
444 #define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001
446 #define REG_DSI_PHY_PLL_CTRL_1 0x00000204
448 #define REG_DSI_PHY_PLL_CTRL_2 0x00000208
450 #define REG_DSI_PHY_PLL_CTRL_3 0x0000020c
452 #define REG_DSI_PHY_PLL_CTRL_4 0x00000210
454 #define REG_DSI_PHY_PLL_CTRL_5 0x00000214
456 #define REG_DSI_PHY_PLL_CTRL_6 0x00000218
458 #define REG_DSI_PHY_PLL_CTRL_7 0x0000021c
460 #define REG_DSI_PHY_PLL_CTRL_8 0x00000220
462 #define REG_DSI_PHY_PLL_CTRL_9 0x00000224
464 #define REG_DSI_PHY_PLL_CTRL_10 0x00000228
466 #define REG_DSI_PHY_PLL_CTRL_11 0x0000022c
468 #define REG_DSI_PHY_PLL_CTRL_12 0x00000230
470 #define REG_DSI_PHY_PLL_CTRL_13 0x00000234
472 #define REG_DSI_PHY_PLL_CTRL_14 0x00000238
474 #define REG_DSI_PHY_PLL_CTRL_15 0x0000023c
476 #define REG_DSI_PHY_PLL_CTRL_16 0x00000240
478 #define REG_DSI_PHY_PLL_CTRL_17 0x00000244
480 #define REG_DSI_PHY_PLL_CTRL_18 0x00000248
482 #define REG_DSI_PHY_PLL_CTRL_19 0x0000024c
484 #define REG_DSI_PHY_PLL_CTRL_20 0x00000250
486 #define REG_DSI_PHY_PLL_STATUS 0x00000280
487 #define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001
489 #define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258
491 #define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c
493 #define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260
495 #define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264
497 #define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268
499 #define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c
501 #define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270
503 #define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274
505 #define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278
507 #define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c
509 #define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280
511 #define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284
513 #define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288
515 #define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c
517 #define REG_DSI_8x60_PHY_CTRL_0 0x00000290
519 #define REG_DSI_8x60_PHY_CTRL_1 0x00000294
521 #define REG_DSI_8x60_PHY_CTRL_2 0x00000298
523 #define REG_DSI_8x60_PHY_CTRL_3 0x0000029c
525 #define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0
527 #define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4
529 #define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8
531 #define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac
533 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc
535 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0
537 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4
539 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8
541 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc
543 #define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0
545 #define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4
547 #define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc
548 #define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000
550 static inline uint32_t REG_DSI_8960_LN(uint32_t i0) { return 0x00000300 + 0x40*i0; }
552 static inline uint32_t REG_DSI_8960_LN_CFG_0(uint32_t i0) { return 0x00000300 + 0x40*i0; }
554 static inline uint32_t REG_DSI_8960_LN_CFG_1(uint32_t i0) { return 0x00000304 + 0x40*i0; }
556 static inline uint32_t REG_DSI_8960_LN_CFG_2(uint32_t i0) { return 0x00000308 + 0x40*i0; }
558 static inline uint32_t REG_DSI_8960_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000030c + 0x40*i0; }
560 static inline uint32_t REG_DSI_8960_LN_TEST_STR_0(uint32_t i0) { return 0x00000314 + 0x40*i0; }
562 static inline uint32_t REG_DSI_8960_LN_TEST_STR_1(uint32_t i0) { return 0x00000318 + 0x40*i0; }
564 #define REG_DSI_8960_PHY_LNCK_CFG_0 0x00000400
566 #define REG_DSI_8960_PHY_LNCK_CFG_1 0x00000404
568 #define REG_DSI_8960_PHY_LNCK_CFG_2 0x00000408
570 #define REG_DSI_8960_PHY_LNCK_TEST_DATAPATH 0x0000040c
572 #define REG_DSI_8960_PHY_LNCK_TEST_STR0 0x00000414
574 #define REG_DSI_8960_PHY_LNCK_TEST_STR1 0x00000418
576 #define REG_DSI_8960_PHY_TIMING_CTRL_0 0x00000440
578 #define REG_DSI_8960_PHY_TIMING_CTRL_1 0x00000444
580 #define REG_DSI_8960_PHY_TIMING_CTRL_2 0x00000448
582 #define REG_DSI_8960_PHY_TIMING_CTRL_3 0x0000044c
584 #define REG_DSI_8960_PHY_TIMING_CTRL_4 0x00000450
586 #define REG_DSI_8960_PHY_TIMING_CTRL_5 0x00000454
588 #define REG_DSI_8960_PHY_TIMING_CTRL_6 0x00000458
590 #define REG_DSI_8960_PHY_TIMING_CTRL_7 0x0000045c
592 #define REG_DSI_8960_PHY_TIMING_CTRL_8 0x00000460
594 #define REG_DSI_8960_PHY_TIMING_CTRL_9 0x00000464
596 #define REG_DSI_8960_PHY_TIMING_CTRL_10 0x00000468
598 #define REG_DSI_8960_PHY_TIMING_CTRL_11 0x0000046c
600 #define REG_DSI_8960_PHY_CTRL_0 0x00000470
602 #define REG_DSI_8960_PHY_CTRL_1 0x00000474
604 #define REG_DSI_8960_PHY_CTRL_2 0x00000478
606 #define REG_DSI_8960_PHY_CTRL_3 0x0000047c
608 #define REG_DSI_8960_PHY_STRENGTH_0 0x00000480
610 #define REG_DSI_8960_PHY_STRENGTH_1 0x00000484
612 #define REG_DSI_8960_PHY_STRENGTH_2 0x00000488
614 #define REG_DSI_8960_PHY_BIST_CTRL_0 0x0000048c
616 #define REG_DSI_8960_PHY_BIST_CTRL_1 0x00000490
618 #define REG_DSI_8960_PHY_BIST_CTRL_2 0x00000494
620 #define REG_DSI_8960_PHY_BIST_CTRL_3 0x00000498
622 #define REG_DSI_8960_PHY_BIST_CTRL_4 0x0000049c
624 #define REG_DSI_8960_PHY_LDO_CTRL 0x000004b0
626 #define REG_DSI_8960_PHY_REGULATOR_CTRL_0 0x00000500
628 #define REG_DSI_8960_PHY_REGULATOR_CTRL_1 0x00000504
630 #define REG_DSI_8960_PHY_REGULATOR_CTRL_2 0x00000508
632 #define REG_DSI_8960_PHY_REGULATOR_CTRL_3 0x0000050c
634 #define REG_DSI_8960_PHY_REGULATOR_CTRL_4 0x00000510
636 #define REG_DSI_8960_PHY_REGULATOR_CAL_PWR_CFG 0x00000518
638 #define REG_DSI_8960_PHY_CAL_HW_TRIGGER 0x00000528
640 #define REG_DSI_8960_PHY_CAL_SW_CFG_0 0x0000052c
642 #define REG_DSI_8960_PHY_CAL_SW_CFG_1 0x00000530
644 #define REG_DSI_8960_PHY_CAL_SW_CFG_2 0x00000534
646 #define REG_DSI_8960_PHY_CAL_HW_CFG_0 0x00000538
648 #define REG_DSI_8960_PHY_CAL_HW_CFG_1 0x0000053c
650 #define REG_DSI_8960_PHY_CAL_HW_CFG_2 0x00000540
652 #define REG_DSI_8960_PHY_CAL_HW_CFG_3 0x00000544
654 #define REG_DSI_8960_PHY_CAL_HW_CFG_4 0x00000548
656 #define REG_DSI_8960_PHY_CAL_STATUS 0x00000550
657 #define DSI_8960_PHY_CAL_STATUS_CAL_BUSY 0x00000010
659 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
661 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
663 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
665 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
667 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
669 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
671 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
673 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
675 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
677 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
679 #define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
681 #define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
683 #define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
685 #define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
687 #define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
689 #define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
691 #define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
693 #define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
695 #define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
697 #define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
698 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
699 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
700 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
702 return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
705 #define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
706 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
707 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
708 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
710 return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
713 #define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
714 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
715 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
716 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
718 return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
721 #define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
722 #define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
724 #define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
725 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
726 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
727 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
729 return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
732 #define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
733 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
734 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
735 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
737 return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
740 #define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
741 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
742 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
743 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
745 return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
748 #define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
749 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
750 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
751 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
753 return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
756 #define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
757 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
758 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
759 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
761 return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
764 #define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
765 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
766 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
767 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
769 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
771 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
772 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
773 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
775 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
778 #define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
779 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
780 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
781 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
783 return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
786 #define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
787 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
788 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
789 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
791 return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
794 #define REG_DSI_28nm_PHY_CTRL_0 0x00000170
796 #define REG_DSI_28nm_PHY_CTRL_1 0x00000174
798 #define REG_DSI_28nm_PHY_CTRL_2 0x00000178
800 #define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
802 #define REG_DSI_28nm_PHY_CTRL_4 0x00000180
804 #define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
806 #define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
808 #define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
810 #define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
812 #define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
814 #define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
816 #define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
818 #define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
820 #define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
822 #define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
824 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
826 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
828 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
830 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
832 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
834 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
836 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018