kernel/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h

   1 #ifndef ADRENO_PM4_XML
   2 #define ADRENO_PM4_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)
  12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2015-05-20 20:03:07)
  13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)
  14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10755 bytes, from 2015-09-14 20:46:55)
  15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14968 bytes, from 2015-05-20 20:12:27)
  16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  67771 bytes, from 2015-09-14 20:46:55)
  17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  63970 bytes, from 2015-09-14 20:50:12)
  18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)
  19
  20 Copyright (C) 2013-2015 by the following authors:
  21 - Rob Clark <robdclark@gmail.com> (robclark)
  22
  23 Permission is hereby granted, free of charge, to any person obtaining
  24 a copy of this software and associated documentation files (the
  25 "Software"), to deal in the Software without restriction, including
  26 without limitation the rights to use, copy, modify, merge, publish,
  27 distribute, sublicense, and/or sell copies of the Software, and to
  28 permit persons to whom the Software is furnished to do so, subject to
  29 the following conditions:
  30
  31 The above copyright notice and this permission notice (including the
  32 next paragraph) shall be included in all copies or substantial
  33 portions of the Software.
  34
  35 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  37 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  38 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  39 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  40 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  41 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  42 */
  43
  44
  45 enum vgt_event_type {
  46         VS_DEALLOC = 0,
  47         PS_DEALLOC = 1,
  48         VS_DONE_TS = 2,
  49         PS_DONE_TS = 3,
  50         CACHE_FLUSH_TS = 4,
  51         CONTEXT_DONE = 5,
  52         CACHE_FLUSH = 6,
  53         HLSQ_FLUSH = 7,
  54         VIZQUERY_START = 7,
  55         VIZQUERY_END = 8,
  56         SC_WAIT_WC = 9,
  57         RST_PIX_CNT = 13,
  58         RST_VTX_CNT = 14,
  59         TILE_FLUSH = 15,
  60         CACHE_FLUSH_AND_INV_TS_EVENT = 20,
  61         ZPASS_DONE = 21,
  62         CACHE_FLUSH_AND_INV_EVENT = 22,
  63         PERFCOUNTER_START = 23,
  64         PERFCOUNTER_STOP = 24,
  65         VS_FETCH_DONE = 27,
  66         FACENESS_FLUSH = 28,
  67 };
  68
  69 enum pc_di_primtype {
  70         DI_PT_NONE = 0,
  71         DI_PT_POINTLIST_PSIZE = 1,
  72         DI_PT_LINELIST = 2,
  73         DI_PT_LINESTRIP = 3,
  74         DI_PT_TRILIST = 4,
  75         DI_PT_TRIFAN = 5,
  76         DI_PT_TRISTRIP = 6,
  77         DI_PT_LINELOOP = 7,
  78         DI_PT_RECTLIST = 8,
  79         DI_PT_POINTLIST = 9,
  80         DI_PT_LINE_ADJ = 10,
  81         DI_PT_LINESTRIP_ADJ = 11,
  82         DI_PT_TRI_ADJ = 12,
  83         DI_PT_TRISTRIP_ADJ = 13,
  84         DI_PT_PATCHES = 34,
  85 };
  86
  87 enum pc_di_src_sel {
  88         DI_SRC_SEL_DMA = 0,
  89         DI_SRC_SEL_IMMEDIATE = 1,
  90         DI_SRC_SEL_AUTO_INDEX = 2,
  91         DI_SRC_SEL_RESERVED = 3,
  92 };
  93
  94 enum pc_di_index_size {
  95         INDEX_SIZE_IGN = 0,
  96         INDEX_SIZE_16_BIT = 0,
  97         INDEX_SIZE_32_BIT = 1,
  98         INDEX_SIZE_8_BIT = 2,
  99         INDEX_SIZE_INVALID = 0,
 100 };
 101
 102 enum pc_di_vis_cull_mode {
 103         IGNORE_VISIBILITY = 0,
 104         USE_VISIBILITY = 1,
 105 };
 106
 107 enum adreno_pm4_packet_type {
 108         CP_TYPE0_PKT = 0,
 109         CP_TYPE1_PKT = 0x40000000,
 110         CP_TYPE2_PKT = 0x80000000,
 111         CP_TYPE3_PKT = 0xc0000000,
 112 };
 113
 114 enum adreno_pm4_type3_packets {
 115         CP_ME_INIT = 72,
 116         CP_NOP = 16,
 117         CP_INDIRECT_BUFFER = 63,
 118         CP_INDIRECT_BUFFER_PFD = 55,
 119         CP_WAIT_FOR_IDLE = 38,
 120         CP_WAIT_REG_MEM = 60,
 121         CP_WAIT_REG_EQ = 82,
 122         CP_WAIT_REG_GTE = 83,
 123         CP_WAIT_UNTIL_READ = 92,
 124         CP_WAIT_IB_PFD_COMPLETE = 93,
 125         CP_REG_RMW = 33,
 126         CP_SET_BIN_DATA = 47,
 127         CP_REG_TO_MEM = 62,
 128         CP_MEM_WRITE = 61,
 129         CP_MEM_WRITE_CNTR = 79,
 130         CP_COND_EXEC = 68,
 131         CP_COND_WRITE = 69,
 132         CP_EVENT_WRITE = 70,
 133         CP_EVENT_WRITE_SHD = 88,
 134         CP_EVENT_WRITE_CFL = 89,
 135         CP_EVENT_WRITE_ZPD = 91,
 136         CP_RUN_OPENCL = 49,
 137         CP_DRAW_INDX = 34,
 138         CP_DRAW_INDX_2 = 54,
 139         CP_DRAW_INDX_BIN = 52,
 140         CP_DRAW_INDX_2_BIN = 53,
 141         CP_VIZ_QUERY = 35,
 142         CP_SET_STATE = 37,
 143         CP_SET_CONSTANT = 45,
 144         CP_IM_LOAD = 39,
 145         CP_IM_LOAD_IMMEDIATE = 43,
 146         CP_LOAD_CONSTANT_CONTEXT = 46,
 147         CP_INVALIDATE_STATE = 59,
 148         CP_SET_SHADER_BASES = 74,
 149         CP_SET_BIN_MASK = 80,
 150         CP_SET_BIN_SELECT = 81,
 151         CP_CONTEXT_UPDATE = 94,
 152         CP_INTERRUPT = 64,
 153         CP_IM_STORE = 44,
 154         CP_SET_DRAW_INIT_FLAGS = 75,
 155         CP_SET_PROTECTED_MODE = 95,
 156         CP_BOOTSTRAP_UCODE = 111,
 157         CP_LOAD_STATE = 48,
 158         CP_COND_INDIRECT_BUFFER_PFE = 58,
 159         CP_COND_INDIRECT_BUFFER_PFD = 50,
 160         CP_INDIRECT_BUFFER_PFE = 63,
 161         CP_SET_BIN = 76,
 162         CP_TEST_TWO_MEMS = 113,
 163         CP_REG_WR_NO_CTXT = 120,
 164         CP_RECORD_PFP_TIMESTAMP = 17,
 165         CP_WAIT_FOR_ME = 19,
 166         CP_SET_DRAW_STATE = 67,
 167         CP_DRAW_INDX_OFFSET = 56,
 168         CP_DRAW_INDIRECT = 40,
 169         CP_DRAW_INDX_INDIRECT = 41,
 170         CP_DRAW_AUTO = 36,
 171         CP_UNKNOWN_19 = 25,
 172         CP_UNKNOWN_1A = 26,
 173         CP_UNKNOWN_4E = 78,
 174         CP_WIDE_REG_WRITE = 116,
 175         IN_IB_PREFETCH_END = 23,
 176         IN_SUBBLK_PREFETCH = 31,
 177         IN_INSTR_PREFETCH = 32,
 178         IN_INSTR_MATCH = 71,
 179         IN_CONST_PREFETCH = 73,
 180         IN_INCR_UPDT_STATE = 85,
 181         IN_INCR_UPDT_CONST = 86,
 182         IN_INCR_UPDT_INSTR = 87,
 183 };
 184
 185 enum adreno_state_block {
 186         SB_VERT_TEX = 0,
 187         SB_VERT_MIPADDR = 1,
 188         SB_FRAG_TEX = 2,
 189         SB_FRAG_MIPADDR = 3,
 190         SB_VERT_SHADER = 4,
 191         SB_GEOM_SHADER = 5,
 192         SB_FRAG_SHADER = 6,
 193 };
 194
 195 enum adreno_state_type {
 196         ST_SHADER = 0,
 197         ST_CONSTANTS = 1,
 198 };
 199
 200 enum adreno_state_src {
 201         SS_DIRECT = 0,
 202         SS_INDIRECT = 4,
 203 };
 204
 205 enum a4xx_index_size {
 206         INDEX4_SIZE_8_BIT = 0,
 207         INDEX4_SIZE_16_BIT = 1,
 208         INDEX4_SIZE_32_BIT = 2,
 209 };
 210
 211 #define REG_CP_LOAD_STATE_0                                     0x00000000
 212 #define CP_LOAD_STATE_0_DST_OFF__MASK                           0x0000ffff
 213 #define CP_LOAD_STATE_0_DST_OFF__SHIFT                          0
 214 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
 215 {
 216         return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
 217 }
 218 #define CP_LOAD_STATE_0_STATE_SRC__MASK                         0x00070000
 219 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT                        16
 220 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
 221 {
 222         return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
 223 }
 224 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK                       0x00380000
 225 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT                      19
 226 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
 227 {
 228         return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
 229 }
 230 #define CP_LOAD_STATE_0_NUM_UNIT__MASK                          0x7fc00000
 231 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT                         22
 232 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
 233 {
 234         return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
 235 }
 236
 237 #define REG_CP_LOAD_STATE_1                                     0x00000001
 238 #define CP_LOAD_STATE_1_STATE_TYPE__MASK                        0x00000003
 239 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT                       0
 240 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
 241 {
 242         return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
 243 }
 244 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK                      0xfffffffc
 245 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT                     2
 246 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
 247 {
 248         return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
 249 }
 250
 251 #define REG_CP_DRAW_INDX_0                                      0x00000000
 252 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK                          0xffffffff
 253 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT                         0
 254 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
 255 {
 256         return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
 257 }
 258
 259 #define REG_CP_DRAW_INDX_1                                      0x00000001
 260 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK                          0x0000003f
 261 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT                         0
 262 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
 263 {
 264         return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
 265 }
 266 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK                      0x000000c0
 267 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT                     6
 268 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
 269 {
 270         return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
 271 }
 272 #define CP_DRAW_INDX_1_VIS_CULL__MASK                           0x00000600
 273 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT                          9
 274 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
 275 {
 276         return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
 277 }
 278 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK                         0x00000800
 279 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT                        11
 280 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
 281 {
 282         return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
 283 }
 284 #define CP_DRAW_INDX_1_NOT_EOP                                  0x00001000
 285 #define CP_DRAW_INDX_1_SMALL_INDEX                              0x00002000
 286 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE                0x00004000
 287 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK                      0xff000000
 288 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT                     24
 289 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
 290 {
 291         return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
 292 }
 293
 294 #define REG_CP_DRAW_INDX_2                                      0x00000002
 295 #define CP_DRAW_INDX_2_NUM_INDICES__MASK                        0xffffffff
 296 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT                       0
 297 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
 298 {
 299         return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
 300 }
 301
 302 #define REG_CP_DRAW_INDX_3                                      0x00000003
 303 #define CP_DRAW_INDX_3_INDX_BASE__MASK                          0xffffffff
 304 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT                         0
 305 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
 306 {
 307         return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
 308 }
 309
 310 #define REG_CP_DRAW_INDX_4                                      0x00000004
 311 #define CP_DRAW_INDX_4_INDX_SIZE__MASK                          0xffffffff
 312 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT                         0
 313 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
 314 {
 315         return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
 316 }
 317
 318 #define REG_CP_DRAW_INDX_2_0                                    0x00000000
 319 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK                        0xffffffff
 320 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT                       0
 321 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
 322 {
 323         return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
 324 }
 325
 326 #define REG_CP_DRAW_INDX_2_1                                    0x00000001
 327 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK                        0x0000003f
 328 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT                       0
 329 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
 330 {
 331         return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
 332 }
 333 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK                    0x000000c0
 334 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT                   6
 335 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
 336 {
 337         return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
 338 }
 339 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK                         0x00000600
 340 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT                        9
 341 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
 342 {
 343         return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
 344 }
 345 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK                       0x00000800
 346 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT                      11
 347 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
 348 {
 349         return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
 350 }
 351 #define CP_DRAW_INDX_2_1_NOT_EOP                                0x00001000
 352 #define CP_DRAW_INDX_2_1_SMALL_INDEX                            0x00002000
 353 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE              0x00004000
 354 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK                    0xff000000
 355 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT                   24
 356 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
 357 {
 358         return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
 359 }
 360
 361 #define REG_CP_DRAW_INDX_2_2                                    0x00000002
 362 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK                      0xffffffff
 363 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT                     0
 364 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
 365 {
 366         return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
 367 }
 368
 369 #define REG_CP_DRAW_INDX_OFFSET_0                               0x00000000
 370 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK                   0x0000003f
 371 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT                  0
 372 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
 373 {
 374         return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
 375 }
 376 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK               0x000000c0
 377 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT              6
 378 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
 379 {
 380         return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
 381 }
 382 #define CP_DRAW_INDX_OFFSET_0_TESSELLATE                        0x00000100
 383 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK                  0x00000c00
 384 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT                 10
 385 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
 386 {
 387         return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
 388 }
 389 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK                   0x01f00000
 390 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT                  20
 391 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
 392 {
 393         return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
 394 }
 395
 396 #define REG_CP_DRAW_INDX_OFFSET_1                               0x00000001
 397 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK               0xffffffff
 398 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT              0
 399 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
 400 {
 401         return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
 402 }
 403
 404 #define REG_CP_DRAW_INDX_OFFSET_2                               0x00000002
 405 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK                 0xffffffff
 406 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT                0
 407 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
 408 {
 409         return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
 410 }
 411
 412 #define REG_CP_DRAW_INDX_OFFSET_3                               0x00000003
 413
 414 #define REG_CP_DRAW_INDX_OFFSET_4                               0x00000004
 415 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK                   0xffffffff
 416 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT                  0
 417 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
 418 {
 419         return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
 420 }
 421
 422 #define REG_CP_DRAW_INDX_OFFSET_5                               0x00000005
 423 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK                   0xffffffff
 424 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT                  0
 425 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
 426 {
 427         return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
 428 }
 429
 430 #define REG_CP_SET_DRAW_STATE_0                                 0x00000000
 431 #define CP_SET_DRAW_STATE_0_COUNT__MASK                         0x0000ffff
 432 #define CP_SET_DRAW_STATE_0_COUNT__SHIFT                        0
 433 static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val)
 434 {
 435         return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK;
 436 }
 437 #define CP_SET_DRAW_STATE_0_DIRTY                               0x00010000
 438 #define CP_SET_DRAW_STATE_0_DISABLE                             0x00020000
 439 #define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS                  0x00040000
 440 #define CP_SET_DRAW_STATE_0_LOAD_IMMED                          0x00080000
 441 #define CP_SET_DRAW_STATE_0_GROUP_ID__MASK                      0x1f000000
 442 #define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT                     24
 443 static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val)
 444 {
 445         return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK;
 446 }
 447
 448 #define REG_CP_SET_DRAW_STATE_1                                 0x00000001
 449 #define CP_SET_DRAW_STATE_1_ADDR__MASK                          0xffffffff
 450 #define CP_SET_DRAW_STATE_1_ADDR__SHIFT                         0
 451 static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val)
 452 {
 453         return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK;
 454 }
 455
 456 #define REG_CP_SET_BIN_0                                        0x00000000
 457
 458 #define REG_CP_SET_BIN_1                                        0x00000001
 459 #define CP_SET_BIN_1_X1__MASK                                   0x0000ffff
 460 #define CP_SET_BIN_1_X1__SHIFT                                  0
 461 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
 462 {
 463         return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
 464 }
 465 #define CP_SET_BIN_1_Y1__MASK                                   0xffff0000
 466 #define CP_SET_BIN_1_Y1__SHIFT                                  16
 467 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
 468 {
 469         return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
 470 }
 471
 472 #define REG_CP_SET_BIN_2                                        0x00000002
 473 #define CP_SET_BIN_2_X2__MASK                                   0x0000ffff
 474 #define CP_SET_BIN_2_X2__SHIFT                                  0
 475 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
 476 {
 477         return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
 478 }
 479 #define CP_SET_BIN_2_Y2__MASK                                   0xffff0000
 480 #define CP_SET_BIN_2_Y2__SHIFT                                  16
 481 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
 482 {
 483         return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
 484 }
 485
 486 #define REG_CP_SET_BIN_DATA_0                                   0x00000000
 487 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK                   0xffffffff
 488 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT                  0
 489 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
 490 {
 491         return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
 492 }
 493
 494 #define REG_CP_SET_BIN_DATA_1                                   0x00000001
 495 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK                0xffffffff
 496 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT               0
 497 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
 498 {
 499         return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
 500 }
 501
 502
 503 #endif /* ADRENO_PM4_XML */