kernel/drivers/gpu/drm/msm/adreno/adreno_common.xml.h

   1 #ifndef ADRENO_COMMON_XML
   2 #define ADRENO_COMMON_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
  12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
  13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
  14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
  15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
  16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
  17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51069 bytes, from 2014-12-21 15:51:54)
  18
  19 Copyright (C) 2013-2014 by the following authors:
  20 - Rob Clark <robdclark@gmail.com> (robclark)
  21
  22 Permission is hereby granted, free of charge, to any person obtaining
  23 a copy of this software and associated documentation files (the
  24 "Software"), to deal in the Software without restriction, including
  25 without limitation the rights to use, copy, modify, merge, publish,
  26 distribute, sublicense, and/or sell copies of the Software, and to
  27 permit persons to whom the Software is furnished to do so, subject to
  28 the following conditions:
  29
  30 The above copyright notice and this permission notice (including the
  31 next paragraph) shall be included in all copies or substantial
  32 portions of the Software.
  33
  34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  41 */
  42
  43
  44 enum adreno_pa_su_sc_draw {
  45         PC_DRAW_POINTS = 0,
  46         PC_DRAW_LINES = 1,
  47         PC_DRAW_TRIANGLES = 2,
  48 };
  49
  50 enum adreno_compare_func {
  51         FUNC_NEVER = 0,
  52         FUNC_LESS = 1,
  53         FUNC_EQUAL = 2,
  54         FUNC_LEQUAL = 3,
  55         FUNC_GREATER = 4,
  56         FUNC_NOTEQUAL = 5,
  57         FUNC_GEQUAL = 6,
  58         FUNC_ALWAYS = 7,
  59 };
  60
  61 enum adreno_stencil_op {
  62         STENCIL_KEEP = 0,
  63         STENCIL_ZERO = 1,
  64         STENCIL_REPLACE = 2,
  65         STENCIL_INCR_CLAMP = 3,
  66         STENCIL_DECR_CLAMP = 4,
  67         STENCIL_INVERT = 5,
  68         STENCIL_INCR_WRAP = 6,
  69         STENCIL_DECR_WRAP = 7,
  70 };
  71
  72 enum adreno_rb_blend_factor {
  73         FACTOR_ZERO = 0,
  74         FACTOR_ONE = 1,
  75         FACTOR_SRC_COLOR = 4,
  76         FACTOR_ONE_MINUS_SRC_COLOR = 5,
  77         FACTOR_SRC_ALPHA = 6,
  78         FACTOR_ONE_MINUS_SRC_ALPHA = 7,
  79         FACTOR_DST_COLOR = 8,
  80         FACTOR_ONE_MINUS_DST_COLOR = 9,
  81         FACTOR_DST_ALPHA = 10,
  82         FACTOR_ONE_MINUS_DST_ALPHA = 11,
  83         FACTOR_CONSTANT_COLOR = 12,
  84         FACTOR_ONE_MINUS_CONSTANT_COLOR = 13,
  85         FACTOR_CONSTANT_ALPHA = 14,
  86         FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
  87         FACTOR_SRC_ALPHA_SATURATE = 16,
  88 };
  89
  90 enum adreno_rb_surface_endian {
  91         ENDIAN_NONE = 0,
  92         ENDIAN_8IN16 = 1,
  93         ENDIAN_8IN32 = 2,
  94         ENDIAN_16IN32 = 3,
  95         ENDIAN_8IN64 = 4,
  96         ENDIAN_8IN128 = 5,
  97 };
  98
  99 enum adreno_rb_dither_mode {
 100         DITHER_DISABLE = 0,
 101         DITHER_ALWAYS = 1,
 102         DITHER_IF_ALPHA_OFF = 2,
 103 };
 104
 105 enum adreno_rb_depth_format {
 106         DEPTHX_16 = 0,
 107         DEPTHX_24_8 = 1,
 108         DEPTHX_32 = 2,
 109 };
 110
 111 enum adreno_rb_copy_control_mode {
 112         RB_COPY_RESOLVE = 1,
 113         RB_COPY_CLEAR = 2,
 114         RB_COPY_DEPTH_STENCIL = 5,
 115 };
 116
 117 enum a3xx_render_mode {
 118         RB_RENDERING_PASS = 0,
 119         RB_TILING_PASS = 1,
 120         RB_RESOLVE_PASS = 2,
 121         RB_COMPUTE_PASS = 3,
 122 };
 123
 124 enum a3xx_msaa_samples {
 125         MSAA_ONE = 0,
 126         MSAA_TWO = 1,
 127         MSAA_FOUR = 2,
 128 };
 129
 130 enum a3xx_threadmode {
 131         MULTI = 0,
 132         SINGLE = 1,
 133 };
 134
 135 enum a3xx_instrbuffermode {
 136         CACHE = 0,
 137         BUFFER = 1,
 138 };
 139
 140 enum a3xx_threadsize {
 141         TWO_QUADS = 0,
 142         FOUR_QUADS = 1,
 143 };
 144
 145 enum a3xx_color_swap {
 146         WZYX = 0,
 147         WXYZ = 1,
 148         ZYXW = 2,
 149         XYZW = 3,
 150 };
 151
 152 #define REG_AXXX_CP_RB_BASE                                     0x000001c0
 153
 154 #define REG_AXXX_CP_RB_CNTL                                     0x000001c1
 155 #define AXXX_CP_RB_CNTL_BUFSZ__MASK                             0x0000003f
 156 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT                            0
 157 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)
 158 {
 159         return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;
 160 }
 161 #define AXXX_CP_RB_CNTL_BLKSZ__MASK                             0x00003f00
 162 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT                            8
 163 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)
 164 {
 165         return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;
 166 }
 167 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK                          0x00030000
 168 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT                         16
 169 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)
 170 {
 171         return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;
 172 }
 173 #define AXXX_CP_RB_CNTL_POLL_EN                                 0x00100000
 174 #define AXXX_CP_RB_CNTL_NO_UPDATE                               0x08000000
 175 #define AXXX_CP_RB_CNTL_RPTR_WR_EN                              0x80000000
 176
 177 #define REG_AXXX_CP_RB_RPTR_ADDR                                0x000001c3
 178 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK                         0x00000003
 179 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT                        0
 180 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
 181 {
 182         return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;
 183 }
 184 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK                         0xfffffffc
 185 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT                        2
 186 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
 187 {
 188         return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
 189 }
 190
 191 #define REG_AXXX_CP_RB_RPTR                                     0x000001c4
 192
 193 #define REG_AXXX_CP_RB_WPTR                                     0x000001c5
 194
 195 #define REG_AXXX_CP_RB_WPTR_DELAY                               0x000001c6
 196
 197 #define REG_AXXX_CP_RB_RPTR_WR                                  0x000001c7
 198
 199 #define REG_AXXX_CP_RB_WPTR_BASE                                0x000001c8
 200
 201 #define REG_AXXX_CP_QUEUE_THRESHOLDS                            0x000001d5
 202 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK            0x0000000f
 203 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT           0
 204 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)
 205 {
 206         return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK;
 207 }
 208 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK            0x00000f00
 209 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT           8
 210 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)
 211 {
 212         return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK;
 213 }
 214 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK             0x000f0000
 215 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT            16
 216 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
 217 {
 218         return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK;
 219 }
 220
 221 #define REG_AXXX_CP_MEQ_THRESHOLDS                              0x000001d6
 222 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK                    0x001f0000
 223 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT                   16
 224 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)
 225 {
 226         return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK;
 227 }
 228 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK                    0x1f000000
 229 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT                   24
 230 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)
 231 {
 232         return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK;
 233 }
 234
 235 #define REG_AXXX_CP_CSQ_AVAIL                                   0x000001d7
 236 #define AXXX_CP_CSQ_AVAIL_RING__MASK                            0x0000007f
 237 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT                           0
 238 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)
 239 {
 240         return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;
 241 }
 242 #define AXXX_CP_CSQ_AVAIL_IB1__MASK                             0x00007f00
 243 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT                            8
 244 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)
 245 {
 246         return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;
 247 }
 248 #define AXXX_CP_CSQ_AVAIL_IB2__MASK                             0x007f0000
 249 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT                            16
 250 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)
 251 {
 252         return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;
 253 }
 254
 255 #define REG_AXXX_CP_STQ_AVAIL                                   0x000001d8
 256 #define AXXX_CP_STQ_AVAIL_ST__MASK                              0x0000007f
 257 #define AXXX_CP_STQ_AVAIL_ST__SHIFT                             0
 258 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)
 259 {
 260         return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;
 261 }
 262
 263 #define REG_AXXX_CP_MEQ_AVAIL                                   0x000001d9
 264 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK                             0x0000001f
 265 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT                            0
 266 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)
 267 {
 268         return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;
 269 }
 270
 271 #define REG_AXXX_SCRATCH_UMSK                                   0x000001dc
 272 #define AXXX_SCRATCH_UMSK_UMSK__MASK                            0x000000ff
 273 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT                           0
 274 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)
 275 {
 276         return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;
 277 }
 278 #define AXXX_SCRATCH_UMSK_SWAP__MASK                            0x00030000
 279 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT                           16
 280 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
 281 {
 282         return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;
 283 }
 284
 285 #define REG_AXXX_SCRATCH_ADDR                                   0x000001dd
 286
 287 #define REG_AXXX_CP_ME_RDADDR                                   0x000001ea
 288
 289 #define REG_AXXX_CP_STATE_DEBUG_INDEX                           0x000001ec
 290
 291 #define REG_AXXX_CP_STATE_DEBUG_DATA                            0x000001ed
 292
 293 #define REG_AXXX_CP_INT_CNTL                                    0x000001f2
 294
 295 #define REG_AXXX_CP_INT_STATUS                                  0x000001f3
 296
 297 #define REG_AXXX_CP_INT_ACK                                     0x000001f4
 298
 299 #define REG_AXXX_CP_ME_CNTL                                     0x000001f6
 300 #define AXXX_CP_ME_CNTL_BUSY                                    0x20000000
 301 #define AXXX_CP_ME_CNTL_HALT                                    0x10000000
 302
 303 #define REG_AXXX_CP_ME_STATUS                                   0x000001f7
 304
 305 #define REG_AXXX_CP_ME_RAM_WADDR                                0x000001f8
 306
 307 #define REG_AXXX_CP_ME_RAM_RADDR                                0x000001f9
 308
 309 #define REG_AXXX_CP_ME_RAM_DATA                                 0x000001fa
 310
 311 #define REG_AXXX_CP_DEBUG                                       0x000001fc
 312 #define AXXX_CP_DEBUG_PREDICATE_DISABLE                         0x00800000
 313 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE                       0x01000000
 314 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE                   0x02000000
 315 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS                        0x04000000
 316 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE                       0x08000000
 317 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE                    0x10000000
 318 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL                    0x40000000
 319 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE                    0x80000000
 320
 321 #define REG_AXXX_CP_CSQ_RB_STAT                                 0x000001fd
 322 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK                          0x0000007f
 323 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT                         0
 324 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)
 325 {
 326         return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;
 327 }
 328 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK                          0x007f0000
 329 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT                         16
 330 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)
 331 {
 332         return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;
 333 }
 334
 335 #define REG_AXXX_CP_CSQ_IB1_STAT                                0x000001fe
 336 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK                         0x0000007f
 337 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT                        0
 338 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)
 339 {
 340         return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;
 341 }
 342 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK                         0x007f0000
 343 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT                        16
 344 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)
 345 {
 346         return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;
 347 }
 348
 349 #define REG_AXXX_CP_CSQ_IB2_STAT                                0x000001ff
 350 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK                         0x0000007f
 351 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT                        0
 352 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)
 353 {
 354         return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;
 355 }
 356 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK                         0x007f0000
 357 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT                        16
 358 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
 359 {
 360         return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
 361 }
 362
 363 #define REG_AXXX_CP_NON_PREFETCH_CNTRS                          0x00000440
 364
 365 #define REG_AXXX_CP_STQ_ST_STAT                                 0x00000443
 366
 367 #define REG_AXXX_CP_ST_BASE                                     0x0000044d
 368
 369 #define REG_AXXX_CP_ST_BUFSZ                                    0x0000044e
 370
 371 #define REG_AXXX_CP_MEQ_STAT                                    0x0000044f
 372
 373 #define REG_AXXX_CP_MIU_TAG_STAT                                0x00000452
 374
 375 #define REG_AXXX_CP_BIN_MASK_LO                                 0x00000454
 376
 377 #define REG_AXXX_CP_BIN_MASK_HI                                 0x00000455
 378
 379 #define REG_AXXX_CP_BIN_SELECT_LO                               0x00000456
 380
 381 #define REG_AXXX_CP_BIN_SELECT_HI                               0x00000457
 382
 383 #define REG_AXXX_CP_IB1_BASE                                    0x00000458
 384
 385 #define REG_AXXX_CP_IB1_BUFSZ                                   0x00000459
 386
 387 #define REG_AXXX_CP_IB2_BASE                                    0x0000045a
 388
 389 #define REG_AXXX_CP_IB2_BUFSZ                                   0x0000045b
 390
 391 #define REG_AXXX_CP_STAT                                        0x0000047f
 392
 393 #define REG_AXXX_CP_SCRATCH_REG0                                0x00000578
 394
 395 #define REG_AXXX_CP_SCRATCH_REG1                                0x00000579
 396
 397 #define REG_AXXX_CP_SCRATCH_REG2                                0x0000057a
 398
 399 #define REG_AXXX_CP_SCRATCH_REG3                                0x0000057b
 400
 401 #define REG_AXXX_CP_SCRATCH_REG4                                0x0000057c
 402
 403 #define REG_AXXX_CP_SCRATCH_REG5                                0x0000057d
 404
 405 #define REG_AXXX_CP_SCRATCH_REG6                                0x0000057e
 406
 407 #define REG_AXXX_CP_SCRATCH_REG7                                0x0000057f
 408
 409 #define REG_AXXX_CP_ME_VS_EVENT_SRC                             0x00000600
 410
 411 #define REG_AXXX_CP_ME_VS_EVENT_ADDR                            0x00000601
 412
 413 #define REG_AXXX_CP_ME_VS_EVENT_DATA                            0x00000602
 414
 415 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM                        0x00000603
 416
 417 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM                        0x00000604
 418
 419 #define REG_AXXX_CP_ME_PS_EVENT_SRC                             0x00000605
 420
 421 #define REG_AXXX_CP_ME_PS_EVENT_ADDR                            0x00000606
 422
 423 #define REG_AXXX_CP_ME_PS_EVENT_DATA                            0x00000607
 424
 425 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM                        0x00000608
 426
 427 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM                        0x00000609
 428
 429 #define REG_AXXX_CP_ME_CF_EVENT_SRC                             0x0000060a
 430
 431 #define REG_AXXX_CP_ME_CF_EVENT_ADDR                            0x0000060b
 432
 433 #define REG_AXXX_CP_ME_CF_EVENT_DATA                            0x0000060c
 434
 435 #define REG_AXXX_CP_ME_NRT_ADDR                                 0x0000060d
 436
 437 #define REG_AXXX_CP_ME_NRT_DATA                                 0x0000060e
 438
 439 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC                        0x00000612
 440
 441 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR                       0x00000613
 442
 443 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA                       0x00000614
 444
 445
 446 #endif /* ADRENO_COMMON_XML */