kernel/drivers/gpu/drm/msm/adreno/a2xx.xml.h

   1 #ifndef A2XX_XML
   2 #define A2XX_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
  12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
  13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
  14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
  15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
  16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
  17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51069 bytes, from 2014-12-21 15:51:54)
  18
  19 Copyright (C) 2013-2014 by the following authors:
  20 - Rob Clark <robdclark@gmail.com> (robclark)
  21
  22 Permission is hereby granted, free of charge, to any person obtaining
  23 a copy of this software and associated documentation files (the
  24 "Software"), to deal in the Software without restriction, including
  25 without limitation the rights to use, copy, modify, merge, publish,
  26 distribute, sublicense, and/or sell copies of the Software, and to
  27 permit persons to whom the Software is furnished to do so, subject to
  28 the following conditions:
  29
  30 The above copyright notice and this permission notice (including the
  31 next paragraph) shall be included in all copies or substantial
  32 portions of the Software.
  33
  34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  41 */
  42
  43
  44 enum a2xx_rb_dither_type {
  45         DITHER_PIXEL = 0,
  46         DITHER_SUBPIXEL = 1,
  47 };
  48
  49 enum a2xx_colorformatx {
  50         COLORX_4_4_4_4 = 0,
  51         COLORX_1_5_5_5 = 1,
  52         COLORX_5_6_5 = 2,
  53         COLORX_8 = 3,
  54         COLORX_8_8 = 4,
  55         COLORX_8_8_8_8 = 5,
  56         COLORX_S8_8_8_8 = 6,
  57         COLORX_16_FLOAT = 7,
  58         COLORX_16_16_FLOAT = 8,
  59         COLORX_16_16_16_16_FLOAT = 9,
  60         COLORX_32_FLOAT = 10,
  61         COLORX_32_32_FLOAT = 11,
  62         COLORX_32_32_32_32_FLOAT = 12,
  63         COLORX_2_3_3 = 13,
  64         COLORX_8_8_8 = 14,
  65 };
  66
  67 enum a2xx_sq_surfaceformat {
  68         FMT_1_REVERSE = 0,
  69         FMT_1 = 1,
  70         FMT_8 = 2,
  71         FMT_1_5_5_5 = 3,
  72         FMT_5_6_5 = 4,
  73         FMT_6_5_5 = 5,
  74         FMT_8_8_8_8 = 6,
  75         FMT_2_10_10_10 = 7,
  76         FMT_8_A = 8,
  77         FMT_8_B = 9,
  78         FMT_8_8 = 10,
  79         FMT_Cr_Y1_Cb_Y0 = 11,
  80         FMT_Y1_Cr_Y0_Cb = 12,
  81         FMT_5_5_5_1 = 13,
  82         FMT_8_8_8_8_A = 14,
  83         FMT_4_4_4_4 = 15,
  84         FMT_10_11_11 = 16,
  85         FMT_11_11_10 = 17,
  86         FMT_DXT1 = 18,
  87         FMT_DXT2_3 = 19,
  88         FMT_DXT4_5 = 20,
  89         FMT_24_8 = 22,
  90         FMT_24_8_FLOAT = 23,
  91         FMT_16 = 24,
  92         FMT_16_16 = 25,
  93         FMT_16_16_16_16 = 26,
  94         FMT_16_EXPAND = 27,
  95         FMT_16_16_EXPAND = 28,
  96         FMT_16_16_16_16_EXPAND = 29,
  97         FMT_16_FLOAT = 30,
  98         FMT_16_16_FLOAT = 31,
  99         FMT_16_16_16_16_FLOAT = 32,
 100         FMT_32 = 33,
 101         FMT_32_32 = 34,
 102         FMT_32_32_32_32 = 35,
 103         FMT_32_FLOAT = 36,
 104         FMT_32_32_FLOAT = 37,
 105         FMT_32_32_32_32_FLOAT = 38,
 106         FMT_32_AS_8 = 39,
 107         FMT_32_AS_8_8 = 40,
 108         FMT_16_MPEG = 41,
 109         FMT_16_16_MPEG = 42,
 110         FMT_8_INTERLACED = 43,
 111         FMT_32_AS_8_INTERLACED = 44,
 112         FMT_32_AS_8_8_INTERLACED = 45,
 113         FMT_16_INTERLACED = 46,
 114         FMT_16_MPEG_INTERLACED = 47,
 115         FMT_16_16_MPEG_INTERLACED = 48,
 116         FMT_DXN = 49,
 117         FMT_8_8_8_8_AS_16_16_16_16 = 50,
 118         FMT_DXT1_AS_16_16_16_16 = 51,
 119         FMT_DXT2_3_AS_16_16_16_16 = 52,
 120         FMT_DXT4_5_AS_16_16_16_16 = 53,
 121         FMT_2_10_10_10_AS_16_16_16_16 = 54,
 122         FMT_10_11_11_AS_16_16_16_16 = 55,
 123         FMT_11_11_10_AS_16_16_16_16 = 56,
 124         FMT_32_32_32_FLOAT = 57,
 125         FMT_DXT3A = 58,
 126         FMT_DXT5A = 59,
 127         FMT_CTX1 = 60,
 128         FMT_DXT3A_AS_1_1_1_1 = 61,
 129 };
 130
 131 enum a2xx_sq_ps_vtx_mode {
 132         POSITION_1_VECTOR = 0,
 133         POSITION_2_VECTORS_UNUSED = 1,
 134         POSITION_2_VECTORS_SPRITE = 2,
 135         POSITION_2_VECTORS_EDGE = 3,
 136         POSITION_2_VECTORS_KILL = 4,
 137         POSITION_2_VECTORS_SPRITE_KILL = 5,
 138         POSITION_2_VECTORS_EDGE_KILL = 6,
 139         MULTIPASS = 7,
 140 };
 141
 142 enum a2xx_sq_sample_cntl {
 143         CENTROIDS_ONLY = 0,
 144         CENTERS_ONLY = 1,
 145         CENTROIDS_AND_CENTERS = 2,
 146 };
 147
 148 enum a2xx_dx_clip_space {
 149         DXCLIP_OPENGL = 0,
 150         DXCLIP_DIRECTX = 1,
 151 };
 152
 153 enum a2xx_pa_su_sc_polymode {
 154         POLY_DISABLED = 0,
 155         POLY_DUALMODE = 1,
 156 };
 157
 158 enum a2xx_rb_edram_mode {
 159         EDRAM_NOP = 0,
 160         COLOR_DEPTH = 4,
 161         DEPTH_ONLY = 5,
 162         EDRAM_COPY = 6,
 163 };
 164
 165 enum a2xx_pa_sc_pattern_bit_order {
 166         LITTLE = 0,
 167         BIG = 1,
 168 };
 169
 170 enum a2xx_pa_sc_auto_reset_cntl {
 171         NEVER = 0,
 172         EACH_PRIMITIVE = 1,
 173         EACH_PACKET = 2,
 174 };
 175
 176 enum a2xx_pa_pixcenter {
 177         PIXCENTER_D3D = 0,
 178         PIXCENTER_OGL = 1,
 179 };
 180
 181 enum a2xx_pa_roundmode {
 182         TRUNCATE = 0,
 183         ROUND = 1,
 184         ROUNDTOEVEN = 2,
 185         ROUNDTOODD = 3,
 186 };
 187
 188 enum a2xx_pa_quantmode {
 189         ONE_SIXTEENTH = 0,
 190         ONE_EIGTH = 1,
 191         ONE_QUARTER = 2,
 192         ONE_HALF = 3,
 193         ONE = 4,
 194 };
 195
 196 enum a2xx_rb_copy_sample_select {
 197         SAMPLE_0 = 0,
 198         SAMPLE_1 = 1,
 199         SAMPLE_2 = 2,
 200         SAMPLE_3 = 3,
 201         SAMPLE_01 = 4,
 202         SAMPLE_23 = 5,
 203         SAMPLE_0123 = 6,
 204 };
 205
 206 enum a2xx_rb_blend_opcode {
 207         BLEND_DST_PLUS_SRC = 0,
 208         BLEND_SRC_MINUS_DST = 1,
 209         BLEND_MIN_DST_SRC = 2,
 210         BLEND_MAX_DST_SRC = 3,
 211         BLEND_DST_MINUS_SRC = 4,
 212         BLEND_DST_PLUS_SRC_BIAS = 5,
 213 };
 214
 215 enum adreno_mmu_clnt_beh {
 216         BEH_NEVR = 0,
 217         BEH_TRAN_RNG = 1,
 218         BEH_TRAN_FLT = 2,
 219 };
 220
 221 enum sq_tex_clamp {
 222         SQ_TEX_WRAP = 0,
 223         SQ_TEX_MIRROR = 1,
 224         SQ_TEX_CLAMP_LAST_TEXEL = 2,
 225         SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3,
 226         SQ_TEX_CLAMP_HALF_BORDER = 4,
 227         SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5,
 228         SQ_TEX_CLAMP_BORDER = 6,
 229         SQ_TEX_MIRROR_ONCE_BORDER = 7,
 230 };
 231
 232 enum sq_tex_swiz {
 233         SQ_TEX_X = 0,
 234         SQ_TEX_Y = 1,
 235         SQ_TEX_Z = 2,
 236         SQ_TEX_W = 3,
 237         SQ_TEX_ZERO = 4,
 238         SQ_TEX_ONE = 5,
 239 };
 240
 241 enum sq_tex_filter {
 242         SQ_TEX_FILTER_POINT = 0,
 243         SQ_TEX_FILTER_BILINEAR = 1,
 244         SQ_TEX_FILTER_BICUBIC = 2,
 245 };
 246
 247 #define REG_A2XX_RBBM_PATCH_RELEASE                             0x00000001
 248
 249 #define REG_A2XX_RBBM_CNTL                                      0x0000003b
 250
 251 #define REG_A2XX_RBBM_SOFT_RESET                                0x0000003c
 252
 253 #define REG_A2XX_CP_PFP_UCODE_ADDR                              0x000000c0
 254
 255 #define REG_A2XX_CP_PFP_UCODE_DATA                              0x000000c1
 256
 257 #define REG_A2XX_MH_MMU_CONFIG                                  0x00000040
 258 #define A2XX_MH_MMU_CONFIG_MMU_ENABLE                           0x00000001
 259 #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE                    0x00000002
 260 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK             0x00000030
 261 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT            4
 262 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 263 {
 264         return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
 265 }
 266 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK             0x000000c0
 267 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT            6
 268 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 269 {
 270         return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
 271 }
 272 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK            0x00000300
 273 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT           8
 274 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 275 {
 276         return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
 277 }
 278 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK            0x00000c00
 279 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT           10
 280 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 281 {
 282         return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
 283 }
 284 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK            0x00003000
 285 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT           12
 286 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 287 {
 288         return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
 289 }
 290 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK            0x0000c000
 291 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT           14
 292 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 293 {
 294         return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
 295 }
 296 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK            0x00030000
 297 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT           16
 298 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 299 {
 300         return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
 301 }
 302 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK           0x000c0000
 303 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT          18
 304 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 305 {
 306         return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
 307 }
 308 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK           0x00300000
 309 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT          20
 310 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 311 {
 312         return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
 313 }
 314 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK             0x00c00000
 315 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT            22
 316 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 317 {
 318         return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
 319 }
 320 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK             0x03000000
 321 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT            24
 322 static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 323 {
 324         return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
 325 }
 326
 327 #define REG_A2XX_MH_MMU_VA_RANGE                                0x00000041
 328
 329 #define REG_A2XX_MH_MMU_PT_BASE                                 0x00000042
 330
 331 #define REG_A2XX_MH_MMU_PAGE_FAULT                              0x00000043
 332
 333 #define REG_A2XX_MH_MMU_TRAN_ERROR                              0x00000044
 334
 335 #define REG_A2XX_MH_MMU_INVALIDATE                              0x00000045
 336
 337 #define REG_A2XX_MH_MMU_MPU_BASE                                0x00000046
 338
 339 #define REG_A2XX_MH_MMU_MPU_END                                 0x00000047
 340
 341 #define REG_A2XX_NQWAIT_UNTIL                                   0x00000394
 342
 343 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT                       0x00000395
 344
 345 #define REG_A2XX_RBBM_PERFCOUNTER1_LO                           0x00000397
 346
 347 #define REG_A2XX_RBBM_PERFCOUNTER1_HI                           0x00000398
 348
 349 #define REG_A2XX_RBBM_DEBUG                                     0x0000039b
 350
 351 #define REG_A2XX_RBBM_PM_OVERRIDE1                              0x0000039c
 352
 353 #define REG_A2XX_RBBM_PM_OVERRIDE2                              0x0000039d
 354
 355 #define REG_A2XX_RBBM_DEBUG_OUT                                 0x000003a0
 356
 357 #define REG_A2XX_RBBM_DEBUG_CNTL                                0x000003a1
 358
 359 #define REG_A2XX_RBBM_READ_ERROR                                0x000003b3
 360
 361 #define REG_A2XX_RBBM_INT_CNTL                                  0x000003b4
 362
 363 #define REG_A2XX_RBBM_INT_STATUS                                0x000003b5
 364
 365 #define REG_A2XX_RBBM_INT_ACK                                   0x000003b6
 366
 367 #define REG_A2XX_MASTER_INT_SIGNAL                              0x000003b7
 368
 369 #define REG_A2XX_RBBM_PERIPHID1                                 0x000003f9
 370
 371 #define REG_A2XX_RBBM_PERIPHID2                                 0x000003fa
 372
 373 #define REG_A2XX_CP_PERFMON_CNTL                                0x00000444
 374
 375 #define REG_A2XX_CP_PERFCOUNTER_SELECT                          0x00000445
 376
 377 #define REG_A2XX_CP_PERFCOUNTER_LO                              0x00000446
 378
 379 #define REG_A2XX_CP_PERFCOUNTER_HI                              0x00000447
 380
 381 #define REG_A2XX_RBBM_STATUS                                    0x000005d0
 382 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK                    0x0000001f
 383 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT                   0
 384 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val)
 385 {
 386         return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK;
 387 }
 388 #define A2XX_RBBM_STATUS_TC_BUSY                                0x00000020
 389 #define A2XX_RBBM_STATUS_HIRQ_PENDING                           0x00000100
 390 #define A2XX_RBBM_STATUS_CPRQ_PENDING                           0x00000200
 391 #define A2XX_RBBM_STATUS_CFRQ_PENDING                           0x00000400
 392 #define A2XX_RBBM_STATUS_PFRQ_PENDING                           0x00000800
 393 #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA                        0x00001000
 394 #define A2XX_RBBM_STATUS_RBBM_WU_BUSY                           0x00004000
 395 #define A2XX_RBBM_STATUS_CP_NRT_BUSY                            0x00010000
 396 #define A2XX_RBBM_STATUS_MH_BUSY                                0x00040000
 397 #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY                      0x00080000
 398 #define A2XX_RBBM_STATUS_SX_BUSY                                0x00200000
 399 #define A2XX_RBBM_STATUS_TPC_BUSY                               0x00400000
 400 #define A2XX_RBBM_STATUS_SC_CNTX_BUSY                           0x01000000
 401 #define A2XX_RBBM_STATUS_PA_BUSY                                0x02000000
 402 #define A2XX_RBBM_STATUS_VGT_BUSY                               0x04000000
 403 #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY                         0x08000000
 404 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY                          0x10000000
 405 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY                           0x40000000
 406 #define A2XX_RBBM_STATUS_GUI_ACTIVE                             0x80000000
 407
 408 #define REG_A2XX_MH_ARBITER_CONFIG                              0x00000a40
 409 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK            0x0000003f
 410 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT           0
 411 static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val)
 412 {
 413         return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK;
 414 }
 415 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY            0x00000040
 416 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE                    0x00000080
 417 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE               0x00000100
 418 #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL                   0x00000200
 419 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK                  0x00001c00
 420 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT                 10
 421 static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val)
 422 {
 423         return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK;
 424 }
 425 #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE                0x00002000
 426 #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE               0x00004000
 427 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE           0x00008000
 428 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK            0x003f0000
 429 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT           16
 430 static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val)
 431 {
 432         return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK;
 433 }
 434 #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE                   0x00400000
 435 #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE                  0x00800000
 436 #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE                   0x01000000
 437 #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE                   0x02000000
 438 #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE                   0x04000000
 439
 440 #define REG_A2XX_A220_VSC_BIN_SIZE                              0x00000c01
 441 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK                      0x0000001f
 442 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT                     0
 443 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val)
 444 {
 445         return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK;
 446 }
 447 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK                     0x000003e0
 448 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT                    5
 449 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)
 450 {
 451         return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;
 452 }
 453
 454 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
 455
 456 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
 457
 458 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
 459
 460 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
 461
 462 #define REG_A2XX_PC_DEBUG_CNTL                                  0x00000c38
 463
 464 #define REG_A2XX_PC_DEBUG_DATA                                  0x00000c39
 465
 466 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS                         0x00000c44
 467
 468 #define REG_A2XX_GRAS_DEBUG_CNTL                                0x00000c80
 469
 470 #define REG_A2XX_PA_SU_DEBUG_CNTL                               0x00000c80
 471
 472 #define REG_A2XX_GRAS_DEBUG_DATA                                0x00000c81
 473
 474 #define REG_A2XX_PA_SU_DEBUG_DATA                               0x00000c81
 475
 476 #define REG_A2XX_PA_SU_FACE_DATA                                0x00000c86
 477
 478 #define REG_A2XX_SQ_GPR_MANAGEMENT                              0x00000d00
 479
 480 #define REG_A2XX_SQ_FLOW_CONTROL                                0x00000d01
 481
 482 #define REG_A2XX_SQ_INST_STORE_MANAGMENT                        0x00000d02
 483
 484 #define REG_A2XX_SQ_DEBUG_MISC                                  0x00000d05
 485
 486 #define REG_A2XX_SQ_INT_CNTL                                    0x00000d34
 487
 488 #define REG_A2XX_SQ_INT_STATUS                                  0x00000d35
 489
 490 #define REG_A2XX_SQ_INT_ACK                                     0x00000d36
 491
 492 #define REG_A2XX_SQ_DEBUG_INPUT_FSM                             0x00000dae
 493
 494 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM                         0x00000daf
 495
 496 #define REG_A2XX_SQ_DEBUG_TP_FSM                                0x00000db0
 497
 498 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0                             0x00000db1
 499
 500 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1                             0x00000db2
 501
 502 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC                             0x00000db3
 503
 504 #define REG_A2XX_SQ_DEBUG_PTR_BUFF                              0x00000db4
 505
 506 #define REG_A2XX_SQ_DEBUG_GPR_VTX                               0x00000db5
 507
 508 #define REG_A2XX_SQ_DEBUG_GPR_PIX                               0x00000db6
 509
 510 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL                         0x00000db7
 511
 512 #define REG_A2XX_SQ_DEBUG_VTX_TB_0                              0x00000db8
 513
 514 #define REG_A2XX_SQ_DEBUG_VTX_TB_1                              0x00000db9
 515
 516 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG                     0x00000dba
 517
 518 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM                      0x00000dbb
 519
 520 #define REG_A2XX_SQ_DEBUG_PIX_TB_0                              0x00000dbc
 521
 522 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0                   0x00000dbd
 523
 524 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1                   0x00000dbe
 525
 526 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2                   0x00000dbf
 527
 528 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3                   0x00000dc0
 529
 530 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM                      0x00000dc1
 531
 532 #define REG_A2XX_TC_CNTL_STATUS                                 0x00000e00
 533 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE                       0x00000001
 534
 535 #define REG_A2XX_TP0_CHICKEN                                    0x00000e1e
 536
 537 #define REG_A2XX_RB_BC_CONTROL                                  0x00000f01
 538 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE             0x00000001
 539 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK           0x00000006
 540 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT          1
 541 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val)
 542 {
 543         return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK;
 544 }
 545 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM                    0x00000008
 546 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH       0x00000010
 547 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP            0x00000020
 548 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP            0x00000040
 549 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE                   0x00000080
 550 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK              0x00001f00
 551 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT             8
 552 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val)
 553 {
 554         return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK;
 555 }
 556 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE                    0x00004000
 557 #define A2XX_RB_BC_CONTROL_CRC_MODE                             0x00008000
 558 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS              0x00010000
 559 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM                        0x00020000
 560 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK               0x003c0000
 561 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT              18
 562 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val)
 563 {
 564         return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK;
 565 }
 566 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE            0x00400000
 567 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK          0x07800000
 568 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT         23
 569 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val)
 570 {
 571         return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK;
 572 }
 573 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK      0x18000000
 574 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT     27
 575 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val)
 576 {
 577         return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK;
 578 }
 579 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE        0x20000000
 580 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM                           0x40000000
 581 #define A2XX_RB_BC_CONTROL_RESERVED6                            0x80000000
 582
 583 #define REG_A2XX_RB_EDRAM_INFO                                  0x00000f02
 584
 585 #define REG_A2XX_RB_DEBUG_CNTL                                  0x00000f26
 586
 587 #define REG_A2XX_RB_DEBUG_DATA                                  0x00000f27
 588
 589 #define REG_A2XX_RB_SURFACE_INFO                                0x00002000
 590
 591 #define REG_A2XX_RB_COLOR_INFO                                  0x00002001
 592 #define A2XX_RB_COLOR_INFO_FORMAT__MASK                         0x0000000f
 593 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT                        0
 594 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val)
 595 {
 596         return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK;
 597 }
 598 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK                     0x00000030
 599 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT                    4
 600 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val)
 601 {
 602         return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK;
 603 }
 604 #define A2XX_RB_COLOR_INFO_LINEAR                               0x00000040
 605 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK                         0x00000180
 606 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT                        7
 607 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val)
 608 {
 609         return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK;
 610 }
 611 #define A2XX_RB_COLOR_INFO_SWAP__MASK                           0x00000600
 612 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT                          9
 613 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val)
 614 {
 615         return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK;
 616 }
 617 #define A2XX_RB_COLOR_INFO_BASE__MASK                           0xfffff000
 618 #define A2XX_RB_COLOR_INFO_BASE__SHIFT                          12
 619 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val)
 620 {
 621         return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;
 622 }
 623
 624 #define REG_A2XX_RB_DEPTH_INFO                                  0x00002002
 625 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK                   0x00000001
 626 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT                  0
 627 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
 628 {
 629         return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
 630 }
 631 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK                     0xfffff000
 632 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT                    12
 633 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
 634 {
 635         return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
 636 }
 637
 638 #define REG_A2XX_A225_RB_COLOR_INFO3                            0x00002005
 639
 640 #define REG_A2XX_COHER_DEST_BASE_0                              0x00002006
 641
 642 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL                        0x0000200e
 643 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE      0x80000000
 644 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK                    0x00007fff
 645 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT                   0
 646 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
 647 {
 648         return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK;
 649 }
 650 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK                    0x7fff0000
 651 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT                   16
 652 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
 653 {
 654         return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK;
 655 }
 656
 657 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR                        0x0000200f
 658 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE      0x80000000
 659 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK                    0x00007fff
 660 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT                   0
 661 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
 662 {
 663         return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK;
 664 }
 665 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK                    0x7fff0000
 666 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT                   16
 667 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
 668 {
 669         return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK;
 670 }
 671
 672 #define REG_A2XX_PA_SC_WINDOW_OFFSET                            0x00002080
 673 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK                        0x00007fff
 674 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT                       0
 675 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val)
 676 {
 677         return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK;
 678 }
 679 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK                        0x7fff0000
 680 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT                       16
 681 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val)
 682 {
 683         return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK;
 684 }
 685 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE                        0x80000000
 686
 687 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL                        0x00002081
 688 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE      0x80000000
 689 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK                    0x00007fff
 690 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT                   0
 691 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
 692 {
 693         return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK;
 694 }
 695 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK                    0x7fff0000
 696 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT                   16
 697 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
 698 {
 699         return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK;
 700 }
 701
 702 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR                        0x00002082
 703 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE      0x80000000
 704 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK                    0x00007fff
 705 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT                   0
 706 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
 707 {
 708         return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK;
 709 }
 710 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK                    0x7fff0000
 711 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT                   16
 712 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
 713 {
 714         return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK;
 715 }
 716
 717 #define REG_A2XX_UNKNOWN_2010                                   0x00002010
 718
 719 #define REG_A2XX_VGT_MAX_VTX_INDX                               0x00002100
 720
 721 #define REG_A2XX_VGT_MIN_VTX_INDX                               0x00002101
 722
 723 #define REG_A2XX_VGT_INDX_OFFSET                                0x00002102
 724
 725 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX               0x00002103
 726
 727 #define REG_A2XX_RB_COLOR_MASK                                  0x00002104
 728 #define A2XX_RB_COLOR_MASK_WRITE_RED                            0x00000001
 729 #define A2XX_RB_COLOR_MASK_WRITE_GREEN                          0x00000002
 730 #define A2XX_RB_COLOR_MASK_WRITE_BLUE                           0x00000004
 731 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA                          0x00000008
 732
 733 #define REG_A2XX_RB_BLEND_RED                                   0x00002105
 734
 735 #define REG_A2XX_RB_BLEND_GREEN                                 0x00002106
 736
 737 #define REG_A2XX_RB_BLEND_BLUE                                  0x00002107
 738
 739 #define REG_A2XX_RB_BLEND_ALPHA                                 0x00002108
 740
 741 #define REG_A2XX_RB_FOG_COLOR                                   0x00002109
 742
 743 #define REG_A2XX_RB_STENCILREFMASK_BF                           0x0000210c
 744 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK              0x000000ff
 745 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT             0
 746 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
 747 {
 748         return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
 749 }
 750 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK             0x0000ff00
 751 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT            8
 752 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
 753 {
 754         return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
 755 }
 756 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK        0x00ff0000
 757 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT       16
 758 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
 759 {
 760         return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
 761 }
 762
 763 #define REG_A2XX_RB_STENCILREFMASK                              0x0000210d
 764 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK                 0x000000ff
 765 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT                0
 766 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
 767 {
 768         return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK;
 769 }
 770 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK                0x0000ff00
 771 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT               8
 772 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
 773 {
 774         return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK;
 775 }
 776 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK           0x00ff0000
 777 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT          16
 778 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
 779 {
 780         return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
 781 }
 782
 783 #define REG_A2XX_RB_ALPHA_REF                                   0x0000210e
 784
 785 #define REG_A2XX_PA_CL_VPORT_XSCALE                             0x0000210f
 786 #define A2XX_PA_CL_VPORT_XSCALE__MASK                           0xffffffff
 787 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT                          0
 788 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val)
 789 {
 790         return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK;
 791 }
 792
 793 #define REG_A2XX_PA_CL_VPORT_XOFFSET                            0x00002110
 794 #define A2XX_PA_CL_VPORT_XOFFSET__MASK                          0xffffffff
 795 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT                         0
 796 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val)
 797 {
 798         return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK;
 799 }
 800
 801 #define REG_A2XX_PA_CL_VPORT_YSCALE                             0x00002111
 802 #define A2XX_PA_CL_VPORT_YSCALE__MASK                           0xffffffff
 803 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT                          0
 804 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val)
 805 {
 806         return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK;
 807 }
 808
 809 #define REG_A2XX_PA_CL_VPORT_YOFFSET                            0x00002112
 810 #define A2XX_PA_CL_VPORT_YOFFSET__MASK                          0xffffffff
 811 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT                         0
 812 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val)
 813 {
 814         return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK;
 815 }
 816
 817 #define REG_A2XX_PA_CL_VPORT_ZSCALE                             0x00002113
 818 #define A2XX_PA_CL_VPORT_ZSCALE__MASK                           0xffffffff
 819 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT                          0
 820 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val)
 821 {
 822         return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK;
 823 }
 824
 825 #define REG_A2XX_PA_CL_VPORT_ZOFFSET                            0x00002114
 826 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK                          0xffffffff
 827 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT                         0
 828 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val)
 829 {
 830         return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK;
 831 }
 832
 833 #define REG_A2XX_SQ_PROGRAM_CNTL                                0x00002180
 834 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK                      0x000000ff
 835 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT                     0
 836 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val)
 837 {
 838         return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK;
 839 }
 840 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK                      0x0000ff00
 841 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT                     8
 842 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val)
 843 {
 844         return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK;
 845 }
 846 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE                        0x00010000
 847 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE                        0x00020000
 848 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN                          0x00040000
 849 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX                      0x00080000
 850 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK              0x00f00000
 851 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT             20
 852 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val)
 853 {
 854         return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK;
 855 }
 856 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK               0x07000000
 857 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT              24
 858 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val)
 859 {
 860         return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK;
 861 }
 862 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK               0x78000000
 863 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT              27
 864 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val)
 865 {
 866         return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK;
 867 }
 868 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX                      0x80000000
 869
 870 #define REG_A2XX_SQ_CONTEXT_MISC                                0x00002181
 871 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE                 0x00000001
 872 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY                0x00000002
 873 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK               0x0000000c
 874 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT              2
 875 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val)
 876 {
 877         return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK;
 878 }
 879 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK                0x0000ff00
 880 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT               8
 881 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
 882 {
 883         return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK;
 884 }
 885 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF                    0x00010000
 886 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE                     0x00020000
 887 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL                       0x00040000
 888
 889 #define REG_A2XX_SQ_INTERPOLATOR_CNTL                           0x00002182
 890
 891 #define REG_A2XX_SQ_WRAPPING_0                                  0x00002183
 892
 893 #define REG_A2XX_SQ_WRAPPING_1                                  0x00002184
 894
 895 #define REG_A2XX_SQ_PS_PROGRAM                                  0x000021f6
 896
 897 #define REG_A2XX_SQ_VS_PROGRAM                                  0x000021f7
 898
 899 #define REG_A2XX_VGT_EVENT_INITIATOR                            0x000021f9
 900
 901 #define REG_A2XX_VGT_DRAW_INITIATOR                             0x000021fc
 902 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK                 0x0000003f
 903 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT                0
 904 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
 905 {
 906         return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
 907 }
 908 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK             0x000000c0
 909 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT            6
 910 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
 911 {
 912         return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
 913 }
 914 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK                  0x00000600
 915 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT                 9
 916 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
 917 {
 918         return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
 919 }
 920 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK                0x00000800
 921 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT               11
 922 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
 923 {
 924         return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
 925 }
 926 #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP                         0x00001000
 927 #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX                     0x00002000
 928 #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE       0x00004000
 929 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK             0xff000000
 930 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT            24
 931 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
 932 {
 933         return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK;
 934 }
 935
 936 #define REG_A2XX_VGT_IMMED_DATA                                 0x000021fd
 937
 938 #define REG_A2XX_RB_DEPTHCONTROL                                0x00002200
 939 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE                     0x00000001
 940 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE                           0x00000002
 941 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE                     0x00000004
 942 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE                     0x00000008
 943 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK                        0x00000070
 944 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT                       4
 945 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val)
 946 {
 947         return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK;
 948 }
 949 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE                    0x00000080
 950 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK                  0x00000700
 951 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT                 8
 952 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val)
 953 {
 954         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK;
 955 }
 956 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK                  0x00003800
 957 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT                 11
 958 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val)
 959 {
 960         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK;
 961 }
 962 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK                 0x0001c000
 963 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT                14
 964 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val)
 965 {
 966         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK;
 967 }
 968 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK                 0x000e0000
 969 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT                17
 970 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val)
 971 {
 972         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK;
 973 }
 974 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK               0x00700000
 975 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT              20
 976 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val)
 977 {
 978         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK;
 979 }
 980 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK               0x03800000
 981 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT              23
 982 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val)
 983 {
 984         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK;
 985 }
 986 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK              0x1c000000
 987 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT             26
 988 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val)
 989 {
 990         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK;
 991 }
 992 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK              0xe0000000
 993 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT             29
 994 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val)
 995 {
 996         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK;
 997 }
 998
 999 #define REG_A2XX_RB_BLEND_CONTROL                               0x00002201
1000 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK              0x0000001f
1001 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT             0
1002 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val)
1003 {
1004         return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK;
1005 }
1006 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK              0x000000e0
1007 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT             5
1008 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val)
1009 {
1010         return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK;
1011 }
1012 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK             0x00001f00
1013 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT            8
1014 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val)
1015 {
1016         return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK;
1017 }
1018 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK              0x001f0000
1019 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT             16
1020 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val)
1021 {
1022         return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK;
1023 }
1024 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK              0x00e00000
1025 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT             21
1026 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val)
1027 {
1028         return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK;
1029 }
1030 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK             0x1f000000
1031 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT            24
1032 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val)
1033 {
1034         return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK;
1035 }
1036 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE                0x20000000
1037 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE                       0x40000000
1038
1039 #define REG_A2XX_RB_COLORCONTROL                                0x00002202
1040 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK                   0x00000007
1041 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT                  0
1042 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val)
1043 {
1044         return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK;
1045 }
1046 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE                  0x00000008
1047 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE               0x00000010
1048 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE                      0x00000020
1049 #define A2XX_RB_COLORCONTROL_VOB_ENABLE                         0x00000040
1050 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG                     0x00000080
1051 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK                     0x00000f00
1052 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT                    8
1053 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val)
1054 {
1055         return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK;
1056 }
1057 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK                  0x00003000
1058 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT                 12
1059 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
1060 {
1061         return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK;
1062 }
1063 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK                  0x0000c000
1064 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT                 14
1065 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val)
1066 {
1067         return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK;
1068 }
1069 #define A2XX_RB_COLORCONTROL_PIXEL_FOG                          0x00010000
1070 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK        0x03000000
1071 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT       24
1072 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val)
1073 {
1074         return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK;
1075 }
1076 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK        0x0c000000
1077 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT       26
1078 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val)
1079 {
1080         return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK;
1081 }
1082 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK        0x30000000
1083 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT       28
1084 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val)
1085 {
1086         return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK;
1087 }
1088 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK        0xc0000000
1089 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT       30
1090 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val)
1091 {
1092         return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK;
1093 }
1094
1095 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX                         0x00002203
1096 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK                0x00000007
1097 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT               0
1098 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val)
1099 {
1100         return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK;
1101 }
1102 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK                   0x00000038
1103 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT                  3
1104 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val)
1105 {
1106         return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK;
1107 }
1108 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK       0x000001c0
1109 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT      6
1110 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val)
1111 {
1112         return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK;
1113 }
1114
1115 #define REG_A2XX_PA_CL_CLIP_CNTL                                0x00002204
1116 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE                       0x00010000
1117 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA             0x00040000
1118 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK            0x00080000
1119 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT           19
1120 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val)
1121 {
1122         return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK;
1123 }
1124 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT                0x00100000
1125 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR                        0x00200000
1126 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN                      0x00400000
1127 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN                       0x00800000
1128 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN                       0x01000000
1129
1130 #define REG_A2XX_PA_SU_SC_MODE_CNTL                             0x00002205
1131 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT                      0x00000001
1132 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK                       0x00000002
1133 #define A2XX_PA_SU_SC_MODE_CNTL_FACE                            0x00000004
1134 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK                  0x00000018
1135 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT                 3
1136 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val)
1137 {
1138         return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK;
1139 }
1140 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK               0x000000e0
1141 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT              5
1142 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
1143 {
1144         return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK;
1145 }
1146 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK                0x00000700
1147 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT               8
1148 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
1149 {
1150         return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK;
1151 }
1152 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE        0x00000800
1153 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE         0x00001000
1154 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE         0x00002000
1155 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE                     0x00008000
1156 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE        0x00010000
1157 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE             0x00040000
1158 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST              0x00080000
1159 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS                  0x00100000
1160 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA               0x00200000
1161 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE               0x00800000
1162 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI            0x02000000
1163 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE        0x04000000
1164 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS                0x10000000
1165 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS              0x20000000
1166 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE                0x40000000
1167 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE               0x80000000
1168
1169 #define REG_A2XX_PA_CL_VTE_CNTL                                 0x00002206
1170 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA                   0x00000001
1171 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA                  0x00000002
1172 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA                   0x00000004
1173 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA                  0x00000008
1174 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA                   0x00000010
1175 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA                  0x00000020
1176 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT                          0x00000100
1177 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT                           0x00000200
1178 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT                          0x00000400
1179 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF                     0x00000800
1180
1181 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN                         0x00002207
1182 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK                0x00000007
1183 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT               0
1184 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val)
1185 {
1186         return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK;
1187 }
1188 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK                   0x00000038
1189 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT                  3
1190 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val)
1191 {
1192         return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK;
1193 }
1194 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK       0x000001c0
1195 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT      6
1196 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val)
1197 {
1198         return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK;
1199 }
1200
1201 #define REG_A2XX_RB_MODECONTROL                                 0x00002208
1202 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK                    0x00000007
1203 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT                   0
1204 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val)
1205 {
1206         return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK;
1207 }
1208
1209 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL                        0x00002209
1210
1211 #define REG_A2XX_RB_SAMPLE_POS                                  0x0000220a
1212
1213 #define REG_A2XX_CLEAR_COLOR                                    0x0000220b
1214 #define A2XX_CLEAR_COLOR_RED__MASK                              0x000000ff
1215 #define A2XX_CLEAR_COLOR_RED__SHIFT                             0
1216 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val)
1217 {
1218         return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK;
1219 }
1220 #define A2XX_CLEAR_COLOR_GREEN__MASK                            0x0000ff00
1221 #define A2XX_CLEAR_COLOR_GREEN__SHIFT                           8
1222 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val)
1223 {
1224         return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK;
1225 }
1226 #define A2XX_CLEAR_COLOR_BLUE__MASK                             0x00ff0000
1227 #define A2XX_CLEAR_COLOR_BLUE__SHIFT                            16
1228 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val)
1229 {
1230         return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK;
1231 }
1232 #define A2XX_CLEAR_COLOR_ALPHA__MASK                            0xff000000
1233 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT                           24
1234 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val)
1235 {
1236         return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK;
1237 }
1238
1239 #define REG_A2XX_A220_GRAS_CONTROL                              0x00002210
1240
1241 #define REG_A2XX_PA_SU_POINT_SIZE                               0x00002280
1242 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK                      0x0000ffff
1243 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT                     0
1244 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val)
1245 {
1246         return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK;
1247 }
1248 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK                       0xffff0000
1249 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT                      16
1250 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val)
1251 {
1252         return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK;
1253 }
1254
1255 #define REG_A2XX_PA_SU_POINT_MINMAX                             0x00002281
1256 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK                       0x0000ffff
1257 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT                      0
1258 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val)
1259 {
1260         return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK;
1261 }
1262 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK                       0xffff0000
1263 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT                      16
1264 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val)
1265 {
1266         return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK;
1267 }
1268
1269 #define REG_A2XX_PA_SU_LINE_CNTL                                0x00002282
1270 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK                        0x0000ffff
1271 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT                       0
1272 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val)
1273 {
1274         return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK;
1275 }
1276
1277 #define REG_A2XX_PA_SC_LINE_STIPPLE                             0x00002283
1278 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK              0x0000ffff
1279 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT             0
1280 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val)
1281 {
1282         return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK;
1283 }
1284 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK              0x00ff0000
1285 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT             16
1286 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val)
1287 {
1288         return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK;
1289 }
1290 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK         0x10000000
1291 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT        28
1292 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val)
1293 {
1294         return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK;
1295 }
1296 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK           0x60000000
1297 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT          29
1298 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val)
1299 {
1300         return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK;
1301 }
1302
1303 #define REG_A2XX_PA_SC_VIZ_QUERY                                0x00002293
1304
1305 #define REG_A2XX_VGT_ENHANCE                                    0x00002294
1306
1307 #define REG_A2XX_PA_SC_LINE_CNTL                                0x00002300
1308 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK                    0x0000ffff
1309 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT                   0
1310 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val)
1311 {
1312         return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK;
1313 }
1314 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL                      0x00000100
1315 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH                  0x00000200
1316 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL                         0x00000400
1317
1318 #define REG_A2XX_PA_SC_AA_CONFIG                                0x00002301
1319
1320 #define REG_A2XX_PA_SU_VTX_CNTL                                 0x00002302
1321 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK                    0x00000001
1322 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT                   0
1323 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val)
1324 {
1325         return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK;
1326 }
1327 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK                    0x00000006
1328 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT                   1
1329 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val)
1330 {
1331         return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK;
1332 }
1333 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK                    0x00000380
1334 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT                   7
1335 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val)
1336 {
1337         return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK;
1338 }
1339
1340 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ                         0x00002303
1341 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK                       0xffffffff
1342 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT                      0
1343 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val)
1344 {
1345         return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK;
1346 }
1347
1348 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ                         0x00002304
1349 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK                       0xffffffff
1350 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT                      0
1351 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val)
1352 {
1353         return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK;
1354 }
1355
1356 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ                         0x00002305
1357 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK                       0xffffffff
1358 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT                      0
1359 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val)
1360 {
1361         return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK;
1362 }
1363
1364 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ                         0x00002306
1365 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK                       0xffffffff
1366 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT                      0
1367 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val)
1368 {
1369         return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK;
1370 }
1371
1372 #define REG_A2XX_SQ_VS_CONST                                    0x00002307
1373 #define A2XX_SQ_VS_CONST_BASE__MASK                             0x000001ff
1374 #define A2XX_SQ_VS_CONST_BASE__SHIFT                            0
1375 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val)
1376 {
1377         return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK;
1378 }
1379 #define A2XX_SQ_VS_CONST_SIZE__MASK                             0x001ff000
1380 #define A2XX_SQ_VS_CONST_SIZE__SHIFT                            12
1381 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val)
1382 {
1383         return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK;
1384 }
1385
1386 #define REG_A2XX_SQ_PS_CONST                                    0x00002308
1387 #define A2XX_SQ_PS_CONST_BASE__MASK                             0x000001ff
1388 #define A2XX_SQ_PS_CONST_BASE__SHIFT                            0
1389 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val)
1390 {
1391         return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK;
1392 }
1393 #define A2XX_SQ_PS_CONST_SIZE__MASK                             0x001ff000
1394 #define A2XX_SQ_PS_CONST_SIZE__SHIFT                            12
1395 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val)
1396 {
1397         return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK;
1398 }
1399
1400 #define REG_A2XX_SQ_DEBUG_MISC_0                                0x00002309
1401
1402 #define REG_A2XX_SQ_DEBUG_MISC_1                                0x0000230a
1403
1404 #define REG_A2XX_PA_SC_AA_MASK                                  0x00002312
1405
1406 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL                    0x00002316
1407
1408 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL                           0x00002317
1409
1410 #define REG_A2XX_RB_COPY_CONTROL                                0x00002318
1411 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK           0x00000007
1412 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT          0
1413 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val)
1414 {
1415         return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK;
1416 }
1417 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE                 0x00000008
1418 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK                   0x000000f0
1419 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT                  4
1420 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val)
1421 {
1422         return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK;
1423 }
1424
1425 #define REG_A2XX_RB_COPY_DEST_BASE                              0x00002319
1426
1427 #define REG_A2XX_RB_COPY_DEST_PITCH                             0x0000231a
1428 #define A2XX_RB_COPY_DEST_PITCH__MASK                           0xffffffff
1429 #define A2XX_RB_COPY_DEST_PITCH__SHIFT                          0
1430 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val)
1431 {
1432         return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK;
1433 }
1434
1435 #define REG_A2XX_RB_COPY_DEST_INFO                              0x0000231b
1436 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK                0x00000007
1437 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT               0
1438 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val)
1439 {
1440         return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK;
1441 }
1442 #define A2XX_RB_COPY_DEST_INFO_LINEAR                           0x00000008
1443 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK                     0x000000f0
1444 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT                    4
1445 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val)
1446 {
1447         return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK;
1448 }
1449 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK                       0x00000300
1450 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT                      8
1451 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val)
1452 {
1453         return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK;
1454 }
1455 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK                0x00000c00
1456 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT               10
1457 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1458 {
1459         return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
1460 }
1461 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK                0x00003000
1462 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT               12
1463 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val)
1464 {
1465         return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK;
1466 }
1467 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED                        0x00004000
1468 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN                      0x00008000
1469 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE                       0x00010000
1470 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA                      0x00020000
1471
1472 #define REG_A2XX_RB_COPY_DEST_OFFSET                            0x0000231c
1473 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK                        0x00001fff
1474 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT                       0
1475 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val)
1476 {
1477         return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK;
1478 }
1479 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK                        0x03ffe000
1480 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT                       13
1481 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
1482 {
1483         return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK;
1484 }
1485
1486 #define REG_A2XX_RB_DEPTH_CLEAR                                 0x0000231d
1487
1488 #define REG_A2XX_RB_SAMPLE_COUNT_CTL                            0x00002324
1489
1490 #define REG_A2XX_RB_COLOR_DEST_MASK                             0x00002326
1491
1492 #define REG_A2XX_A225_GRAS_UCP0X                                0x00002340
1493
1494 #define REG_A2XX_A225_GRAS_UCP5W                                0x00002357
1495
1496 #define REG_A2XX_A225_GRAS_UCP_ENABLED                          0x00002360
1497
1498 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE                  0x00002380
1499
1500 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET                  0x00002383
1501
1502 #define REG_A2XX_SQ_CONSTANT_0                                  0x00004000
1503
1504 #define REG_A2XX_SQ_FETCH_0                                     0x00004800
1505
1506 #define REG_A2XX_SQ_CF_BOOLEANS                                 0x00004900
1507
1508 #define REG_A2XX_SQ_CF_LOOP                                     0x00004908
1509
1510 #define REG_A2XX_COHER_SIZE_PM4                                 0x00000a29
1511
1512 #define REG_A2XX_COHER_BASE_PM4                                 0x00000a2a
1513
1514 #define REG_A2XX_COHER_STATUS_PM4                               0x00000a2b
1515
1516 #define REG_A2XX_SQ_TEX_0                                       0x00000000
1517 #define A2XX_SQ_TEX_0_CLAMP_X__MASK                             0x00001c00
1518 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT                            10
1519 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val)
1520 {
1521         return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK;
1522 }
1523 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK                             0x0000e000
1524 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT                            13
1525 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val)
1526 {
1527         return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK;
1528 }
1529 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK                             0x00070000
1530 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT                            16
1531 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val)
1532 {
1533         return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK;
1534 }
1535 #define A2XX_SQ_TEX_0_PITCH__MASK                               0xffc00000
1536 #define A2XX_SQ_TEX_0_PITCH__SHIFT                              22
1537 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val)
1538 {
1539         return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;
1540 }
1541
1542 #define REG_A2XX_SQ_TEX_1                                       0x00000001
1543
1544 #define REG_A2XX_SQ_TEX_2                                       0x00000002
1545 #define A2XX_SQ_TEX_2_WIDTH__MASK                               0x00001fff
1546 #define A2XX_SQ_TEX_2_WIDTH__SHIFT                              0
1547 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val)
1548 {
1549         return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK;
1550 }
1551 #define A2XX_SQ_TEX_2_HEIGHT__MASK                              0x03ffe000
1552 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT                             13
1553 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val)
1554 {
1555         return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK;
1556 }
1557
1558 #define REG_A2XX_SQ_TEX_3                                       0x00000003
1559 #define A2XX_SQ_TEX_3_SWIZ_X__MASK                              0x0000000e
1560 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT                             1
1561 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val)
1562 {
1563         return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK;
1564 }
1565 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK                              0x00000070
1566 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT                             4
1567 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val)
1568 {
1569         return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK;
1570 }
1571 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK                              0x00000380
1572 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT                             7
1573 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val)
1574 {
1575         return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK;
1576 }
1577 #define A2XX_SQ_TEX_3_SWIZ_W__MASK                              0x00001c00
1578 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT                             10
1579 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val)
1580 {
1581         return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK;
1582 }
1583 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK                       0x00180000
1584 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT                      19
1585 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val)
1586 {
1587         return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK;
1588 }
1589 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK                       0x00600000
1590 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT                      21
1591 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val)
1592 {
1593         return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK;
1594 }
1595
1596
1597 #endif /* A2XX_XML */