kernel/drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41 #include <linux/locallock.h>
  42
  43 static bool
  44 format_is_yuv(uint32_t format)
  45 {
  46         switch (format) {
  47         case DRM_FORMAT_YUYV:
  48         case DRM_FORMAT_UYVY:
  49         case DRM_FORMAT_VYUY:
  50         case DRM_FORMAT_YVYU:
  51                 return true;
  52         default:
  53                 return false;
  54         }
  55 }
  56
  57 static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  58                               int usecs)
  59 {
  60         /* paranoia */
  61         if (!adjusted_mode->crtc_htotal)
  62                 return 1;
  63
  64         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  65                             1000 * adjusted_mode->crtc_htotal);
  66 }
  67
  68 static DEFINE_LOCAL_IRQ_LOCK(pipe_update_lock);
  69
  70 /**
  71  * intel_pipe_update_start() - start update of a set of display registers
  72  * @crtc: the crtc of which the registers are going to be updated
  73  * @start_vbl_count: vblank counter return pointer used for error checking
  74  *
  75  * Mark the start of an update to pipe registers that should be updated
  76  * atomically regarding vblank. If the next vblank will happens within
  77  * the next 100 us, this function waits until the vblank passes.
  78  *
  79  * After a successful call to this function, interrupts will be disabled
  80  * until a subsequent call to intel_pipe_update_end(). That is done to
  81  * avoid random delays. The value written to @start_vbl_count should be
  82  * supplied to intel_pipe_update_end() for error checking.
  83  */
  84 void intel_pipe_update_start(struct intel_crtc *crtc)
  85 {
  86         struct drm_device *dev = crtc->base.dev;
  87         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  88         enum pipe pipe = crtc->pipe;
  89         long timeout = msecs_to_jiffies_timeout(1);
  90         int scanline, min, max, vblank_start;
  91         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  92         DEFINE_WAIT(wait);
  93
  94         vblank_start = adjusted_mode->crtc_vblank_start;
  95         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  96                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  97
  98         /* FIXME needs to be calibrated sensibly */
  99         min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
 100         max = vblank_start - 1;
 101
 102         local_lock_irq(pipe_update_lock);
 103
 104         if (min <= 0 || max <= 0)
 105                 return;
 106
 107         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 108                 return;
 109
 110         crtc->debug.min_vbl = min;
 111         crtc->debug.max_vbl = max;
 112         trace_i915_pipe_update_start(crtc);
 113
 114         for (;;) {
 115                 /*
 116                  * prepare_to_wait() has a memory barrier, which guarantees
 117                  * other CPUs can see the task state update by the time we
 118                  * read the scanline.
 119                  */
 120                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 121
 122                 scanline = intel_get_crtc_scanline(crtc);
 123                 if (scanline < min || scanline > max)
 124                         break;
 125
 126                 if (timeout <= 0) {
 127                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 128                                   pipe_name(crtc->pipe));
 129                         break;
 130                 }
 131
 132                 local_unlock_irq(pipe_update_lock);
 133
 134                 timeout = schedule_timeout(timeout);
 135
 136                 local_lock_irq(pipe_update_lock);
 137         }
 138
 139         finish_wait(wq, &wait);
 140
 141         drm_crtc_vblank_put(&crtc->base);
 142
 143         crtc->debug.scanline_start = scanline;
 144         crtc->debug.start_vbl_time = ktime_get();
 145         crtc->debug.start_vbl_count =
 146                 dev->driver->get_vblank_counter(dev, pipe);
 147
 148         trace_i915_pipe_update_vblank_evaded(crtc);
 149 }
 150
 151 /**
 152  * intel_pipe_update_end() - end update of a set of display registers
 153  * @crtc: the crtc of which the registers were updated
 154  * @start_vbl_count: start vblank counter (used for error checking)
 155  *
 156  * Mark the end of an update started with intel_pipe_update_start(). This
 157  * re-enables interrupts and verifies the update was actually completed
 158  * before a vblank using the value of @start_vbl_count.
 159  */
 160 void intel_pipe_update_end(struct intel_crtc *crtc)
 161 {
 162         struct drm_device *dev = crtc->base.dev;
 163         enum pipe pipe = crtc->pipe;
 164         int scanline_end = intel_get_crtc_scanline(crtc);
 165         u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 166         ktime_t end_vbl_time = ktime_get();
 167
 168         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 169
 170         local_unlock_irq(pipe_update_lock);
 171
 172         if (crtc->debug.start_vbl_count &&
 173             crtc->debug.start_vbl_count != end_vbl_count) {
 174                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 175                           pipe_name(pipe), crtc->debug.start_vbl_count,
 176                           end_vbl_count,
 177                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 178                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 179                           crtc->debug.scanline_start, scanline_end);
 180         }
 181 }
 182
 183 static void
 184 skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 185                  struct drm_framebuffer *fb,
 186                  int crtc_x, int crtc_y,
 187                  unsigned int crtc_w, unsigned int crtc_h,
 188                  uint32_t x, uint32_t y,
 189                  uint32_t src_w, uint32_t src_h)
 190 {
 191         struct drm_device *dev = drm_plane->dev;
 192         struct drm_i915_private *dev_priv = dev->dev_private;
 193         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 194         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 195         const int pipe = intel_plane->pipe;
 196         const int plane = intel_plane->plane + 1;
 197         u32 plane_ctl, stride_div, stride;
 198         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 199         const struct drm_intel_sprite_colorkey *key =
 200                 &to_intel_plane_state(drm_plane->state)->ckey;
 201         unsigned long surf_addr;
 202         u32 tile_height, plane_offset, plane_size;
 203         unsigned int rotation;
 204         int x_offset, y_offset;
 205         struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
 206         int scaler_id;
 207
 208         plane_ctl = PLANE_CTL_ENABLE |
 209                 PLANE_CTL_PIPE_GAMMA_ENABLE |
 210                 PLANE_CTL_PIPE_CSC_ENABLE;
 211
 212         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
 213         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
 214
 215         rotation = drm_plane->state->rotation;
 216         plane_ctl |= skl_plane_ctl_rotation(rotation);
 217
 218         intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
 219                                        pixel_size, true,
 220                                        src_w != crtc_w || src_h != crtc_h);
 221
 222         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
 223                                                fb->pixel_format);
 224
 225         scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id;
 226
 227         /* Sizes are 0 based */
 228         src_w--;
 229         src_h--;
 230         crtc_w--;
 231         crtc_h--;
 232
 233         if (key->flags) {
 234                 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
 235                 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
 236                 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
 237         }
 238
 239         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 240                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 241         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 242                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 243
 244         surf_addr = intel_plane_obj_offset(intel_plane, obj, 0);
 245
 246         if (intel_rotation_90_or_270(rotation)) {
 247                 /* stride: Surface height in tiles */
 248                 tile_height = intel_tile_height(dev, fb->pixel_format,
 249                                                 fb->modifier[0], 0);
 250                 stride = DIV_ROUND_UP(fb->height, tile_height);
 251                 plane_size = (src_w << 16) | src_h;
 252                 x_offset = stride * tile_height - y - (src_h + 1);
 253                 y_offset = x;
 254         } else {
 255                 stride = fb->pitches[0] / stride_div;
 256                 plane_size = (src_h << 16) | src_w;
 257                 x_offset = x;
 258                 y_offset = y;
 259         }
 260         plane_offset = y_offset << 16 | x_offset;
 261
 262         I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
 263         I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
 264         I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
 265
 266         /* program plane scaler */
 267         if (scaler_id >= 0) {
 268                 uint32_t ps_ctrl = 0;
 269
 270                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
 271                         PS_PLANE_SEL(plane));
 272                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
 273                         crtc_state->scaler_state.scalers[scaler_id].mode;
 274                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
 275                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 276                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 277                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
 278                         ((crtc_w + 1) << 16)|(crtc_h + 1));
 279
 280                 I915_WRITE(PLANE_POS(pipe, plane), 0);
 281         } else {
 282                 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
 283         }
 284
 285         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
 286         I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
 287         POSTING_READ(PLANE_SURF(pipe, plane));
 288 }
 289
 290 static void
 291 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 292 {
 293         struct drm_device *dev = dplane->dev;
 294         struct drm_i915_private *dev_priv = dev->dev_private;
 295         struct intel_plane *intel_plane = to_intel_plane(dplane);
 296         const int pipe = intel_plane->pipe;
 297         const int plane = intel_plane->plane + 1;
 298
 299         I915_WRITE(PLANE_CTL(pipe, plane), 0);
 300
 301         I915_WRITE(PLANE_SURF(pipe, plane), 0);
 302         POSTING_READ(PLANE_SURF(pipe, plane));
 303
 304         intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
 305 }
 306
 307 static void
 308 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 309 {
 310         struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
 311         int plane = intel_plane->plane;
 312
 313         /* Seems RGB data bypasses the CSC always */
 314         if (!format_is_yuv(format))
 315                 return;
 316
 317         /*
 318          * BT.601 limited range YCbCr -> full range RGB
 319          *
 320          * |r|   | 6537 4769     0|   |cr  |
 321          * |g| = |-3330 4769 -1605| x |y-64|
 322          * |b|   |    0 4769  8263|   |cb  |
 323          *
 324          * Cb and Cr apparently come in as signed already, so no
 325          * need for any offset. For Y we need to remove the offset.
 326          */
 327         I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 328         I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 329         I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 330
 331         I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
 332         I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
 333         I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
 334         I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
 335         I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
 336
 337         I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 338         I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 339         I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 340
 341         I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 342         I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 343         I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 344 }
 345
 346 static void
 347 vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 348                  struct drm_framebuffer *fb,
 349                  int crtc_x, int crtc_y,
 350                  unsigned int crtc_w, unsigned int crtc_h,
 351                  uint32_t x, uint32_t y,
 352                  uint32_t src_w, uint32_t src_h)
 353 {
 354         struct drm_device *dev = dplane->dev;
 355         struct drm_i915_private *dev_priv = dev->dev_private;
 356         struct intel_plane *intel_plane = to_intel_plane(dplane);
 357         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 358         int pipe = intel_plane->pipe;
 359         int plane = intel_plane->plane;
 360         u32 sprctl;
 361         unsigned long sprsurf_offset, linear_offset;
 362         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 363         const struct drm_intel_sprite_colorkey *key =
 364                 &to_intel_plane_state(dplane->state)->ckey;
 365
 366         sprctl = SP_ENABLE;
 367
 368         switch (fb->pixel_format) {
 369         case DRM_FORMAT_YUYV:
 370                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 371                 break;
 372         case DRM_FORMAT_YVYU:
 373                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 374                 break;
 375         case DRM_FORMAT_UYVY:
 376                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 377                 break;
 378         case DRM_FORMAT_VYUY:
 379                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 380                 break;
 381         case DRM_FORMAT_RGB565:
 382                 sprctl |= SP_FORMAT_BGR565;
 383                 break;
 384         case DRM_FORMAT_XRGB8888:
 385                 sprctl |= SP_FORMAT_BGRX8888;
 386                 break;
 387         case DRM_FORMAT_ARGB8888:
 388                 sprctl |= SP_FORMAT_BGRA8888;
 389                 break;
 390         case DRM_FORMAT_XBGR2101010:
 391                 sprctl |= SP_FORMAT_RGBX1010102;
 392                 break;
 393         case DRM_FORMAT_ABGR2101010:
 394                 sprctl |= SP_FORMAT_RGBA1010102;
 395                 break;
 396         case DRM_FORMAT_XBGR8888:
 397                 sprctl |= SP_FORMAT_RGBX8888;
 398                 break;
 399         case DRM_FORMAT_ABGR8888:
 400                 sprctl |= SP_FORMAT_RGBA8888;
 401                 break;
 402         default:
 403                 /*
 404                  * If we get here one of the upper layers failed to filter
 405                  * out the unsupported plane formats
 406                  */
 407                 BUG();
 408                 break;
 409         }
 410
 411         /*
 412          * Enable gamma to match primary/cursor plane behaviour.
 413          * FIXME should be user controllable via propertiesa.
 414          */
 415         sprctl |= SP_GAMMA_ENABLE;
 416
 417         if (obj->tiling_mode != I915_TILING_NONE)
 418                 sprctl |= SP_TILED;
 419
 420         /* Sizes are 0 based */
 421         src_w--;
 422         src_h--;
 423         crtc_w--;
 424         crtc_h--;
 425
 426         linear_offset = y * fb->pitches[0] + x * pixel_size;
 427         sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
 428                                                         &x, &y,
 429                                                         obj->tiling_mode,
 430                                                         pixel_size,
 431                                                         fb->pitches[0]);
 432         linear_offset -= sprsurf_offset;
 433
 434         if (dplane->state->rotation == BIT(DRM_ROTATE_180)) {
 435                 sprctl |= SP_ROTATE_180;
 436
 437                 x += src_w;
 438                 y += src_h;
 439                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
 440         }
 441
 442         if (key->flags) {
 443                 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
 444                 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
 445                 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
 446         }
 447
 448         if (key->flags & I915_SET_COLORKEY_SOURCE)
 449                 sprctl |= SP_SOURCE_KEY;
 450
 451         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
 452                 chv_update_csc(intel_plane, fb->pixel_format);
 453
 454         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 455         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 456
 457         if (obj->tiling_mode != I915_TILING_NONE)
 458                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 459         else
 460                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 461
 462         I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
 463
 464         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 465         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 466         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
 467                    sprsurf_offset);
 468         POSTING_READ(SPSURF(pipe, plane));
 469 }
 470
 471 static void
 472 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 473 {
 474         struct drm_device *dev = dplane->dev;
 475         struct drm_i915_private *dev_priv = dev->dev_private;
 476         struct intel_plane *intel_plane = to_intel_plane(dplane);
 477         int pipe = intel_plane->pipe;
 478         int plane = intel_plane->plane;
 479
 480         I915_WRITE(SPCNTR(pipe, plane), 0);
 481
 482         I915_WRITE(SPSURF(pipe, plane), 0);
 483         POSTING_READ(SPSURF(pipe, plane));
 484 }
 485
 486 static void
 487 ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 488                  struct drm_framebuffer *fb,
 489                  int crtc_x, int crtc_y,
 490                  unsigned int crtc_w, unsigned int crtc_h,
 491                  uint32_t x, uint32_t y,
 492                  uint32_t src_w, uint32_t src_h)
 493 {
 494         struct drm_device *dev = plane->dev;
 495         struct drm_i915_private *dev_priv = dev->dev_private;
 496         struct intel_plane *intel_plane = to_intel_plane(plane);
 497         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 498         enum pipe pipe = intel_plane->pipe;
 499         u32 sprctl, sprscale = 0;
 500         unsigned long sprsurf_offset, linear_offset;
 501         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 502         const struct drm_intel_sprite_colorkey *key =
 503                 &to_intel_plane_state(plane->state)->ckey;
 504
 505         sprctl = SPRITE_ENABLE;
 506
 507         switch (fb->pixel_format) {
 508         case DRM_FORMAT_XBGR8888:
 509                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 510                 break;
 511         case DRM_FORMAT_XRGB8888:
 512                 sprctl |= SPRITE_FORMAT_RGBX888;
 513                 break;
 514         case DRM_FORMAT_YUYV:
 515                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 516                 break;
 517         case DRM_FORMAT_YVYU:
 518                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 519                 break;
 520         case DRM_FORMAT_UYVY:
 521                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 522                 break;
 523         case DRM_FORMAT_VYUY:
 524                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 525                 break;
 526         default:
 527                 BUG();
 528         }
 529
 530         /*
 531          * Enable gamma to match primary/cursor plane behaviour.
 532          * FIXME should be user controllable via propertiesa.
 533          */
 534         sprctl |= SPRITE_GAMMA_ENABLE;
 535
 536         if (obj->tiling_mode != I915_TILING_NONE)
 537                 sprctl |= SPRITE_TILED;
 538
 539         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 540                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 541         else
 542                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 543
 544         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 545                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 546
 547         intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
 548                                        true,
 549                                        src_w != crtc_w || src_h != crtc_h);
 550
 551         /* Sizes are 0 based */
 552         src_w--;
 553         src_h--;
 554         crtc_w--;
 555         crtc_h--;
 556
 557         if (crtc_w != src_w || crtc_h != src_h)
 558                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 559
 560         linear_offset = y * fb->pitches[0] + x * pixel_size;
 561         sprsurf_offset =
 562                 intel_gen4_compute_page_offset(dev_priv,
 563                                                &x, &y, obj->tiling_mode,
 564                                                pixel_size, fb->pitches[0]);
 565         linear_offset -= sprsurf_offset;
 566
 567         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
 568                 sprctl |= SPRITE_ROTATE_180;
 569
 570                 /* HSW and BDW does this automagically in hardware */
 571                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
 572                         x += src_w;
 573                         y += src_h;
 574                         linear_offset += src_h * fb->pitches[0] +
 575                                 src_w * pixel_size;
 576                 }
 577         }
 578
 579         if (key->flags) {
 580                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
 581                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
 582                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
 583         }
 584
 585         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 586                 sprctl |= SPRITE_DEST_KEY;
 587         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 588                 sprctl |= SPRITE_SOURCE_KEY;
 589
 590         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 591         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 592
 593         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 594          * register */
 595         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 596                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 597         else if (obj->tiling_mode != I915_TILING_NONE)
 598                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 599         else
 600                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 601
 602         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 603         if (intel_plane->can_scale)
 604                 I915_WRITE(SPRSCALE(pipe), sprscale);
 605         I915_WRITE(SPRCTL(pipe), sprctl);
 606         I915_WRITE(SPRSURF(pipe),
 607                    i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
 608         POSTING_READ(SPRSURF(pipe));
 609 }
 610
 611 static void
 612 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 613 {
 614         struct drm_device *dev = plane->dev;
 615         struct drm_i915_private *dev_priv = dev->dev_private;
 616         struct intel_plane *intel_plane = to_intel_plane(plane);
 617         int pipe = intel_plane->pipe;
 618
 619         I915_WRITE(SPRCTL(pipe), 0);
 620         /* Can't leave the scaler enabled... */
 621         if (intel_plane->can_scale)
 622                 I915_WRITE(SPRSCALE(pipe), 0);
 623
 624         I915_WRITE(SPRSURF(pipe), 0);
 625         POSTING_READ(SPRSURF(pipe));
 626 }
 627
 628 static void
 629 ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 630                  struct drm_framebuffer *fb,
 631                  int crtc_x, int crtc_y,
 632                  unsigned int crtc_w, unsigned int crtc_h,
 633                  uint32_t x, uint32_t y,
 634                  uint32_t src_w, uint32_t src_h)
 635 {
 636         struct drm_device *dev = plane->dev;
 637         struct drm_i915_private *dev_priv = dev->dev_private;
 638         struct intel_plane *intel_plane = to_intel_plane(plane);
 639         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 640         int pipe = intel_plane->pipe;
 641         unsigned long dvssurf_offset, linear_offset;
 642         u32 dvscntr, dvsscale;
 643         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 644         const struct drm_intel_sprite_colorkey *key =
 645                 &to_intel_plane_state(plane->state)->ckey;
 646
 647         dvscntr = DVS_ENABLE;
 648
 649         switch (fb->pixel_format) {
 650         case DRM_FORMAT_XBGR8888:
 651                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 652                 break;
 653         case DRM_FORMAT_XRGB8888:
 654                 dvscntr |= DVS_FORMAT_RGBX888;
 655                 break;
 656         case DRM_FORMAT_YUYV:
 657                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 658                 break;
 659         case DRM_FORMAT_YVYU:
 660                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 661                 break;
 662         case DRM_FORMAT_UYVY:
 663                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 664                 break;
 665         case DRM_FORMAT_VYUY:
 666                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 667                 break;
 668         default:
 669                 BUG();
 670         }
 671
 672         /*
 673          * Enable gamma to match primary/cursor plane behaviour.
 674          * FIXME should be user controllable via propertiesa.
 675          */
 676         dvscntr |= DVS_GAMMA_ENABLE;
 677
 678         if (obj->tiling_mode != I915_TILING_NONE)
 679                 dvscntr |= DVS_TILED;
 680
 681         if (IS_GEN6(dev))
 682                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 683
 684         intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
 685                                        pixel_size, true,
 686                                        src_w != crtc_w || src_h != crtc_h);
 687
 688         /* Sizes are 0 based */
 689         src_w--;
 690         src_h--;
 691         crtc_w--;
 692         crtc_h--;
 693
 694         dvsscale = 0;
 695         if (crtc_w != src_w || crtc_h != src_h)
 696                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 697
 698         linear_offset = y * fb->pitches[0] + x * pixel_size;
 699         dvssurf_offset =
 700                 intel_gen4_compute_page_offset(dev_priv,
 701                                                &x, &y, obj->tiling_mode,
 702                                                pixel_size, fb->pitches[0]);
 703         linear_offset -= dvssurf_offset;
 704
 705         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
 706                 dvscntr |= DVS_ROTATE_180;
 707
 708                 x += src_w;
 709                 y += src_h;
 710                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
 711         }
 712
 713         if (key->flags) {
 714                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
 715                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
 716                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
 717         }
 718
 719         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 720                 dvscntr |= DVS_DEST_KEY;
 721         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 722                 dvscntr |= DVS_SOURCE_KEY;
 723
 724         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 725         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 726
 727         if (obj->tiling_mode != I915_TILING_NONE)
 728                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 729         else
 730                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 731
 732         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 733         I915_WRITE(DVSSCALE(pipe), dvsscale);
 734         I915_WRITE(DVSCNTR(pipe), dvscntr);
 735         I915_WRITE(DVSSURF(pipe),
 736                    i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
 737         POSTING_READ(DVSSURF(pipe));
 738 }
 739
 740 static void
 741 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 742 {
 743         struct drm_device *dev = plane->dev;
 744         struct drm_i915_private *dev_priv = dev->dev_private;
 745         struct intel_plane *intel_plane = to_intel_plane(plane);
 746         int pipe = intel_plane->pipe;
 747
 748         I915_WRITE(DVSCNTR(pipe), 0);
 749         /* Disable the scaler */
 750         I915_WRITE(DVSSCALE(pipe), 0);
 751
 752         I915_WRITE(DVSSURF(pipe), 0);
 753         POSTING_READ(DVSSURF(pipe));
 754 }
 755
 756 static int
 757 intel_check_sprite_plane(struct drm_plane *plane,
 758                          struct intel_crtc_state *crtc_state,
 759                          struct intel_plane_state *state)
 760 {
 761         struct drm_device *dev = plane->dev;
 762         struct drm_crtc *crtc = state->base.crtc;
 763         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 764         struct intel_plane *intel_plane = to_intel_plane(plane);
 765         struct drm_framebuffer *fb = state->base.fb;
 766         int crtc_x, crtc_y;
 767         unsigned int crtc_w, crtc_h;
 768         uint32_t src_x, src_y, src_w, src_h;
 769         struct drm_rect *src = &state->src;
 770         struct drm_rect *dst = &state->dst;
 771         const struct drm_rect *clip = &state->clip;
 772         int hscale, vscale;
 773         int max_scale, min_scale;
 774         bool can_scale;
 775         int pixel_size;
 776
 777         if (!fb) {
 778                 state->visible = false;
 779                 return 0;
 780         }
 781
 782         /* Don't modify another pipe's plane */
 783         if (intel_plane->pipe != intel_crtc->pipe) {
 784                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 785                 return -EINVAL;
 786         }
 787
 788         /* FIXME check all gen limits */
 789         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 790                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 791                 return -EINVAL;
 792         }
 793
 794         /* setup can_scale, min_scale, max_scale */
 795         if (INTEL_INFO(dev)->gen >= 9) {
 796                 /* use scaler when colorkey is not required */
 797                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 798                         can_scale = 1;
 799                         min_scale = 1;
 800                         max_scale = skl_max_scale(intel_crtc, crtc_state);
 801                 } else {
 802                         can_scale = 0;
 803                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 804                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 805                 }
 806         } else {
 807                 can_scale = intel_plane->can_scale;
 808                 max_scale = intel_plane->max_downscale << 16;
 809                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
 810         }
 811
 812         /*
 813          * FIXME the following code does a bunch of fuzzy adjustments to the
 814          * coordinates and sizes. We probably need some way to decide whether
 815          * more strict checking should be done instead.
 816          */
 817         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 818                         state->base.rotation);
 819
 820         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 821         BUG_ON(hscale < 0);
 822
 823         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 824         BUG_ON(vscale < 0);
 825
 826         state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 827
 828         crtc_x = dst->x1;
 829         crtc_y = dst->y1;
 830         crtc_w = drm_rect_width(dst);
 831         crtc_h = drm_rect_height(dst);
 832
 833         if (state->visible) {
 834                 /* check again in case clipping clamped the results */
 835                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 836                 if (hscale < 0) {
 837                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 838                         drm_rect_debug_print(src, true);
 839                         drm_rect_debug_print(dst, false);
 840
 841                         return hscale;
 842                 }
 843
 844                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 845                 if (vscale < 0) {
 846                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 847                         drm_rect_debug_print(src, true);
 848                         drm_rect_debug_print(dst, false);
 849
 850                         return vscale;
 851                 }
 852
 853                 /* Make the source viewport size an exact multiple of the scaling factors. */
 854                 drm_rect_adjust_size(src,
 855                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 856                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 857
 858                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 859                                     state->base.rotation);
 860
 861                 /* sanity check to make sure the src viewport wasn't enlarged */
 862                 WARN_ON(src->x1 < (int) state->base.src_x ||
 863                         src->y1 < (int) state->base.src_y ||
 864                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 865                         src->y2 > (int) state->base.src_y + state->base.src_h);
 866
 867                 /*
 868                  * Hardware doesn't handle subpixel coordinates.
 869                  * Adjust to (macro)pixel boundary, but be careful not to
 870                  * increase the source viewport size, because that could
 871                  * push the downscaling factor out of bounds.
 872                  */
 873                 src_x = src->x1 >> 16;
 874                 src_w = drm_rect_width(src) >> 16;
 875                 src_y = src->y1 >> 16;
 876                 src_h = drm_rect_height(src) >> 16;
 877
 878                 if (format_is_yuv(fb->pixel_format)) {
 879                         src_x &= ~1;
 880                         src_w &= ~1;
 881
 882                         /*
 883                          * Must keep src and dst the
 884                          * same if we can't scale.
 885                          */
 886                         if (!can_scale)
 887                                 crtc_w &= ~1;
 888
 889                         if (crtc_w == 0)
 890                                 state->visible = false;
 891                 }
 892         }
 893
 894         /* Check size restrictions when scaling */
 895         if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
 896                 unsigned int width_bytes;
 897
 898                 WARN_ON(!can_scale);
 899
 900                 /* FIXME interlacing min height is 6 */
 901
 902                 if (crtc_w < 3 || crtc_h < 3)
 903                         state->visible = false;
 904
 905                 if (src_w < 3 || src_h < 3)
 906                         state->visible = false;
 907
 908                 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 909                 width_bytes = ((src_x * pixel_size) & 63) +
 910                                         src_w * pixel_size;
 911
 912                 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
 913                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 914                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 915                         return -EINVAL;
 916                 }
 917         }
 918
 919         if (state->visible) {
 920                 src->x1 = src_x << 16;
 921                 src->x2 = (src_x + src_w) << 16;
 922                 src->y1 = src_y << 16;
 923                 src->y2 = (src_y + src_h) << 16;
 924         }
 925
 926         dst->x1 = crtc_x;
 927         dst->x2 = crtc_x + crtc_w;
 928         dst->y1 = crtc_y;
 929         dst->y2 = crtc_y + crtc_h;
 930
 931         return 0;
 932 }
 933
 934 static void
 935 intel_commit_sprite_plane(struct drm_plane *plane,
 936                           struct intel_plane_state *state)
 937 {
 938         struct drm_crtc *crtc = state->base.crtc;
 939         struct intel_plane *intel_plane = to_intel_plane(plane);
 940         struct drm_framebuffer *fb = state->base.fb;
 941
 942         crtc = crtc ? crtc : plane->crtc;
 943
 944         if (!crtc->state->active)
 945                 return;
 946
 947         if (state->visible) {
 948                 intel_plane->update_plane(plane, crtc, fb,
 949                                           state->dst.x1, state->dst.y1,
 950                                           drm_rect_width(&state->dst),
 951                                           drm_rect_height(&state->dst),
 952                                           state->src.x1 >> 16,
 953                                           state->src.y1 >> 16,
 954                                           drm_rect_width(&state->src) >> 16,
 955                                           drm_rect_height(&state->src) >> 16);
 956         } else {
 957                 intel_plane->disable_plane(plane, crtc);
 958         }
 959 }
 960
 961 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 962                               struct drm_file *file_priv)
 963 {
 964         struct drm_intel_sprite_colorkey *set = data;
 965         struct drm_plane *plane;
 966         struct drm_plane_state *plane_state;
 967         struct drm_atomic_state *state;
 968         struct drm_modeset_acquire_ctx ctx;
 969         int ret = 0;
 970
 971         /* Make sure we don't try to enable both src & dest simultaneously */
 972         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 973                 return -EINVAL;
 974
 975         if (IS_VALLEYVIEW(dev) &&
 976             set->flags & I915_SET_COLORKEY_DESTINATION)
 977                 return -EINVAL;
 978
 979         plane = drm_plane_find(dev, set->plane_id);
 980         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
 981                 return -ENOENT;
 982
 983         drm_modeset_acquire_init(&ctx, 0);
 984
 985         state = drm_atomic_state_alloc(plane->dev);
 986         if (!state) {
 987                 ret = -ENOMEM;
 988                 goto out;
 989         }
 990         state->acquire_ctx = &ctx;
 991
 992         while (1) {
 993                 plane_state = drm_atomic_get_plane_state(state, plane);
 994                 ret = PTR_ERR_OR_ZERO(plane_state);
 995                 if (!ret) {
 996                         to_intel_plane_state(plane_state)->ckey = *set;
 997                         ret = drm_atomic_commit(state);
 998                 }
 999
1000                 if (ret != -EDEADLK)
1001                         break;
1002
1003                 drm_atomic_state_clear(state);
1004                 drm_modeset_backoff(&ctx);
1005         }
1006
1007         if (ret)
1008                 drm_atomic_state_free(state);
1009
1010 out:
1011         drm_modeset_drop_locks(&ctx);
1012         drm_modeset_acquire_fini(&ctx);
1013         return ret;
1014 }
1015
1016 static const uint32_t ilk_plane_formats[] = {
1017         DRM_FORMAT_XRGB8888,
1018         DRM_FORMAT_YUYV,
1019         DRM_FORMAT_YVYU,
1020         DRM_FORMAT_UYVY,
1021         DRM_FORMAT_VYUY,
1022 };
1023
1024 static const uint32_t snb_plane_formats[] = {
1025         DRM_FORMAT_XBGR8888,
1026         DRM_FORMAT_XRGB8888,
1027         DRM_FORMAT_YUYV,
1028         DRM_FORMAT_YVYU,
1029         DRM_FORMAT_UYVY,
1030         DRM_FORMAT_VYUY,
1031 };
1032
1033 static const uint32_t vlv_plane_formats[] = {
1034         DRM_FORMAT_RGB565,
1035         DRM_FORMAT_ABGR8888,
1036         DRM_FORMAT_ARGB8888,
1037         DRM_FORMAT_XBGR8888,
1038         DRM_FORMAT_XRGB8888,
1039         DRM_FORMAT_XBGR2101010,
1040         DRM_FORMAT_ABGR2101010,
1041         DRM_FORMAT_YUYV,
1042         DRM_FORMAT_YVYU,
1043         DRM_FORMAT_UYVY,
1044         DRM_FORMAT_VYUY,
1045 };
1046
1047 static uint32_t skl_plane_formats[] = {
1048         DRM_FORMAT_RGB565,
1049         DRM_FORMAT_ABGR8888,
1050         DRM_FORMAT_ARGB8888,
1051         DRM_FORMAT_XBGR8888,
1052         DRM_FORMAT_XRGB8888,
1053         DRM_FORMAT_YUYV,
1054         DRM_FORMAT_YVYU,
1055         DRM_FORMAT_UYVY,
1056         DRM_FORMAT_VYUY,
1057 };
1058
1059 int
1060 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1061 {
1062         struct intel_plane *intel_plane;
1063         struct intel_plane_state *state;
1064         unsigned long possible_crtcs;
1065         const uint32_t *plane_formats;
1066         int num_plane_formats;
1067         int ret;
1068
1069         if (INTEL_INFO(dev)->gen < 5)
1070                 return -ENODEV;
1071
1072         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1073         if (!intel_plane)
1074                 return -ENOMEM;
1075
1076         state = intel_create_plane_state(&intel_plane->base);
1077         if (!state) {
1078                 kfree(intel_plane);
1079                 return -ENOMEM;
1080         }
1081         intel_plane->base.state = &state->base;
1082
1083         switch (INTEL_INFO(dev)->gen) {
1084         case 5:
1085         case 6:
1086                 intel_plane->can_scale = true;
1087                 intel_plane->max_downscale = 16;
1088                 intel_plane->update_plane = ilk_update_plane;
1089                 intel_plane->disable_plane = ilk_disable_plane;
1090
1091                 if (IS_GEN6(dev)) {
1092                         plane_formats = snb_plane_formats;
1093                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1094                 } else {
1095                         plane_formats = ilk_plane_formats;
1096                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1097                 }
1098                 break;
1099
1100         case 7:
1101         case 8:
1102                 if (IS_IVYBRIDGE(dev)) {
1103                         intel_plane->can_scale = true;
1104                         intel_plane->max_downscale = 2;
1105                 } else {
1106                         intel_plane->can_scale = false;
1107                         intel_plane->max_downscale = 1;
1108                 }
1109
1110                 if (IS_VALLEYVIEW(dev)) {
1111                         intel_plane->update_plane = vlv_update_plane;
1112                         intel_plane->disable_plane = vlv_disable_plane;
1113
1114                         plane_formats = vlv_plane_formats;
1115                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1116                 } else {
1117                         intel_plane->update_plane = ivb_update_plane;
1118                         intel_plane->disable_plane = ivb_disable_plane;
1119
1120                         plane_formats = snb_plane_formats;
1121                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1122                 }
1123                 break;
1124         case 9:
1125                 intel_plane->can_scale = true;
1126                 intel_plane->update_plane = skl_update_plane;
1127                 intel_plane->disable_plane = skl_disable_plane;
1128                 state->scaler_id = -1;
1129
1130                 plane_formats = skl_plane_formats;
1131                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1132                 break;
1133         default:
1134                 kfree(intel_plane);
1135                 return -ENODEV;
1136         }
1137
1138         intel_plane->pipe = pipe;
1139         intel_plane->plane = plane;
1140         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1141         intel_plane->check_plane = intel_check_sprite_plane;
1142         intel_plane->commit_plane = intel_commit_sprite_plane;
1143         possible_crtcs = (1 << pipe);
1144         ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1145                                        &intel_plane_funcs,
1146                                        plane_formats, num_plane_formats,
1147                                        DRM_PLANE_TYPE_OVERLAY);
1148         if (ret) {
1149                 kfree(intel_plane);
1150                 goto out;
1151         }
1152
1153         intel_create_rotation_property(dev, intel_plane);
1154
1155         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1156
1157 out:
1158         return ret;
1159 }