kernel/drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * RC6 is a special power stage which allows the GPU to enter an very
  36  * low-voltage mode when idle, using down to 0V while at this stage.  This
  37  * stage is entered automatically when the GPU is idle when RC6 support is
  38  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  39  *
  40  * There are different RC6 modes available in Intel GPU, which differentiate
  41  * among each other with the latency required to enter and leave RC6 and
  42  * voltage consumed by the GPU in different states.
  43  *
  44  * The combination of the following flags define which states GPU is allowed
  45  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  46  * RC6pp is deepest RC6. Their support by hardware varies according to the
  47  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  48  * which brings the most power savings; deeper states save more power, but
  49  * require higher latency to switch to and wake up.
  50  */
  51 #define INTEL_RC6_ENABLE                        (1<<0)
  52 #define INTEL_RC6p_ENABLE                       (1<<1)
  53 #define INTEL_RC6pp_ENABLE                      (1<<2)
  54
  55 static void bxt_init_clock_gating(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58
  59         /* WaDisableSDEUnitClockGating:bxt */
  60         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  61                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  62
  63         /*
  64          * FIXME:
  65          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  66          */
  67         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  68                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  69 }
  70
  71 static void i915_pineview_get_mem_freq(struct drm_device *dev)
  72 {
  73         struct drm_i915_private *dev_priv = dev->dev_private;
  74         u32 tmp;
  75
  76         tmp = I915_READ(CLKCFG);
  77
  78         switch (tmp & CLKCFG_FSB_MASK) {
  79         case CLKCFG_FSB_533:
  80                 dev_priv->fsb_freq = 533; /* 133*4 */
  81                 break;
  82         case CLKCFG_FSB_800:
  83                 dev_priv->fsb_freq = 800; /* 200*4 */
  84                 break;
  85         case CLKCFG_FSB_667:
  86                 dev_priv->fsb_freq =  667; /* 167*4 */
  87                 break;
  88         case CLKCFG_FSB_400:
  89                 dev_priv->fsb_freq = 400; /* 100*4 */
  90                 break;
  91         }
  92
  93         switch (tmp & CLKCFG_MEM_MASK) {
  94         case CLKCFG_MEM_533:
  95                 dev_priv->mem_freq = 533;
  96                 break;
  97         case CLKCFG_MEM_667:
  98                 dev_priv->mem_freq = 667;
  99                 break;
 100         case CLKCFG_MEM_800:
 101                 dev_priv->mem_freq = 800;
 102                 break;
 103         }
 104
 105         /* detect pineview DDR3 setting */
 106         tmp = I915_READ(CSHRDDR3CTL);
 107         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 108 }
 109
 110 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 111 {
 112         struct drm_i915_private *dev_priv = dev->dev_private;
 113         u16 ddrpll, csipll;
 114
 115         ddrpll = I915_READ16(DDRMPLL1);
 116         csipll = I915_READ16(CSIPLL0);
 117
 118         switch (ddrpll & 0xff) {
 119         case 0xc:
 120                 dev_priv->mem_freq = 800;
 121                 break;
 122         case 0x10:
 123                 dev_priv->mem_freq = 1066;
 124                 break;
 125         case 0x14:
 126                 dev_priv->mem_freq = 1333;
 127                 break;
 128         case 0x18:
 129                 dev_priv->mem_freq = 1600;
 130                 break;
 131         default:
 132                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 133                                  ddrpll & 0xff);
 134                 dev_priv->mem_freq = 0;
 135                 break;
 136         }
 137
 138         dev_priv->ips.r_t = dev_priv->mem_freq;
 139
 140         switch (csipll & 0x3ff) {
 141         case 0x00c:
 142                 dev_priv->fsb_freq = 3200;
 143                 break;
 144         case 0x00e:
 145                 dev_priv->fsb_freq = 3733;
 146                 break;
 147         case 0x010:
 148                 dev_priv->fsb_freq = 4266;
 149                 break;
 150         case 0x012:
 151                 dev_priv->fsb_freq = 4800;
 152                 break;
 153         case 0x014:
 154                 dev_priv->fsb_freq = 5333;
 155                 break;
 156         case 0x016:
 157                 dev_priv->fsb_freq = 5866;
 158                 break;
 159         case 0x018:
 160                 dev_priv->fsb_freq = 6400;
 161                 break;
 162         default:
 163                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 164                                  csipll & 0x3ff);
 165                 dev_priv->fsb_freq = 0;
 166                 break;
 167         }
 168
 169         if (dev_priv->fsb_freq == 3200) {
 170                 dev_priv->ips.c_m = 0;
 171         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 172                 dev_priv->ips.c_m = 1;
 173         } else {
 174                 dev_priv->ips.c_m = 2;
 175         }
 176 }
 177
 178 static const struct cxsr_latency cxsr_latency_table[] = {
 179         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 180         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 181         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 182         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 183         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 184
 185         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 186         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 187         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 188         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 189         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 190
 191         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 192         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 193         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 194         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 195         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 196
 197         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 198         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 199         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 200         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 201         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 202
 203         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 204         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 205         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 206         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 207         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 208
 209         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 210         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 211         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 212         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 213         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 214 };
 215
 216 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 217                                                          int is_ddr3,
 218                                                          int fsb,
 219                                                          int mem)
 220 {
 221         const struct cxsr_latency *latency;
 222         int i;
 223
 224         if (fsb == 0 || mem == 0)
 225                 return NULL;
 226
 227         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 228                 latency = &cxsr_latency_table[i];
 229                 if (is_desktop == latency->is_desktop &&
 230                     is_ddr3 == latency->is_ddr3 &&
 231                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 232                         return latency;
 233         }
 234
 235         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 236
 237         return NULL;
 238 }
 239
 240 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 241 {
 242         u32 val;
 243
 244         mutex_lock(&dev_priv->rps.hw_lock);
 245
 246         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 247         if (enable)
 248                 val &= ~FORCE_DDR_HIGH_FREQ;
 249         else
 250                 val |= FORCE_DDR_HIGH_FREQ;
 251         val &= ~FORCE_DDR_LOW_FREQ;
 252         val |= FORCE_DDR_FREQ_REQ_ACK;
 253         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 254
 255         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 256                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 257                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 258
 259         mutex_unlock(&dev_priv->rps.hw_lock);
 260 }
 261
 262 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 263 {
 264         u32 val;
 265
 266         mutex_lock(&dev_priv->rps.hw_lock);
 267
 268         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 269         if (enable)
 270                 val |= DSP_MAXFIFO_PM5_ENABLE;
 271         else
 272                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 273         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 274
 275         mutex_unlock(&dev_priv->rps.hw_lock);
 276 }
 277
 278 #define FW_WM(value, plane) \
 279         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 280
 281 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 282 {
 283         struct drm_device *dev = dev_priv->dev;
 284         u32 val;
 285
 286         if (IS_VALLEYVIEW(dev)) {
 287                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 288                 POSTING_READ(FW_BLC_SELF_VLV);
 289                 dev_priv->wm.vlv.cxsr = enable;
 290         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 291                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 292                 POSTING_READ(FW_BLC_SELF);
 293         } else if (IS_PINEVIEW(dev)) {
 294                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 295                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 296                 I915_WRITE(DSPFW3, val);
 297                 POSTING_READ(DSPFW3);
 298         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 299                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 300                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 301                 I915_WRITE(FW_BLC_SELF, val);
 302                 POSTING_READ(FW_BLC_SELF);
 303         } else if (IS_I915GM(dev)) {
 304                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 305                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 306                 I915_WRITE(INSTPM, val);
 307                 POSTING_READ(INSTPM);
 308         } else {
 309                 return;
 310         }
 311
 312         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 313                       enable ? "enabled" : "disabled");
 314 }
 315
 316
 317 /*
 318  * Latency for FIFO fetches is dependent on several factors:
 319  *   - memory configuration (speed, channels)
 320  *   - chipset
 321  *   - current MCH state
 322  * It can be fairly high in some situations, so here we assume a fairly
 323  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 324  * set this value too high, the FIFO will fetch frequently to stay full)
 325  * and power consumption (set it too low to save power and we might see
 326  * FIFO underruns and display "flicker").
 327  *
 328  * A value of 5us seems to be a good balance; safe for very low end
 329  * platforms but not overly aggressive on lower latency configs.
 330  */
 331 static const int pessimal_latency_ns = 5000;
 332
 333 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 334         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 335
 336 static int vlv_get_fifo_size(struct drm_device *dev,
 337                               enum pipe pipe, int plane)
 338 {
 339         struct drm_i915_private *dev_priv = dev->dev_private;
 340         int sprite0_start, sprite1_start, size;
 341
 342         switch (pipe) {
 343                 uint32_t dsparb, dsparb2, dsparb3;
 344         case PIPE_A:
 345                 dsparb = I915_READ(DSPARB);
 346                 dsparb2 = I915_READ(DSPARB2);
 347                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 348                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 349                 break;
 350         case PIPE_B:
 351                 dsparb = I915_READ(DSPARB);
 352                 dsparb2 = I915_READ(DSPARB2);
 353                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 354                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 355                 break;
 356         case PIPE_C:
 357                 dsparb2 = I915_READ(DSPARB2);
 358                 dsparb3 = I915_READ(DSPARB3);
 359                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 360                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 361                 break;
 362         default:
 363                 return 0;
 364         }
 365
 366         switch (plane) {
 367         case 0:
 368                 size = sprite0_start;
 369                 break;
 370         case 1:
 371                 size = sprite1_start - sprite0_start;
 372                 break;
 373         case 2:
 374                 size = 512 - 1 - sprite1_start;
 375                 break;
 376         default:
 377                 return 0;
 378         }
 379
 380         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 381                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 382                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 383                       size);
 384
 385         return size;
 386 }
 387
 388 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 389 {
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         uint32_t dsparb = I915_READ(DSPARB);
 392         int size;
 393
 394         size = dsparb & 0x7f;
 395         if (plane)
 396                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 397
 398         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 399                       plane ? "B" : "A", size);
 400
 401         return size;
 402 }
 403
 404 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 405 {
 406         struct drm_i915_private *dev_priv = dev->dev_private;
 407         uint32_t dsparb = I915_READ(DSPARB);
 408         int size;
 409
 410         size = dsparb & 0x1ff;
 411         if (plane)
 412                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 413         size >>= 1; /* Convert to cachelines */
 414
 415         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 416                       plane ? "B" : "A", size);
 417
 418         return size;
 419 }
 420
 421 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 422 {
 423         struct drm_i915_private *dev_priv = dev->dev_private;
 424         uint32_t dsparb = I915_READ(DSPARB);
 425         int size;
 426
 427         size = dsparb & 0x7f;
 428         size >>= 2; /* Convert to cachelines */
 429
 430         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 431                       plane ? "B" : "A",
 432                       size);
 433
 434         return size;
 435 }
 436
 437 /* Pineview has different values for various configs */
 438 static const struct intel_watermark_params pineview_display_wm = {
 439         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 440         .max_wm = PINEVIEW_MAX_WM,
 441         .default_wm = PINEVIEW_DFT_WM,
 442         .guard_size = PINEVIEW_GUARD_WM,
 443         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 444 };
 445 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 446         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 447         .max_wm = PINEVIEW_MAX_WM,
 448         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 449         .guard_size = PINEVIEW_GUARD_WM,
 450         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 451 };
 452 static const struct intel_watermark_params pineview_cursor_wm = {
 453         .fifo_size = PINEVIEW_CURSOR_FIFO,
 454         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 455         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 456         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 457         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 458 };
 459 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 460         .fifo_size = PINEVIEW_CURSOR_FIFO,
 461         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 462         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 463         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 464         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 465 };
 466 static const struct intel_watermark_params g4x_wm_info = {
 467         .fifo_size = G4X_FIFO_SIZE,
 468         .max_wm = G4X_MAX_WM,
 469         .default_wm = G4X_MAX_WM,
 470         .guard_size = 2,
 471         .cacheline_size = G4X_FIFO_LINE_SIZE,
 472 };
 473 static const struct intel_watermark_params g4x_cursor_wm_info = {
 474         .fifo_size = I965_CURSOR_FIFO,
 475         .max_wm = I965_CURSOR_MAX_WM,
 476         .default_wm = I965_CURSOR_DFT_WM,
 477         .guard_size = 2,
 478         .cacheline_size = G4X_FIFO_LINE_SIZE,
 479 };
 480 static const struct intel_watermark_params valleyview_wm_info = {
 481         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 482         .max_wm = VALLEYVIEW_MAX_WM,
 483         .default_wm = VALLEYVIEW_MAX_WM,
 484         .guard_size = 2,
 485         .cacheline_size = G4X_FIFO_LINE_SIZE,
 486 };
 487 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 488         .fifo_size = I965_CURSOR_FIFO,
 489         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 490         .default_wm = I965_CURSOR_DFT_WM,
 491         .guard_size = 2,
 492         .cacheline_size = G4X_FIFO_LINE_SIZE,
 493 };
 494 static const struct intel_watermark_params i965_cursor_wm_info = {
 495         .fifo_size = I965_CURSOR_FIFO,
 496         .max_wm = I965_CURSOR_MAX_WM,
 497         .default_wm = I965_CURSOR_DFT_WM,
 498         .guard_size = 2,
 499         .cacheline_size = I915_FIFO_LINE_SIZE,
 500 };
 501 static const struct intel_watermark_params i945_wm_info = {
 502         .fifo_size = I945_FIFO_SIZE,
 503         .max_wm = I915_MAX_WM,
 504         .default_wm = 1,
 505         .guard_size = 2,
 506         .cacheline_size = I915_FIFO_LINE_SIZE,
 507 };
 508 static const struct intel_watermark_params i915_wm_info = {
 509         .fifo_size = I915_FIFO_SIZE,
 510         .max_wm = I915_MAX_WM,
 511         .default_wm = 1,
 512         .guard_size = 2,
 513         .cacheline_size = I915_FIFO_LINE_SIZE,
 514 };
 515 static const struct intel_watermark_params i830_a_wm_info = {
 516         .fifo_size = I855GM_FIFO_SIZE,
 517         .max_wm = I915_MAX_WM,
 518         .default_wm = 1,
 519         .guard_size = 2,
 520         .cacheline_size = I830_FIFO_LINE_SIZE,
 521 };
 522 static const struct intel_watermark_params i830_bc_wm_info = {
 523         .fifo_size = I855GM_FIFO_SIZE,
 524         .max_wm = I915_MAX_WM/2,
 525         .default_wm = 1,
 526         .guard_size = 2,
 527         .cacheline_size = I830_FIFO_LINE_SIZE,
 528 };
 529 static const struct intel_watermark_params i845_wm_info = {
 530         .fifo_size = I830_FIFO_SIZE,
 531         .max_wm = I915_MAX_WM,
 532         .default_wm = 1,
 533         .guard_size = 2,
 534         .cacheline_size = I830_FIFO_LINE_SIZE,
 535 };
 536
 537 /**
 538  * intel_calculate_wm - calculate watermark level
 539  * @clock_in_khz: pixel clock
 540  * @wm: chip FIFO params
 541  * @pixel_size: display pixel size
 542  * @latency_ns: memory latency for the platform
 543  *
 544  * Calculate the watermark level (the level at which the display plane will
 545  * start fetching from memory again).  Each chip has a different display
 546  * FIFO size and allocation, so the caller needs to figure that out and pass
 547  * in the correct intel_watermark_params structure.
 548  *
 549  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 550  * on the pixel size.  When it reaches the watermark level, it'll start
 551  * fetching FIFO line sized based chunks from memory until the FIFO fills
 552  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 553  * will occur, and a display engine hang could result.
 554  */
 555 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 556                                         const struct intel_watermark_params *wm,
 557                                         int fifo_size,
 558                                         int pixel_size,
 559                                         unsigned long latency_ns)
 560 {
 561         long entries_required, wm_size;
 562
 563         /*
 564          * Note: we need to make sure we don't overflow for various clock &
 565          * latency values.
 566          * clocks go from a few thousand to several hundred thousand.
 567          * latency is usually a few thousand
 568          */
 569         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 570                 1000;
 571         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 572
 573         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 574
 575         wm_size = fifo_size - (entries_required + wm->guard_size);
 576
 577         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 578
 579         /* Don't promote wm_size to unsigned... */
 580         if (wm_size > (long)wm->max_wm)
 581                 wm_size = wm->max_wm;
 582         if (wm_size <= 0)
 583                 wm_size = wm->default_wm;
 584
 585         /*
 586          * Bspec seems to indicate that the value shouldn't be lower than
 587          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 588          * Lets go for 8 which is the burst size since certain platforms
 589          * already use a hardcoded 8 (which is what the spec says should be
 590          * done).
 591          */
 592         if (wm_size <= 8)
 593                 wm_size = 8;
 594
 595         return wm_size;
 596 }
 597
 598 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 599 {
 600         struct drm_crtc *crtc, *enabled = NULL;
 601
 602         for_each_crtc(dev, crtc) {
 603                 if (intel_crtc_active(crtc)) {
 604                         if (enabled)
 605                                 return NULL;
 606                         enabled = crtc;
 607                 }
 608         }
 609
 610         return enabled;
 611 }
 612
 613 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 614 {
 615         struct drm_device *dev = unused_crtc->dev;
 616         struct drm_i915_private *dev_priv = dev->dev_private;
 617         struct drm_crtc *crtc;
 618         const struct cxsr_latency *latency;
 619         u32 reg;
 620         unsigned long wm;
 621
 622         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 623                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 624         if (!latency) {
 625                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 626                 intel_set_memory_cxsr(dev_priv, false);
 627                 return;
 628         }
 629
 630         crtc = single_enabled_crtc(dev);
 631         if (crtc) {
 632                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 633                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 634                 int clock = adjusted_mode->crtc_clock;
 635
 636                 /* Display SR */
 637                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 638                                         pineview_display_wm.fifo_size,
 639                                         pixel_size, latency->display_sr);
 640                 reg = I915_READ(DSPFW1);
 641                 reg &= ~DSPFW_SR_MASK;
 642                 reg |= FW_WM(wm, SR);
 643                 I915_WRITE(DSPFW1, reg);
 644                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 645
 646                 /* cursor SR */
 647                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 648                                         pineview_display_wm.fifo_size,
 649                                         pixel_size, latency->cursor_sr);
 650                 reg = I915_READ(DSPFW3);
 651                 reg &= ~DSPFW_CURSOR_SR_MASK;
 652                 reg |= FW_WM(wm, CURSOR_SR);
 653                 I915_WRITE(DSPFW3, reg);
 654
 655                 /* Display HPLL off SR */
 656                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 657                                         pineview_display_hplloff_wm.fifo_size,
 658                                         pixel_size, latency->display_hpll_disable);
 659                 reg = I915_READ(DSPFW3);
 660                 reg &= ~DSPFW_HPLL_SR_MASK;
 661                 reg |= FW_WM(wm, HPLL_SR);
 662                 I915_WRITE(DSPFW3, reg);
 663
 664                 /* cursor HPLL off SR */
 665                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 666                                         pineview_display_hplloff_wm.fifo_size,
 667                                         pixel_size, latency->cursor_hpll_disable);
 668                 reg = I915_READ(DSPFW3);
 669                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 670                 reg |= FW_WM(wm, HPLL_CURSOR);
 671                 I915_WRITE(DSPFW3, reg);
 672                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 673
 674                 intel_set_memory_cxsr(dev_priv, true);
 675         } else {
 676                 intel_set_memory_cxsr(dev_priv, false);
 677         }
 678 }
 679
 680 static bool g4x_compute_wm0(struct drm_device *dev,
 681                             int plane,
 682                             const struct intel_watermark_params *display,
 683                             int display_latency_ns,
 684                             const struct intel_watermark_params *cursor,
 685                             int cursor_latency_ns,
 686                             int *plane_wm,
 687                             int *cursor_wm)
 688 {
 689         struct drm_crtc *crtc;
 690         const struct drm_display_mode *adjusted_mode;
 691         int htotal, hdisplay, clock, pixel_size;
 692         int line_time_us, line_count;
 693         int entries, tlb_miss;
 694
 695         crtc = intel_get_crtc_for_plane(dev, plane);
 696         if (!intel_crtc_active(crtc)) {
 697                 *cursor_wm = cursor->guard_size;
 698                 *plane_wm = display->guard_size;
 699                 return false;
 700         }
 701
 702         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 703         clock = adjusted_mode->crtc_clock;
 704         htotal = adjusted_mode->crtc_htotal;
 705         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 706         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 707
 708         /* Use the small buffer method to calculate plane watermark */
 709         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
 710         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 711         if (tlb_miss > 0)
 712                 entries += tlb_miss;
 713         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 714         *plane_wm = entries + display->guard_size;
 715         if (*plane_wm > (int)display->max_wm)
 716                 *plane_wm = display->max_wm;
 717
 718         /* Use the large buffer method to calculate cursor watermark */
 719         line_time_us = max(htotal * 1000 / clock, 1);
 720         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 721         entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
 722         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 723         if (tlb_miss > 0)
 724                 entries += tlb_miss;
 725         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 726         *cursor_wm = entries + cursor->guard_size;
 727         if (*cursor_wm > (int)cursor->max_wm)
 728                 *cursor_wm = (int)cursor->max_wm;
 729
 730         return true;
 731 }
 732
 733 /*
 734  * Check the wm result.
 735  *
 736  * If any calculated watermark values is larger than the maximum value that
 737  * can be programmed into the associated watermark register, that watermark
 738  * must be disabled.
 739  */
 740 static bool g4x_check_srwm(struct drm_device *dev,
 741                            int display_wm, int cursor_wm,
 742                            const struct intel_watermark_params *display,
 743                            const struct intel_watermark_params *cursor)
 744 {
 745         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 746                       display_wm, cursor_wm);
 747
 748         if (display_wm > display->max_wm) {
 749                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 750                               display_wm, display->max_wm);
 751                 return false;
 752         }
 753
 754         if (cursor_wm > cursor->max_wm) {
 755                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 756                               cursor_wm, cursor->max_wm);
 757                 return false;
 758         }
 759
 760         if (!(display_wm || cursor_wm)) {
 761                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 762                 return false;
 763         }
 764
 765         return true;
 766 }
 767
 768 static bool g4x_compute_srwm(struct drm_device *dev,
 769                              int plane,
 770                              int latency_ns,
 771                              const struct intel_watermark_params *display,
 772                              const struct intel_watermark_params *cursor,
 773                              int *display_wm, int *cursor_wm)
 774 {
 775         struct drm_crtc *crtc;
 776         const struct drm_display_mode *adjusted_mode;
 777         int hdisplay, htotal, pixel_size, clock;
 778         unsigned long line_time_us;
 779         int line_count, line_size;
 780         int small, large;
 781         int entries;
 782
 783         if (!latency_ns) {
 784                 *display_wm = *cursor_wm = 0;
 785                 return false;
 786         }
 787
 788         crtc = intel_get_crtc_for_plane(dev, plane);
 789         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 790         clock = adjusted_mode->crtc_clock;
 791         htotal = adjusted_mode->crtc_htotal;
 792         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 793         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 794
 795         line_time_us = max(htotal * 1000 / clock, 1);
 796         line_count = (latency_ns / line_time_us + 1000) / 1000;
 797         line_size = hdisplay * pixel_size;
 798
 799         /* Use the minimum of the small and large buffer method for primary */
 800         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 801         large = line_count * line_size;
 802
 803         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 804         *display_wm = entries + display->guard_size;
 805
 806         /* calculate the self-refresh watermark for display cursor */
 807         entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
 808         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 809         *cursor_wm = entries + cursor->guard_size;
 810
 811         return g4x_check_srwm(dev,
 812                               *display_wm, *cursor_wm,
 813                               display, cursor);
 814 }
 815
 816 #define FW_WM_VLV(value, plane) \
 817         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 818
 819 static void vlv_write_wm_values(struct intel_crtc *crtc,
 820                                 const struct vlv_wm_values *wm)
 821 {
 822         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 823         enum pipe pipe = crtc->pipe;
 824
 825         I915_WRITE(VLV_DDL(pipe),
 826                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 827                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 828                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 829                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 830
 831         I915_WRITE(DSPFW1,
 832                    FW_WM(wm->sr.plane, SR) |
 833                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 834                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 835                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 836         I915_WRITE(DSPFW2,
 837                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 838                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 839                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 840         I915_WRITE(DSPFW3,
 841                    FW_WM(wm->sr.cursor, CURSOR_SR));
 842
 843         if (IS_CHERRYVIEW(dev_priv)) {
 844                 I915_WRITE(DSPFW7_CHV,
 845                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 846                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 847                 I915_WRITE(DSPFW8_CHV,
 848                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 849                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 850                 I915_WRITE(DSPFW9_CHV,
 851                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 852                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 853                 I915_WRITE(DSPHOWM,
 854                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 855                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 856                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 857                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 858                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 859                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 860                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 861                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 862                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 863                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 864         } else {
 865                 I915_WRITE(DSPFW7,
 866                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 867                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 868                 I915_WRITE(DSPHOWM,
 869                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 870                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 871                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 872                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 873                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 874                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 875                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 876         }
 877
 878         /* zero (unused) WM1 watermarks */
 879         I915_WRITE(DSPFW4, 0);
 880         I915_WRITE(DSPFW5, 0);
 881         I915_WRITE(DSPFW6, 0);
 882         I915_WRITE(DSPHOWM1, 0);
 883
 884         POSTING_READ(DSPFW1);
 885 }
 886
 887 #undef FW_WM_VLV
 888
 889 enum vlv_wm_level {
 890         VLV_WM_LEVEL_PM2,
 891         VLV_WM_LEVEL_PM5,
 892         VLV_WM_LEVEL_DDR_DVFS,
 893 };
 894
 895 /* latency must be in 0.1us units. */
 896 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 897                                    unsigned int pipe_htotal,
 898                                    unsigned int horiz_pixels,
 899                                    unsigned int bytes_per_pixel,
 900                                    unsigned int latency)
 901 {
 902         unsigned int ret;
 903
 904         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 905         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
 906         ret = DIV_ROUND_UP(ret, 64);
 907
 908         return ret;
 909 }
 910
 911 static void vlv_setup_wm_latency(struct drm_device *dev)
 912 {
 913         struct drm_i915_private *dev_priv = dev->dev_private;
 914
 915         /* all latencies in usec */
 916         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 917
 918         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 919
 920         if (IS_CHERRYVIEW(dev_priv)) {
 921                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 922                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 923
 924                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 925         }
 926 }
 927
 928 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 929                                      struct intel_crtc *crtc,
 930                                      const struct intel_plane_state *state,
 931                                      int level)
 932 {
 933         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 934         int clock, htotal, pixel_size, width, wm;
 935
 936         if (dev_priv->wm.pri_latency[level] == 0)
 937                 return USHRT_MAX;
 938
 939         if (!state->visible)
 940                 return 0;
 941
 942         pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 943         clock = crtc->config->base.adjusted_mode.crtc_clock;
 944         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 945         width = crtc->config->pipe_src_w;
 946         if (WARN_ON(htotal == 0))
 947                 htotal = 1;
 948
 949         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 950                 /*
 951                  * FIXME the formula gives values that are
 952                  * too big for the cursor FIFO, and hence we
 953                  * would never be able to use cursors. For
 954                  * now just hardcode the watermark.
 955                  */
 956                 wm = 63;
 957         } else {
 958                 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
 959                                     dev_priv->wm.pri_latency[level] * 10);
 960         }
 961
 962         return min_t(int, wm, USHRT_MAX);
 963 }
 964
 965 static void vlv_compute_fifo(struct intel_crtc *crtc)
 966 {
 967         struct drm_device *dev = crtc->base.dev;
 968         struct vlv_wm_state *wm_state = &crtc->wm_state;
 969         struct intel_plane *plane;
 970         unsigned int total_rate = 0;
 971         const int fifo_size = 512 - 1;
 972         int fifo_extra, fifo_left = fifo_size;
 973
 974         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 975                 struct intel_plane_state *state =
 976                         to_intel_plane_state(plane->base.state);
 977
 978                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 979                         continue;
 980
 981                 if (state->visible) {
 982                         wm_state->num_active_planes++;
 983                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 984                 }
 985         }
 986
 987         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 988                 struct intel_plane_state *state =
 989                         to_intel_plane_state(plane->base.state);
 990                 unsigned int rate;
 991
 992                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 993                         plane->wm.fifo_size = 63;
 994                         continue;
 995                 }
 996
 997                 if (!state->visible) {
 998                         plane->wm.fifo_size = 0;
 999                         continue;
1000                 }
1001
1002                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1003                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1004                 fifo_left -= plane->wm.fifo_size;
1005         }
1006
1007         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1008
1009         /* spread the remainder evenly */
1010         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1011                 int plane_extra;
1012
1013                 if (fifo_left == 0)
1014                         break;
1015
1016                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1017                         continue;
1018
1019                 /* give it all to the first plane if none are active */
1020                 if (plane->wm.fifo_size == 0 &&
1021                     wm_state->num_active_planes)
1022                         continue;
1023
1024                 plane_extra = min(fifo_extra, fifo_left);
1025                 plane->wm.fifo_size += plane_extra;
1026                 fifo_left -= plane_extra;
1027         }
1028
1029         WARN_ON(fifo_left != 0);
1030 }
1031
1032 static void vlv_invert_wms(struct intel_crtc *crtc)
1033 {
1034         struct vlv_wm_state *wm_state = &crtc->wm_state;
1035         int level;
1036
1037         for (level = 0; level < wm_state->num_levels; level++) {
1038                 struct drm_device *dev = crtc->base.dev;
1039                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1040                 struct intel_plane *plane;
1041
1042                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1043                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1044
1045                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1046                         switch (plane->base.type) {
1047                                 int sprite;
1048                         case DRM_PLANE_TYPE_CURSOR:
1049                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1050                                         wm_state->wm[level].cursor;
1051                                 break;
1052                         case DRM_PLANE_TYPE_PRIMARY:
1053                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1054                                         wm_state->wm[level].primary;
1055                                 break;
1056                         case DRM_PLANE_TYPE_OVERLAY:
1057                                 sprite = plane->plane;
1058                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1059                                         wm_state->wm[level].sprite[sprite];
1060                                 break;
1061                         }
1062                 }
1063         }
1064 }
1065
1066 static void vlv_compute_wm(struct intel_crtc *crtc)
1067 {
1068         struct drm_device *dev = crtc->base.dev;
1069         struct vlv_wm_state *wm_state = &crtc->wm_state;
1070         struct intel_plane *plane;
1071         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1072         int level;
1073
1074         memset(wm_state, 0, sizeof(*wm_state));
1075
1076         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1077         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1078
1079         wm_state->num_active_planes = 0;
1080
1081         vlv_compute_fifo(crtc);
1082
1083         if (wm_state->num_active_planes != 1)
1084                 wm_state->cxsr = false;
1085
1086         if (wm_state->cxsr) {
1087                 for (level = 0; level < wm_state->num_levels; level++) {
1088                         wm_state->sr[level].plane = sr_fifo_size;
1089                         wm_state->sr[level].cursor = 63;
1090                 }
1091         }
1092
1093         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1094                 struct intel_plane_state *state =
1095                         to_intel_plane_state(plane->base.state);
1096
1097                 if (!state->visible)
1098                         continue;
1099
1100                 /* normal watermarks */
1101                 for (level = 0; level < wm_state->num_levels; level++) {
1102                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1103                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1104
1105                         /* hack */
1106                         if (WARN_ON(level == 0 && wm > max_wm))
1107                                 wm = max_wm;
1108
1109                         if (wm > plane->wm.fifo_size)
1110                                 break;
1111
1112                         switch (plane->base.type) {
1113                                 int sprite;
1114                         case DRM_PLANE_TYPE_CURSOR:
1115                                 wm_state->wm[level].cursor = wm;
1116                                 break;
1117                         case DRM_PLANE_TYPE_PRIMARY:
1118                                 wm_state->wm[level].primary = wm;
1119                                 break;
1120                         case DRM_PLANE_TYPE_OVERLAY:
1121                                 sprite = plane->plane;
1122                                 wm_state->wm[level].sprite[sprite] = wm;
1123                                 break;
1124                         }
1125                 }
1126
1127                 wm_state->num_levels = level;
1128
1129                 if (!wm_state->cxsr)
1130                         continue;
1131
1132                 /* maxfifo watermarks */
1133                 switch (plane->base.type) {
1134                         int sprite, level;
1135                 case DRM_PLANE_TYPE_CURSOR:
1136                         for (level = 0; level < wm_state->num_levels; level++)
1137                                 wm_state->sr[level].cursor =
1138                                         wm_state->wm[level].cursor;
1139                         break;
1140                 case DRM_PLANE_TYPE_PRIMARY:
1141                         for (level = 0; level < wm_state->num_levels; level++)
1142                                 wm_state->sr[level].plane =
1143                                         min(wm_state->sr[level].plane,
1144                                             wm_state->wm[level].primary);
1145                         break;
1146                 case DRM_PLANE_TYPE_OVERLAY:
1147                         sprite = plane->plane;
1148                         for (level = 0; level < wm_state->num_levels; level++)
1149                                 wm_state->sr[level].plane =
1150                                         min(wm_state->sr[level].plane,
1151                                             wm_state->wm[level].sprite[sprite]);
1152                         break;
1153                 }
1154         }
1155
1156         /* clear any (partially) filled invalid levels */
1157         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1158                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1159                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1160         }
1161
1162         vlv_invert_wms(crtc);
1163 }
1164
1165 #define VLV_FIFO(plane, value) \
1166         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1167
1168 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1169 {
1170         struct drm_device *dev = crtc->base.dev;
1171         struct drm_i915_private *dev_priv = to_i915(dev);
1172         struct intel_plane *plane;
1173         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1174
1175         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1176                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1177                         WARN_ON(plane->wm.fifo_size != 63);
1178                         continue;
1179                 }
1180
1181                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1182                         sprite0_start = plane->wm.fifo_size;
1183                 else if (plane->plane == 0)
1184                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1185                 else
1186                         fifo_size = sprite1_start + plane->wm.fifo_size;
1187         }
1188
1189         WARN_ON(fifo_size != 512 - 1);
1190
1191         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1192                       pipe_name(crtc->pipe), sprite0_start,
1193                       sprite1_start, fifo_size);
1194
1195         switch (crtc->pipe) {
1196                 uint32_t dsparb, dsparb2, dsparb3;
1197         case PIPE_A:
1198                 dsparb = I915_READ(DSPARB);
1199                 dsparb2 = I915_READ(DSPARB2);
1200
1201                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1202                             VLV_FIFO(SPRITEB, 0xff));
1203                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1204                            VLV_FIFO(SPRITEB, sprite1_start));
1205
1206                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1207                              VLV_FIFO(SPRITEB_HI, 0x1));
1208                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1209                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1210
1211                 I915_WRITE(DSPARB, dsparb);
1212                 I915_WRITE(DSPARB2, dsparb2);
1213                 break;
1214         case PIPE_B:
1215                 dsparb = I915_READ(DSPARB);
1216                 dsparb2 = I915_READ(DSPARB2);
1217
1218                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1219                             VLV_FIFO(SPRITED, 0xff));
1220                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1221                            VLV_FIFO(SPRITED, sprite1_start));
1222
1223                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1224                              VLV_FIFO(SPRITED_HI, 0xff));
1225                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1226                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1227
1228                 I915_WRITE(DSPARB, dsparb);
1229                 I915_WRITE(DSPARB2, dsparb2);
1230                 break;
1231         case PIPE_C:
1232                 dsparb3 = I915_READ(DSPARB3);
1233                 dsparb2 = I915_READ(DSPARB2);
1234
1235                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1236                              VLV_FIFO(SPRITEF, 0xff));
1237                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1238                             VLV_FIFO(SPRITEF, sprite1_start));
1239
1240                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1241                              VLV_FIFO(SPRITEF_HI, 0xff));
1242                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1243                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1244
1245                 I915_WRITE(DSPARB3, dsparb3);
1246                 I915_WRITE(DSPARB2, dsparb2);
1247                 break;
1248         default:
1249                 break;
1250         }
1251 }
1252
1253 #undef VLV_FIFO
1254
1255 static void vlv_merge_wm(struct drm_device *dev,
1256                          struct vlv_wm_values *wm)
1257 {
1258         struct intel_crtc *crtc;
1259         int num_active_crtcs = 0;
1260
1261         wm->level = to_i915(dev)->wm.max_level;
1262         wm->cxsr = true;
1263
1264         for_each_intel_crtc(dev, crtc) {
1265                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1266
1267                 if (!crtc->active)
1268                         continue;
1269
1270                 if (!wm_state->cxsr)
1271                         wm->cxsr = false;
1272
1273                 num_active_crtcs++;
1274                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1275         }
1276
1277         if (num_active_crtcs != 1)
1278                 wm->cxsr = false;
1279
1280         if (num_active_crtcs > 1)
1281                 wm->level = VLV_WM_LEVEL_PM2;
1282
1283         for_each_intel_crtc(dev, crtc) {
1284                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1285                 enum pipe pipe = crtc->pipe;
1286
1287                 if (!crtc->active)
1288                         continue;
1289
1290                 wm->pipe[pipe] = wm_state->wm[wm->level];
1291                 if (wm->cxsr)
1292                         wm->sr = wm_state->sr[wm->level];
1293
1294                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1295                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1296                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1297                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1298         }
1299 }
1300
1301 static void vlv_update_wm(struct drm_crtc *crtc)
1302 {
1303         struct drm_device *dev = crtc->dev;
1304         struct drm_i915_private *dev_priv = dev->dev_private;
1305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1306         enum pipe pipe = intel_crtc->pipe;
1307         struct vlv_wm_values wm = {};
1308
1309         vlv_compute_wm(intel_crtc);
1310         vlv_merge_wm(dev, &wm);
1311
1312         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1313                 /* FIXME should be part of crtc atomic commit */
1314                 vlv_pipe_set_fifo_size(intel_crtc);
1315                 return;
1316         }
1317
1318         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1319             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1320                 chv_set_memory_dvfs(dev_priv, false);
1321
1322         if (wm.level < VLV_WM_LEVEL_PM5 &&
1323             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1324                 chv_set_memory_pm5(dev_priv, false);
1325
1326         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1327                 intel_set_memory_cxsr(dev_priv, false);
1328
1329         /* FIXME should be part of crtc atomic commit */
1330         vlv_pipe_set_fifo_size(intel_crtc);
1331
1332         vlv_write_wm_values(intel_crtc, &wm);
1333
1334         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1335                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1336                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1337                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1338                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1339
1340         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1341                 intel_set_memory_cxsr(dev_priv, true);
1342
1343         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1344             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1345                 chv_set_memory_pm5(dev_priv, true);
1346
1347         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1348             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1349                 chv_set_memory_dvfs(dev_priv, true);
1350
1351         dev_priv->wm.vlv = wm;
1352 }
1353
1354 #define single_plane_enabled(mask) is_power_of_2(mask)
1355
1356 static void g4x_update_wm(struct drm_crtc *crtc)
1357 {
1358         struct drm_device *dev = crtc->dev;
1359         static const int sr_latency_ns = 12000;
1360         struct drm_i915_private *dev_priv = dev->dev_private;
1361         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1362         int plane_sr, cursor_sr;
1363         unsigned int enabled = 0;
1364         bool cxsr_enabled;
1365
1366         if (g4x_compute_wm0(dev, PIPE_A,
1367                             &g4x_wm_info, pessimal_latency_ns,
1368                             &g4x_cursor_wm_info, pessimal_latency_ns,
1369                             &planea_wm, &cursora_wm))
1370                 enabled |= 1 << PIPE_A;
1371
1372         if (g4x_compute_wm0(dev, PIPE_B,
1373                             &g4x_wm_info, pessimal_latency_ns,
1374                             &g4x_cursor_wm_info, pessimal_latency_ns,
1375                             &planeb_wm, &cursorb_wm))
1376                 enabled |= 1 << PIPE_B;
1377
1378         if (single_plane_enabled(enabled) &&
1379             g4x_compute_srwm(dev, ffs(enabled) - 1,
1380                              sr_latency_ns,
1381                              &g4x_wm_info,
1382                              &g4x_cursor_wm_info,
1383                              &plane_sr, &cursor_sr)) {
1384                 cxsr_enabled = true;
1385         } else {
1386                 cxsr_enabled = false;
1387                 intel_set_memory_cxsr(dev_priv, false);
1388                 plane_sr = cursor_sr = 0;
1389         }
1390
1391         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1392                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1393                       planea_wm, cursora_wm,
1394                       planeb_wm, cursorb_wm,
1395                       plane_sr, cursor_sr);
1396
1397         I915_WRITE(DSPFW1,
1398                    FW_WM(plane_sr, SR) |
1399                    FW_WM(cursorb_wm, CURSORB) |
1400                    FW_WM(planeb_wm, PLANEB) |
1401                    FW_WM(planea_wm, PLANEA));
1402         I915_WRITE(DSPFW2,
1403                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1404                    FW_WM(cursora_wm, CURSORA));
1405         /* HPLL off in SR has some issues on G4x... disable it */
1406         I915_WRITE(DSPFW3,
1407                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1408                    FW_WM(cursor_sr, CURSOR_SR));
1409
1410         if (cxsr_enabled)
1411                 intel_set_memory_cxsr(dev_priv, true);
1412 }
1413
1414 static void i965_update_wm(struct drm_crtc *unused_crtc)
1415 {
1416         struct drm_device *dev = unused_crtc->dev;
1417         struct drm_i915_private *dev_priv = dev->dev_private;
1418         struct drm_crtc *crtc;
1419         int srwm = 1;
1420         int cursor_sr = 16;
1421         bool cxsr_enabled;
1422
1423         /* Calc sr entries for one plane configs */
1424         crtc = single_enabled_crtc(dev);
1425         if (crtc) {
1426                 /* self-refresh has much higher latency */
1427                 static const int sr_latency_ns = 12000;
1428                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1429                 int clock = adjusted_mode->crtc_clock;
1430                 int htotal = adjusted_mode->crtc_htotal;
1431                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1432                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1433                 unsigned long line_time_us;
1434                 int entries;
1435
1436                 line_time_us = max(htotal * 1000 / clock, 1);
1437
1438                 /* Use ns/us then divide to preserve precision */
1439                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1440                         pixel_size * hdisplay;
1441                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1442                 srwm = I965_FIFO_SIZE - entries;
1443                 if (srwm < 0)
1444                         srwm = 1;
1445                 srwm &= 0x1ff;
1446                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1447                               entries, srwm);
1448
1449                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450                         pixel_size * crtc->cursor->state->crtc_w;
1451                 entries = DIV_ROUND_UP(entries,
1452                                           i965_cursor_wm_info.cacheline_size);
1453                 cursor_sr = i965_cursor_wm_info.fifo_size -
1454                         (entries + i965_cursor_wm_info.guard_size);
1455
1456                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1457                         cursor_sr = i965_cursor_wm_info.max_wm;
1458
1459                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1460                               "cursor %d\n", srwm, cursor_sr);
1461
1462                 cxsr_enabled = true;
1463         } else {
1464                 cxsr_enabled = false;
1465                 /* Turn off self refresh if both pipes are enabled */
1466                 intel_set_memory_cxsr(dev_priv, false);
1467         }
1468
1469         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1470                       srwm);
1471
1472         /* 965 has limitations... */
1473         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1474                    FW_WM(8, CURSORB) |
1475                    FW_WM(8, PLANEB) |
1476                    FW_WM(8, PLANEA));
1477         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1478                    FW_WM(8, PLANEC_OLD));
1479         /* update cursor SR watermark */
1480         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1481
1482         if (cxsr_enabled)
1483                 intel_set_memory_cxsr(dev_priv, true);
1484 }
1485
1486 #undef FW_WM
1487
1488 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1489 {
1490         struct drm_device *dev = unused_crtc->dev;
1491         struct drm_i915_private *dev_priv = dev->dev_private;
1492         const struct intel_watermark_params *wm_info;
1493         uint32_t fwater_lo;
1494         uint32_t fwater_hi;
1495         int cwm, srwm = 1;
1496         int fifo_size;
1497         int planea_wm, planeb_wm;
1498         struct drm_crtc *crtc, *enabled = NULL;
1499
1500         if (IS_I945GM(dev))
1501                 wm_info = &i945_wm_info;
1502         else if (!IS_GEN2(dev))
1503                 wm_info = &i915_wm_info;
1504         else
1505                 wm_info = &i830_a_wm_info;
1506
1507         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1508         crtc = intel_get_crtc_for_plane(dev, 0);
1509         if (intel_crtc_active(crtc)) {
1510                 const struct drm_display_mode *adjusted_mode;
1511                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1512                 if (IS_GEN2(dev))
1513                         cpp = 4;
1514
1515                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1516                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1517                                                wm_info, fifo_size, cpp,
1518                                                pessimal_latency_ns);
1519                 enabled = crtc;
1520         } else {
1521                 planea_wm = fifo_size - wm_info->guard_size;
1522                 if (planea_wm > (long)wm_info->max_wm)
1523                         planea_wm = wm_info->max_wm;
1524         }
1525
1526         if (IS_GEN2(dev))
1527                 wm_info = &i830_bc_wm_info;
1528
1529         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1530         crtc = intel_get_crtc_for_plane(dev, 1);
1531         if (intel_crtc_active(crtc)) {
1532                 const struct drm_display_mode *adjusted_mode;
1533                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1534                 if (IS_GEN2(dev))
1535                         cpp = 4;
1536
1537                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1538                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1539                                                wm_info, fifo_size, cpp,
1540                                                pessimal_latency_ns);
1541                 if (enabled == NULL)
1542                         enabled = crtc;
1543                 else
1544                         enabled = NULL;
1545         } else {
1546                 planeb_wm = fifo_size - wm_info->guard_size;
1547                 if (planeb_wm > (long)wm_info->max_wm)
1548                         planeb_wm = wm_info->max_wm;
1549         }
1550
1551         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1552
1553         if (IS_I915GM(dev) && enabled) {
1554                 struct drm_i915_gem_object *obj;
1555
1556                 obj = intel_fb_obj(enabled->primary->state->fb);
1557
1558                 /* self-refresh seems busted with untiled */
1559                 if (obj->tiling_mode == I915_TILING_NONE)
1560                         enabled = NULL;
1561         }
1562
1563         /*
1564          * Overlay gets an aggressive default since video jitter is bad.
1565          */
1566         cwm = 2;
1567
1568         /* Play safe and disable self-refresh before adjusting watermarks. */
1569         intel_set_memory_cxsr(dev_priv, false);
1570
1571         /* Calc sr entries for one plane configs */
1572         if (HAS_FW_BLC(dev) && enabled) {
1573                 /* self-refresh has much higher latency */
1574                 static const int sr_latency_ns = 6000;
1575                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1576                 int clock = adjusted_mode->crtc_clock;
1577                 int htotal = adjusted_mode->crtc_htotal;
1578                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1579                 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1580                 unsigned long line_time_us;
1581                 int entries;
1582
1583                 line_time_us = max(htotal * 1000 / clock, 1);
1584
1585                 /* Use ns/us then divide to preserve precision */
1586                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1587                         pixel_size * hdisplay;
1588                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1589                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1590                 srwm = wm_info->fifo_size - entries;
1591                 if (srwm < 0)
1592                         srwm = 1;
1593
1594                 if (IS_I945G(dev) || IS_I945GM(dev))
1595                         I915_WRITE(FW_BLC_SELF,
1596                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1597                 else if (IS_I915GM(dev))
1598                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1599         }
1600
1601         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1602                       planea_wm, planeb_wm, cwm, srwm);
1603
1604         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1605         fwater_hi = (cwm & 0x1f);
1606
1607         /* Set request length to 8 cachelines per fetch */
1608         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1609         fwater_hi = fwater_hi | (1 << 8);
1610
1611         I915_WRITE(FW_BLC, fwater_lo);
1612         I915_WRITE(FW_BLC2, fwater_hi);
1613
1614         if (enabled)
1615                 intel_set_memory_cxsr(dev_priv, true);
1616 }
1617
1618 static void i845_update_wm(struct drm_crtc *unused_crtc)
1619 {
1620         struct drm_device *dev = unused_crtc->dev;
1621         struct drm_i915_private *dev_priv = dev->dev_private;
1622         struct drm_crtc *crtc;
1623         const struct drm_display_mode *adjusted_mode;
1624         uint32_t fwater_lo;
1625         int planea_wm;
1626
1627         crtc = single_enabled_crtc(dev);
1628         if (crtc == NULL)
1629                 return;
1630
1631         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1632         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1633                                        &i845_wm_info,
1634                                        dev_priv->display.get_fifo_size(dev, 0),
1635                                        4, pessimal_latency_ns);
1636         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1637         fwater_lo |= (3<<8) | planea_wm;
1638
1639         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1640
1641         I915_WRITE(FW_BLC, fwater_lo);
1642 }
1643
1644 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1645 {
1646         uint32_t pixel_rate;
1647
1648         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1649
1650         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1651          * adjust the pixel_rate here. */
1652
1653         if (pipe_config->pch_pfit.enabled) {
1654                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1655                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1656
1657                 pipe_w = pipe_config->pipe_src_w;
1658                 pipe_h = pipe_config->pipe_src_h;
1659
1660                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1661                 pfit_h = pfit_size & 0xFFFF;
1662                 if (pipe_w < pfit_w)
1663                         pipe_w = pfit_w;
1664                 if (pipe_h < pfit_h)
1665                         pipe_h = pfit_h;
1666
1667                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1668                                      pfit_w * pfit_h);
1669         }
1670
1671         return pixel_rate;
1672 }
1673
1674 /* latency must be in 0.1us units. */
1675 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1676                                uint32_t latency)
1677 {
1678         uint64_t ret;
1679
1680         if (WARN(latency == 0, "Latency value missing\n"))
1681                 return UINT_MAX;
1682
1683         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1684         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1685
1686         return ret;
1687 }
1688
1689 /* latency must be in 0.1us units. */
1690 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1691                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1692                                uint32_t latency)
1693 {
1694         uint32_t ret;
1695
1696         if (WARN(latency == 0, "Latency value missing\n"))
1697                 return UINT_MAX;
1698
1699         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1700         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1701         ret = DIV_ROUND_UP(ret, 64) + 2;
1702         return ret;
1703 }
1704
1705 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1706                            uint8_t bytes_per_pixel)
1707 {
1708         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1709 }
1710
1711 struct skl_pipe_wm_parameters {
1712         bool active;
1713         uint32_t pipe_htotal;
1714         uint32_t pixel_rate; /* in KHz */
1715         struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1716 };
1717
1718 struct ilk_wm_maximums {
1719         uint16_t pri;
1720         uint16_t spr;
1721         uint16_t cur;
1722         uint16_t fbc;
1723 };
1724
1725 /* used in computing the new watermarks state */
1726 struct intel_wm_config {
1727         unsigned int num_pipes_active;
1728         bool sprites_enabled;
1729         bool sprites_scaled;
1730 };
1731
1732 /*
1733  * For both WM_PIPE and WM_LP.
1734  * mem_value must be in 0.1us units.
1735  */
1736 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1737                                    const struct intel_plane_state *pstate,
1738                                    uint32_t mem_value,
1739                                    bool is_lp)
1740 {
1741         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1742         uint32_t method1, method2;
1743
1744         if (!cstate->base.active || !pstate->visible)
1745                 return 0;
1746
1747         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1748
1749         if (!is_lp)
1750                 return method1;
1751
1752         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1753                                  cstate->base.adjusted_mode.crtc_htotal,
1754                                  drm_rect_width(&pstate->dst),
1755                                  bpp,
1756                                  mem_value);
1757
1758         return min(method1, method2);
1759 }
1760
1761 /*
1762  * For both WM_PIPE and WM_LP.
1763  * mem_value must be in 0.1us units.
1764  */
1765 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1766                                    const struct intel_plane_state *pstate,
1767                                    uint32_t mem_value)
1768 {
1769         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1770         uint32_t method1, method2;
1771
1772         if (!cstate->base.active || !pstate->visible)
1773                 return 0;
1774
1775         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1776         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1777                                  cstate->base.adjusted_mode.crtc_htotal,
1778                                  drm_rect_width(&pstate->dst),
1779                                  bpp,
1780                                  mem_value);
1781         return min(method1, method2);
1782 }
1783
1784 /*
1785  * For both WM_PIPE and WM_LP.
1786  * mem_value must be in 0.1us units.
1787  */
1788 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1789                                    const struct intel_plane_state *pstate,
1790                                    uint32_t mem_value)
1791 {
1792         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1793
1794         if (!cstate->base.active || !pstate->visible)
1795                 return 0;
1796
1797         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1798                               cstate->base.adjusted_mode.crtc_htotal,
1799                               drm_rect_width(&pstate->dst),
1800                               bpp,
1801                               mem_value);
1802 }
1803
1804 /* Only for WM_LP. */
1805 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1806                                    const struct intel_plane_state *pstate,
1807                                    uint32_t pri_val)
1808 {
1809         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1810
1811         if (!cstate->base.active || !pstate->visible)
1812                 return 0;
1813
1814         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
1815 }
1816
1817 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1818 {
1819         if (INTEL_INFO(dev)->gen >= 8)
1820                 return 3072;
1821         else if (INTEL_INFO(dev)->gen >= 7)
1822                 return 768;
1823         else
1824                 return 512;
1825 }
1826
1827 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1828                                          int level, bool is_sprite)
1829 {
1830         if (INTEL_INFO(dev)->gen >= 8)
1831                 /* BDW primary/sprite plane watermarks */
1832                 return level == 0 ? 255 : 2047;
1833         else if (INTEL_INFO(dev)->gen >= 7)
1834                 /* IVB/HSW primary/sprite plane watermarks */
1835                 return level == 0 ? 127 : 1023;
1836         else if (!is_sprite)
1837                 /* ILK/SNB primary plane watermarks */
1838                 return level == 0 ? 127 : 511;
1839         else
1840                 /* ILK/SNB sprite plane watermarks */
1841                 return level == 0 ? 63 : 255;
1842 }
1843
1844 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1845                                           int level)
1846 {
1847         if (INTEL_INFO(dev)->gen >= 7)
1848                 return level == 0 ? 63 : 255;
1849         else
1850                 return level == 0 ? 31 : 63;
1851 }
1852
1853 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1854 {
1855         if (INTEL_INFO(dev)->gen >= 8)
1856                 return 31;
1857         else
1858                 return 15;
1859 }
1860
1861 /* Calculate the maximum primary/sprite plane watermark */
1862 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1863                                      int level,
1864                                      const struct intel_wm_config *config,
1865                                      enum intel_ddb_partitioning ddb_partitioning,
1866                                      bool is_sprite)
1867 {
1868         unsigned int fifo_size = ilk_display_fifo_size(dev);
1869
1870         /* if sprites aren't enabled, sprites get nothing */
1871         if (is_sprite && !config->sprites_enabled)
1872                 return 0;
1873
1874         /* HSW allows LP1+ watermarks even with multiple pipes */
1875         if (level == 0 || config->num_pipes_active > 1) {
1876                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1877
1878                 /*
1879                  * For some reason the non self refresh
1880                  * FIFO size is only half of the self
1881                  * refresh FIFO size on ILK/SNB.
1882                  */
1883                 if (INTEL_INFO(dev)->gen <= 6)
1884                         fifo_size /= 2;
1885         }
1886
1887         if (config->sprites_enabled) {
1888                 /* level 0 is always calculated with 1:1 split */
1889                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1890                         if (is_sprite)
1891                                 fifo_size *= 5;
1892                         fifo_size /= 6;
1893                 } else {
1894                         fifo_size /= 2;
1895                 }
1896         }
1897
1898         /* clamp to max that the registers can hold */
1899         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1900 }
1901
1902 /* Calculate the maximum cursor plane watermark */
1903 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1904                                       int level,
1905                                       const struct intel_wm_config *config)
1906 {
1907         /* HSW LP1+ watermarks w/ multiple pipes */
1908         if (level > 0 && config->num_pipes_active > 1)
1909                 return 64;
1910
1911         /* otherwise just report max that registers can hold */
1912         return ilk_cursor_wm_reg_max(dev, level);
1913 }
1914
1915 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1916                                     int level,
1917                                     const struct intel_wm_config *config,
1918                                     enum intel_ddb_partitioning ddb_partitioning,
1919                                     struct ilk_wm_maximums *max)
1920 {
1921         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1922         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1923         max->cur = ilk_cursor_wm_max(dev, level, config);
1924         max->fbc = ilk_fbc_wm_reg_max(dev);
1925 }
1926
1927 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1928                                         int level,
1929                                         struct ilk_wm_maximums *max)
1930 {
1931         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1932         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1933         max->cur = ilk_cursor_wm_reg_max(dev, level);
1934         max->fbc = ilk_fbc_wm_reg_max(dev);
1935 }
1936
1937 static bool ilk_validate_wm_level(int level,
1938                                   const struct ilk_wm_maximums *max,
1939                                   struct intel_wm_level *result)
1940 {
1941         bool ret;
1942
1943         /* already determined to be invalid? */
1944         if (!result->enable)
1945                 return false;
1946
1947         result->enable = result->pri_val <= max->pri &&
1948                          result->spr_val <= max->spr &&
1949                          result->cur_val <= max->cur;
1950
1951         ret = result->enable;
1952
1953         /*
1954          * HACK until we can pre-compute everything,
1955          * and thus fail gracefully if LP0 watermarks
1956          * are exceeded...
1957          */
1958         if (level == 0 && !result->enable) {
1959                 if (result->pri_val > max->pri)
1960                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1961                                       level, result->pri_val, max->pri);
1962                 if (result->spr_val > max->spr)
1963                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1964                                       level, result->spr_val, max->spr);
1965                 if (result->cur_val > max->cur)
1966                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1967                                       level, result->cur_val, max->cur);
1968
1969                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1970                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1971                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1972                 result->enable = true;
1973         }
1974
1975         return ret;
1976 }
1977
1978 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1979                                  const struct intel_crtc *intel_crtc,
1980                                  int level,
1981                                  struct intel_crtc_state *cstate,
1982                                  struct intel_wm_level *result)
1983 {
1984         struct intel_plane *intel_plane;
1985         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1986         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1987         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1988
1989         /* WM1+ latency values stored in 0.5us units */
1990         if (level > 0) {
1991                 pri_latency *= 5;
1992                 spr_latency *= 5;
1993                 cur_latency *= 5;
1994         }
1995
1996         for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) {
1997                 struct intel_plane_state *pstate =
1998                         to_intel_plane_state(intel_plane->base.state);
1999
2000                 switch (intel_plane->base.type) {
2001                 case DRM_PLANE_TYPE_PRIMARY:
2002                         result->pri_val = ilk_compute_pri_wm(cstate, pstate,
2003                                                              pri_latency,
2004                                                              level);
2005                         result->fbc_val = ilk_compute_fbc_wm(cstate, pstate,
2006                                                              result->pri_val);
2007                         break;
2008                 case DRM_PLANE_TYPE_OVERLAY:
2009                         result->spr_val = ilk_compute_spr_wm(cstate, pstate,
2010                                                              spr_latency);
2011                         break;
2012                 case DRM_PLANE_TYPE_CURSOR:
2013                         result->cur_val = ilk_compute_cur_wm(cstate, pstate,
2014                                                              cur_latency);
2015                         break;
2016                 }
2017         }
2018
2019         result->enable = true;
2020 }
2021
2022 static uint32_t
2023 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2024 {
2025         struct drm_i915_private *dev_priv = dev->dev_private;
2026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2027         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
2028         u32 linetime, ips_linetime;
2029
2030         if (!intel_crtc->active)
2031                 return 0;
2032
2033         /* The WM are computed with base on how long it takes to fill a single
2034          * row at the given clock rate, multiplied by 8.
2035          * */
2036         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2037                                      adjusted_mode->crtc_clock);
2038         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2039                                          dev_priv->cdclk_freq);
2040
2041         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2042                PIPE_WM_LINETIME_TIME(linetime);
2043 }
2044
2045 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2046 {
2047         struct drm_i915_private *dev_priv = dev->dev_private;
2048
2049         if (IS_GEN9(dev)) {
2050                 uint32_t val;
2051                 int ret, i;
2052                 int level, max_level = ilk_wm_max_level(dev);
2053
2054                 /* read the first set of memory latencies[0:3] */
2055                 val = 0; /* data0 to be programmed to 0 for first set */
2056                 mutex_lock(&dev_priv->rps.hw_lock);
2057                 ret = sandybridge_pcode_read(dev_priv,
2058                                              GEN9_PCODE_READ_MEM_LATENCY,
2059                                              &val);
2060                 mutex_unlock(&dev_priv->rps.hw_lock);
2061
2062                 if (ret) {
2063                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2064                         return;
2065                 }
2066
2067                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2068                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2069                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2070                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2071                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2072                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2073                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2074
2075                 /* read the second set of memory latencies[4:7] */
2076                 val = 1; /* data0 to be programmed to 1 for second set */
2077                 mutex_lock(&dev_priv->rps.hw_lock);
2078                 ret = sandybridge_pcode_read(dev_priv,
2079                                              GEN9_PCODE_READ_MEM_LATENCY,
2080                                              &val);
2081                 mutex_unlock(&dev_priv->rps.hw_lock);
2082                 if (ret) {
2083                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2084                         return;
2085                 }
2086
2087                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2088                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2089                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2090                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2091                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2092                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2093                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2094
2095                 /*
2096                  * WaWmMemoryReadLatency:skl
2097                  *
2098                  * punit doesn't take into account the read latency so we need
2099                  * to add 2us to the various latency levels we retrieve from
2100                  * the punit.
2101                  *   - W0 is a bit special in that it's the only level that
2102                  *   can't be disabled if we want to have display working, so
2103                  *   we always add 2us there.
2104                  *   - For levels >=1, punit returns 0us latency when they are
2105                  *   disabled, so we respect that and don't add 2us then
2106                  *
2107                  * Additionally, if a level n (n > 1) has a 0us latency, all
2108                  * levels m (m >= n) need to be disabled. We make sure to
2109                  * sanitize the values out of the punit to satisfy this
2110                  * requirement.
2111                  */
2112                 wm[0] += 2;
2113                 for (level = 1; level <= max_level; level++)
2114                         if (wm[level] != 0)
2115                                 wm[level] += 2;
2116                         else {
2117                                 for (i = level + 1; i <= max_level; i++)
2118                                         wm[i] = 0;
2119
2120                                 break;
2121                         }
2122         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2123                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2124
2125                 wm[0] = (sskpd >> 56) & 0xFF;
2126                 if (wm[0] == 0)
2127                         wm[0] = sskpd & 0xF;
2128                 wm[1] = (sskpd >> 4) & 0xFF;
2129                 wm[2] = (sskpd >> 12) & 0xFF;
2130                 wm[3] = (sskpd >> 20) & 0x1FF;
2131                 wm[4] = (sskpd >> 32) & 0x1FF;
2132         } else if (INTEL_INFO(dev)->gen >= 6) {
2133                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2134
2135                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2136                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2137                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2138                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2139         } else if (INTEL_INFO(dev)->gen >= 5) {
2140                 uint32_t mltr = I915_READ(MLTR_ILK);
2141
2142                 /* ILK primary LP0 latency is 700 ns */
2143                 wm[0] = 7;
2144                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2145                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2146         }
2147 }
2148
2149 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2150 {
2151         /* ILK sprite LP0 latency is 1300 ns */
2152         if (INTEL_INFO(dev)->gen == 5)
2153                 wm[0] = 13;
2154 }
2155
2156 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2157 {
2158         /* ILK cursor LP0 latency is 1300 ns */
2159         if (INTEL_INFO(dev)->gen == 5)
2160                 wm[0] = 13;
2161
2162         /* WaDoubleCursorLP3Latency:ivb */
2163         if (IS_IVYBRIDGE(dev))
2164                 wm[3] *= 2;
2165 }
2166
2167 int ilk_wm_max_level(const struct drm_device *dev)
2168 {
2169         /* how many WM levels are we expecting */
2170         if (INTEL_INFO(dev)->gen >= 9)
2171                 return 7;
2172         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2173                 return 4;
2174         else if (INTEL_INFO(dev)->gen >= 6)
2175                 return 3;
2176         else
2177                 return 2;
2178 }
2179
2180 static void intel_print_wm_latency(struct drm_device *dev,
2181                                    const char *name,
2182                                    const uint16_t wm[8])
2183 {
2184         int level, max_level = ilk_wm_max_level(dev);
2185
2186         for (level = 0; level <= max_level; level++) {
2187                 unsigned int latency = wm[level];
2188
2189                 if (latency == 0) {
2190                         DRM_ERROR("%s WM%d latency not provided\n",
2191                                   name, level);
2192                         continue;
2193                 }
2194
2195                 /*
2196                  * - latencies are in us on gen9.
2197                  * - before then, WM1+ latency values are in 0.5us units
2198                  */
2199                 if (IS_GEN9(dev))
2200                         latency *= 10;
2201                 else if (level > 0)
2202                         latency *= 5;
2203
2204                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2205                               name, level, wm[level],
2206                               latency / 10, latency % 10);
2207         }
2208 }
2209
2210 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2211                                     uint16_t wm[5], uint16_t min)
2212 {
2213         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2214
2215         if (wm[0] >= min)
2216                 return false;
2217
2218         wm[0] = max(wm[0], min);
2219         for (level = 1; level <= max_level; level++)
2220                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2221
2222         return true;
2223 }
2224
2225 static void snb_wm_latency_quirk(struct drm_device *dev)
2226 {
2227         struct drm_i915_private *dev_priv = dev->dev_private;
2228         bool changed;
2229
2230         /*
2231          * The BIOS provided WM memory latency values are often
2232          * inadequate for high resolution displays. Adjust them.
2233          */
2234         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2235                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2236                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2237
2238         if (!changed)
2239                 return;
2240
2241         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2242         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2243         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2244         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2245 }
2246
2247 static void ilk_setup_wm_latency(struct drm_device *dev)
2248 {
2249         struct drm_i915_private *dev_priv = dev->dev_private;
2250
2251         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2252
2253         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2254                sizeof(dev_priv->wm.pri_latency));
2255         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2256                sizeof(dev_priv->wm.pri_latency));
2257
2258         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2259         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2260
2261         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2262         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2263         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2264
2265         if (IS_GEN6(dev))
2266                 snb_wm_latency_quirk(dev);
2267 }
2268
2269 static void skl_setup_wm_latency(struct drm_device *dev)
2270 {
2271         struct drm_i915_private *dev_priv = dev->dev_private;
2272
2273         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2274         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2275 }
2276
2277 static void ilk_compute_wm_config(struct drm_device *dev,
2278                                   struct intel_wm_config *config)
2279 {
2280         struct intel_crtc *intel_crtc;
2281
2282         /* Compute the currently _active_ config */
2283         for_each_intel_crtc(dev, intel_crtc) {
2284                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2285
2286                 if (!wm->pipe_enabled)
2287                         continue;
2288
2289                 config->sprites_enabled |= wm->sprites_enabled;
2290                 config->sprites_scaled |= wm->sprites_scaled;
2291                 config->num_pipes_active++;
2292         }
2293 }
2294
2295 /* Compute new watermarks for the pipe */
2296 static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
2297                                   struct intel_pipe_wm *pipe_wm)
2298 {
2299         struct drm_crtc *crtc = cstate->base.crtc;
2300         struct drm_device *dev = crtc->dev;
2301         const struct drm_i915_private *dev_priv = dev->dev_private;
2302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2303         struct intel_plane *intel_plane;
2304         struct intel_plane_state *sprstate = NULL;
2305         int level, max_level = ilk_wm_max_level(dev);
2306         /* LP0 watermark maximums depend on this pipe alone */
2307         struct intel_wm_config config = {
2308                 .num_pipes_active = 1,
2309         };
2310         struct ilk_wm_maximums max;
2311
2312         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2313                 if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) {
2314                         sprstate = to_intel_plane_state(intel_plane->base.state);
2315                         break;
2316                 }
2317         }
2318
2319         config.sprites_enabled = sprstate->visible;
2320         config.sprites_scaled = sprstate->visible &&
2321                 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2322                 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2323
2324         pipe_wm->pipe_enabled = cstate->base.active;
2325         pipe_wm->sprites_enabled = sprstate->visible;
2326         pipe_wm->sprites_scaled = config.sprites_scaled;
2327
2328         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2329         if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2330                 max_level = 1;
2331
2332         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2333         if (config.sprites_scaled)
2334                 max_level = 0;
2335
2336         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]);
2337
2338         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2339                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2340
2341         /* LP0 watermarks always use 1/2 DDB partitioning */
2342         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2343
2344         /* At least LP0 must be valid */
2345         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2346                 return false;
2347
2348         ilk_compute_wm_reg_maximums(dev, 1, &max);
2349
2350         for (level = 1; level <= max_level; level++) {
2351                 struct intel_wm_level wm = {};
2352
2353                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm);
2354
2355                 /*
2356                  * Disable any watermark level that exceeds the
2357                  * register maximums since such watermarks are
2358                  * always invalid.
2359                  */
2360                 if (!ilk_validate_wm_level(level, &max, &wm))
2361                         break;
2362
2363                 pipe_wm->wm[level] = wm;
2364         }
2365
2366         return true;
2367 }
2368
2369 /*
2370  * Merge the watermarks from all active pipes for a specific level.
2371  */
2372 static void ilk_merge_wm_level(struct drm_device *dev,
2373                                int level,
2374                                struct intel_wm_level *ret_wm)
2375 {
2376         const struct intel_crtc *intel_crtc;
2377
2378         ret_wm->enable = true;
2379
2380         for_each_intel_crtc(dev, intel_crtc) {
2381                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2382                 const struct intel_wm_level *wm = &active->wm[level];
2383
2384                 if (!active->pipe_enabled)
2385                         continue;
2386
2387                 /*
2388                  * The watermark values may have been used in the past,
2389                  * so we must maintain them in the registers for some
2390                  * time even if the level is now disabled.
2391                  */
2392                 if (!wm->enable)
2393                         ret_wm->enable = false;
2394
2395                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2396                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2397                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2398                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2399         }
2400 }
2401
2402 /*
2403  * Merge all low power watermarks for all active pipes.
2404  */
2405 static void ilk_wm_merge(struct drm_device *dev,
2406                          const struct intel_wm_config *config,
2407                          const struct ilk_wm_maximums *max,
2408                          struct intel_pipe_wm *merged)
2409 {
2410         struct drm_i915_private *dev_priv = dev->dev_private;
2411         int level, max_level = ilk_wm_max_level(dev);
2412         int last_enabled_level = max_level;
2413
2414         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2415         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2416             config->num_pipes_active > 1)
2417                 return;
2418
2419         /* ILK: FBC WM must be disabled always */
2420         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2421
2422         /* merge each WM1+ level */
2423         for (level = 1; level <= max_level; level++) {
2424                 struct intel_wm_level *wm = &merged->wm[level];
2425
2426                 ilk_merge_wm_level(dev, level, wm);
2427
2428                 if (level > last_enabled_level)
2429                         wm->enable = false;
2430                 else if (!ilk_validate_wm_level(level, max, wm))
2431                         /* make sure all following levels get disabled */
2432                         last_enabled_level = level - 1;
2433
2434                 /*
2435                  * The spec says it is preferred to disable
2436                  * FBC WMs instead of disabling a WM level.
2437                  */
2438                 if (wm->fbc_val > max->fbc) {
2439                         if (wm->enable)
2440                                 merged->fbc_wm_enabled = false;
2441                         wm->fbc_val = 0;
2442                 }
2443         }
2444
2445         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2446         /*
2447          * FIXME this is racy. FBC might get enabled later.
2448          * What we should check here is whether FBC can be
2449          * enabled sometime later.
2450          */
2451         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2452             intel_fbc_enabled(dev_priv)) {
2453                 for (level = 2; level <= max_level; level++) {
2454                         struct intel_wm_level *wm = &merged->wm[level];
2455
2456                         wm->enable = false;
2457                 }
2458         }
2459 }
2460
2461 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2462 {
2463         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2464         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2465 }
2466
2467 /* The value we need to program into the WM_LPx latency field */
2468 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2469 {
2470         struct drm_i915_private *dev_priv = dev->dev_private;
2471
2472         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2473                 return 2 * level;
2474         else
2475                 return dev_priv->wm.pri_latency[level];
2476 }
2477
2478 static void ilk_compute_wm_results(struct drm_device *dev,
2479                                    const struct intel_pipe_wm *merged,
2480                                    enum intel_ddb_partitioning partitioning,
2481                                    struct ilk_wm_values *results)
2482 {
2483         struct intel_crtc *intel_crtc;
2484         int level, wm_lp;
2485
2486         results->enable_fbc_wm = merged->fbc_wm_enabled;
2487         results->partitioning = partitioning;
2488
2489         /* LP1+ register values */
2490         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2491                 const struct intel_wm_level *r;
2492
2493                 level = ilk_wm_lp_to_level(wm_lp, merged);
2494
2495                 r = &merged->wm[level];
2496
2497                 /*
2498                  * Maintain the watermark values even if the level is
2499                  * disabled. Doing otherwise could cause underruns.
2500                  */
2501                 results->wm_lp[wm_lp - 1] =
2502                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2503                         (r->pri_val << WM1_LP_SR_SHIFT) |
2504                         r->cur_val;
2505
2506                 if (r->enable)
2507                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2508
2509                 if (INTEL_INFO(dev)->gen >= 8)
2510                         results->wm_lp[wm_lp - 1] |=
2511                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2512                 else
2513                         results->wm_lp[wm_lp - 1] |=
2514                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2515
2516                 /*
2517                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2518                  * level is disabled. Doing otherwise could cause underruns.
2519                  */
2520                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2521                         WARN_ON(wm_lp != 1);
2522                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2523                 } else
2524                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2525         }
2526
2527         /* LP0 register values */
2528         for_each_intel_crtc(dev, intel_crtc) {
2529                 enum pipe pipe = intel_crtc->pipe;
2530                 const struct intel_wm_level *r =
2531                         &intel_crtc->wm.active.wm[0];
2532
2533                 if (WARN_ON(!r->enable))
2534                         continue;
2535
2536                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2537
2538                 results->wm_pipe[pipe] =
2539                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2540                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2541                         r->cur_val;
2542         }
2543 }
2544
2545 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2546  * case both are at the same level. Prefer r1 in case they're the same. */
2547 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2548                                                   struct intel_pipe_wm *r1,
2549                                                   struct intel_pipe_wm *r2)
2550 {
2551         int level, max_level = ilk_wm_max_level(dev);
2552         int level1 = 0, level2 = 0;
2553
2554         for (level = 1; level <= max_level; level++) {
2555                 if (r1->wm[level].enable)
2556                         level1 = level;
2557                 if (r2->wm[level].enable)
2558                         level2 = level;
2559         }
2560
2561         if (level1 == level2) {
2562                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2563                         return r2;
2564                 else
2565                         return r1;
2566         } else if (level1 > level2) {
2567                 return r1;
2568         } else {
2569                 return r2;
2570         }
2571 }
2572
2573 /* dirty bits used to track which watermarks need changes */
2574 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2575 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2576 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2577 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2578 #define WM_DIRTY_FBC (1 << 24)
2579 #define WM_DIRTY_DDB (1 << 25)
2580
2581 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2582                                          const struct ilk_wm_values *old,
2583                                          const struct ilk_wm_values *new)
2584 {
2585         unsigned int dirty = 0;
2586         enum pipe pipe;
2587         int wm_lp;
2588
2589         for_each_pipe(dev_priv, pipe) {
2590                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2591                         dirty |= WM_DIRTY_LINETIME(pipe);
2592                         /* Must disable LP1+ watermarks too */
2593                         dirty |= WM_DIRTY_LP_ALL;
2594                 }
2595
2596                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2597                         dirty |= WM_DIRTY_PIPE(pipe);
2598                         /* Must disable LP1+ watermarks too */
2599                         dirty |= WM_DIRTY_LP_ALL;
2600                 }
2601         }
2602
2603         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2604                 dirty |= WM_DIRTY_FBC;
2605                 /* Must disable LP1+ watermarks too */
2606                 dirty |= WM_DIRTY_LP_ALL;
2607         }
2608
2609         if (old->partitioning != new->partitioning) {
2610                 dirty |= WM_DIRTY_DDB;
2611                 /* Must disable LP1+ watermarks too */
2612                 dirty |= WM_DIRTY_LP_ALL;
2613         }
2614
2615         /* LP1+ watermarks already deemed dirty, no need to continue */
2616         if (dirty & WM_DIRTY_LP_ALL)
2617                 return dirty;
2618
2619         /* Find the lowest numbered LP1+ watermark in need of an update... */
2620         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2621                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2622                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2623                         break;
2624         }
2625
2626         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2627         for (; wm_lp <= 3; wm_lp++)
2628                 dirty |= WM_DIRTY_LP(wm_lp);
2629
2630         return dirty;
2631 }
2632
2633 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2634                                unsigned int dirty)
2635 {
2636         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2637         bool changed = false;
2638
2639         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2640                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2641                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2642                 changed = true;
2643         }
2644         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2645                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2646                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2647                 changed = true;
2648         }
2649         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2650                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2651                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2652                 changed = true;
2653         }
2654
2655         /*
2656          * Don't touch WM1S_LP_EN here.
2657          * Doing so could cause underruns.
2658          */
2659
2660         return changed;
2661 }
2662
2663 /*
2664  * The spec says we shouldn't write when we don't need, because every write
2665  * causes WMs to be re-evaluated, expending some power.
2666  */
2667 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2668                                 struct ilk_wm_values *results)
2669 {
2670         struct drm_device *dev = dev_priv->dev;
2671         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2672         unsigned int dirty;
2673         uint32_t val;
2674
2675         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2676         if (!dirty)
2677                 return;
2678
2679         _ilk_disable_lp_wm(dev_priv, dirty);
2680
2681         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2682                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2683         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2684                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2685         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2686                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2687
2688         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2689                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2690         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2691                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2692         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2693                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2694
2695         if (dirty & WM_DIRTY_DDB) {
2696                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2697                         val = I915_READ(WM_MISC);
2698                         if (results->partitioning == INTEL_DDB_PART_1_2)
2699                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2700                         else
2701                                 val |= WM_MISC_DATA_PARTITION_5_6;
2702                         I915_WRITE(WM_MISC, val);
2703                 } else {
2704                         val = I915_READ(DISP_ARB_CTL2);
2705                         if (results->partitioning == INTEL_DDB_PART_1_2)
2706                                 val &= ~DISP_DATA_PARTITION_5_6;
2707                         else
2708                                 val |= DISP_DATA_PARTITION_5_6;
2709                         I915_WRITE(DISP_ARB_CTL2, val);
2710                 }
2711         }
2712
2713         if (dirty & WM_DIRTY_FBC) {
2714                 val = I915_READ(DISP_ARB_CTL);
2715                 if (results->enable_fbc_wm)
2716                         val &= ~DISP_FBC_WM_DIS;
2717                 else
2718                         val |= DISP_FBC_WM_DIS;
2719                 I915_WRITE(DISP_ARB_CTL, val);
2720         }
2721
2722         if (dirty & WM_DIRTY_LP(1) &&
2723             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2724                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2725
2726         if (INTEL_INFO(dev)->gen >= 7) {
2727                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2728                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2729                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2730                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2731         }
2732
2733         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2734                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2735         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2736                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2737         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2738                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2739
2740         dev_priv->wm.hw = *results;
2741 }
2742
2743 static bool ilk_disable_lp_wm(struct drm_device *dev)
2744 {
2745         struct drm_i915_private *dev_priv = dev->dev_private;
2746
2747         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2748 }
2749
2750 /*
2751  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2752  * different active planes.
2753  */
2754
2755 #define SKL_DDB_SIZE            896     /* in blocks */
2756 #define BXT_DDB_SIZE            512
2757
2758 static void
2759 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2760                                    struct drm_crtc *for_crtc,
2761                                    const struct intel_wm_config *config,
2762                                    const struct skl_pipe_wm_parameters *params,
2763                                    struct skl_ddb_entry *alloc /* out */)
2764 {
2765         struct drm_crtc *crtc;
2766         unsigned int pipe_size, ddb_size;
2767         int nth_active_pipe;
2768
2769         if (!params->active) {
2770                 alloc->start = 0;
2771                 alloc->end = 0;
2772                 return;
2773         }
2774
2775         if (IS_BROXTON(dev))
2776                 ddb_size = BXT_DDB_SIZE;
2777         else
2778                 ddb_size = SKL_DDB_SIZE;
2779
2780         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2781
2782         nth_active_pipe = 0;
2783         for_each_crtc(dev, crtc) {
2784                 if (!to_intel_crtc(crtc)->active)
2785                         continue;
2786
2787                 if (crtc == for_crtc)
2788                         break;
2789
2790                 nth_active_pipe++;
2791         }
2792
2793         pipe_size = ddb_size / config->num_pipes_active;
2794         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2795         alloc->end = alloc->start + pipe_size;
2796 }
2797
2798 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2799 {
2800         if (config->num_pipes_active == 1)
2801                 return 32;
2802
2803         return 8;
2804 }
2805
2806 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2807 {
2808         entry->start = reg & 0x3ff;
2809         entry->end = (reg >> 16) & 0x3ff;
2810         if (entry->end)
2811                 entry->end += 1;
2812 }
2813
2814 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2815                           struct skl_ddb_allocation *ddb /* out */)
2816 {
2817         enum pipe pipe;
2818         int plane;
2819         u32 val;
2820
2821         memset(ddb, 0, sizeof(*ddb));
2822
2823         for_each_pipe(dev_priv, pipe) {
2824                 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2825                         continue;
2826
2827                 for_each_plane(dev_priv, pipe, plane) {
2828                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2829                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2830                                                    val);
2831                 }
2832
2833                 val = I915_READ(CUR_BUF_CFG(pipe));
2834                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2835                                            val);
2836         }
2837 }
2838
2839 static unsigned int
2840 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2841 {
2842
2843         /* for planar format */
2844         if (p->y_bytes_per_pixel) {
2845                 if (y)  /* y-plane data rate */
2846                         return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2847                 else    /* uv-plane data rate */
2848                         return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2849         }
2850
2851         /* for packed formats */
2852         return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2853 }
2854
2855 /*
2856  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2857  * a 8192x4096@32bpp framebuffer:
2858  *   3 * 4096 * 8192  * 4 < 2^32
2859  */
2860 static unsigned int
2861 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2862                                  const struct skl_pipe_wm_parameters *params)
2863 {
2864         unsigned int total_data_rate = 0;
2865         int plane;
2866
2867         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2868                 const struct intel_plane_wm_parameters *p;
2869
2870                 p = &params->plane[plane];
2871                 if (!p->enabled)
2872                         continue;
2873
2874                 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2875                 if (p->y_bytes_per_pixel) {
2876                         total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2877                 }
2878         }
2879
2880         return total_data_rate;
2881 }
2882
2883 static void
2884 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2885                       const struct intel_wm_config *config,
2886                       const struct skl_pipe_wm_parameters *params,
2887                       struct skl_ddb_allocation *ddb /* out */)
2888 {
2889         struct drm_device *dev = crtc->dev;
2890         struct drm_i915_private *dev_priv = dev->dev_private;
2891         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2892         enum pipe pipe = intel_crtc->pipe;
2893         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2894         uint16_t alloc_size, start, cursor_blocks;
2895         uint16_t minimum[I915_MAX_PLANES];
2896         uint16_t y_minimum[I915_MAX_PLANES];
2897         unsigned int total_data_rate;
2898         int plane;
2899
2900         skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2901         alloc_size = skl_ddb_entry_size(alloc);
2902         if (alloc_size == 0) {
2903                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2904                 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2905                        sizeof(ddb->plane[pipe][PLANE_CURSOR]));
2906                 return;
2907         }
2908
2909         cursor_blocks = skl_cursor_allocation(config);
2910         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2911         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
2912
2913         alloc_size -= cursor_blocks;
2914         alloc->end -= cursor_blocks;
2915
2916         /* 1. Allocate the mininum required blocks for each active plane */
2917         for_each_plane(dev_priv, pipe, plane) {
2918                 const struct intel_plane_wm_parameters *p;
2919
2920                 p = &params->plane[plane];
2921                 if (!p->enabled)
2922                         continue;
2923
2924                 minimum[plane] = 8;
2925                 alloc_size -= minimum[plane];
2926                 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2927                 alloc_size -= y_minimum[plane];
2928         }
2929
2930         /*
2931          * 2. Distribute the remaining space in proportion to the amount of
2932          * data each plane needs to fetch from memory.
2933          *
2934          * FIXME: we may not allocate every single block here.
2935          */
2936         total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2937
2938         start = alloc->start;
2939         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2940                 const struct intel_plane_wm_parameters *p;
2941                 unsigned int data_rate, y_data_rate;
2942                 uint16_t plane_blocks, y_plane_blocks = 0;
2943
2944                 p = &params->plane[plane];
2945                 if (!p->enabled)
2946                         continue;
2947
2948                 data_rate = skl_plane_relative_data_rate(p, 0);
2949
2950                 /*
2951                  * allocation for (packed formats) or (uv-plane part of planar format):
2952                  * promote the expression to 64 bits to avoid overflowing, the
2953                  * result is < available as data_rate / total_data_rate < 1
2954                  */
2955                 plane_blocks = minimum[plane];
2956                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2957                                         total_data_rate);
2958
2959                 ddb->plane[pipe][plane].start = start;
2960                 ddb->plane[pipe][plane].end = start + plane_blocks;
2961
2962                 start += plane_blocks;
2963
2964                 /*
2965                  * allocation for y_plane part of planar format:
2966                  */
2967                 if (p->y_bytes_per_pixel) {
2968                         y_data_rate = skl_plane_relative_data_rate(p, 1);
2969                         y_plane_blocks = y_minimum[plane];
2970                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
2971                                                 total_data_rate);
2972
2973                         ddb->y_plane[pipe][plane].start = start;
2974                         ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
2975
2976                         start += y_plane_blocks;
2977                 }
2978
2979         }
2980
2981 }
2982
2983 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2984 {
2985         /* TODO: Take into account the scalers once we support them */
2986         return config->base.adjusted_mode.crtc_clock;
2987 }
2988
2989 /*
2990  * The max latency should be 257 (max the punit can code is 255 and we add 2us
2991  * for the read latency) and bytes_per_pixel should always be <= 8, so that
2992  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2993  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2994 */
2995 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2996                                uint32_t latency)
2997 {
2998         uint32_t wm_intermediate_val, ret;
2999
3000         if (latency == 0)
3001                 return UINT_MAX;
3002
3003         wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3004         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3005
3006         return ret;
3007 }
3008
3009 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3010                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3011                                uint64_t tiling, uint32_t latency)
3012 {
3013         uint32_t ret;
3014         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3015         uint32_t wm_intermediate_val;
3016
3017         if (latency == 0)
3018                 return UINT_MAX;
3019
3020         plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3021
3022         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3023             tiling == I915_FORMAT_MOD_Yf_TILED) {
3024                 plane_bytes_per_line *= 4;
3025                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3026                 plane_blocks_per_line /= 4;
3027         } else {
3028                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3029         }
3030
3031         wm_intermediate_val = latency * pixel_rate;
3032         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3033                                 plane_blocks_per_line;
3034
3035         return ret;
3036 }
3037
3038 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3039                                        const struct intel_crtc *intel_crtc)
3040 {
3041         struct drm_device *dev = intel_crtc->base.dev;
3042         struct drm_i915_private *dev_priv = dev->dev_private;
3043         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3044         enum pipe pipe = intel_crtc->pipe;
3045
3046         if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3047                    sizeof(new_ddb->plane[pipe])))
3048                 return true;
3049
3050         if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR],
3051                     sizeof(new_ddb->plane[pipe][PLANE_CURSOR])))
3052                 return true;
3053
3054         return false;
3055 }
3056
3057 static void skl_compute_wm_global_parameters(struct drm_device *dev,
3058                                              struct intel_wm_config *config)
3059 {
3060         struct drm_crtc *crtc;
3061         struct drm_plane *plane;
3062
3063         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3064                 config->num_pipes_active += to_intel_crtc(crtc)->active;
3065
3066         /* FIXME: I don't think we need those two global parameters on SKL */
3067         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3068                 struct intel_plane *intel_plane = to_intel_plane(plane);
3069
3070                 config->sprites_enabled |= intel_plane->wm.enabled;
3071                 config->sprites_scaled |= intel_plane->wm.scaled;
3072         }
3073 }
3074
3075 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3076                                            struct skl_pipe_wm_parameters *p)
3077 {
3078         struct drm_device *dev = crtc->dev;
3079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3080         enum pipe pipe = intel_crtc->pipe;
3081         struct drm_plane *plane;
3082         struct drm_framebuffer *fb;
3083         int i = 1; /* Index for sprite planes start */
3084
3085         p->active = intel_crtc->active;
3086         if (p->active) {
3087                 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3088                 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
3089
3090                 fb = crtc->primary->state->fb;
3091                 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
3092                 if (fb) {
3093                         p->plane[0].enabled = true;
3094                         p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3095                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3096                                 drm_format_plane_cpp(fb->pixel_format, 0);
3097                         p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3098                                 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
3099                         p->plane[0].tiling = fb->modifier[0];
3100                 } else {
3101                         p->plane[0].enabled = false;
3102                         p->plane[0].bytes_per_pixel = 0;
3103                         p->plane[0].y_bytes_per_pixel = 0;
3104                         p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3105                 }
3106                 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3107                 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
3108                 p->plane[0].rotation = crtc->primary->state->rotation;
3109
3110                 fb = crtc->cursor->state->fb;
3111                 p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0;
3112                 if (fb) {
3113                         p->plane[PLANE_CURSOR].enabled = true;
3114                         p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8;
3115                         p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w;
3116                         p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h;
3117                 } else {
3118                         p->plane[PLANE_CURSOR].enabled = false;
3119                         p->plane[PLANE_CURSOR].bytes_per_pixel = 0;
3120                         p->plane[PLANE_CURSOR].horiz_pixels = 64;
3121                         p->plane[PLANE_CURSOR].vert_pixels = 64;
3122                 }
3123         }
3124
3125         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3126                 struct intel_plane *intel_plane = to_intel_plane(plane);
3127
3128                 if (intel_plane->pipe == pipe &&
3129                         plane->type == DRM_PLANE_TYPE_OVERLAY)
3130                         p->plane[i++] = intel_plane->wm;
3131         }
3132 }
3133
3134 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3135                                  struct skl_pipe_wm_parameters *p,
3136                                  struct intel_plane_wm_parameters *p_params,
3137                                  uint16_t ddb_allocation,
3138                                  int level,
3139                                  uint16_t *out_blocks, /* out */
3140                                  uint8_t *out_lines /* out */)
3141 {
3142         uint32_t latency = dev_priv->wm.skl_latency[level];
3143         uint32_t method1, method2;
3144         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3145         uint32_t res_blocks, res_lines;
3146         uint32_t selected_result;
3147         uint8_t bytes_per_pixel;
3148
3149         if (latency == 0 || !p->active || !p_params->enabled)
3150                 return false;
3151
3152         bytes_per_pixel = p_params->y_bytes_per_pixel ?
3153                 p_params->y_bytes_per_pixel :
3154                 p_params->bytes_per_pixel;
3155         method1 = skl_wm_method1(p->pixel_rate,
3156                                  bytes_per_pixel,
3157                                  latency);
3158         method2 = skl_wm_method2(p->pixel_rate,
3159                                  p->pipe_htotal,
3160                                  p_params->horiz_pixels,
3161                                  bytes_per_pixel,
3162                                  p_params->tiling,
3163                                  latency);
3164
3165         plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
3166         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3167
3168         if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3169             p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
3170                 uint32_t min_scanlines = 4;
3171                 uint32_t y_tile_minimum;
3172                 if (intel_rotation_90_or_270(p_params->rotation)) {
3173                         switch (p_params->bytes_per_pixel) {
3174                         case 1:
3175                                 min_scanlines = 16;
3176                                 break;
3177                         case 2:
3178                                 min_scanlines = 8;
3179                                 break;
3180                         case 8:
3181                                 WARN(1, "Unsupported pixel depth for rotation");
3182                         }
3183                 }
3184                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3185                 selected_result = max(method2, y_tile_minimum);
3186         } else {
3187                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3188                         selected_result = min(method1, method2);
3189                 else
3190                         selected_result = method1;
3191         }
3192
3193         res_blocks = selected_result + 1;
3194         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3195
3196         if (level >= 1 && level <= 7) {
3197                 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3198                     p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3199                         res_lines += 4;
3200                 else
3201                         res_blocks++;
3202         }
3203
3204         if (res_blocks >= ddb_allocation || res_lines > 31)
3205                 return false;
3206
3207         *out_blocks = res_blocks;
3208         *out_lines = res_lines;
3209
3210         return true;
3211 }
3212
3213 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3214                                  struct skl_ddb_allocation *ddb,
3215                                  struct skl_pipe_wm_parameters *p,
3216                                  enum pipe pipe,
3217                                  int level,
3218                                  int num_planes,
3219                                  struct skl_wm_level *result)
3220 {
3221         uint16_t ddb_blocks;
3222         int i;
3223
3224         for (i = 0; i < num_planes; i++) {
3225                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3226
3227                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3228                                                 p, &p->plane[i],
3229                                                 ddb_blocks,
3230                                                 level,
3231                                                 &result->plane_res_b[i],
3232                                                 &result->plane_res_l[i]);
3233         }
3234
3235         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]);
3236         result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p,
3237                                                  &p->plane[PLANE_CURSOR],
3238                                                  ddb_blocks, level,
3239                                                  &result->plane_res_b[PLANE_CURSOR],
3240                                                  &result->plane_res_l[PLANE_CURSOR]);
3241 }
3242
3243 static uint32_t
3244 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3245 {
3246         if (!to_intel_crtc(crtc)->active)
3247                 return 0;
3248
3249         if (WARN_ON(p->pixel_rate == 0))
3250                 return 0;
3251
3252         return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3253 }
3254
3255 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3256                                       struct skl_pipe_wm_parameters *params,
3257                                       struct skl_wm_level *trans_wm /* out */)
3258 {
3259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3260         int i;
3261
3262         if (!params->active)
3263                 return;
3264
3265         /* Until we know more, just disable transition WMs */
3266         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3267                 trans_wm->plane_en[i] = false;
3268         trans_wm->plane_en[PLANE_CURSOR] = false;
3269 }
3270
3271 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3272                                 struct skl_ddb_allocation *ddb,
3273                                 struct skl_pipe_wm_parameters *params,
3274                                 struct skl_pipe_wm *pipe_wm)
3275 {
3276         struct drm_device *dev = crtc->dev;
3277         const struct drm_i915_private *dev_priv = dev->dev_private;
3278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3279         int level, max_level = ilk_wm_max_level(dev);
3280
3281         for (level = 0; level <= max_level; level++) {
3282                 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3283                                      level, intel_num_planes(intel_crtc),
3284                                      &pipe_wm->wm[level]);
3285         }
3286         pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3287
3288         skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3289 }
3290
3291 static void skl_compute_wm_results(struct drm_device *dev,
3292                                    struct skl_pipe_wm_parameters *p,
3293                                    struct skl_pipe_wm *p_wm,
3294                                    struct skl_wm_values *r,
3295                                    struct intel_crtc *intel_crtc)
3296 {
3297         int level, max_level = ilk_wm_max_level(dev);
3298         enum pipe pipe = intel_crtc->pipe;
3299         uint32_t temp;
3300         int i;
3301
3302         for (level = 0; level <= max_level; level++) {
3303                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3304                         temp = 0;
3305
3306                         temp |= p_wm->wm[level].plane_res_l[i] <<
3307                                         PLANE_WM_LINES_SHIFT;
3308                         temp |= p_wm->wm[level].plane_res_b[i];
3309                         if (p_wm->wm[level].plane_en[i])
3310                                 temp |= PLANE_WM_EN;
3311
3312                         r->plane[pipe][i][level] = temp;
3313                 }
3314
3315                 temp = 0;
3316
3317                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3318                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3319
3320                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3321                         temp |= PLANE_WM_EN;
3322
3323                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3324
3325         }
3326
3327         /* transition WMs */
3328         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3329                 temp = 0;
3330                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3331                 temp |= p_wm->trans_wm.plane_res_b[i];
3332                 if (p_wm->trans_wm.plane_en[i])
3333                         temp |= PLANE_WM_EN;
3334
3335                 r->plane_trans[pipe][i] = temp;
3336         }
3337
3338         temp = 0;
3339         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3340         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3341         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3342                 temp |= PLANE_WM_EN;
3343
3344         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3345
3346         r->wm_linetime[pipe] = p_wm->linetime;
3347 }
3348
3349 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3350                                 const struct skl_ddb_entry *entry)
3351 {
3352         if (entry->end)
3353                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3354         else
3355                 I915_WRITE(reg, 0);
3356 }
3357
3358 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3359                                 const struct skl_wm_values *new)
3360 {
3361         struct drm_device *dev = dev_priv->dev;
3362         struct intel_crtc *crtc;
3363
3364         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3365                 int i, level, max_level = ilk_wm_max_level(dev);
3366                 enum pipe pipe = crtc->pipe;
3367
3368                 if (!new->dirty[pipe])
3369                         continue;
3370
3371                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3372
3373                 for (level = 0; level <= max_level; level++) {
3374                         for (i = 0; i < intel_num_planes(crtc); i++)
3375                                 I915_WRITE(PLANE_WM(pipe, i, level),
3376                                            new->plane[pipe][i][level]);
3377                         I915_WRITE(CUR_WM(pipe, level),
3378                                    new->plane[pipe][PLANE_CURSOR][level]);
3379                 }
3380                 for (i = 0; i < intel_num_planes(crtc); i++)
3381                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3382                                    new->plane_trans[pipe][i]);
3383                 I915_WRITE(CUR_WM_TRANS(pipe),
3384                            new->plane_trans[pipe][PLANE_CURSOR]);
3385
3386                 for (i = 0; i < intel_num_planes(crtc); i++) {
3387                         skl_ddb_entry_write(dev_priv,
3388                                             PLANE_BUF_CFG(pipe, i),
3389                                             &new->ddb.plane[pipe][i]);
3390                         skl_ddb_entry_write(dev_priv,
3391                                             PLANE_NV12_BUF_CFG(pipe, i),
3392                                             &new->ddb.y_plane[pipe][i]);
3393                 }
3394
3395                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3396                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3397         }
3398 }
3399
3400 /*
3401  * When setting up a new DDB allocation arrangement, we need to correctly
3402  * sequence the times at which the new allocations for the pipes are taken into
3403  * account or we'll have pipes fetching from space previously allocated to
3404  * another pipe.
3405  *
3406  * Roughly the sequence looks like:
3407  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3408  *     overlapping with a previous light-up pipe (another way to put it is:
3409  *     pipes with their new allocation strickly included into their old ones).
3410  *  2. re-allocate the other pipes that get their allocation reduced
3411  *  3. allocate the pipes having their allocation increased
3412  *
3413  * Steps 1. and 2. are here to take care of the following case:
3414  * - Initially DDB looks like this:
3415  *     |   B    |   C    |
3416  * - enable pipe A.
3417  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3418  *   allocation
3419  *     |  A  |  B  |  C  |
3420  *
3421  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3422  */
3423
3424 static void
3425 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3426 {
3427         int plane;
3428
3429         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3430
3431         for_each_plane(dev_priv, pipe, plane) {
3432                 I915_WRITE(PLANE_SURF(pipe, plane),
3433                            I915_READ(PLANE_SURF(pipe, plane)));
3434         }
3435         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3436 }
3437
3438 static bool
3439 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3440                             const struct skl_ddb_allocation *new,
3441                             enum pipe pipe)
3442 {
3443         uint16_t old_size, new_size;
3444
3445         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3446         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3447
3448         return old_size != new_size &&
3449                new->pipe[pipe].start >= old->pipe[pipe].start &&
3450                new->pipe[pipe].end <= old->pipe[pipe].end;
3451 }
3452
3453 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3454                                 struct skl_wm_values *new_values)
3455 {
3456         struct drm_device *dev = dev_priv->dev;
3457         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3458         bool reallocated[I915_MAX_PIPES] = {};
3459         struct intel_crtc *crtc;
3460         enum pipe pipe;
3461
3462         new_ddb = &new_values->ddb;
3463         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3464
3465         /*
3466          * First pass: flush the pipes with the new allocation contained into
3467          * the old space.
3468          *
3469          * We'll wait for the vblank on those pipes to ensure we can safely
3470          * re-allocate the freed space without this pipe fetching from it.
3471          */
3472         for_each_intel_crtc(dev, crtc) {
3473                 if (!crtc->active)
3474                         continue;
3475
3476                 pipe = crtc->pipe;
3477
3478                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3479                         continue;
3480
3481                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3482                 intel_wait_for_vblank(dev, pipe);
3483
3484                 reallocated[pipe] = true;
3485         }
3486
3487
3488         /*
3489          * Second pass: flush the pipes that are having their allocation
3490          * reduced, but overlapping with a previous allocation.
3491          *
3492          * Here as well we need to wait for the vblank to make sure the freed
3493          * space is not used anymore.
3494          */
3495         for_each_intel_crtc(dev, crtc) {
3496                 if (!crtc->active)
3497                         continue;
3498
3499                 pipe = crtc->pipe;
3500
3501                 if (reallocated[pipe])
3502                         continue;
3503
3504                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3505                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3506                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3507                         intel_wait_for_vblank(dev, pipe);
3508                         reallocated[pipe] = true;
3509                 }
3510         }
3511
3512         /*
3513          * Third pass: flush the pipes that got more space allocated.
3514          *
3515          * We don't need to actively wait for the update here, next vblank
3516          * will just get more DDB space with the correct WM values.
3517          */
3518         for_each_intel_crtc(dev, crtc) {
3519                 if (!crtc->active)
3520                         continue;
3521
3522                 pipe = crtc->pipe;
3523
3524                 /*
3525                  * At this point, only the pipes more space than before are
3526                  * left to re-allocate.
3527                  */
3528                 if (reallocated[pipe])
3529                         continue;
3530
3531                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3532         }
3533 }
3534
3535 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3536                                struct skl_pipe_wm_parameters *params,
3537                                struct intel_wm_config *config,
3538                                struct skl_ddb_allocation *ddb, /* out */
3539                                struct skl_pipe_wm *pipe_wm /* out */)
3540 {
3541         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3542
3543         skl_compute_wm_pipe_parameters(crtc, params);
3544         skl_allocate_pipe_ddb(crtc, config, params, ddb);
3545         skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3546
3547         if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3548                 return false;
3549
3550         intel_crtc->wm.skl_active = *pipe_wm;
3551
3552         return true;
3553 }
3554
3555 static void skl_update_other_pipe_wm(struct drm_device *dev,
3556                                      struct drm_crtc *crtc,
3557                                      struct intel_wm_config *config,
3558                                      struct skl_wm_values *r)
3559 {
3560         struct intel_crtc *intel_crtc;
3561         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3562
3563         /*
3564          * If the WM update hasn't changed the allocation for this_crtc (the
3565          * crtc we are currently computing the new WM values for), other
3566          * enabled crtcs will keep the same allocation and we don't need to
3567          * recompute anything for them.
3568          */
3569         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3570                 return;
3571
3572         /*
3573          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3574          * other active pipes need new DDB allocation and WM values.
3575          */
3576         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3577                                 base.head) {
3578                 struct skl_pipe_wm_parameters params = {};
3579                 struct skl_pipe_wm pipe_wm = {};
3580                 bool wm_changed;
3581
3582                 if (this_crtc->pipe == intel_crtc->pipe)
3583                         continue;
3584
3585                 if (!intel_crtc->active)
3586                         continue;
3587
3588                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3589                                                 &params, config,
3590                                                 &r->ddb, &pipe_wm);
3591
3592                 /*
3593                  * If we end up re-computing the other pipe WM values, it's
3594                  * because it was really needed, so we expect the WM values to
3595                  * be different.
3596                  */
3597                 WARN_ON(!wm_changed);
3598
3599                 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3600                 r->dirty[intel_crtc->pipe] = true;
3601         }
3602 }
3603
3604 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3605 {
3606         watermarks->wm_linetime[pipe] = 0;
3607         memset(watermarks->plane[pipe], 0,
3608                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3609         memset(watermarks->plane_trans[pipe],
3610                0, sizeof(uint32_t) * I915_MAX_PLANES);
3611         watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3612
3613         /* Clear ddb entries for pipe */
3614         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3615         memset(&watermarks->ddb.plane[pipe], 0,
3616                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3617         memset(&watermarks->ddb.y_plane[pipe], 0,
3618                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3619         memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3620                sizeof(struct skl_ddb_entry));
3621
3622 }
3623
3624 static void skl_update_wm(struct drm_crtc *crtc)
3625 {
3626         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3627         struct drm_device *dev = crtc->dev;
3628         struct drm_i915_private *dev_priv = dev->dev_private;
3629         struct skl_pipe_wm_parameters params = {};
3630         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3631         struct skl_pipe_wm pipe_wm = {};
3632         struct intel_wm_config config = {};
3633
3634
3635         /* Clear all dirty flags */
3636         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3637
3638         skl_clear_wm(results, intel_crtc->pipe);
3639
3640         skl_compute_wm_global_parameters(dev, &config);
3641
3642         if (!skl_update_pipe_wm(crtc, &params, &config,
3643                                 &results->ddb, &pipe_wm))
3644                 return;
3645
3646         skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3647         results->dirty[intel_crtc->pipe] = true;
3648
3649         skl_update_other_pipe_wm(dev, crtc, &config, results);
3650         skl_write_wm_values(dev_priv, results);
3651         skl_flush_wm_values(dev_priv, results);
3652
3653         /* store the new configuration */
3654         dev_priv->wm.skl_hw = *results;
3655 }
3656
3657 static void
3658 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3659                      uint32_t sprite_width, uint32_t sprite_height,
3660                      int pixel_size, bool enabled, bool scaled)
3661 {
3662         struct intel_plane *intel_plane = to_intel_plane(plane);
3663         struct drm_framebuffer *fb = plane->state->fb;
3664
3665         intel_plane->wm.enabled = enabled;
3666         intel_plane->wm.scaled = scaled;
3667         intel_plane->wm.horiz_pixels = sprite_width;
3668         intel_plane->wm.vert_pixels = sprite_height;
3669         intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3670
3671         /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3672         intel_plane->wm.bytes_per_pixel =
3673                 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3674                 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3675         intel_plane->wm.y_bytes_per_pixel =
3676                 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3677                 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3678
3679         /*
3680          * Framebuffer can be NULL on plane disable, but it does not
3681          * matter for watermarks if we assume no tiling in that case.
3682          */
3683         if (fb)
3684                 intel_plane->wm.tiling = fb->modifier[0];
3685         intel_plane->wm.rotation = plane->state->rotation;
3686
3687         skl_update_wm(crtc);
3688 }
3689
3690 static void ilk_update_wm(struct drm_crtc *crtc)
3691 {
3692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3693         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3694         struct drm_device *dev = crtc->dev;
3695         struct drm_i915_private *dev_priv = dev->dev_private;
3696         struct ilk_wm_maximums max;
3697         struct ilk_wm_values results = {};
3698         enum intel_ddb_partitioning partitioning;
3699         struct intel_pipe_wm pipe_wm = {};
3700         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3701         struct intel_wm_config config = {};
3702
3703         WARN_ON(cstate->base.active != intel_crtc->active);
3704
3705         intel_compute_pipe_wm(cstate, &pipe_wm);
3706
3707         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3708                 return;
3709
3710         intel_crtc->wm.active = pipe_wm;
3711
3712         ilk_compute_wm_config(dev, &config);
3713
3714         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3715         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3716
3717         /* 5/6 split only in single pipe config on IVB+ */
3718         if (INTEL_INFO(dev)->gen >= 7 &&
3719             config.num_pipes_active == 1 && config.sprites_enabled) {
3720                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3721                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3722
3723                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3724         } else {
3725                 best_lp_wm = &lp_wm_1_2;
3726         }
3727
3728         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3729                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3730
3731         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3732
3733         ilk_write_wm_values(dev_priv, &results);
3734 }
3735
3736 static void
3737 ilk_update_sprite_wm(struct drm_plane *plane,
3738                      struct drm_crtc *crtc,
3739                      uint32_t sprite_width, uint32_t sprite_height,
3740                      int pixel_size, bool enabled, bool scaled)
3741 {
3742         struct drm_device *dev = plane->dev;
3743         struct intel_plane *intel_plane = to_intel_plane(plane);
3744
3745         /*
3746          * IVB workaround: must disable low power watermarks for at least
3747          * one frame before enabling scaling.  LP watermarks can be re-enabled
3748          * when scaling is disabled.
3749          *
3750          * WaCxSRDisabledForSpriteScaling:ivb
3751          */
3752         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3753                 intel_wait_for_vblank(dev, intel_plane->pipe);
3754
3755         ilk_update_wm(crtc);
3756 }
3757
3758 static void skl_pipe_wm_active_state(uint32_t val,
3759                                      struct skl_pipe_wm *active,
3760                                      bool is_transwm,
3761                                      bool is_cursor,
3762                                      int i,
3763                                      int level)
3764 {
3765         bool is_enabled = (val & PLANE_WM_EN) != 0;
3766
3767         if (!is_transwm) {
3768                 if (!is_cursor) {
3769                         active->wm[level].plane_en[i] = is_enabled;
3770                         active->wm[level].plane_res_b[i] =
3771                                         val & PLANE_WM_BLOCKS_MASK;
3772                         active->wm[level].plane_res_l[i] =
3773                                         (val >> PLANE_WM_LINES_SHIFT) &
3774                                                 PLANE_WM_LINES_MASK;
3775                 } else {
3776                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3777                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3778                                         val & PLANE_WM_BLOCKS_MASK;
3779                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3780                                         (val >> PLANE_WM_LINES_SHIFT) &
3781                                                 PLANE_WM_LINES_MASK;
3782                 }
3783         } else {
3784                 if (!is_cursor) {
3785                         active->trans_wm.plane_en[i] = is_enabled;
3786                         active->trans_wm.plane_res_b[i] =
3787                                         val & PLANE_WM_BLOCKS_MASK;
3788                         active->trans_wm.plane_res_l[i] =
3789                                         (val >> PLANE_WM_LINES_SHIFT) &
3790                                                 PLANE_WM_LINES_MASK;
3791                 } else {
3792                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3793                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3794                                         val & PLANE_WM_BLOCKS_MASK;
3795                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3796                                         (val >> PLANE_WM_LINES_SHIFT) &
3797                                                 PLANE_WM_LINES_MASK;
3798                 }
3799         }
3800 }
3801
3802 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3803 {
3804         struct drm_device *dev = crtc->dev;
3805         struct drm_i915_private *dev_priv = dev->dev_private;
3806         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3807         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3808         struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3809         enum pipe pipe = intel_crtc->pipe;
3810         int level, i, max_level;
3811         uint32_t temp;
3812
3813         max_level = ilk_wm_max_level(dev);
3814
3815         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3816
3817         for (level = 0; level <= max_level; level++) {
3818                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3819                         hw->plane[pipe][i][level] =
3820                                         I915_READ(PLANE_WM(pipe, i, level));
3821                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3822         }
3823
3824         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3825                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3826         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3827
3828         if (!intel_crtc->active)
3829                 return;
3830
3831         hw->dirty[pipe] = true;
3832
3833         active->linetime = hw->wm_linetime[pipe];
3834
3835         for (level = 0; level <= max_level; level++) {
3836                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3837                         temp = hw->plane[pipe][i][level];
3838                         skl_pipe_wm_active_state(temp, active, false,
3839                                                 false, i, level);
3840                 }
3841                 temp = hw->plane[pipe][PLANE_CURSOR][level];
3842                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3843         }
3844
3845         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3846                 temp = hw->plane_trans[pipe][i];
3847                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3848         }
3849
3850         temp = hw->plane_trans[pipe][PLANE_CURSOR];
3851         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3852 }
3853
3854 void skl_wm_get_hw_state(struct drm_device *dev)
3855 {
3856         struct drm_i915_private *dev_priv = dev->dev_private;
3857         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3858         struct drm_crtc *crtc;
3859
3860         skl_ddb_get_hw_state(dev_priv, ddb);
3861         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3862                 skl_pipe_wm_get_hw_state(crtc);
3863 }
3864
3865 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3866 {
3867         struct drm_device *dev = crtc->dev;
3868         struct drm_i915_private *dev_priv = dev->dev_private;
3869         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3871         struct intel_pipe_wm *active = &intel_crtc->wm.active;
3872         enum pipe pipe = intel_crtc->pipe;
3873         static const unsigned int wm0_pipe_reg[] = {
3874                 [PIPE_A] = WM0_PIPEA_ILK,
3875                 [PIPE_B] = WM0_PIPEB_ILK,
3876                 [PIPE_C] = WM0_PIPEC_IVB,
3877         };
3878
3879         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3880         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3881                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3882
3883         active->pipe_enabled = intel_crtc->active;
3884
3885         if (active->pipe_enabled) {
3886                 u32 tmp = hw->wm_pipe[pipe];
3887
3888                 /*
3889                  * For active pipes LP0 watermark is marked as
3890                  * enabled, and LP1+ watermaks as disabled since
3891                  * we can't really reverse compute them in case
3892                  * multiple pipes are active.
3893                  */
3894                 active->wm[0].enable = true;
3895                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3896                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3897                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3898                 active->linetime = hw->wm_linetime[pipe];
3899         } else {
3900                 int level, max_level = ilk_wm_max_level(dev);
3901
3902                 /*
3903                  * For inactive pipes, all watermark levels
3904                  * should be marked as enabled but zeroed,
3905                  * which is what we'd compute them to.
3906                  */
3907                 for (level = 0; level <= max_level; level++)
3908                         active->wm[level].enable = true;
3909         }
3910 }
3911
3912 #define _FW_WM(value, plane) \
3913         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3914 #define _FW_WM_VLV(value, plane) \
3915         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3916
3917 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3918                                struct vlv_wm_values *wm)
3919 {
3920         enum pipe pipe;
3921         uint32_t tmp;
3922
3923         for_each_pipe(dev_priv, pipe) {
3924                 tmp = I915_READ(VLV_DDL(pipe));
3925
3926                 wm->ddl[pipe].primary =
3927                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3928                 wm->ddl[pipe].cursor =
3929                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3930                 wm->ddl[pipe].sprite[0] =
3931                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3932                 wm->ddl[pipe].sprite[1] =
3933                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3934         }
3935
3936         tmp = I915_READ(DSPFW1);
3937         wm->sr.plane = _FW_WM(tmp, SR);
3938         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3939         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3940         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3941
3942         tmp = I915_READ(DSPFW2);
3943         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3944         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3945         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3946
3947         tmp = I915_READ(DSPFW3);
3948         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3949
3950         if (IS_CHERRYVIEW(dev_priv)) {
3951                 tmp = I915_READ(DSPFW7_CHV);
3952                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3953                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3954
3955                 tmp = I915_READ(DSPFW8_CHV);
3956                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3957                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3958
3959                 tmp = I915_READ(DSPFW9_CHV);
3960                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3961                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3962
3963                 tmp = I915_READ(DSPHOWM);
3964                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3965                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3966                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3967                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3968                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3969                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3970                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3971                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3972                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3973                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3974         } else {
3975                 tmp = I915_READ(DSPFW7);
3976                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3977                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3978
3979                 tmp = I915_READ(DSPHOWM);
3980                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3981                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3982                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3983                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3984                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3985                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3986                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3987         }
3988 }
3989
3990 #undef _FW_WM
3991 #undef _FW_WM_VLV
3992
3993 void vlv_wm_get_hw_state(struct drm_device *dev)
3994 {
3995         struct drm_i915_private *dev_priv = to_i915(dev);
3996         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3997         struct intel_plane *plane;
3998         enum pipe pipe;
3999         u32 val;
4000
4001         vlv_read_wm_values(dev_priv, wm);
4002
4003         for_each_intel_plane(dev, plane) {
4004                 switch (plane->base.type) {
4005                         int sprite;
4006                 case DRM_PLANE_TYPE_CURSOR:
4007                         plane->wm.fifo_size = 63;
4008                         break;
4009                 case DRM_PLANE_TYPE_PRIMARY:
4010                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4011                         break;
4012                 case DRM_PLANE_TYPE_OVERLAY:
4013                         sprite = plane->plane;
4014                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4015                         break;
4016                 }
4017         }
4018
4019         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4020         wm->level = VLV_WM_LEVEL_PM2;
4021
4022         if (IS_CHERRYVIEW(dev_priv)) {
4023                 mutex_lock(&dev_priv->rps.hw_lock);
4024
4025                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4026                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4027                         wm->level = VLV_WM_LEVEL_PM5;
4028
4029                 /*
4030                  * If DDR DVFS is disabled in the BIOS, Punit
4031                  * will never ack the request. So if that happens
4032                  * assume we don't have to enable/disable DDR DVFS
4033                  * dynamically. To test that just set the REQ_ACK
4034                  * bit to poke the Punit, but don't change the
4035                  * HIGH/LOW bits so that we don't actually change
4036                  * the current state.
4037                  */
4038                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4039                 val |= FORCE_DDR_FREQ_REQ_ACK;
4040                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4041
4042                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4043                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4044                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4045                                       "assuming DDR DVFS is disabled\n");
4046                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4047                 } else {
4048                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4049                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4050                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4051                 }
4052
4053                 mutex_unlock(&dev_priv->rps.hw_lock);
4054         }
4055
4056         for_each_pipe(dev_priv, pipe)
4057                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4058                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4059                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4060
4061         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4062                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4063 }
4064
4065 void ilk_wm_get_hw_state(struct drm_device *dev)
4066 {
4067         struct drm_i915_private *dev_priv = dev->dev_private;
4068         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4069         struct drm_crtc *crtc;
4070
4071         for_each_crtc(dev, crtc)
4072                 ilk_pipe_wm_get_hw_state(crtc);
4073
4074         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4075         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4076         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4077
4078         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4079         if (INTEL_INFO(dev)->gen >= 7) {
4080                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4081                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4082         }
4083
4084         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4085                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4086                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4087         else if (IS_IVYBRIDGE(dev))
4088                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4089                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4090
4091         hw->enable_fbc_wm =
4092                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4093 }
4094
4095 /**
4096  * intel_update_watermarks - update FIFO watermark values based on current modes
4097  *
4098  * Calculate watermark values for the various WM regs based on current mode
4099  * and plane configuration.
4100  *
4101  * There are several cases to deal with here:
4102  *   - normal (i.e. non-self-refresh)
4103  *   - self-refresh (SR) mode
4104  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4105  *   - lines are small relative to FIFO size (buffer can hold more than 2
4106  *     lines), so need to account for TLB latency
4107  *
4108  *   The normal calculation is:
4109  *     watermark = dotclock * bytes per pixel * latency
4110  *   where latency is platform & configuration dependent (we assume pessimal
4111  *   values here).
4112  *
4113  *   The SR calculation is:
4114  *     watermark = (trunc(latency/line time)+1) * surface width *
4115  *       bytes per pixel
4116  *   where
4117  *     line time = htotal / dotclock
4118  *     surface width = hdisplay for normal plane and 64 for cursor
4119  *   and latency is assumed to be high, as above.
4120  *
4121  * The final value programmed to the register should always be rounded up,
4122  * and include an extra 2 entries to account for clock crossings.
4123  *
4124  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4125  * to set the non-SR watermarks to 8.
4126  */
4127 void intel_update_watermarks(struct drm_crtc *crtc)
4128 {
4129         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4130
4131         if (dev_priv->display.update_wm)
4132                 dev_priv->display.update_wm(crtc);
4133 }
4134
4135 void intel_update_sprite_watermarks(struct drm_plane *plane,
4136                                     struct drm_crtc *crtc,
4137                                     uint32_t sprite_width,
4138                                     uint32_t sprite_height,
4139                                     int pixel_size,
4140                                     bool enabled, bool scaled)
4141 {
4142         struct drm_i915_private *dev_priv = plane->dev->dev_private;
4143
4144         if (dev_priv->display.update_sprite_wm)
4145                 dev_priv->display.update_sprite_wm(plane, crtc,
4146                                                    sprite_width, sprite_height,
4147                                                    pixel_size, enabled, scaled);
4148 }
4149
4150 /**
4151  * Lock protecting IPS related data structures
4152  */
4153 DEFINE_SPINLOCK(mchdev_lock);
4154
4155 /* Global for IPS driver to get at the current i915 device. Protected by
4156  * mchdev_lock. */
4157 static struct drm_i915_private *i915_mch_dev;
4158
4159 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4160 {
4161         struct drm_i915_private *dev_priv = dev->dev_private;
4162         u16 rgvswctl;
4163
4164         assert_spin_locked(&mchdev_lock);
4165
4166         rgvswctl = I915_READ16(MEMSWCTL);
4167         if (rgvswctl & MEMCTL_CMD_STS) {
4168                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4169                 return false; /* still busy with another command */
4170         }
4171
4172         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4173                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4174         I915_WRITE16(MEMSWCTL, rgvswctl);
4175         POSTING_READ16(MEMSWCTL);
4176
4177         rgvswctl |= MEMCTL_CMD_STS;
4178         I915_WRITE16(MEMSWCTL, rgvswctl);
4179
4180         return true;
4181 }
4182
4183 static void ironlake_enable_drps(struct drm_device *dev)
4184 {
4185         struct drm_i915_private *dev_priv = dev->dev_private;
4186         u32 rgvmodectl = I915_READ(MEMMODECTL);
4187         u8 fmax, fmin, fstart, vstart;
4188
4189         spin_lock_irq(&mchdev_lock);
4190
4191         /* Enable temp reporting */
4192         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4193         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4194
4195         /* 100ms RC evaluation intervals */
4196         I915_WRITE(RCUPEI, 100000);
4197         I915_WRITE(RCDNEI, 100000);
4198
4199         /* Set max/min thresholds to 90ms and 80ms respectively */
4200         I915_WRITE(RCBMAXAVG, 90000);
4201         I915_WRITE(RCBMINAVG, 80000);
4202
4203         I915_WRITE(MEMIHYST, 1);
4204
4205         /* Set up min, max, and cur for interrupt handling */
4206         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4207         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4208         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4209                 MEMMODE_FSTART_SHIFT;
4210
4211         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4212                 PXVFREQ_PX_SHIFT;
4213
4214         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4215         dev_priv->ips.fstart = fstart;
4216
4217         dev_priv->ips.max_delay = fstart;
4218         dev_priv->ips.min_delay = fmin;
4219         dev_priv->ips.cur_delay = fstart;
4220
4221         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4222                          fmax, fmin, fstart);
4223
4224         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4225
4226         /*
4227          * Interrupts will be enabled in ironlake_irq_postinstall
4228          */
4229
4230         I915_WRITE(VIDSTART, vstart);
4231         POSTING_READ(VIDSTART);
4232
4233         rgvmodectl |= MEMMODE_SWMODE_EN;
4234         I915_WRITE(MEMMODECTL, rgvmodectl);
4235
4236         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4237                 DRM_ERROR("stuck trying to change perf mode\n");
4238         mdelay(1);
4239
4240         ironlake_set_drps(dev, fstart);
4241
4242         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4243                 I915_READ(DDREC) + I915_READ(CSIEC);
4244         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4245         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4246         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4247
4248         spin_unlock_irq(&mchdev_lock);
4249 }
4250
4251 static void ironlake_disable_drps(struct drm_device *dev)
4252 {
4253         struct drm_i915_private *dev_priv = dev->dev_private;
4254         u16 rgvswctl;
4255
4256         spin_lock_irq(&mchdev_lock);
4257
4258         rgvswctl = I915_READ16(MEMSWCTL);
4259
4260         /* Ack interrupts, disable EFC interrupt */
4261         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4262         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4263         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4264         I915_WRITE(DEIIR, DE_PCU_EVENT);
4265         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4266
4267         /* Go back to the starting frequency */
4268         ironlake_set_drps(dev, dev_priv->ips.fstart);
4269         mdelay(1);
4270         rgvswctl |= MEMCTL_CMD_STS;
4271         I915_WRITE(MEMSWCTL, rgvswctl);
4272         mdelay(1);
4273
4274         spin_unlock_irq(&mchdev_lock);
4275 }
4276
4277 /* There's a funny hw issue where the hw returns all 0 when reading from
4278  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4279  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4280  * all limits and the gpu stuck at whatever frequency it is at atm).
4281  */
4282 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4283 {
4284         u32 limits;
4285
4286         /* Only set the down limit when we've reached the lowest level to avoid
4287          * getting more interrupts, otherwise leave this clear. This prevents a
4288          * race in the hw when coming out of rc6: There's a tiny window where
4289          * the hw runs at the minimal clock before selecting the desired
4290          * frequency, if the down threshold expires in that window we will not
4291          * receive a down interrupt. */
4292         if (IS_GEN9(dev_priv->dev)) {
4293                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4294                 if (val <= dev_priv->rps.min_freq_softlimit)
4295                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4296         } else {
4297                 limits = dev_priv->rps.max_freq_softlimit << 24;
4298                 if (val <= dev_priv->rps.min_freq_softlimit)
4299                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4300         }
4301
4302         return limits;
4303 }
4304
4305 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4306 {
4307         int new_power;
4308         u32 threshold_up = 0, threshold_down = 0; /* in % */
4309         u32 ei_up = 0, ei_down = 0;
4310
4311         new_power = dev_priv->rps.power;
4312         switch (dev_priv->rps.power) {
4313         case LOW_POWER:
4314                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4315                         new_power = BETWEEN;
4316                 break;
4317
4318         case BETWEEN:
4319                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4320                         new_power = LOW_POWER;
4321                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4322                         new_power = HIGH_POWER;
4323                 break;
4324
4325         case HIGH_POWER:
4326                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4327                         new_power = BETWEEN;
4328                 break;
4329         }
4330         /* Max/min bins are special */
4331         if (val <= dev_priv->rps.min_freq_softlimit)
4332                 new_power = LOW_POWER;
4333         if (val >= dev_priv->rps.max_freq_softlimit)
4334                 new_power = HIGH_POWER;
4335         if (new_power == dev_priv->rps.power)
4336                 return;
4337
4338         /* Note the units here are not exactly 1us, but 1280ns. */
4339         switch (new_power) {
4340         case LOW_POWER:
4341                 /* Upclock if more than 95% busy over 16ms */
4342                 ei_up = 16000;
4343                 threshold_up = 95;
4344
4345                 /* Downclock if less than 85% busy over 32ms */
4346                 ei_down = 32000;
4347                 threshold_down = 85;
4348                 break;
4349
4350         case BETWEEN:
4351                 /* Upclock if more than 90% busy over 13ms */
4352                 ei_up = 13000;
4353                 threshold_up = 90;
4354
4355                 /* Downclock if less than 75% busy over 32ms */
4356                 ei_down = 32000;
4357                 threshold_down = 75;
4358                 break;
4359
4360         case HIGH_POWER:
4361                 /* Upclock if more than 85% busy over 10ms */
4362                 ei_up = 10000;
4363                 threshold_up = 85;
4364
4365                 /* Downclock if less than 60% busy over 32ms */
4366                 ei_down = 32000;
4367                 threshold_down = 60;
4368                 break;
4369         }
4370
4371         I915_WRITE(GEN6_RP_UP_EI,
4372                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4373         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4374                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4375
4376         I915_WRITE(GEN6_RP_DOWN_EI,
4377                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4378         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4379                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4380
4381          I915_WRITE(GEN6_RP_CONTROL,
4382                     GEN6_RP_MEDIA_TURBO |
4383                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4384                     GEN6_RP_MEDIA_IS_GFX |
4385                     GEN6_RP_ENABLE |
4386                     GEN6_RP_UP_BUSY_AVG |
4387                     GEN6_RP_DOWN_IDLE_AVG);
4388
4389         dev_priv->rps.power = new_power;
4390         dev_priv->rps.up_threshold = threshold_up;
4391         dev_priv->rps.down_threshold = threshold_down;
4392         dev_priv->rps.last_adj = 0;
4393 }
4394
4395 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4396 {
4397         u32 mask = 0;
4398
4399         if (val > dev_priv->rps.min_freq_softlimit)
4400                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4401         if (val < dev_priv->rps.max_freq_softlimit)
4402                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4403
4404         mask &= dev_priv->pm_rps_events;
4405
4406         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4407 }
4408
4409 /* gen6_set_rps is called to update the frequency request, but should also be
4410  * called when the range (min_delay and max_delay) is modified so that we can
4411  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4412 static void gen6_set_rps(struct drm_device *dev, u8 val)
4413 {
4414         struct drm_i915_private *dev_priv = dev->dev_private;
4415
4416         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4417         if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
4418                 return;
4419
4420         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4421         WARN_ON(val > dev_priv->rps.max_freq);
4422         WARN_ON(val < dev_priv->rps.min_freq);
4423
4424         /* min/max delay may still have been modified so be sure to
4425          * write the limits value.
4426          */
4427         if (val != dev_priv->rps.cur_freq) {
4428                 gen6_set_rps_thresholds(dev_priv, val);
4429
4430                 if (IS_GEN9(dev))
4431                         I915_WRITE(GEN6_RPNSWREQ,
4432                                    GEN9_FREQUENCY(val));
4433                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4434                         I915_WRITE(GEN6_RPNSWREQ,
4435                                    HSW_FREQUENCY(val));
4436                 else
4437                         I915_WRITE(GEN6_RPNSWREQ,
4438                                    GEN6_FREQUENCY(val) |
4439                                    GEN6_OFFSET(0) |
4440                                    GEN6_AGGRESSIVE_TURBO);
4441         }
4442
4443         /* Make sure we continue to get interrupts
4444          * until we hit the minimum or maximum frequencies.
4445          */
4446         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4447         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4448
4449         POSTING_READ(GEN6_RPNSWREQ);
4450
4451         dev_priv->rps.cur_freq = val;
4452         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4453 }
4454
4455 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4456 {
4457         struct drm_i915_private *dev_priv = dev->dev_private;
4458
4459         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4460         WARN_ON(val > dev_priv->rps.max_freq);
4461         WARN_ON(val < dev_priv->rps.min_freq);
4462
4463         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4464                       "Odd GPU freq value\n"))
4465                 val &= ~1;
4466
4467         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4468
4469         if (val != dev_priv->rps.cur_freq) {
4470                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4471                 if (!IS_CHERRYVIEW(dev_priv))
4472                         gen6_set_rps_thresholds(dev_priv, val);
4473         }
4474
4475         dev_priv->rps.cur_freq = val;
4476         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4477 }
4478
4479 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4480  *
4481  * * If Gfx is Idle, then
4482  * 1. Forcewake Media well.
4483  * 2. Request idle freq.
4484  * 3. Release Forcewake of Media well.
4485 */
4486 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4487 {
4488         u32 val = dev_priv->rps.idle_freq;
4489
4490         if (dev_priv->rps.cur_freq <= val)
4491                 return;
4492
4493         /* Wake up the media well, as that takes a lot less
4494          * power than the Render well. */
4495         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4496         valleyview_set_rps(dev_priv->dev, val);
4497         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4498 }
4499
4500 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4501 {
4502         mutex_lock(&dev_priv->rps.hw_lock);
4503         if (dev_priv->rps.enabled) {
4504                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4505                         gen6_rps_reset_ei(dev_priv);
4506                 I915_WRITE(GEN6_PMINTRMSK,
4507                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4508         }
4509         mutex_unlock(&dev_priv->rps.hw_lock);
4510 }
4511
4512 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4513 {
4514         struct drm_device *dev = dev_priv->dev;
4515
4516         mutex_lock(&dev_priv->rps.hw_lock);
4517         if (dev_priv->rps.enabled) {
4518                 if (IS_VALLEYVIEW(dev))
4519                         vlv_set_rps_idle(dev_priv);
4520                 else
4521                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4522                 dev_priv->rps.last_adj = 0;
4523                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4524         }
4525         mutex_unlock(&dev_priv->rps.hw_lock);
4526
4527         spin_lock(&dev_priv->rps.client_lock);
4528         while (!list_empty(&dev_priv->rps.clients))
4529                 list_del_init(dev_priv->rps.clients.next);
4530         spin_unlock(&dev_priv->rps.client_lock);
4531 }
4532
4533 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4534                     struct intel_rps_client *rps,
4535                     unsigned long submitted)
4536 {
4537         /* This is intentionally racy! We peek at the state here, then
4538          * validate inside the RPS worker.
4539          */
4540         if (!(dev_priv->mm.busy &&
4541               dev_priv->rps.enabled &&
4542               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4543                 return;
4544
4545         /* Force a RPS boost (and don't count it against the client) if
4546          * the GPU is severely congested.
4547          */
4548         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4549                 rps = NULL;
4550
4551         spin_lock(&dev_priv->rps.client_lock);
4552         if (rps == NULL || list_empty(&rps->link)) {
4553                 spin_lock_irq(&dev_priv->irq_lock);
4554                 if (dev_priv->rps.interrupts_enabled) {
4555                         dev_priv->rps.client_boost = true;
4556                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4557                 }
4558                 spin_unlock_irq(&dev_priv->irq_lock);
4559
4560                 if (rps != NULL) {
4561                         list_add(&rps->link, &dev_priv->rps.clients);
4562                         rps->boosts++;
4563                 } else
4564                         dev_priv->rps.boosts++;
4565         }
4566         spin_unlock(&dev_priv->rps.client_lock);
4567 }
4568
4569 void intel_set_rps(struct drm_device *dev, u8 val)
4570 {
4571         if (IS_VALLEYVIEW(dev))
4572                 valleyview_set_rps(dev, val);
4573         else
4574                 gen6_set_rps(dev, val);
4575 }
4576
4577 static void gen9_disable_rps(struct drm_device *dev)
4578 {
4579         struct drm_i915_private *dev_priv = dev->dev_private;
4580
4581         I915_WRITE(GEN6_RC_CONTROL, 0);
4582         I915_WRITE(GEN9_PG_ENABLE, 0);
4583 }
4584
4585 static void gen6_disable_rps(struct drm_device *dev)
4586 {
4587         struct drm_i915_private *dev_priv = dev->dev_private;
4588
4589         I915_WRITE(GEN6_RC_CONTROL, 0);
4590         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4591 }
4592
4593 static void cherryview_disable_rps(struct drm_device *dev)
4594 {
4595         struct drm_i915_private *dev_priv = dev->dev_private;
4596
4597         I915_WRITE(GEN6_RC_CONTROL, 0);
4598 }
4599
4600 static void valleyview_disable_rps(struct drm_device *dev)
4601 {
4602         struct drm_i915_private *dev_priv = dev->dev_private;
4603
4604         /* we're doing forcewake before Disabling RC6,
4605          * This what the BIOS expects when going into suspend */
4606         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4607
4608         I915_WRITE(GEN6_RC_CONTROL, 0);
4609
4610         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4611 }
4612
4613 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4614 {
4615         if (IS_VALLEYVIEW(dev)) {
4616                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4617                         mode = GEN6_RC_CTL_RC6_ENABLE;
4618                 else
4619                         mode = 0;
4620         }
4621         if (HAS_RC6p(dev))
4622                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4623                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4624                               (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4625                               (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4626
4627         else
4628                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4629                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4630 }
4631
4632 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4633 {
4634         /* No RC6 before Ironlake and code is gone for ilk. */
4635         if (INTEL_INFO(dev)->gen < 6)
4636                 return 0;
4637
4638         /* Respect the kernel parameter if it is set */
4639         if (enable_rc6 >= 0) {
4640                 int mask;
4641
4642                 if (HAS_RC6p(dev))
4643                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4644                                INTEL_RC6pp_ENABLE;
4645                 else
4646                         mask = INTEL_RC6_ENABLE;
4647
4648                 if ((enable_rc6 & mask) != enable_rc6)
4649                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4650                                       enable_rc6 & mask, enable_rc6, mask);
4651
4652                 return enable_rc6 & mask;
4653         }
4654
4655         if (IS_IVYBRIDGE(dev))
4656                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4657
4658         return INTEL_RC6_ENABLE;
4659 }
4660
4661 int intel_enable_rc6(const struct drm_device *dev)
4662 {
4663         return i915.enable_rc6;
4664 }
4665
4666 static void gen6_init_rps_frequencies(struct drm_device *dev)
4667 {
4668         struct drm_i915_private *dev_priv = dev->dev_private;
4669         uint32_t rp_state_cap;
4670         u32 ddcc_status = 0;
4671         int ret;
4672
4673         /* All of these values are in units of 50MHz */
4674         dev_priv->rps.cur_freq          = 0;
4675         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4676         if (IS_BROXTON(dev)) {
4677                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4678                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4679                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4680                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4681         } else {
4682                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4683                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4684                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4685                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4686         }
4687
4688         /* hw_max = RP0 until we check for overclocking */
4689         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4690
4691         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4692         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
4693                 ret = sandybridge_pcode_read(dev_priv,
4694                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4695                                         &ddcc_status);
4696                 if (0 == ret)
4697                         dev_priv->rps.efficient_freq =
4698                                 clamp_t(u8,
4699                                         ((ddcc_status >> 8) & 0xff),
4700                                         dev_priv->rps.min_freq,
4701                                         dev_priv->rps.max_freq);
4702         }
4703
4704         if (IS_SKYLAKE(dev)) {
4705                 /* Store the frequency values in 16.66 MHZ units, which is
4706                    the natural hardware unit for SKL */
4707                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4708                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4709                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4710                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4711                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4712         }
4713
4714         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4715
4716         /* Preserve min/max settings in case of re-init */
4717         if (dev_priv->rps.max_freq_softlimit == 0)
4718                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4719
4720         if (dev_priv->rps.min_freq_softlimit == 0) {
4721                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4722                         dev_priv->rps.min_freq_softlimit =
4723                                 max_t(int, dev_priv->rps.efficient_freq,
4724                                       intel_freq_opcode(dev_priv, 450));
4725                 else
4726                         dev_priv->rps.min_freq_softlimit =
4727                                 dev_priv->rps.min_freq;
4728         }
4729 }
4730
4731 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4732 static void gen9_enable_rps(struct drm_device *dev)
4733 {
4734         struct drm_i915_private *dev_priv = dev->dev_private;
4735
4736         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4737
4738         gen6_init_rps_frequencies(dev);
4739
4740         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4741         if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
4742                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4743                 return;
4744         }
4745
4746         /* Program defaults and thresholds for RPS*/
4747         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4748                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4749
4750         /* 1 second timeout*/
4751         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4752                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4753
4754         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4755
4756         /* Leaning on the below call to gen6_set_rps to program/setup the
4757          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4758          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4759         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4760         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4761
4762         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4763 }
4764
4765 static void gen9_enable_rc6(struct drm_device *dev)
4766 {
4767         struct drm_i915_private *dev_priv = dev->dev_private;
4768         struct intel_engine_cs *ring;
4769         uint32_t rc6_mask = 0;
4770         int unused;
4771
4772         /* 1a: Software RC state - RC0 */
4773         I915_WRITE(GEN6_RC_STATE, 0);
4774
4775         /* 1b: Get forcewake during program sequence. Although the driver
4776          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4777         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4778
4779         /* 2a: Disable RC states. */
4780         I915_WRITE(GEN6_RC_CONTROL, 0);
4781
4782         /* 2b: Program RC6 thresholds.*/
4783
4784         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4785         if (IS_SKYLAKE(dev))
4786                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4787         else
4788                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4789         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4790         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4791         for_each_ring(ring, dev_priv, unused)
4792                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4793
4794         if (HAS_GUC_UCODE(dev))
4795                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4796
4797         I915_WRITE(GEN6_RC_SLEEP, 0);
4798
4799         /* 2c: Program Coarse Power Gating Policies. */
4800         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4801         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4802
4803         /* 3a: Enable RC6 */
4804         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4805                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4806         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4807                         "on" : "off");
4808         /* WaRsUseTimeoutMode */
4809         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
4810             (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {
4811                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4812                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4813                            GEN7_RC_CTL_TO_MODE |
4814                            rc6_mask);
4815         } else {
4816                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4817                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4818                            GEN6_RC_CTL_EI_MODE(1) |
4819                            rc6_mask);
4820         }
4821
4822         /*
4823          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4824          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4825          */
4826         if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4827             ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0)))
4828                 I915_WRITE(GEN9_PG_ENABLE, 0);
4829         else
4830                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4831                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4832
4833         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4834
4835 }
4836
4837 static void gen8_enable_rps(struct drm_device *dev)
4838 {
4839         struct drm_i915_private *dev_priv = dev->dev_private;
4840         struct intel_engine_cs *ring;
4841         uint32_t rc6_mask = 0;
4842         int unused;
4843
4844         /* 1a: Software RC state - RC0 */
4845         I915_WRITE(GEN6_RC_STATE, 0);
4846
4847         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4848          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4849         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4850
4851         /* 2a: Disable RC states. */
4852         I915_WRITE(GEN6_RC_CONTROL, 0);
4853
4854         /* Initialize rps frequencies */
4855         gen6_init_rps_frequencies(dev);
4856
4857         /* 2b: Program RC6 thresholds.*/
4858         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4859         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4860         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4861         for_each_ring(ring, dev_priv, unused)
4862                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4863         I915_WRITE(GEN6_RC_SLEEP, 0);
4864         if (IS_BROADWELL(dev))
4865                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4866         else
4867                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4868
4869         /* 3: Enable RC6 */
4870         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4871                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4872         intel_print_rc6_info(dev, rc6_mask);
4873         if (IS_BROADWELL(dev))
4874                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4875                                 GEN7_RC_CTL_TO_MODE |
4876                                 rc6_mask);
4877         else
4878                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4879                                 GEN6_RC_CTL_EI_MODE(1) |
4880                                 rc6_mask);
4881
4882         /* 4 Program defaults and thresholds for RPS*/
4883         I915_WRITE(GEN6_RPNSWREQ,
4884                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4885         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4886                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4887         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4888         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4889
4890         /* Docs recommend 900MHz, and 300 MHz respectively */
4891         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4892                    dev_priv->rps.max_freq_softlimit << 24 |
4893                    dev_priv->rps.min_freq_softlimit << 16);
4894
4895         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4896         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4897         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4898         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4899
4900         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4901
4902         /* 5: Enable RPS */
4903         I915_WRITE(GEN6_RP_CONTROL,
4904                    GEN6_RP_MEDIA_TURBO |
4905                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4906                    GEN6_RP_MEDIA_IS_GFX |
4907                    GEN6_RP_ENABLE |
4908                    GEN6_RP_UP_BUSY_AVG |
4909                    GEN6_RP_DOWN_IDLE_AVG);
4910
4911         /* 6: Ring frequency + overclocking (our driver does this later */
4912
4913         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4914         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4915
4916         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4917 }
4918
4919 static void gen6_enable_rps(struct drm_device *dev)
4920 {
4921         struct drm_i915_private *dev_priv = dev->dev_private;
4922         struct intel_engine_cs *ring;
4923         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4924         u32 gtfifodbg;
4925         int rc6_mode;
4926         int i, ret;
4927
4928         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4929
4930         /* Here begins a magic sequence of register writes to enable
4931          * auto-downclocking.
4932          *
4933          * Perhaps there might be some value in exposing these to
4934          * userspace...
4935          */
4936         I915_WRITE(GEN6_RC_STATE, 0);
4937
4938         /* Clear the DBG now so we don't confuse earlier errors */
4939         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4940                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4941                 I915_WRITE(GTFIFODBG, gtfifodbg);
4942         }
4943
4944         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4945
4946         /* Initialize rps frequencies */
4947         gen6_init_rps_frequencies(dev);
4948
4949         /* disable the counters and set deterministic thresholds */
4950         I915_WRITE(GEN6_RC_CONTROL, 0);
4951
4952         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4953         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4954         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4955         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4956         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4957
4958         for_each_ring(ring, dev_priv, i)
4959                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4960
4961         I915_WRITE(GEN6_RC_SLEEP, 0);
4962         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4963         if (IS_IVYBRIDGE(dev))
4964                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4965         else
4966                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4967         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4968         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4969
4970         /* Check if we are enabling RC6 */
4971         rc6_mode = intel_enable_rc6(dev_priv->dev);
4972         if (rc6_mode & INTEL_RC6_ENABLE)
4973                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4974
4975         /* We don't use those on Haswell */
4976         if (!IS_HASWELL(dev)) {
4977                 if (rc6_mode & INTEL_RC6p_ENABLE)
4978                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4979
4980                 if (rc6_mode & INTEL_RC6pp_ENABLE)
4981                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4982         }
4983
4984         intel_print_rc6_info(dev, rc6_mask);
4985
4986         I915_WRITE(GEN6_RC_CONTROL,
4987                    rc6_mask |
4988                    GEN6_RC_CTL_EI_MODE(1) |
4989                    GEN6_RC_CTL_HW_ENABLE);
4990
4991         /* Power down if completely idle for over 50ms */
4992         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4993         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4994
4995         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4996         if (ret)
4997                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4998
4999         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5000         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5001                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5002                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5003                                  (pcu_mbox & 0xff) * 50);
5004                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5005         }
5006
5007         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5008         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5009
5010         rc6vids = 0;
5011         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5012         if (IS_GEN6(dev) && ret) {
5013                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5014         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5015                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5016                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5017                 rc6vids &= 0xffff00;
5018                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5019                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5020                 if (ret)
5021                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5022         }
5023
5024         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5025 }
5026
5027 static void __gen6_update_ring_freq(struct drm_device *dev)
5028 {
5029         struct drm_i915_private *dev_priv = dev->dev_private;
5030         int min_freq = 15;
5031         unsigned int gpu_freq;
5032         unsigned int max_ia_freq, min_ring_freq;
5033         unsigned int max_gpu_freq, min_gpu_freq;
5034         int scaling_factor = 180;
5035         struct cpufreq_policy *policy;
5036
5037         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5038
5039         policy = cpufreq_cpu_get(0);
5040         if (policy) {
5041                 max_ia_freq = policy->cpuinfo.max_freq;
5042                 cpufreq_cpu_put(policy);
5043         } else {
5044                 /*
5045                  * Default to measured freq if none found, PCU will ensure we
5046                  * don't go over
5047                  */
5048                 max_ia_freq = tsc_khz;
5049         }
5050
5051         /* Convert from kHz to MHz */
5052         max_ia_freq /= 1000;
5053
5054         min_ring_freq = I915_READ(DCLK) & 0xf;
5055         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5056         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5057
5058         if (IS_SKYLAKE(dev)) {
5059                 /* Convert GT frequency to 50 HZ units */
5060                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5061                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5062         } else {
5063                 min_gpu_freq = dev_priv->rps.min_freq;
5064                 max_gpu_freq = dev_priv->rps.max_freq;
5065         }
5066
5067         /*
5068          * For each potential GPU frequency, load a ring frequency we'd like
5069          * to use for memory access.  We do this by specifying the IA frequency
5070          * the PCU should use as a reference to determine the ring frequency.
5071          */
5072         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5073                 int diff = max_gpu_freq - gpu_freq;
5074                 unsigned int ia_freq = 0, ring_freq = 0;
5075
5076                 if (IS_SKYLAKE(dev)) {
5077                         /*
5078                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5079                          * No floor required for ring frequency on SKL.
5080                          */
5081                         ring_freq = gpu_freq;
5082                 } else if (INTEL_INFO(dev)->gen >= 8) {
5083                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5084                         ring_freq = max(min_ring_freq, gpu_freq);
5085                 } else if (IS_HASWELL(dev)) {
5086                         ring_freq = mult_frac(gpu_freq, 5, 4);
5087                         ring_freq = max(min_ring_freq, ring_freq);
5088                         /* leave ia_freq as the default, chosen by cpufreq */
5089                 } else {
5090                         /* On older processors, there is no separate ring
5091                          * clock domain, so in order to boost the bandwidth
5092                          * of the ring, we need to upclock the CPU (ia_freq).
5093                          *
5094                          * For GPU frequencies less than 750MHz,
5095                          * just use the lowest ring freq.
5096                          */
5097                         if (gpu_freq < min_freq)
5098                                 ia_freq = 800;
5099                         else
5100                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5101                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5102                 }
5103
5104                 sandybridge_pcode_write(dev_priv,
5105                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5106                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5107                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5108                                         gpu_freq);
5109         }
5110 }
5111
5112 void gen6_update_ring_freq(struct drm_device *dev)
5113 {
5114         struct drm_i915_private *dev_priv = dev->dev_private;
5115
5116         if (!HAS_CORE_RING_FREQ(dev))
5117                 return;
5118
5119         mutex_lock(&dev_priv->rps.hw_lock);
5120         __gen6_update_ring_freq(dev);
5121         mutex_unlock(&dev_priv->rps.hw_lock);
5122 }
5123
5124 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5125 {
5126         struct drm_device *dev = dev_priv->dev;
5127         u32 val, rp0;
5128
5129         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5130
5131         switch (INTEL_INFO(dev)->eu_total) {
5132         case 8:
5133                 /* (2 * 4) config */
5134                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5135                 break;
5136         case 12:
5137                 /* (2 * 6) config */
5138                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5139                 break;
5140         case 16:
5141                 /* (2 * 8) config */
5142         default:
5143                 /* Setting (2 * 8) Min RP0 for any other combination */
5144                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5145                 break;
5146         }
5147
5148         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5149
5150         return rp0;
5151 }
5152
5153 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5154 {
5155         u32 val, rpe;
5156
5157         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5158         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5159
5160         return rpe;
5161 }
5162
5163 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5164 {
5165         u32 val, rp1;
5166
5167         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5168         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5169
5170         return rp1;
5171 }
5172
5173 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5174 {
5175         u32 val, rp1;
5176
5177         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5178
5179         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5180
5181         return rp1;
5182 }
5183
5184 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5185 {
5186         u32 val, rp0;
5187
5188         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5189
5190         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5191         /* Clamp to max */
5192         rp0 = min_t(u32, rp0, 0xea);
5193
5194         return rp0;
5195 }
5196
5197 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5198 {
5199         u32 val, rpe;
5200
5201         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5202         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5203         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5204         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5205
5206         return rpe;
5207 }
5208
5209 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5210 {
5211         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5212 }
5213
5214 /* Check that the pctx buffer wasn't move under us. */
5215 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5216 {
5217         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5218
5219         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5220                              dev_priv->vlv_pctx->stolen->start);
5221 }
5222
5223
5224 /* Check that the pcbr address is not empty. */
5225 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5226 {
5227         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5228
5229         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5230 }
5231
5232 static void cherryview_setup_pctx(struct drm_device *dev)
5233 {
5234         struct drm_i915_private *dev_priv = dev->dev_private;
5235         unsigned long pctx_paddr, paddr;
5236         struct i915_gtt *gtt = &dev_priv->gtt;
5237         u32 pcbr;
5238         int pctx_size = 32*1024;
5239
5240         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5241
5242         pcbr = I915_READ(VLV_PCBR);
5243         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5244                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5245                 paddr = (dev_priv->mm.stolen_base +
5246                          (gtt->stolen_size - pctx_size));
5247
5248                 pctx_paddr = (paddr & (~4095));
5249                 I915_WRITE(VLV_PCBR, pctx_paddr);
5250         }
5251
5252         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5253 }
5254
5255 static void valleyview_setup_pctx(struct drm_device *dev)
5256 {
5257         struct drm_i915_private *dev_priv = dev->dev_private;
5258         struct drm_i915_gem_object *pctx;
5259         unsigned long pctx_paddr;
5260         u32 pcbr;
5261         int pctx_size = 24*1024;
5262
5263         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5264
5265         pcbr = I915_READ(VLV_PCBR);
5266         if (pcbr) {
5267                 /* BIOS set it up already, grab the pre-alloc'd space */
5268                 int pcbr_offset;
5269
5270                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5271                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5272                                                                       pcbr_offset,
5273                                                                       I915_GTT_OFFSET_NONE,
5274                                                                       pctx_size);
5275                 goto out;
5276         }
5277
5278         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5279
5280         /*
5281          * From the Gunit register HAS:
5282          * The Gfx driver is expected to program this register and ensure
5283          * proper allocation within Gfx stolen memory.  For example, this
5284          * register should be programmed such than the PCBR range does not
5285          * overlap with other ranges, such as the frame buffer, protected
5286          * memory, or any other relevant ranges.
5287          */
5288         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5289         if (!pctx) {
5290                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5291                 return;
5292         }
5293
5294         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5295         I915_WRITE(VLV_PCBR, pctx_paddr);
5296
5297 out:
5298         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5299         dev_priv->vlv_pctx = pctx;
5300 }
5301
5302 static void valleyview_cleanup_pctx(struct drm_device *dev)
5303 {
5304         struct drm_i915_private *dev_priv = dev->dev_private;
5305
5306         if (WARN_ON(!dev_priv->vlv_pctx))
5307                 return;
5308
5309         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5310         dev_priv->vlv_pctx = NULL;
5311 }
5312
5313 static void valleyview_init_gt_powersave(struct drm_device *dev)
5314 {
5315         struct drm_i915_private *dev_priv = dev->dev_private;
5316         u32 val;
5317
5318         valleyview_setup_pctx(dev);
5319
5320         mutex_lock(&dev_priv->rps.hw_lock);
5321
5322         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5323         switch ((val >> 6) & 3) {
5324         case 0:
5325         case 1:
5326                 dev_priv->mem_freq = 800;
5327                 break;
5328         case 2:
5329                 dev_priv->mem_freq = 1066;
5330                 break;
5331         case 3:
5332                 dev_priv->mem_freq = 1333;
5333                 break;
5334         }
5335         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5336
5337         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5338         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5339         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5340                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5341                          dev_priv->rps.max_freq);
5342
5343         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5344         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5345                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5346                          dev_priv->rps.efficient_freq);
5347
5348         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5349         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5350                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5351                          dev_priv->rps.rp1_freq);
5352
5353         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5354         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5355                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5356                          dev_priv->rps.min_freq);
5357
5358         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5359
5360         /* Preserve min/max settings in case of re-init */
5361         if (dev_priv->rps.max_freq_softlimit == 0)
5362                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5363
5364         if (dev_priv->rps.min_freq_softlimit == 0)
5365                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5366
5367         mutex_unlock(&dev_priv->rps.hw_lock);
5368 }
5369
5370 static void cherryview_init_gt_powersave(struct drm_device *dev)
5371 {
5372         struct drm_i915_private *dev_priv = dev->dev_private;
5373         u32 val;
5374
5375         cherryview_setup_pctx(dev);
5376
5377         mutex_lock(&dev_priv->rps.hw_lock);
5378
5379         mutex_lock(&dev_priv->sb_lock);
5380         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5381         mutex_unlock(&dev_priv->sb_lock);
5382
5383         switch ((val >> 2) & 0x7) {
5384         case 3:
5385                 dev_priv->mem_freq = 2000;
5386                 break;
5387         default:
5388                 dev_priv->mem_freq = 1600;
5389                 break;
5390         }
5391         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5392
5393         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5394         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5395         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5396                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5397                          dev_priv->rps.max_freq);
5398
5399         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5400         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5401                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5402                          dev_priv->rps.efficient_freq);
5403
5404         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5405         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5406                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5407                          dev_priv->rps.rp1_freq);
5408
5409         /* PUnit validated range is only [RPe, RP0] */
5410         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5411         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5412                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5413                          dev_priv->rps.min_freq);
5414
5415         WARN_ONCE((dev_priv->rps.max_freq |
5416                    dev_priv->rps.efficient_freq |
5417                    dev_priv->rps.rp1_freq |
5418                    dev_priv->rps.min_freq) & 1,
5419                   "Odd GPU freq values\n");
5420
5421         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5422
5423         /* Preserve min/max settings in case of re-init */
5424         if (dev_priv->rps.max_freq_softlimit == 0)
5425                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5426
5427         if (dev_priv->rps.min_freq_softlimit == 0)
5428                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5429
5430         mutex_unlock(&dev_priv->rps.hw_lock);
5431 }
5432
5433 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5434 {
5435         valleyview_cleanup_pctx(dev);
5436 }
5437
5438 static void cherryview_enable_rps(struct drm_device *dev)
5439 {
5440         struct drm_i915_private *dev_priv = dev->dev_private;
5441         struct intel_engine_cs *ring;
5442         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5443         int i;
5444
5445         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5446
5447         gtfifodbg = I915_READ(GTFIFODBG);
5448         if (gtfifodbg) {
5449                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5450                                  gtfifodbg);
5451                 I915_WRITE(GTFIFODBG, gtfifodbg);
5452         }
5453
5454         cherryview_check_pctx(dev_priv);
5455
5456         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5457          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5458         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5459
5460         /*  Disable RC states. */
5461         I915_WRITE(GEN6_RC_CONTROL, 0);
5462
5463         /* 2a: Program RC6 thresholds.*/
5464         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5465         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5466         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5467
5468         for_each_ring(ring, dev_priv, i)
5469                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5470         I915_WRITE(GEN6_RC_SLEEP, 0);
5471
5472         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5473         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5474
5475         /* allows RC6 residency counter to work */
5476         I915_WRITE(VLV_COUNTER_CONTROL,
5477                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5478                                       VLV_MEDIA_RC6_COUNT_EN |
5479                                       VLV_RENDER_RC6_COUNT_EN));
5480
5481         /* For now we assume BIOS is allocating and populating the PCBR  */
5482         pcbr = I915_READ(VLV_PCBR);
5483
5484         /* 3: Enable RC6 */
5485         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5486                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5487                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5488
5489         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5490
5491         /* 4 Program defaults and thresholds for RPS*/
5492         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5493         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5494         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5495         I915_WRITE(GEN6_RP_UP_EI, 66000);
5496         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5497
5498         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5499
5500         /* 5: Enable RPS */
5501         I915_WRITE(GEN6_RP_CONTROL,
5502                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5503                    GEN6_RP_MEDIA_IS_GFX |
5504                    GEN6_RP_ENABLE |
5505                    GEN6_RP_UP_BUSY_AVG |
5506                    GEN6_RP_DOWN_IDLE_AVG);
5507
5508         /* Setting Fixed Bias */
5509         val = VLV_OVERRIDE_EN |
5510                   VLV_SOC_TDP_EN |
5511                   CHV_BIAS_CPU_50_SOC_50;
5512         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5513
5514         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5515
5516         /* RPS code assumes GPLL is used */
5517         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5518
5519         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5520         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5521
5522         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5523         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5524                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5525                          dev_priv->rps.cur_freq);
5526
5527         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5528                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5529                          dev_priv->rps.efficient_freq);
5530
5531         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5532
5533         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5534 }
5535
5536 static void valleyview_enable_rps(struct drm_device *dev)
5537 {
5538         struct drm_i915_private *dev_priv = dev->dev_private;
5539         struct intel_engine_cs *ring;
5540         u32 gtfifodbg, val, rc6_mode = 0;
5541         int i;
5542
5543         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5544
5545         valleyview_check_pctx(dev_priv);
5546
5547         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5548                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5549                                  gtfifodbg);
5550                 I915_WRITE(GTFIFODBG, gtfifodbg);
5551         }
5552
5553         /* If VLV, Forcewake all wells, else re-direct to regular path */
5554         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5555
5556         /*  Disable RC states. */
5557         I915_WRITE(GEN6_RC_CONTROL, 0);
5558
5559         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5560         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5561         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5562         I915_WRITE(GEN6_RP_UP_EI, 66000);
5563         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5564
5565         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5566
5567         I915_WRITE(GEN6_RP_CONTROL,
5568                    GEN6_RP_MEDIA_TURBO |
5569                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5570                    GEN6_RP_MEDIA_IS_GFX |
5571                    GEN6_RP_ENABLE |
5572                    GEN6_RP_UP_BUSY_AVG |
5573                    GEN6_RP_DOWN_IDLE_CONT);
5574
5575         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5576         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5577         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5578
5579         for_each_ring(ring, dev_priv, i)
5580                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5581
5582         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5583
5584         /* allows RC6 residency counter to work */
5585         I915_WRITE(VLV_COUNTER_CONTROL,
5586                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5587                                       VLV_RENDER_RC0_COUNT_EN |
5588                                       VLV_MEDIA_RC6_COUNT_EN |
5589                                       VLV_RENDER_RC6_COUNT_EN));
5590
5591         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5592                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5593
5594         intel_print_rc6_info(dev, rc6_mode);
5595
5596         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5597
5598         /* Setting Fixed Bias */
5599         val = VLV_OVERRIDE_EN |
5600                   VLV_SOC_TDP_EN |
5601                   VLV_BIAS_CPU_125_SOC_875;
5602         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5603
5604         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5605
5606         /* RPS code assumes GPLL is used */
5607         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5608
5609         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5610         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5611
5612         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5613         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5614                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5615                          dev_priv->rps.cur_freq);
5616
5617         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5618                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5619                          dev_priv->rps.efficient_freq);
5620
5621         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5622
5623         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5624 }
5625
5626 static unsigned long intel_pxfreq(u32 vidfreq)
5627 {
5628         unsigned long freq;
5629         int div = (vidfreq & 0x3f0000) >> 16;
5630         int post = (vidfreq & 0x3000) >> 12;
5631         int pre = (vidfreq & 0x7);
5632
5633         if (!pre)
5634                 return 0;
5635
5636         freq = ((div * 133333) / ((1<<post) * pre));
5637
5638         return freq;
5639 }
5640
5641 static const struct cparams {
5642         u16 i;
5643         u16 t;
5644         u16 m;
5645         u16 c;
5646 } cparams[] = {
5647         { 1, 1333, 301, 28664 },
5648         { 1, 1066, 294, 24460 },
5649         { 1, 800, 294, 25192 },
5650         { 0, 1333, 276, 27605 },
5651         { 0, 1066, 276, 27605 },
5652         { 0, 800, 231, 23784 },
5653 };
5654
5655 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5656 {
5657         u64 total_count, diff, ret;
5658         u32 count1, count2, count3, m = 0, c = 0;
5659         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5660         int i;
5661
5662         assert_spin_locked(&mchdev_lock);
5663
5664         diff1 = now - dev_priv->ips.last_time1;
5665
5666         /* Prevent division-by-zero if we are asking too fast.
5667          * Also, we don't get interesting results if we are polling
5668          * faster than once in 10ms, so just return the saved value
5669          * in such cases.
5670          */
5671         if (diff1 <= 10)
5672                 return dev_priv->ips.chipset_power;
5673
5674         count1 = I915_READ(DMIEC);
5675         count2 = I915_READ(DDREC);
5676         count3 = I915_READ(CSIEC);
5677
5678         total_count = count1 + count2 + count3;
5679
5680         /* FIXME: handle per-counter overflow */
5681         if (total_count < dev_priv->ips.last_count1) {
5682                 diff = ~0UL - dev_priv->ips.last_count1;
5683                 diff += total_count;
5684         } else {
5685                 diff = total_count - dev_priv->ips.last_count1;
5686         }
5687
5688         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5689                 if (cparams[i].i == dev_priv->ips.c_m &&
5690                     cparams[i].t == dev_priv->ips.r_t) {
5691                         m = cparams[i].m;
5692                         c = cparams[i].c;
5693                         break;
5694                 }
5695         }
5696
5697         diff = div_u64(diff, diff1);
5698         ret = ((m * diff) + c);
5699         ret = div_u64(ret, 10);
5700
5701         dev_priv->ips.last_count1 = total_count;
5702         dev_priv->ips.last_time1 = now;
5703
5704         dev_priv->ips.chipset_power = ret;
5705
5706         return ret;
5707 }
5708
5709 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5710 {
5711         struct drm_device *dev = dev_priv->dev;
5712         unsigned long val;
5713
5714         if (INTEL_INFO(dev)->gen != 5)
5715                 return 0;
5716
5717         spin_lock_irq(&mchdev_lock);
5718
5719         val = __i915_chipset_val(dev_priv);
5720
5721         spin_unlock_irq(&mchdev_lock);
5722
5723         return val;
5724 }
5725
5726 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5727 {
5728         unsigned long m, x, b;
5729         u32 tsfs;
5730
5731         tsfs = I915_READ(TSFS);
5732
5733         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5734         x = I915_READ8(TR1);
5735
5736         b = tsfs & TSFS_INTR_MASK;
5737
5738         return ((m * x) / 127) - b;
5739 }
5740
5741 static int _pxvid_to_vd(u8 pxvid)
5742 {
5743         if (pxvid == 0)
5744                 return 0;
5745
5746         if (pxvid >= 8 && pxvid < 31)
5747                 pxvid = 31;
5748
5749         return (pxvid + 2) * 125;
5750 }
5751
5752 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5753 {
5754         struct drm_device *dev = dev_priv->dev;
5755         const int vd = _pxvid_to_vd(pxvid);
5756         const int vm = vd - 1125;
5757
5758         if (INTEL_INFO(dev)->is_mobile)
5759                 return vm > 0 ? vm : 0;
5760
5761         return vd;
5762 }
5763
5764 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5765 {
5766         u64 now, diff, diffms;
5767         u32 count;
5768
5769         assert_spin_locked(&mchdev_lock);
5770
5771         now = ktime_get_raw_ns();
5772         diffms = now - dev_priv->ips.last_time2;
5773         do_div(diffms, NSEC_PER_MSEC);
5774
5775         /* Don't divide by 0 */
5776         if (!diffms)
5777                 return;
5778
5779         count = I915_READ(GFXEC);
5780
5781         if (count < dev_priv->ips.last_count2) {
5782                 diff = ~0UL - dev_priv->ips.last_count2;
5783                 diff += count;
5784         } else {
5785                 diff = count - dev_priv->ips.last_count2;
5786         }
5787
5788         dev_priv->ips.last_count2 = count;
5789         dev_priv->ips.last_time2 = now;
5790
5791         /* More magic constants... */
5792         diff = diff * 1181;
5793         diff = div_u64(diff, diffms * 10);
5794         dev_priv->ips.gfx_power = diff;
5795 }
5796
5797 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5798 {
5799         struct drm_device *dev = dev_priv->dev;
5800
5801         if (INTEL_INFO(dev)->gen != 5)
5802                 return;
5803
5804         spin_lock_irq(&mchdev_lock);
5805
5806         __i915_update_gfx_val(dev_priv);
5807
5808         spin_unlock_irq(&mchdev_lock);
5809 }
5810
5811 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5812 {
5813         unsigned long t, corr, state1, corr2, state2;
5814         u32 pxvid, ext_v;
5815
5816         assert_spin_locked(&mchdev_lock);
5817
5818         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5819         pxvid = (pxvid >> 24) & 0x7f;
5820         ext_v = pvid_to_extvid(dev_priv, pxvid);
5821
5822         state1 = ext_v;
5823
5824         t = i915_mch_val(dev_priv);
5825
5826         /* Revel in the empirically derived constants */
5827
5828         /* Correction factor in 1/100000 units */
5829         if (t > 80)
5830                 corr = ((t * 2349) + 135940);
5831         else if (t >= 50)
5832                 corr = ((t * 964) + 29317);
5833         else /* < 50 */
5834                 corr = ((t * 301) + 1004);
5835
5836         corr = corr * ((150142 * state1) / 10000 - 78642);
5837         corr /= 100000;
5838         corr2 = (corr * dev_priv->ips.corr);
5839
5840         state2 = (corr2 * state1) / 10000;
5841         state2 /= 100; /* convert to mW */
5842
5843         __i915_update_gfx_val(dev_priv);
5844
5845         return dev_priv->ips.gfx_power + state2;
5846 }
5847
5848 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5849 {
5850         struct drm_device *dev = dev_priv->dev;
5851         unsigned long val;
5852
5853         if (INTEL_INFO(dev)->gen != 5)
5854                 return 0;
5855
5856         spin_lock_irq(&mchdev_lock);
5857
5858         val = __i915_gfx_val(dev_priv);
5859
5860         spin_unlock_irq(&mchdev_lock);
5861
5862         return val;
5863 }
5864
5865 /**
5866  * i915_read_mch_val - return value for IPS use
5867  *
5868  * Calculate and return a value for the IPS driver to use when deciding whether
5869  * we have thermal and power headroom to increase CPU or GPU power budget.
5870  */
5871 unsigned long i915_read_mch_val(void)
5872 {
5873         struct drm_i915_private *dev_priv;
5874         unsigned long chipset_val, graphics_val, ret = 0;
5875
5876         spin_lock_irq(&mchdev_lock);
5877         if (!i915_mch_dev)
5878                 goto out_unlock;
5879         dev_priv = i915_mch_dev;
5880
5881         chipset_val = __i915_chipset_val(dev_priv);
5882         graphics_val = __i915_gfx_val(dev_priv);
5883
5884         ret = chipset_val + graphics_val;
5885
5886 out_unlock:
5887         spin_unlock_irq(&mchdev_lock);
5888
5889         return ret;
5890 }
5891 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5892
5893 /**
5894  * i915_gpu_raise - raise GPU frequency limit
5895  *
5896  * Raise the limit; IPS indicates we have thermal headroom.
5897  */
5898 bool i915_gpu_raise(void)
5899 {
5900         struct drm_i915_private *dev_priv;
5901         bool ret = true;
5902
5903         spin_lock_irq(&mchdev_lock);
5904         if (!i915_mch_dev) {
5905                 ret = false;
5906                 goto out_unlock;
5907         }
5908         dev_priv = i915_mch_dev;
5909
5910         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5911                 dev_priv->ips.max_delay--;
5912
5913 out_unlock:
5914         spin_unlock_irq(&mchdev_lock);
5915
5916         return ret;
5917 }
5918 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5919
5920 /**
5921  * i915_gpu_lower - lower GPU frequency limit
5922  *
5923  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5924  * frequency maximum.
5925  */
5926 bool i915_gpu_lower(void)
5927 {
5928         struct drm_i915_private *dev_priv;
5929         bool ret = true;
5930
5931         spin_lock_irq(&mchdev_lock);
5932         if (!i915_mch_dev) {
5933                 ret = false;
5934                 goto out_unlock;
5935         }
5936         dev_priv = i915_mch_dev;
5937
5938         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5939                 dev_priv->ips.max_delay++;
5940
5941 out_unlock:
5942         spin_unlock_irq(&mchdev_lock);
5943
5944         return ret;
5945 }
5946 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5947
5948 /**
5949  * i915_gpu_busy - indicate GPU business to IPS
5950  *
5951  * Tell the IPS driver whether or not the GPU is busy.
5952  */
5953 bool i915_gpu_busy(void)
5954 {
5955         struct drm_i915_private *dev_priv;
5956         struct intel_engine_cs *ring;
5957         bool ret = false;
5958         int i;
5959
5960         spin_lock_irq(&mchdev_lock);
5961         if (!i915_mch_dev)
5962                 goto out_unlock;
5963         dev_priv = i915_mch_dev;
5964
5965         for_each_ring(ring, dev_priv, i)
5966                 ret |= !list_empty(&ring->request_list);
5967
5968 out_unlock:
5969         spin_unlock_irq(&mchdev_lock);
5970
5971         return ret;
5972 }
5973 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5974
5975 /**
5976  * i915_gpu_turbo_disable - disable graphics turbo
5977  *
5978  * Disable graphics turbo by resetting the max frequency and setting the
5979  * current frequency to the default.
5980  */
5981 bool i915_gpu_turbo_disable(void)
5982 {
5983         struct drm_i915_private *dev_priv;
5984         bool ret = true;
5985
5986         spin_lock_irq(&mchdev_lock);
5987         if (!i915_mch_dev) {
5988                 ret = false;
5989                 goto out_unlock;
5990         }
5991         dev_priv = i915_mch_dev;
5992
5993         dev_priv->ips.max_delay = dev_priv->ips.fstart;
5994
5995         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5996                 ret = false;
5997
5998 out_unlock:
5999         spin_unlock_irq(&mchdev_lock);
6000
6001         return ret;
6002 }
6003 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6004
6005 /**
6006  * Tells the intel_ips driver that the i915 driver is now loaded, if
6007  * IPS got loaded first.
6008  *
6009  * This awkward dance is so that neither module has to depend on the
6010  * other in order for IPS to do the appropriate communication of
6011  * GPU turbo limits to i915.
6012  */
6013 static void
6014 ips_ping_for_i915_load(void)
6015 {
6016         void (*link)(void);
6017
6018         link = symbol_get(ips_link_to_i915_driver);
6019         if (link) {
6020                 link();
6021                 symbol_put(ips_link_to_i915_driver);
6022         }
6023 }
6024
6025 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6026 {
6027         /* We only register the i915 ips part with intel-ips once everything is
6028          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6029         spin_lock_irq(&mchdev_lock);
6030         i915_mch_dev = dev_priv;
6031         spin_unlock_irq(&mchdev_lock);
6032
6033         ips_ping_for_i915_load();
6034 }
6035
6036 void intel_gpu_ips_teardown(void)
6037 {
6038         spin_lock_irq(&mchdev_lock);
6039         i915_mch_dev = NULL;
6040         spin_unlock_irq(&mchdev_lock);
6041 }
6042
6043 static void intel_init_emon(struct drm_device *dev)
6044 {
6045         struct drm_i915_private *dev_priv = dev->dev_private;
6046         u32 lcfuse;
6047         u8 pxw[16];
6048         int i;
6049
6050         /* Disable to program */
6051         I915_WRITE(ECR, 0);
6052         POSTING_READ(ECR);
6053
6054         /* Program energy weights for various events */
6055         I915_WRITE(SDEW, 0x15040d00);
6056         I915_WRITE(CSIEW0, 0x007f0000);
6057         I915_WRITE(CSIEW1, 0x1e220004);
6058         I915_WRITE(CSIEW2, 0x04000004);
6059
6060         for (i = 0; i < 5; i++)
6061                 I915_WRITE(PEW(i), 0);
6062         for (i = 0; i < 3; i++)
6063                 I915_WRITE(DEW(i), 0);
6064
6065         /* Program P-state weights to account for frequency power adjustment */
6066         for (i = 0; i < 16; i++) {
6067                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6068                 unsigned long freq = intel_pxfreq(pxvidfreq);
6069                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6070                         PXVFREQ_PX_SHIFT;
6071                 unsigned long val;
6072
6073                 val = vid * vid;
6074                 val *= (freq / 1000);
6075                 val *= 255;
6076                 val /= (127*127*900);
6077                 if (val > 0xff)
6078                         DRM_ERROR("bad pxval: %ld\n", val);
6079                 pxw[i] = val;
6080         }
6081         /* Render standby states get 0 weight */
6082         pxw[14] = 0;
6083         pxw[15] = 0;
6084
6085         for (i = 0; i < 4; i++) {
6086                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6087                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6088                 I915_WRITE(PXW(i), val);
6089         }
6090
6091         /* Adjust magic regs to magic values (more experimental results) */
6092         I915_WRITE(OGW0, 0);
6093         I915_WRITE(OGW1, 0);
6094         I915_WRITE(EG0, 0x00007f00);
6095         I915_WRITE(EG1, 0x0000000e);
6096         I915_WRITE(EG2, 0x000e0000);
6097         I915_WRITE(EG3, 0x68000300);
6098         I915_WRITE(EG4, 0x42000000);
6099         I915_WRITE(EG5, 0x00140031);
6100         I915_WRITE(EG6, 0);
6101         I915_WRITE(EG7, 0);
6102
6103         for (i = 0; i < 8; i++)
6104                 I915_WRITE(PXWL(i), 0);
6105
6106         /* Enable PMON + select events */
6107         I915_WRITE(ECR, 0x80000019);
6108
6109         lcfuse = I915_READ(LCFUSE02);
6110
6111         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6112 }
6113
6114 void intel_init_gt_powersave(struct drm_device *dev)
6115 {
6116         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6117
6118         if (IS_CHERRYVIEW(dev))
6119                 cherryview_init_gt_powersave(dev);
6120         else if (IS_VALLEYVIEW(dev))
6121                 valleyview_init_gt_powersave(dev);
6122 }
6123
6124 void intel_cleanup_gt_powersave(struct drm_device *dev)
6125 {
6126         if (IS_CHERRYVIEW(dev))
6127                 return;
6128         else if (IS_VALLEYVIEW(dev))
6129                 valleyview_cleanup_gt_powersave(dev);
6130 }
6131
6132 static void gen6_suspend_rps(struct drm_device *dev)
6133 {
6134         struct drm_i915_private *dev_priv = dev->dev_private;
6135
6136         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6137
6138         gen6_disable_rps_interrupts(dev);
6139 }
6140
6141 /**
6142  * intel_suspend_gt_powersave - suspend PM work and helper threads
6143  * @dev: drm device
6144  *
6145  * We don't want to disable RC6 or other features here, we just want
6146  * to make sure any work we've queued has finished and won't bother
6147  * us while we're suspended.
6148  */
6149 void intel_suspend_gt_powersave(struct drm_device *dev)
6150 {
6151         struct drm_i915_private *dev_priv = dev->dev_private;
6152
6153         if (INTEL_INFO(dev)->gen < 6)
6154                 return;
6155
6156         gen6_suspend_rps(dev);
6157
6158         /* Force GPU to min freq during suspend */
6159         gen6_rps_idle(dev_priv);
6160 }
6161
6162 void intel_disable_gt_powersave(struct drm_device *dev)
6163 {
6164         struct drm_i915_private *dev_priv = dev->dev_private;
6165
6166         if (IS_IRONLAKE_M(dev)) {
6167                 ironlake_disable_drps(dev);
6168         } else if (INTEL_INFO(dev)->gen >= 6) {
6169                 intel_suspend_gt_powersave(dev);
6170
6171                 mutex_lock(&dev_priv->rps.hw_lock);
6172                 if (INTEL_INFO(dev)->gen >= 9)
6173                         gen9_disable_rps(dev);
6174                 else if (IS_CHERRYVIEW(dev))
6175                         cherryview_disable_rps(dev);
6176                 else if (IS_VALLEYVIEW(dev))
6177                         valleyview_disable_rps(dev);
6178                 else
6179                         gen6_disable_rps(dev);
6180
6181                 dev_priv->rps.enabled = false;
6182                 mutex_unlock(&dev_priv->rps.hw_lock);
6183         }
6184 }
6185
6186 static void intel_gen6_powersave_work(struct work_struct *work)
6187 {
6188         struct drm_i915_private *dev_priv =
6189                 container_of(work, struct drm_i915_private,
6190                              rps.delayed_resume_work.work);
6191         struct drm_device *dev = dev_priv->dev;
6192
6193         mutex_lock(&dev_priv->rps.hw_lock);
6194
6195         gen6_reset_rps_interrupts(dev);
6196
6197         if (IS_CHERRYVIEW(dev)) {
6198                 cherryview_enable_rps(dev);
6199         } else if (IS_VALLEYVIEW(dev)) {
6200                 valleyview_enable_rps(dev);
6201         } else if (INTEL_INFO(dev)->gen >= 9) {
6202                 gen9_enable_rc6(dev);
6203                 gen9_enable_rps(dev);
6204                 if (IS_SKYLAKE(dev))
6205                         __gen6_update_ring_freq(dev);
6206         } else if (IS_BROADWELL(dev)) {
6207                 gen8_enable_rps(dev);
6208                 __gen6_update_ring_freq(dev);
6209         } else {
6210                 gen6_enable_rps(dev);
6211                 __gen6_update_ring_freq(dev);
6212         }
6213
6214         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6215         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6216
6217         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6218         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6219
6220         dev_priv->rps.enabled = true;
6221
6222         gen6_enable_rps_interrupts(dev);
6223
6224         mutex_unlock(&dev_priv->rps.hw_lock);
6225
6226         intel_runtime_pm_put(dev_priv);
6227 }
6228
6229 void intel_enable_gt_powersave(struct drm_device *dev)
6230 {
6231         struct drm_i915_private *dev_priv = dev->dev_private;
6232
6233         /* Powersaving is controlled by the host when inside a VM */
6234         if (intel_vgpu_active(dev))
6235                 return;
6236
6237         if (IS_IRONLAKE_M(dev)) {
6238                 mutex_lock(&dev->struct_mutex);
6239                 ironlake_enable_drps(dev);
6240                 intel_init_emon(dev);
6241                 mutex_unlock(&dev->struct_mutex);
6242         } else if (INTEL_INFO(dev)->gen >= 6) {
6243                 /*
6244                  * PCU communication is slow and this doesn't need to be
6245                  * done at any specific time, so do this out of our fast path
6246                  * to make resume and init faster.
6247                  *
6248                  * We depend on the HW RC6 power context save/restore
6249                  * mechanism when entering D3 through runtime PM suspend. So
6250                  * disable RPM until RPS/RC6 is properly setup. We can only
6251                  * get here via the driver load/system resume/runtime resume
6252                  * paths, so the _noresume version is enough (and in case of
6253                  * runtime resume it's necessary).
6254                  */
6255                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6256                                            round_jiffies_up_relative(HZ)))
6257                         intel_runtime_pm_get_noresume(dev_priv);
6258         }
6259 }
6260
6261 void intel_reset_gt_powersave(struct drm_device *dev)
6262 {
6263         struct drm_i915_private *dev_priv = dev->dev_private;
6264
6265         if (INTEL_INFO(dev)->gen < 6)
6266                 return;
6267
6268         gen6_suspend_rps(dev);
6269         dev_priv->rps.enabled = false;
6270 }
6271
6272 static void ibx_init_clock_gating(struct drm_device *dev)
6273 {
6274         struct drm_i915_private *dev_priv = dev->dev_private;
6275
6276         /*
6277          * On Ibex Peak and Cougar Point, we need to disable clock
6278          * gating for the panel power sequencer or it will fail to
6279          * start up when no ports are active.
6280          */
6281         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6282 }
6283
6284 static void g4x_disable_trickle_feed(struct drm_device *dev)
6285 {
6286         struct drm_i915_private *dev_priv = dev->dev_private;
6287         enum pipe pipe;
6288
6289         for_each_pipe(dev_priv, pipe) {
6290                 I915_WRITE(DSPCNTR(pipe),
6291                            I915_READ(DSPCNTR(pipe)) |
6292                            DISPPLANE_TRICKLE_FEED_DISABLE);
6293
6294                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6295                 POSTING_READ(DSPSURF(pipe));
6296         }
6297 }
6298
6299 static void ilk_init_lp_watermarks(struct drm_device *dev)
6300 {
6301         struct drm_i915_private *dev_priv = dev->dev_private;
6302
6303         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6304         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6305         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6306
6307         /*
6308          * Don't touch WM1S_LP_EN here.
6309          * Doing so could cause underruns.
6310          */
6311 }
6312
6313 static void ironlake_init_clock_gating(struct drm_device *dev)
6314 {
6315         struct drm_i915_private *dev_priv = dev->dev_private;
6316         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6317
6318         /*
6319          * Required for FBC
6320          * WaFbcDisableDpfcClockGating:ilk
6321          */
6322         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6323                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6324                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6325
6326         I915_WRITE(PCH_3DCGDIS0,
6327                    MARIUNIT_CLOCK_GATE_DISABLE |
6328                    SVSMUNIT_CLOCK_GATE_DISABLE);
6329         I915_WRITE(PCH_3DCGDIS1,
6330                    VFMUNIT_CLOCK_GATE_DISABLE);
6331
6332         /*
6333          * According to the spec the following bits should be set in
6334          * order to enable memory self-refresh
6335          * The bit 22/21 of 0x42004
6336          * The bit 5 of 0x42020
6337          * The bit 15 of 0x45000
6338          */
6339         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6340                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6341                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6342         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6343         I915_WRITE(DISP_ARB_CTL,
6344                    (I915_READ(DISP_ARB_CTL) |
6345                     DISP_FBC_WM_DIS));
6346
6347         ilk_init_lp_watermarks(dev);
6348
6349         /*
6350          * Based on the document from hardware guys the following bits
6351          * should be set unconditionally in order to enable FBC.
6352          * The bit 22 of 0x42000
6353          * The bit 22 of 0x42004
6354          * The bit 7,8,9 of 0x42020.
6355          */
6356         if (IS_IRONLAKE_M(dev)) {
6357                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6358                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6359                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6360                            ILK_FBCQ_DIS);
6361                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6362                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6363                            ILK_DPARB_GATE);
6364         }
6365
6366         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6367
6368         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6369                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6370                    ILK_ELPIN_409_SELECT);
6371         I915_WRITE(_3D_CHICKEN2,
6372                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6373                    _3D_CHICKEN2_WM_READ_PIPELINED);
6374
6375         /* WaDisableRenderCachePipelinedFlush:ilk */
6376         I915_WRITE(CACHE_MODE_0,
6377                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6378
6379         /* WaDisable_RenderCache_OperationalFlush:ilk */
6380         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6381
6382         g4x_disable_trickle_feed(dev);
6383
6384         ibx_init_clock_gating(dev);
6385 }
6386
6387 static void cpt_init_clock_gating(struct drm_device *dev)
6388 {
6389         struct drm_i915_private *dev_priv = dev->dev_private;
6390         int pipe;
6391         uint32_t val;
6392
6393         /*
6394          * On Ibex Peak and Cougar Point, we need to disable clock
6395          * gating for the panel power sequencer or it will fail to
6396          * start up when no ports are active.
6397          */
6398         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6399                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6400                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6401         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6402                    DPLS_EDP_PPS_FIX_DIS);
6403         /* The below fixes the weird display corruption, a few pixels shifted
6404          * downward, on (only) LVDS of some HP laptops with IVY.
6405          */
6406         for_each_pipe(dev_priv, pipe) {
6407                 val = I915_READ(TRANS_CHICKEN2(pipe));
6408                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6409                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6410                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6411                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6412                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6413                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6414                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6415                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6416         }
6417         /* WADP0ClockGatingDisable */
6418         for_each_pipe(dev_priv, pipe) {
6419                 I915_WRITE(TRANS_CHICKEN1(pipe),
6420                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6421         }
6422 }
6423
6424 static void gen6_check_mch_setup(struct drm_device *dev)
6425 {
6426         struct drm_i915_private *dev_priv = dev->dev_private;
6427         uint32_t tmp;
6428
6429         tmp = I915_READ(MCH_SSKPD);
6430         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6431                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6432                               tmp);
6433 }
6434
6435 static void gen6_init_clock_gating(struct drm_device *dev)
6436 {
6437         struct drm_i915_private *dev_priv = dev->dev_private;
6438         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6439
6440         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6441
6442         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6443                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6444                    ILK_ELPIN_409_SELECT);
6445
6446         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6447         I915_WRITE(_3D_CHICKEN,
6448                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6449
6450         /* WaDisable_RenderCache_OperationalFlush:snb */
6451         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6452
6453         /*
6454          * BSpec recoomends 8x4 when MSAA is used,
6455          * however in practice 16x4 seems fastest.
6456          *
6457          * Note that PS/WM thread counts depend on the WIZ hashing
6458          * disable bit, which we don't touch here, but it's good
6459          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6460          */
6461         I915_WRITE(GEN6_GT_MODE,
6462                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6463
6464         ilk_init_lp_watermarks(dev);
6465
6466         I915_WRITE(CACHE_MODE_0,
6467                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6468
6469         I915_WRITE(GEN6_UCGCTL1,
6470                    I915_READ(GEN6_UCGCTL1) |
6471                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6472                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6473
6474         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6475          * gating disable must be set.  Failure to set it results in
6476          * flickering pixels due to Z write ordering failures after
6477          * some amount of runtime in the Mesa "fire" demo, and Unigine
6478          * Sanctuary and Tropics, and apparently anything else with
6479          * alpha test or pixel discard.
6480          *
6481          * According to the spec, bit 11 (RCCUNIT) must also be set,
6482          * but we didn't debug actual testcases to find it out.
6483          *
6484          * WaDisableRCCUnitClockGating:snb
6485          * WaDisableRCPBUnitClockGating:snb
6486          */
6487         I915_WRITE(GEN6_UCGCTL2,
6488                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6489                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6490
6491         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6492         I915_WRITE(_3D_CHICKEN3,
6493                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6494
6495         /*
6496          * Bspec says:
6497          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6498          * 3DSTATE_SF number of SF output attributes is more than 16."
6499          */
6500         I915_WRITE(_3D_CHICKEN3,
6501                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6502
6503         /*
6504          * According to the spec the following bits should be
6505          * set in order to enable memory self-refresh and fbc:
6506          * The bit21 and bit22 of 0x42000
6507          * The bit21 and bit22 of 0x42004
6508          * The bit5 and bit7 of 0x42020
6509          * The bit14 of 0x70180
6510          * The bit14 of 0x71180
6511          *
6512          * WaFbcAsynchFlipDisableFbcQueue:snb
6513          */
6514         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6515                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6516                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6517         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6518                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6519                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6520         I915_WRITE(ILK_DSPCLK_GATE_D,
6521                    I915_READ(ILK_DSPCLK_GATE_D) |
6522                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6523                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6524
6525         g4x_disable_trickle_feed(dev);
6526
6527         cpt_init_clock_gating(dev);
6528
6529         gen6_check_mch_setup(dev);
6530 }
6531
6532 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6533 {
6534         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6535
6536         /*
6537          * WaVSThreadDispatchOverride:ivb,vlv
6538          *
6539          * This actually overrides the dispatch
6540          * mode for all thread types.
6541          */
6542         reg &= ~GEN7_FF_SCHED_MASK;
6543         reg |= GEN7_FF_TS_SCHED_HW;
6544         reg |= GEN7_FF_VS_SCHED_HW;
6545         reg |= GEN7_FF_DS_SCHED_HW;
6546
6547         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6548 }
6549
6550 static void lpt_init_clock_gating(struct drm_device *dev)
6551 {
6552         struct drm_i915_private *dev_priv = dev->dev_private;
6553
6554         /*
6555          * TODO: this bit should only be enabled when really needed, then
6556          * disabled when not needed anymore in order to save power.
6557          */
6558         if (HAS_PCH_LPT_LP(dev))
6559                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6560                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6561                            PCH_LP_PARTITION_LEVEL_DISABLE);
6562
6563         /* WADPOClockGatingDisable:hsw */
6564         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6565                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6566                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6567 }
6568
6569 static void lpt_suspend_hw(struct drm_device *dev)
6570 {
6571         struct drm_i915_private *dev_priv = dev->dev_private;
6572
6573         if (HAS_PCH_LPT_LP(dev)) {
6574                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6575
6576                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6577                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6578         }
6579 }
6580
6581 static void broadwell_init_clock_gating(struct drm_device *dev)
6582 {
6583         struct drm_i915_private *dev_priv = dev->dev_private;
6584         enum pipe pipe;
6585         uint32_t misccpctl;
6586
6587         ilk_init_lp_watermarks(dev);
6588
6589         /* WaSwitchSolVfFArbitrationPriority:bdw */
6590         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6591
6592         /* WaPsrDPAMaskVBlankInSRD:bdw */
6593         I915_WRITE(CHICKEN_PAR1_1,
6594                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6595
6596         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6597         for_each_pipe(dev_priv, pipe) {
6598                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6599                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6600                            BDW_DPRS_MASK_VBLANK_SRD);
6601         }
6602
6603         /* WaVSRefCountFullforceMissDisable:bdw */
6604         /* WaDSRefCountFullforceMissDisable:bdw */
6605         I915_WRITE(GEN7_FF_THREAD_MODE,
6606                    I915_READ(GEN7_FF_THREAD_MODE) &
6607                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6608
6609         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6610                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6611
6612         /* WaDisableSDEUnitClockGating:bdw */
6613         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6614                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6615
6616         /*
6617          * WaProgramL3SqcReg1Default:bdw
6618          * WaTempDisableDOPClkGating:bdw
6619          */
6620         misccpctl = I915_READ(GEN7_MISCCPCTL);
6621         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6622         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6623         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6624
6625         /*
6626          * WaGttCachingOffByDefault:bdw
6627          * GTT cache may not work with big pages, so if those
6628          * are ever enabled GTT cache may need to be disabled.
6629          */
6630         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6631
6632         lpt_init_clock_gating(dev);
6633 }
6634
6635 static void haswell_init_clock_gating(struct drm_device *dev)
6636 {
6637         struct drm_i915_private *dev_priv = dev->dev_private;
6638
6639         ilk_init_lp_watermarks(dev);
6640
6641         /* L3 caching of data atomics doesn't work -- disable it. */
6642         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6643         I915_WRITE(HSW_ROW_CHICKEN3,
6644                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6645
6646         /* This is required by WaCatErrorRejectionIssue:hsw */
6647         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6648                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6649                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6650
6651         /* WaVSRefCountFullforceMissDisable:hsw */
6652         I915_WRITE(GEN7_FF_THREAD_MODE,
6653                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6654
6655         /* WaDisable_RenderCache_OperationalFlush:hsw */
6656         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6657
6658         /* enable HiZ Raw Stall Optimization */
6659         I915_WRITE(CACHE_MODE_0_GEN7,
6660                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6661
6662         /* WaDisable4x2SubspanOptimization:hsw */
6663         I915_WRITE(CACHE_MODE_1,
6664                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6665
6666         /*
6667          * BSpec recommends 8x4 when MSAA is used,
6668          * however in practice 16x4 seems fastest.
6669          *
6670          * Note that PS/WM thread counts depend on the WIZ hashing
6671          * disable bit, which we don't touch here, but it's good
6672          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6673          */
6674         I915_WRITE(GEN7_GT_MODE,
6675                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6676
6677         /* WaSampleCChickenBitEnable:hsw */
6678         I915_WRITE(HALF_SLICE_CHICKEN3,
6679                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6680
6681         /* WaSwitchSolVfFArbitrationPriority:hsw */
6682         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6683
6684         /* WaRsPkgCStateDisplayPMReq:hsw */
6685         I915_WRITE(CHICKEN_PAR1_1,
6686                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6687
6688         lpt_init_clock_gating(dev);
6689 }
6690
6691 static void ivybridge_init_clock_gating(struct drm_device *dev)
6692 {
6693         struct drm_i915_private *dev_priv = dev->dev_private;
6694         uint32_t snpcr;
6695
6696         ilk_init_lp_watermarks(dev);
6697
6698         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6699
6700         /* WaDisableEarlyCull:ivb */
6701         I915_WRITE(_3D_CHICKEN3,
6702                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6703
6704         /* WaDisableBackToBackFlipFix:ivb */
6705         I915_WRITE(IVB_CHICKEN3,
6706                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6707                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6708
6709         /* WaDisablePSDDualDispatchEnable:ivb */
6710         if (IS_IVB_GT1(dev))
6711                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6712                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6713
6714         /* WaDisable_RenderCache_OperationalFlush:ivb */
6715         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6716
6717         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6718         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6719                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6720
6721         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6722         I915_WRITE(GEN7_L3CNTLREG1,
6723                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6724         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6725                    GEN7_WA_L3_CHICKEN_MODE);
6726         if (IS_IVB_GT1(dev))
6727                 I915_WRITE(GEN7_ROW_CHICKEN2,
6728                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6729         else {
6730                 /* must write both registers */
6731                 I915_WRITE(GEN7_ROW_CHICKEN2,
6732                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6733                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6734                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6735         }
6736
6737         /* WaForceL3Serialization:ivb */
6738         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6739                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6740
6741         /*
6742          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6743          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6744          */
6745         I915_WRITE(GEN6_UCGCTL2,
6746                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6747
6748         /* This is required by WaCatErrorRejectionIssue:ivb */
6749         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6750                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6751                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6752
6753         g4x_disable_trickle_feed(dev);
6754
6755         gen7_setup_fixed_func_scheduler(dev_priv);
6756
6757         if (0) { /* causes HiZ corruption on ivb:gt1 */
6758                 /* enable HiZ Raw Stall Optimization */
6759                 I915_WRITE(CACHE_MODE_0_GEN7,
6760                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6761         }
6762
6763         /* WaDisable4x2SubspanOptimization:ivb */
6764         I915_WRITE(CACHE_MODE_1,
6765                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6766
6767         /*
6768          * BSpec recommends 8x4 when MSAA is used,
6769          * however in practice 16x4 seems fastest.
6770          *
6771          * Note that PS/WM thread counts depend on the WIZ hashing
6772          * disable bit, which we don't touch here, but it's good
6773          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6774          */
6775         I915_WRITE(GEN7_GT_MODE,
6776                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6777
6778         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6779         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6780         snpcr |= GEN6_MBC_SNPCR_MED;
6781         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6782
6783         if (!HAS_PCH_NOP(dev))
6784                 cpt_init_clock_gating(dev);
6785
6786         gen6_check_mch_setup(dev);
6787 }
6788
6789 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6790 {
6791         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6792
6793         /*
6794          * Disable trickle feed and enable pnd deadline calculation
6795          */
6796         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6797         I915_WRITE(CBR1_VLV, 0);
6798 }
6799
6800 static void valleyview_init_clock_gating(struct drm_device *dev)
6801 {
6802         struct drm_i915_private *dev_priv = dev->dev_private;
6803
6804         vlv_init_display_clock_gating(dev_priv);
6805
6806         /* WaDisableEarlyCull:vlv */
6807         I915_WRITE(_3D_CHICKEN3,
6808                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6809
6810         /* WaDisableBackToBackFlipFix:vlv */
6811         I915_WRITE(IVB_CHICKEN3,
6812                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6813                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6814
6815         /* WaPsdDispatchEnable:vlv */
6816         /* WaDisablePSDDualDispatchEnable:vlv */
6817         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6818                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6819                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6820
6821         /* WaDisable_RenderCache_OperationalFlush:vlv */
6822         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6823
6824         /* WaForceL3Serialization:vlv */
6825         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6826                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6827
6828         /* WaDisableDopClockGating:vlv */
6829         I915_WRITE(GEN7_ROW_CHICKEN2,
6830                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6831
6832         /* This is required by WaCatErrorRejectionIssue:vlv */
6833         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6834                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6835                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6836
6837         gen7_setup_fixed_func_scheduler(dev_priv);
6838
6839         /*
6840          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6841          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6842          */
6843         I915_WRITE(GEN6_UCGCTL2,
6844                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6845
6846         /* WaDisableL3Bank2xClockGate:vlv
6847          * Disabling L3 clock gating- MMIO 940c[25] = 1
6848          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6849         I915_WRITE(GEN7_UCGCTL4,
6850                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6851
6852         /*
6853          * BSpec says this must be set, even though
6854          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6855          */
6856         I915_WRITE(CACHE_MODE_1,
6857                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6858
6859         /*
6860          * BSpec recommends 8x4 when MSAA is used,
6861          * however in practice 16x4 seems fastest.
6862          *
6863          * Note that PS/WM thread counts depend on the WIZ hashing
6864          * disable bit, which we don't touch here, but it's good
6865          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6866          */
6867         I915_WRITE(GEN7_GT_MODE,
6868                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6869
6870         /*
6871          * WaIncreaseL3CreditsForVLVB0:vlv
6872          * This is the hardware default actually.
6873          */
6874         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6875
6876         /*
6877          * WaDisableVLVClockGating_VBIIssue:vlv
6878          * Disable clock gating on th GCFG unit to prevent a delay
6879          * in the reporting of vblank events.
6880          */
6881         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6882 }
6883
6884 static void cherryview_init_clock_gating(struct drm_device *dev)
6885 {
6886         struct drm_i915_private *dev_priv = dev->dev_private;
6887
6888         vlv_init_display_clock_gating(dev_priv);
6889
6890         /* WaVSRefCountFullforceMissDisable:chv */
6891         /* WaDSRefCountFullforceMissDisable:chv */
6892         I915_WRITE(GEN7_FF_THREAD_MODE,
6893                    I915_READ(GEN7_FF_THREAD_MODE) &
6894                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6895
6896         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6897         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6898                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6899
6900         /* WaDisableCSUnitClockGating:chv */
6901         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6902                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6903
6904         /* WaDisableSDEUnitClockGating:chv */
6905         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6906                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6907
6908         /*
6909          * GTT cache may not work with big pages, so if those
6910          * are ever enabled GTT cache may need to be disabled.
6911          */
6912         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6913 }
6914
6915 static void g4x_init_clock_gating(struct drm_device *dev)
6916 {
6917         struct drm_i915_private *dev_priv = dev->dev_private;
6918         uint32_t dspclk_gate;
6919
6920         I915_WRITE(RENCLK_GATE_D1, 0);
6921         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6922                    GS_UNIT_CLOCK_GATE_DISABLE |
6923                    CL_UNIT_CLOCK_GATE_DISABLE);
6924         I915_WRITE(RAMCLK_GATE_D, 0);
6925         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6926                 OVRUNIT_CLOCK_GATE_DISABLE |
6927                 OVCUNIT_CLOCK_GATE_DISABLE;
6928         if (IS_GM45(dev))
6929                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6930         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6931
6932         /* WaDisableRenderCachePipelinedFlush */
6933         I915_WRITE(CACHE_MODE_0,
6934                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6935
6936         /* WaDisable_RenderCache_OperationalFlush:g4x */
6937         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6938
6939         g4x_disable_trickle_feed(dev);
6940 }
6941
6942 static void crestline_init_clock_gating(struct drm_device *dev)
6943 {
6944         struct drm_i915_private *dev_priv = dev->dev_private;
6945
6946         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6947         I915_WRITE(RENCLK_GATE_D2, 0);
6948         I915_WRITE(DSPCLK_GATE_D, 0);
6949         I915_WRITE(RAMCLK_GATE_D, 0);
6950         I915_WRITE16(DEUC, 0);
6951         I915_WRITE(MI_ARB_STATE,
6952                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6953
6954         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6955         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6956 }
6957
6958 static void broadwater_init_clock_gating(struct drm_device *dev)
6959 {
6960         struct drm_i915_private *dev_priv = dev->dev_private;
6961
6962         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6963                    I965_RCC_CLOCK_GATE_DISABLE |
6964                    I965_RCPB_CLOCK_GATE_DISABLE |
6965                    I965_ISC_CLOCK_GATE_DISABLE |
6966                    I965_FBC_CLOCK_GATE_DISABLE);
6967         I915_WRITE(RENCLK_GATE_D2, 0);
6968         I915_WRITE(MI_ARB_STATE,
6969                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6970
6971         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6972         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6973 }
6974
6975 static void gen3_init_clock_gating(struct drm_device *dev)
6976 {
6977         struct drm_i915_private *dev_priv = dev->dev_private;
6978         u32 dstate = I915_READ(D_STATE);
6979
6980         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6981                 DSTATE_DOT_CLOCK_GATING;
6982         I915_WRITE(D_STATE, dstate);
6983
6984         if (IS_PINEVIEW(dev))
6985                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6986
6987         /* IIR "flip pending" means done if this bit is set */
6988         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6989
6990         /* interrupts should cause a wake up from C3 */
6991         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6992
6993         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6994         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6995
6996         I915_WRITE(MI_ARB_STATE,
6997                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6998 }
6999
7000 static void i85x_init_clock_gating(struct drm_device *dev)
7001 {
7002         struct drm_i915_private *dev_priv = dev->dev_private;
7003
7004         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7005
7006         /* interrupts should cause a wake up from C3 */
7007         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7008                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7009
7010         I915_WRITE(MEM_MODE,
7011                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7012 }
7013
7014 static void i830_init_clock_gating(struct drm_device *dev)
7015 {
7016         struct drm_i915_private *dev_priv = dev->dev_private;
7017
7018         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7019
7020         I915_WRITE(MEM_MODE,
7021                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7022                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7023 }
7024
7025 void intel_init_clock_gating(struct drm_device *dev)
7026 {
7027         struct drm_i915_private *dev_priv = dev->dev_private;
7028
7029         if (dev_priv->display.init_clock_gating)
7030                 dev_priv->display.init_clock_gating(dev);
7031 }
7032
7033 void intel_suspend_hw(struct drm_device *dev)
7034 {
7035         if (HAS_PCH_LPT(dev))
7036                 lpt_suspend_hw(dev);
7037 }
7038
7039 /* Set up chip specific power management-related functions */
7040 void intel_init_pm(struct drm_device *dev)
7041 {
7042         struct drm_i915_private *dev_priv = dev->dev_private;
7043
7044         intel_fbc_init(dev_priv);
7045
7046         /* For cxsr */
7047         if (IS_PINEVIEW(dev))
7048                 i915_pineview_get_mem_freq(dev);
7049         else if (IS_GEN5(dev))
7050                 i915_ironlake_get_mem_freq(dev);
7051
7052         /* For FIFO watermark updates */
7053         if (INTEL_INFO(dev)->gen >= 9) {
7054                 skl_setup_wm_latency(dev);
7055
7056                 if (IS_BROXTON(dev))
7057                         dev_priv->display.init_clock_gating =
7058                                 bxt_init_clock_gating;
7059                 dev_priv->display.update_wm = skl_update_wm;
7060                 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
7061         } else if (HAS_PCH_SPLIT(dev)) {
7062                 ilk_setup_wm_latency(dev);
7063
7064                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7065                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7066                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7067                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7068                         dev_priv->display.update_wm = ilk_update_wm;
7069                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7070                 } else {
7071                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7072                                       "Disable CxSR\n");
7073                 }
7074
7075                 if (IS_GEN5(dev))
7076                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7077                 else if (IS_GEN6(dev))
7078                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7079                 else if (IS_IVYBRIDGE(dev))
7080                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7081                 else if (IS_HASWELL(dev))
7082                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7083                 else if (INTEL_INFO(dev)->gen == 8)
7084                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7085         } else if (IS_CHERRYVIEW(dev)) {
7086                 vlv_setup_wm_latency(dev);
7087
7088                 dev_priv->display.update_wm = vlv_update_wm;
7089                 dev_priv->display.init_clock_gating =
7090                         cherryview_init_clock_gating;
7091         } else if (IS_VALLEYVIEW(dev)) {
7092                 vlv_setup_wm_latency(dev);
7093
7094                 dev_priv->display.update_wm = vlv_update_wm;
7095                 dev_priv->display.init_clock_gating =
7096                         valleyview_init_clock_gating;
7097         } else if (IS_PINEVIEW(dev)) {
7098                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7099                                             dev_priv->is_ddr3,
7100                                             dev_priv->fsb_freq,
7101                                             dev_priv->mem_freq)) {
7102                         DRM_INFO("failed to find known CxSR latency "
7103                                  "(found ddr%s fsb freq %d, mem freq %d), "
7104                                  "disabling CxSR\n",
7105                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7106                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7107                         /* Disable CxSR and never update its watermark again */
7108                         intel_set_memory_cxsr(dev_priv, false);
7109                         dev_priv->display.update_wm = NULL;
7110                 } else
7111                         dev_priv->display.update_wm = pineview_update_wm;
7112                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7113         } else if (IS_G4X(dev)) {
7114                 dev_priv->display.update_wm = g4x_update_wm;
7115                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7116         } else if (IS_GEN4(dev)) {
7117                 dev_priv->display.update_wm = i965_update_wm;
7118                 if (IS_CRESTLINE(dev))
7119                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7120                 else if (IS_BROADWATER(dev))
7121                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7122         } else if (IS_GEN3(dev)) {
7123                 dev_priv->display.update_wm = i9xx_update_wm;
7124                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7125                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7126         } else if (IS_GEN2(dev)) {
7127                 if (INTEL_INFO(dev)->num_pipes == 1) {
7128                         dev_priv->display.update_wm = i845_update_wm;
7129                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7130                 } else {
7131                         dev_priv->display.update_wm = i9xx_update_wm;
7132                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7133                 }
7134
7135                 if (IS_I85X(dev) || IS_I865G(dev))
7136                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7137                 else
7138                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7139         } else {
7140                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7141         }
7142 }
7143
7144 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7145 {
7146         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7147
7148         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7149                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7150                 return -EAGAIN;
7151         }
7152
7153         I915_WRITE(GEN6_PCODE_DATA, *val);
7154         I915_WRITE(GEN6_PCODE_DATA1, 0);
7155         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7156
7157         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7158                      500)) {
7159                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7160                 return -ETIMEDOUT;
7161         }
7162
7163         *val = I915_READ(GEN6_PCODE_DATA);
7164         I915_WRITE(GEN6_PCODE_DATA, 0);
7165
7166         return 0;
7167 }
7168
7169 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7170 {
7171         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7172
7173         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7174                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7175                 return -EAGAIN;
7176         }
7177
7178         I915_WRITE(GEN6_PCODE_DATA, val);
7179         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7180
7181         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7182                      500)) {
7183                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7184                 return -ETIMEDOUT;
7185         }
7186
7187         I915_WRITE(GEN6_PCODE_DATA, 0);
7188
7189         return 0;
7190 }
7191
7192 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7193 {
7194         switch (czclk_freq) {
7195         case 200:
7196                 return 10;
7197         case 267:
7198                 return 12;
7199         case 320:
7200         case 333:
7201                 return 16;
7202         case 400:
7203                 return 20;
7204         default:
7205                 return -1;
7206         }
7207 }
7208
7209 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7210 {
7211         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7212
7213         div = vlv_gpu_freq_div(czclk_freq);
7214         if (div < 0)
7215                 return div;
7216
7217         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7218 }
7219
7220 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7221 {
7222         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7223
7224         mul = vlv_gpu_freq_div(czclk_freq);
7225         if (mul < 0)
7226                 return mul;
7227
7228         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7229 }
7230
7231 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7232 {
7233         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7234
7235         div = vlv_gpu_freq_div(czclk_freq) / 2;
7236         if (div < 0)
7237                 return div;
7238
7239         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7240 }
7241
7242 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7243 {
7244         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7245
7246         mul = vlv_gpu_freq_div(czclk_freq) / 2;
7247         if (mul < 0)
7248                 return mul;
7249
7250         /* CHV needs even values */
7251         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7252 }
7253
7254 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7255 {
7256         if (IS_GEN9(dev_priv->dev))
7257                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7258                                          GEN9_FREQ_SCALER);
7259         else if (IS_CHERRYVIEW(dev_priv->dev))
7260                 return chv_gpu_freq(dev_priv, val);
7261         else if (IS_VALLEYVIEW(dev_priv->dev))
7262                 return byt_gpu_freq(dev_priv, val);
7263         else
7264                 return val * GT_FREQUENCY_MULTIPLIER;
7265 }
7266
7267 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7268 {
7269         if (IS_GEN9(dev_priv->dev))
7270                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7271                                          GT_FREQUENCY_MULTIPLIER);
7272         else if (IS_CHERRYVIEW(dev_priv->dev))
7273                 return chv_freq_opcode(dev_priv, val);
7274         else if (IS_VALLEYVIEW(dev_priv->dev))
7275                 return byt_freq_opcode(dev_priv, val);
7276         else
7277                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7278 }
7279
7280 struct request_boost {
7281         struct work_struct work;
7282         struct drm_i915_gem_request *req;
7283 };
7284
7285 static void __intel_rps_boost_work(struct work_struct *work)
7286 {
7287         struct request_boost *boost = container_of(work, struct request_boost, work);
7288         struct drm_i915_gem_request *req = boost->req;
7289
7290         if (!i915_gem_request_completed(req, true))
7291                 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7292                                req->emitted_jiffies);
7293
7294         i915_gem_request_unreference__unlocked(req);
7295         kfree(boost);
7296 }
7297
7298 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7299                                        struct drm_i915_gem_request *req)
7300 {
7301         struct request_boost *boost;
7302
7303         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7304                 return;
7305
7306         if (i915_gem_request_completed(req, true))
7307                 return;
7308
7309         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7310         if (boost == NULL)
7311                 return;
7312
7313         i915_gem_request_reference(req);
7314         boost->req = req;
7315
7316         INIT_WORK(&boost->work, __intel_rps_boost_work);
7317         queue_work(to_i915(dev)->wq, &boost->work);
7318 }
7319
7320 void intel_pm_setup(struct drm_device *dev)
7321 {
7322         struct drm_i915_private *dev_priv = dev->dev_private;
7323
7324         mutex_init(&dev_priv->rps.hw_lock);
7325         spin_lock_init(&dev_priv->rps.client_lock);
7326
7327         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7328                           intel_gen6_powersave_work);
7329         INIT_LIST_HEAD(&dev_priv->rps.clients);
7330         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7331         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7332
7333         dev_priv->pm.suspended = false;
7334 }