2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
143 #define RING_EXECLIST_QFULL (1 << 0x2)
144 #define RING_EXECLIST1_VALID (1 << 0x3)
145 #define RING_EXECLIST0_VALID (1 << 0x4)
146 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
147 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
148 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
150 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
151 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
153 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
154 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
155 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
157 #define CTX_LRI_HEADER_0 0x01
158 #define CTX_CONTEXT_CONTROL 0x02
159 #define CTX_RING_HEAD 0x04
160 #define CTX_RING_TAIL 0x06
161 #define CTX_RING_BUFFER_START 0x08
162 #define CTX_RING_BUFFER_CONTROL 0x0a
163 #define CTX_BB_HEAD_U 0x0c
164 #define CTX_BB_HEAD_L 0x0e
165 #define CTX_BB_STATE 0x10
166 #define CTX_SECOND_BB_HEAD_U 0x12
167 #define CTX_SECOND_BB_HEAD_L 0x14
168 #define CTX_SECOND_BB_STATE 0x16
169 #define CTX_BB_PER_CTX_PTR 0x18
170 #define CTX_RCS_INDIRECT_CTX 0x1a
171 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
172 #define CTX_LRI_HEADER_1 0x21
173 #define CTX_CTX_TIMESTAMP 0x22
174 #define CTX_PDP3_UDW 0x24
175 #define CTX_PDP3_LDW 0x26
176 #define CTX_PDP2_UDW 0x28
177 #define CTX_PDP2_LDW 0x2a
178 #define CTX_PDP1_UDW 0x2c
179 #define CTX_PDP1_LDW 0x2e
180 #define CTX_PDP0_UDW 0x30
181 #define CTX_PDP0_LDW 0x32
182 #define CTX_LRI_HEADER_2 0x41
183 #define CTX_R_PWR_CLK_STATE 0x42
184 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
186 #define GEN8_CTX_VALID (1<<0)
187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
190 #define GEN8_CTX_PRIVILEGE (1<<8)
192 ADVANCED_CONTEXT = 0,
197 #define GEN8_CTX_MODE_SHIFT 3
200 FAULT_AND_HALT, /* Debug only */
202 FAULT_AND_CONTINUE /* Unsupported */
204 #define GEN8_CTX_ID_SHIFT 32
206 static int intel_lr_context_pin(struct intel_engine_cs *ring,
207 struct intel_context *ctx);
210 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
212 * @enable_execlists: value of i915.enable_execlists module parameter.
214 * Only certain platforms support Execlists (the prerequisites being
215 * support for Logical Ring Contexts and Aliasing PPGTT or better).
217 * Return: 1 if Execlists is supported and has to be enabled.
219 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
221 WARN_ON(i915.enable_ppgtt == -1);
223 if (INTEL_INFO(dev)->gen >= 9)
226 if (enable_execlists == 0)
229 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
230 i915.use_mmio_flip >= 0)
237 * intel_execlists_ctx_id() - get the Execlists Context ID
238 * @ctx_obj: Logical Ring Context backing object.
240 * Do not confuse with ctx->id! Unfortunately we have a name overload
241 * here: the old context ID we pass to userspace as a handler so that
242 * they can refer to a context, and the new context ID we pass to the
243 * ELSP so that the GPU can inform us of the context status via
246 * Return: 20-bits globally unique context ID.
248 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
250 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
252 /* LRCA is required to be 4K aligned so the more significant 20 bits
253 * are globally unique */
257 static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
258 struct drm_i915_gem_object *ctx_obj)
260 struct drm_device *dev = ring->dev;
262 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
264 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
266 desc = GEN8_CTX_VALID;
267 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
268 desc |= GEN8_CTX_L3LLC_COHERENT;
269 desc |= GEN8_CTX_PRIVILEGE;
271 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
273 /* TODO: WaDisableLiteRestore when we start using semaphore
274 * signalling between Command Streamers */
275 /* desc |= GEN8_CTX_FORCE_RESTORE; */
277 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
279 INTEL_REVID(dev) <= SKL_REVID_B0 &&
280 (ring->id == BCS || ring->id == VCS ||
281 ring->id == VECS || ring->id == VCS2))
282 desc |= GEN8_CTX_FORCE_RESTORE;
287 static void execlists_elsp_write(struct intel_engine_cs *ring,
288 struct drm_i915_gem_object *ctx_obj0,
289 struct drm_i915_gem_object *ctx_obj1)
291 struct drm_device *dev = ring->dev;
292 struct drm_i915_private *dev_priv = dev->dev_private;
296 /* XXX: You must always write both descriptors in the order below. */
298 temp = execlists_ctx_descriptor(ring, ctx_obj1);
301 desc[1] = (u32)(temp >> 32);
304 temp = execlists_ctx_descriptor(ring, ctx_obj0);
305 desc[3] = (u32)(temp >> 32);
308 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
309 I915_WRITE(RING_ELSP(ring), desc[1]);
310 I915_WRITE(RING_ELSP(ring), desc[0]);
311 I915_WRITE(RING_ELSP(ring), desc[3]);
313 /* The context is automatically loaded after the following */
314 I915_WRITE(RING_ELSP(ring), desc[2]);
316 /* ELSP is a wo register, so use another nearby reg for posting instead */
317 POSTING_READ(RING_EXECLIST_STATUS(ring));
318 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
321 static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
322 struct drm_i915_gem_object *ring_obj,
328 page = i915_gem_object_get_page(ctx_obj, 1);
329 reg_state = kmap_atomic(page);
331 reg_state[CTX_RING_TAIL+1] = tail;
332 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
334 kunmap_atomic(reg_state);
339 static void execlists_submit_contexts(struct intel_engine_cs *ring,
340 struct intel_context *to0, u32 tail0,
341 struct intel_context *to1, u32 tail1)
343 struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state;
344 struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf;
345 struct drm_i915_gem_object *ctx_obj1 = NULL;
346 struct intel_ringbuffer *ringbuf1 = NULL;
349 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
350 WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj));
352 execlists_update_context(ctx_obj0, ringbuf0->obj, tail0);
355 ringbuf1 = to1->engine[ring->id].ringbuf;
356 ctx_obj1 = to1->engine[ring->id].state;
358 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
359 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj));
361 execlists_update_context(ctx_obj1, ringbuf1->obj, tail1);
364 execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
367 static void execlists_context_unqueue(struct intel_engine_cs *ring)
369 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
370 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
372 assert_spin_locked(&ring->execlist_lock);
374 if (list_empty(&ring->execlist_queue))
377 /* Try to read in pairs */
378 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
382 } else if (req0->ctx == cursor->ctx) {
383 /* Same ctx: ignore first request, as second request
384 * will update tail past first request's workload */
385 cursor->elsp_submitted = req0->elsp_submitted;
386 list_del(&req0->execlist_link);
387 list_add_tail(&req0->execlist_link,
388 &ring->execlist_retired_req_list);
396 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
398 * WaIdleLiteRestore: make sure we never cause a lite
399 * restore with HEAD==TAIL
401 if (req0 && req0->elsp_submitted) {
403 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
404 * as we resubmit the request. See gen8_emit_request()
405 * for where we prepare the padding after the end of the
408 struct intel_ringbuffer *ringbuf;
410 ringbuf = req0->ctx->engine[ring->id].ringbuf;
412 req0->tail &= ringbuf->size - 1;
416 WARN_ON(req1 && req1->elsp_submitted);
418 execlists_submit_contexts(ring, req0->ctx, req0->tail,
419 req1 ? req1->ctx : NULL,
420 req1 ? req1->tail : 0);
422 req0->elsp_submitted++;
424 req1->elsp_submitted++;
427 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
430 struct drm_i915_gem_request *head_req;
432 assert_spin_locked(&ring->execlist_lock);
434 head_req = list_first_entry_or_null(&ring->execlist_queue,
435 struct drm_i915_gem_request,
438 if (head_req != NULL) {
439 struct drm_i915_gem_object *ctx_obj =
440 head_req->ctx->engine[ring->id].state;
441 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
442 WARN(head_req->elsp_submitted == 0,
443 "Never submitted head request\n");
445 if (--head_req->elsp_submitted <= 0) {
446 list_del(&head_req->execlist_link);
447 list_add_tail(&head_req->execlist_link,
448 &ring->execlist_retired_req_list);
458 * intel_lrc_irq_handler() - handle Context Switch interrupts
459 * @ring: Engine Command Streamer to handle.
461 * Check the unread Context Status Buffers and manage the submission of new
462 * contexts to the ELSP accordingly.
464 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
466 struct drm_i915_private *dev_priv = ring->dev->dev_private;
472 u32 submit_contexts = 0;
474 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
476 read_pointer = ring->next_context_status_buffer;
477 write_pointer = status_pointer & 0x07;
478 if (read_pointer > write_pointer)
481 spin_lock(&ring->execlist_lock);
483 while (read_pointer < write_pointer) {
485 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
486 (read_pointer % 6) * 8);
487 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
488 (read_pointer % 6) * 8 + 4);
490 if (status & GEN8_CTX_STATUS_PREEMPTED) {
491 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
492 if (execlists_check_remove_request(ring, status_id))
493 WARN(1, "Lite Restored request removed from queue\n");
495 WARN(1, "Preemption without Lite Restore\n");
498 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
499 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
500 if (execlists_check_remove_request(ring, status_id))
505 if (submit_contexts != 0)
506 execlists_context_unqueue(ring);
508 spin_unlock(&ring->execlist_lock);
510 WARN(submit_contexts > 2, "More than two context complete events?\n");
511 ring->next_context_status_buffer = write_pointer % 6;
513 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
514 ((u32)ring->next_context_status_buffer & 0x07) << 8);
517 static int execlists_context_queue(struct intel_engine_cs *ring,
518 struct intel_context *to,
520 struct drm_i915_gem_request *request)
522 struct drm_i915_gem_request *cursor;
523 struct drm_i915_private *dev_priv = ring->dev->dev_private;
525 int num_elements = 0;
527 if (to != ring->default_context)
528 intel_lr_context_pin(ring, to);
532 * If there isn't a request associated with this submission,
533 * create one as a temporary holder.
535 request = kzalloc(sizeof(*request), GFP_KERNEL);
538 request->ring = ring;
540 kref_init(&request->ref);
541 request->uniq = dev_priv->request_uniq++;
542 i915_gem_context_reference(request->ctx);
544 i915_gem_request_reference(request);
545 WARN_ON(to != request->ctx);
547 request->tail = tail;
549 intel_runtime_pm_get(dev_priv);
551 spin_lock_irqsave(&ring->execlist_lock, flags);
553 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
554 if (++num_elements > 2)
557 if (num_elements > 2) {
558 struct drm_i915_gem_request *tail_req;
560 tail_req = list_last_entry(&ring->execlist_queue,
561 struct drm_i915_gem_request,
564 if (to == tail_req->ctx) {
565 WARN(tail_req->elsp_submitted != 0,
566 "More than 2 already-submitted reqs queued\n");
567 list_del(&tail_req->execlist_link);
568 list_add_tail(&tail_req->execlist_link,
569 &ring->execlist_retired_req_list);
573 list_add_tail(&request->execlist_link, &ring->execlist_queue);
574 if (num_elements == 0)
575 execlists_context_unqueue(ring);
577 spin_unlock_irqrestore(&ring->execlist_lock, flags);
582 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf,
583 struct intel_context *ctx)
585 struct intel_engine_cs *ring = ringbuf->ring;
586 uint32_t flush_domains;
590 if (ring->gpu_caches_dirty)
591 flush_domains = I915_GEM_GPU_DOMAINS;
593 ret = ring->emit_flush(ringbuf, ctx,
594 I915_GEM_GPU_DOMAINS, flush_domains);
598 ring->gpu_caches_dirty = false;
602 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
603 struct intel_context *ctx,
604 struct list_head *vmas)
606 struct intel_engine_cs *ring = ringbuf->ring;
607 struct i915_vma *vma;
608 uint32_t flush_domains = 0;
609 bool flush_chipset = false;
612 list_for_each_entry(vma, vmas, exec_list) {
613 struct drm_i915_gem_object *obj = vma->obj;
615 ret = i915_gem_object_sync(obj, ring);
619 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
620 flush_chipset |= i915_gem_clflush_object(obj, false);
622 flush_domains |= obj->base.write_domain;
625 if (flush_domains & I915_GEM_DOMAIN_GTT)
628 /* Unconditionally invalidate gpu caches and ensure that we do flush
629 * any residual writes from the previous batch.
631 return logical_ring_invalidate_all_caches(ringbuf, ctx);
635 * execlists_submission() - submit a batchbuffer for execution, Execlists style
638 * @ring: Engine Command Streamer to submit to.
639 * @ctx: Context to employ for this submission.
640 * @args: execbuffer call arguments.
641 * @vmas: list of vmas.
642 * @batch_obj: the batchbuffer to submit.
643 * @exec_start: batchbuffer start virtual address pointer.
644 * @dispatch_flags: translated execbuffer call flags.
646 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
647 * away the submission details of the execbuffer ioctl call.
649 * Return: non-zero if the submission fails.
651 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
652 struct intel_engine_cs *ring,
653 struct intel_context *ctx,
654 struct drm_i915_gem_execbuffer2 *args,
655 struct list_head *vmas,
656 struct drm_i915_gem_object *batch_obj,
657 u64 exec_start, u32 dispatch_flags)
659 struct drm_i915_private *dev_priv = dev->dev_private;
660 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
665 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
666 instp_mask = I915_EXEC_CONSTANTS_MASK;
667 switch (instp_mode) {
668 case I915_EXEC_CONSTANTS_REL_GENERAL:
669 case I915_EXEC_CONSTANTS_ABSOLUTE:
670 case I915_EXEC_CONSTANTS_REL_SURFACE:
671 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
672 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
676 if (instp_mode != dev_priv->relative_constants_mode) {
677 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
678 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
682 /* The HW changed the meaning on this bit on gen6 */
683 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
687 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
691 if (args->num_cliprects != 0) {
692 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
695 if (args->DR4 == 0xffffffff) {
696 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
700 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
701 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
706 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
707 DRM_DEBUG("sol reset is gen7 only\n");
711 ret = execlists_move_to_gpu(ringbuf, ctx, vmas);
715 if (ring == &dev_priv->ring[RCS] &&
716 instp_mode != dev_priv->relative_constants_mode) {
717 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
721 intel_logical_ring_emit(ringbuf, MI_NOOP);
722 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
723 intel_logical_ring_emit(ringbuf, INSTPM);
724 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
725 intel_logical_ring_advance(ringbuf);
727 dev_priv->relative_constants_mode = instp_mode;
730 ret = ring->emit_bb_start(ringbuf, ctx, exec_start, dispatch_flags);
734 trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), dispatch_flags);
736 i915_gem_execbuffer_move_to_active(vmas, ring);
737 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
742 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
744 struct drm_i915_gem_request *req, *tmp;
745 struct drm_i915_private *dev_priv = ring->dev->dev_private;
747 struct list_head retired_list;
749 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
750 if (list_empty(&ring->execlist_retired_req_list))
753 INIT_LIST_HEAD(&retired_list);
754 spin_lock_irqsave(&ring->execlist_lock, flags);
755 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
756 spin_unlock_irqrestore(&ring->execlist_lock, flags);
758 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
759 struct intel_context *ctx = req->ctx;
760 struct drm_i915_gem_object *ctx_obj =
761 ctx->engine[ring->id].state;
763 if (ctx_obj && (ctx != ring->default_context))
764 intel_lr_context_unpin(ring, ctx);
765 intel_runtime_pm_put(dev_priv);
766 list_del(&req->execlist_link);
767 i915_gem_request_unreference(req);
771 void intel_logical_ring_stop(struct intel_engine_cs *ring)
773 struct drm_i915_private *dev_priv = ring->dev->dev_private;
776 if (!intel_ring_initialized(ring))
779 ret = intel_ring_idle(ring);
780 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
781 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
784 /* TODO: Is this correct with Execlists enabled? */
785 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
786 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
787 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
790 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
793 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
794 struct intel_context *ctx)
796 struct intel_engine_cs *ring = ringbuf->ring;
799 if (!ring->gpu_caches_dirty)
802 ret = ring->emit_flush(ringbuf, ctx, 0, I915_GEM_GPU_DOMAINS);
806 ring->gpu_caches_dirty = false;
811 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
812 * @ringbuf: Logical Ringbuffer to advance.
814 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
815 * really happens during submission is that the context and current tail will be placed
816 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
817 * point, the tail *inside* the context is updated and the ELSP written to.
820 intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
821 struct intel_context *ctx,
822 struct drm_i915_gem_request *request)
824 struct intel_engine_cs *ring = ringbuf->ring;
826 intel_logical_ring_advance(ringbuf);
828 if (intel_ring_stopped(ring))
831 execlists_context_queue(ring, ctx, ringbuf->tail, request);
834 static int intel_lr_context_pin(struct intel_engine_cs *ring,
835 struct intel_context *ctx)
837 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
838 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
841 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
842 if (ctx->engine[ring->id].pin_count++ == 0) {
843 ret = i915_gem_obj_ggtt_pin(ctx_obj,
844 GEN8_LR_CONTEXT_ALIGN, 0);
846 goto reset_pin_count;
848 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
852 ctx_obj->dirty = true;
858 i915_gem_object_ggtt_unpin(ctx_obj);
860 ctx->engine[ring->id].pin_count = 0;
865 void intel_lr_context_unpin(struct intel_engine_cs *ring,
866 struct intel_context *ctx)
868 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
869 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
872 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
873 if (--ctx->engine[ring->id].pin_count == 0) {
874 intel_unpin_ringbuffer_obj(ringbuf);
875 i915_gem_object_ggtt_unpin(ctx_obj);
880 static int logical_ring_alloc_request(struct intel_engine_cs *ring,
881 struct intel_context *ctx)
883 struct drm_i915_gem_request *request;
884 struct drm_i915_private *dev_private = ring->dev->dev_private;
887 if (ring->outstanding_lazy_request)
890 request = kzalloc(sizeof(*request), GFP_KERNEL);
894 if (ctx != ring->default_context) {
895 ret = intel_lr_context_pin(ring, ctx);
902 kref_init(&request->ref);
903 request->ring = ring;
904 request->uniq = dev_private->request_uniq++;
906 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
908 intel_lr_context_unpin(ring, ctx);
914 i915_gem_context_reference(request->ctx);
915 request->ringbuf = ctx->engine[ring->id].ringbuf;
917 ring->outstanding_lazy_request = request;
921 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
924 struct intel_engine_cs *ring = ringbuf->ring;
925 struct drm_i915_gem_request *request;
928 if (intel_ring_space(ringbuf) >= bytes)
931 list_for_each_entry(request, &ring->request_list, list) {
933 * The request queue is per-engine, so can contain requests
934 * from multiple ringbuffers. Here, we must ignore any that
935 * aren't from the ringbuffer we're considering.
937 struct intel_context *ctx = request->ctx;
938 if (ctx->engine[ring->id].ringbuf != ringbuf)
941 /* Would completion of this request free enough space? */
942 if (__intel_ring_space(request->tail, ringbuf->tail,
943 ringbuf->size) >= bytes) {
948 if (&request->list == &ring->request_list)
951 ret = i915_wait_request(request);
955 i915_gem_retire_requests_ring(ring);
957 return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC;
960 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
961 struct intel_context *ctx,
964 struct intel_engine_cs *ring = ringbuf->ring;
965 struct drm_device *dev = ring->dev;
966 struct drm_i915_private *dev_priv = dev->dev_private;
970 ret = logical_ring_wait_request(ringbuf, bytes);
974 /* Force the context submission in case we have been skipping it */
975 intel_logical_ring_advance_and_submit(ringbuf, ctx, NULL);
977 /* With GEM the hangcheck timer should kick us out of the loop,
978 * leaving it early runs the risk of corrupting GEM state (due
979 * to running on almost untested codepaths). But on resume
980 * timers don't work yet, so prevent a complete hang in that
981 * case by choosing an insanely large timeout. */
982 end = jiffies + 60 * HZ;
986 if (intel_ring_space(ringbuf) >= bytes)
991 if (dev_priv->mm.interruptible && signal_pending(current)) {
996 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
997 dev_priv->mm.interruptible);
1001 if (time_after(jiffies, end)) {
1010 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf,
1011 struct intel_context *ctx)
1013 uint32_t __iomem *virt;
1014 int rem = ringbuf->size - ringbuf->tail;
1016 if (ringbuf->space < rem) {
1017 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem);
1023 virt = ringbuf->virtual_start + ringbuf->tail;
1026 iowrite32(MI_NOOP, virt++);
1029 intel_ring_update_space(ringbuf);
1034 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf,
1035 struct intel_context *ctx, int bytes)
1039 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
1040 ret = logical_ring_wrap_buffer(ringbuf, ctx);
1045 if (unlikely(ringbuf->space < bytes)) {
1046 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes);
1055 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
1057 * @ringbuf: Logical ringbuffer.
1058 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
1060 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
1061 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
1062 * and also preallocates a request (every workload submission is still mediated through
1063 * requests, same as it did with legacy ringbuffer submission).
1065 * Return: non-zero if the ringbuffer is not ready to be written to.
1067 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
1068 struct intel_context *ctx, int num_dwords)
1070 struct intel_engine_cs *ring = ringbuf->ring;
1071 struct drm_device *dev = ring->dev;
1072 struct drm_i915_private *dev_priv = dev->dev_private;
1075 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1076 dev_priv->mm.interruptible);
1080 ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t));
1084 /* Preallocate the olr before touching the ring */
1085 ret = logical_ring_alloc_request(ring, ctx);
1089 ringbuf->space -= num_dwords * sizeof(uint32_t);
1093 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1094 struct intel_context *ctx)
1097 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1098 struct drm_device *dev = ring->dev;
1099 struct drm_i915_private *dev_priv = dev->dev_private;
1100 struct i915_workarounds *w = &dev_priv->workarounds;
1102 if (WARN_ON_ONCE(w->count == 0))
1105 ring->gpu_caches_dirty = true;
1106 ret = logical_ring_flush_all_caches(ringbuf, ctx);
1110 ret = intel_logical_ring_begin(ringbuf, ctx, w->count * 2 + 2);
1114 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1115 for (i = 0; i < w->count; i++) {
1116 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1117 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1119 intel_logical_ring_emit(ringbuf, MI_NOOP);
1121 intel_logical_ring_advance(ringbuf);
1123 ring->gpu_caches_dirty = true;
1124 ret = logical_ring_flush_all_caches(ringbuf, ctx);
1131 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1133 struct drm_device *dev = ring->dev;
1134 struct drm_i915_private *dev_priv = dev->dev_private;
1136 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1137 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1139 if (ring->status_page.obj) {
1140 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1141 (u32)ring->status_page.gfx_addr);
1142 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1145 I915_WRITE(RING_MODE_GEN7(ring),
1146 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1147 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1148 POSTING_READ(RING_MODE_GEN7(ring));
1149 ring->next_context_status_buffer = 0;
1150 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1152 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1157 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1159 struct drm_device *dev = ring->dev;
1160 struct drm_i915_private *dev_priv = dev->dev_private;
1163 ret = gen8_init_common_ring(ring);
1167 /* We need to disable the AsyncFlip performance optimisations in order
1168 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1169 * programmed to '1' on all products.
1171 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1173 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1175 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1177 return init_workarounds_ring(ring);
1180 static int gen9_init_render_ring(struct intel_engine_cs *ring)
1184 ret = gen8_init_common_ring(ring);
1188 return init_workarounds_ring(ring);
1191 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1192 struct intel_context *ctx,
1193 u64 offset, unsigned dispatch_flags)
1195 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1198 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1202 /* FIXME(BDW): Address space and security selectors. */
1203 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1204 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1205 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1206 intel_logical_ring_emit(ringbuf, MI_NOOP);
1207 intel_logical_ring_advance(ringbuf);
1212 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1214 struct drm_device *dev = ring->dev;
1215 struct drm_i915_private *dev_priv = dev->dev_private;
1216 unsigned long flags;
1218 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1221 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1222 if (ring->irq_refcount++ == 0) {
1223 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1224 POSTING_READ(RING_IMR(ring->mmio_base));
1226 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1231 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1233 struct drm_device *dev = ring->dev;
1234 struct drm_i915_private *dev_priv = dev->dev_private;
1235 unsigned long flags;
1237 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1238 if (--ring->irq_refcount == 0) {
1239 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1240 POSTING_READ(RING_IMR(ring->mmio_base));
1242 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1245 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1246 struct intel_context *ctx,
1247 u32 invalidate_domains,
1250 struct intel_engine_cs *ring = ringbuf->ring;
1251 struct drm_device *dev = ring->dev;
1252 struct drm_i915_private *dev_priv = dev->dev_private;
1256 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1260 cmd = MI_FLUSH_DW + 1;
1262 /* We always require a command barrier so that subsequent
1263 * commands, such as breadcrumb interrupts, are strictly ordered
1264 * wrt the contents of the write cache being flushed to memory
1265 * (and thus being coherent from the CPU).
1267 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1269 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1270 cmd |= MI_INVALIDATE_TLB;
1271 if (ring == &dev_priv->ring[VCS])
1272 cmd |= MI_INVALIDATE_BSD;
1275 intel_logical_ring_emit(ringbuf, cmd);
1276 intel_logical_ring_emit(ringbuf,
1277 I915_GEM_HWS_SCRATCH_ADDR |
1278 MI_FLUSH_DW_USE_GTT);
1279 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1280 intel_logical_ring_emit(ringbuf, 0); /* value */
1281 intel_logical_ring_advance(ringbuf);
1286 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1287 struct intel_context *ctx,
1288 u32 invalidate_domains,
1291 struct intel_engine_cs *ring = ringbuf->ring;
1292 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1296 flags |= PIPE_CONTROL_CS_STALL;
1298 if (flush_domains) {
1299 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1300 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1303 if (invalidate_domains) {
1304 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1305 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1306 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1307 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1308 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1309 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1310 flags |= PIPE_CONTROL_QW_WRITE;
1311 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1314 ret = intel_logical_ring_begin(ringbuf, ctx, 6);
1318 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1319 intel_logical_ring_emit(ringbuf, flags);
1320 intel_logical_ring_emit(ringbuf, scratch_addr);
1321 intel_logical_ring_emit(ringbuf, 0);
1322 intel_logical_ring_emit(ringbuf, 0);
1323 intel_logical_ring_emit(ringbuf, 0);
1324 intel_logical_ring_advance(ringbuf);
1329 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1331 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1334 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1336 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1339 static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
1340 struct drm_i915_gem_request *request)
1342 struct intel_engine_cs *ring = ringbuf->ring;
1347 * Reserve space for 2 NOOPs at the end of each request to be
1348 * used as a workaround for not being allowed to do lite
1349 * restore with HEAD==TAIL (WaIdleLiteRestore).
1351 ret = intel_logical_ring_begin(ringbuf, request->ctx, 8);
1355 cmd = MI_STORE_DWORD_IMM_GEN4;
1356 cmd |= MI_GLOBAL_GTT;
1358 intel_logical_ring_emit(ringbuf, cmd);
1359 intel_logical_ring_emit(ringbuf,
1360 (ring->status_page.gfx_addr +
1361 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1362 intel_logical_ring_emit(ringbuf, 0);
1363 intel_logical_ring_emit(ringbuf,
1364 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1365 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1366 intel_logical_ring_emit(ringbuf, MI_NOOP);
1367 intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request);
1370 * Here we add two extra NOOPs as padding to avoid
1371 * lite restore of a context with HEAD==TAIL.
1373 intel_logical_ring_emit(ringbuf, MI_NOOP);
1374 intel_logical_ring_emit(ringbuf, MI_NOOP);
1375 intel_logical_ring_advance(ringbuf);
1380 static int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1381 struct intel_context *ctx)
1383 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1384 struct render_state so;
1385 struct drm_i915_file_private *file_priv = ctx->file_priv;
1386 struct drm_file *file = file_priv ? file_priv->file : NULL;
1389 ret = i915_gem_render_state_prepare(ring, &so);
1393 if (so.rodata == NULL)
1396 ret = ring->emit_bb_start(ringbuf,
1399 I915_DISPATCH_SECURE);
1403 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1405 ret = __i915_add_request(ring, file, so.obj);
1406 /* intel_logical_ring_add_request moves object to inactive if it
1409 i915_gem_render_state_fini(&so);
1413 static int gen8_init_rcs_context(struct intel_engine_cs *ring,
1414 struct intel_context *ctx)
1418 ret = intel_logical_ring_workarounds_emit(ring, ctx);
1422 return intel_lr_context_render_state_init(ring, ctx);
1426 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1428 * @ring: Engine Command Streamer.
1431 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1433 struct drm_i915_private *dev_priv;
1435 if (!intel_ring_initialized(ring))
1438 dev_priv = ring->dev->dev_private;
1440 intel_logical_ring_stop(ring);
1441 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1442 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1445 ring->cleanup(ring);
1447 i915_cmd_parser_fini_ring(ring);
1449 if (ring->status_page.obj) {
1450 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1451 ring->status_page.obj = NULL;
1455 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1459 /* Intentionally left blank. */
1460 ring->buffer = NULL;
1463 INIT_LIST_HEAD(&ring->active_list);
1464 INIT_LIST_HEAD(&ring->request_list);
1465 init_waitqueue_head(&ring->irq_queue);
1467 INIT_LIST_HEAD(&ring->execlist_queue);
1468 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1469 spin_lock_init(&ring->execlist_lock);
1471 ret = i915_cmd_parser_init_ring(ring);
1475 ret = intel_lr_context_deferred_create(ring->default_context, ring);
1480 static int logical_render_ring_init(struct drm_device *dev)
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1483 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1486 ring->name = "render ring";
1488 ring->mmio_base = RENDER_RING_BASE;
1489 ring->irq_enable_mask =
1490 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1491 ring->irq_keep_mask =
1492 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1493 if (HAS_L3_DPF(dev))
1494 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1496 if (INTEL_INFO(dev)->gen >= 9)
1497 ring->init_hw = gen9_init_render_ring;
1499 ring->init_hw = gen8_init_render_ring;
1500 ring->init_context = gen8_init_rcs_context;
1501 ring->cleanup = intel_fini_pipe_control;
1502 ring->get_seqno = gen8_get_seqno;
1503 ring->set_seqno = gen8_set_seqno;
1504 ring->emit_request = gen8_emit_request;
1505 ring->emit_flush = gen8_emit_flush_render;
1506 ring->irq_get = gen8_logical_ring_get_irq;
1507 ring->irq_put = gen8_logical_ring_put_irq;
1508 ring->emit_bb_start = gen8_emit_bb_start;
1511 ret = logical_ring_init(dev, ring);
1515 return intel_init_pipe_control(ring);
1518 static int logical_bsd_ring_init(struct drm_device *dev)
1520 struct drm_i915_private *dev_priv = dev->dev_private;
1521 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1523 ring->name = "bsd ring";
1525 ring->mmio_base = GEN6_BSD_RING_BASE;
1526 ring->irq_enable_mask =
1527 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1528 ring->irq_keep_mask =
1529 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1531 ring->init_hw = gen8_init_common_ring;
1532 ring->get_seqno = gen8_get_seqno;
1533 ring->set_seqno = gen8_set_seqno;
1534 ring->emit_request = gen8_emit_request;
1535 ring->emit_flush = gen8_emit_flush;
1536 ring->irq_get = gen8_logical_ring_get_irq;
1537 ring->irq_put = gen8_logical_ring_put_irq;
1538 ring->emit_bb_start = gen8_emit_bb_start;
1540 return logical_ring_init(dev, ring);
1543 static int logical_bsd2_ring_init(struct drm_device *dev)
1545 struct drm_i915_private *dev_priv = dev->dev_private;
1546 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1548 ring->name = "bds2 ring";
1550 ring->mmio_base = GEN8_BSD2_RING_BASE;
1551 ring->irq_enable_mask =
1552 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1553 ring->irq_keep_mask =
1554 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1556 ring->init_hw = gen8_init_common_ring;
1557 ring->get_seqno = gen8_get_seqno;
1558 ring->set_seqno = gen8_set_seqno;
1559 ring->emit_request = gen8_emit_request;
1560 ring->emit_flush = gen8_emit_flush;
1561 ring->irq_get = gen8_logical_ring_get_irq;
1562 ring->irq_put = gen8_logical_ring_put_irq;
1563 ring->emit_bb_start = gen8_emit_bb_start;
1565 return logical_ring_init(dev, ring);
1568 static int logical_blt_ring_init(struct drm_device *dev)
1570 struct drm_i915_private *dev_priv = dev->dev_private;
1571 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1573 ring->name = "blitter ring";
1575 ring->mmio_base = BLT_RING_BASE;
1576 ring->irq_enable_mask =
1577 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1578 ring->irq_keep_mask =
1579 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1581 ring->init_hw = gen8_init_common_ring;
1582 ring->get_seqno = gen8_get_seqno;
1583 ring->set_seqno = gen8_set_seqno;
1584 ring->emit_request = gen8_emit_request;
1585 ring->emit_flush = gen8_emit_flush;
1586 ring->irq_get = gen8_logical_ring_get_irq;
1587 ring->irq_put = gen8_logical_ring_put_irq;
1588 ring->emit_bb_start = gen8_emit_bb_start;
1590 return logical_ring_init(dev, ring);
1593 static int logical_vebox_ring_init(struct drm_device *dev)
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1598 ring->name = "video enhancement ring";
1600 ring->mmio_base = VEBOX_RING_BASE;
1601 ring->irq_enable_mask =
1602 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1603 ring->irq_keep_mask =
1604 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1606 ring->init_hw = gen8_init_common_ring;
1607 ring->get_seqno = gen8_get_seqno;
1608 ring->set_seqno = gen8_set_seqno;
1609 ring->emit_request = gen8_emit_request;
1610 ring->emit_flush = gen8_emit_flush;
1611 ring->irq_get = gen8_logical_ring_get_irq;
1612 ring->irq_put = gen8_logical_ring_put_irq;
1613 ring->emit_bb_start = gen8_emit_bb_start;
1615 return logical_ring_init(dev, ring);
1619 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1622 * This function inits the engines for an Execlists submission style (the equivalent in the
1623 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1624 * those engines that are present in the hardware.
1626 * Return: non-zero if the initialization failed.
1628 int intel_logical_rings_init(struct drm_device *dev)
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1633 ret = logical_render_ring_init(dev);
1638 ret = logical_bsd_ring_init(dev);
1640 goto cleanup_render_ring;
1644 ret = logical_blt_ring_init(dev);
1646 goto cleanup_bsd_ring;
1649 if (HAS_VEBOX(dev)) {
1650 ret = logical_vebox_ring_init(dev);
1652 goto cleanup_blt_ring;
1655 if (HAS_BSD2(dev)) {
1656 ret = logical_bsd2_ring_init(dev);
1658 goto cleanup_vebox_ring;
1661 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1663 goto cleanup_bsd2_ring;
1668 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1670 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1672 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1674 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1675 cleanup_render_ring:
1676 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1682 make_rpcs(struct drm_device *dev)
1687 * No explicit RPCS request is needed to ensure full
1688 * slice/subslice/EU enablement prior to Gen9.
1690 if (INTEL_INFO(dev)->gen < 9)
1694 * Starting in Gen9, render power gating can leave
1695 * slice/subslice/EU in a partially enabled state. We
1696 * must make an explicit request through RPCS for full
1699 if (INTEL_INFO(dev)->has_slice_pg) {
1700 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1701 rpcs |= INTEL_INFO(dev)->slice_total <<
1702 GEN8_RPCS_S_CNT_SHIFT;
1703 rpcs |= GEN8_RPCS_ENABLE;
1706 if (INTEL_INFO(dev)->has_subslice_pg) {
1707 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1708 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
1709 GEN8_RPCS_SS_CNT_SHIFT;
1710 rpcs |= GEN8_RPCS_ENABLE;
1713 if (INTEL_INFO(dev)->has_eu_pg) {
1714 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
1715 GEN8_RPCS_EU_MIN_SHIFT;
1716 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
1717 GEN8_RPCS_EU_MAX_SHIFT;
1718 rpcs |= GEN8_RPCS_ENABLE;
1725 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1726 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1728 struct drm_device *dev = ring->dev;
1729 struct drm_i915_private *dev_priv = dev->dev_private;
1730 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1732 uint32_t *reg_state;
1736 ppgtt = dev_priv->mm.aliasing_ppgtt;
1738 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1740 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1744 ret = i915_gem_object_get_pages(ctx_obj);
1746 DRM_DEBUG_DRIVER("Could not get object pages\n");
1750 i915_gem_object_pin_pages(ctx_obj);
1752 /* The second page of the context object contains some fields which must
1753 * be set up prior to the first execution. */
1754 page = i915_gem_object_get_page(ctx_obj, 1);
1755 reg_state = kmap_atomic(page);
1757 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1758 * commands followed by (reg, value) pairs. The values we are setting here are
1759 * only for the first context restore: on a subsequent save, the GPU will
1760 * recreate this batchbuffer with new values (including all the missing
1761 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1762 if (ring->id == RCS)
1763 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1765 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1766 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1767 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1768 reg_state[CTX_CONTEXT_CONTROL+1] =
1769 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
1770 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
1771 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1772 reg_state[CTX_RING_HEAD+1] = 0;
1773 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1774 reg_state[CTX_RING_TAIL+1] = 0;
1775 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1776 /* Ring buffer start address is not known until the buffer is pinned.
1777 * It is written to the context image in execlists_update_context()
1779 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1780 reg_state[CTX_RING_BUFFER_CONTROL+1] =
1781 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1782 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1783 reg_state[CTX_BB_HEAD_U+1] = 0;
1784 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1785 reg_state[CTX_BB_HEAD_L+1] = 0;
1786 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1787 reg_state[CTX_BB_STATE+1] = (1<<5);
1788 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1789 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1790 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1791 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1792 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1793 reg_state[CTX_SECOND_BB_STATE+1] = 0;
1794 if (ring->id == RCS) {
1795 /* TODO: according to BSpec, the register state context
1796 * for CHV does not have these. OTOH, these registers do
1797 * exist in CHV. I'm waiting for a clarification */
1798 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1799 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1800 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1801 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1802 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1803 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1805 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1806 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1807 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1808 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1809 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1810 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1811 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1812 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1813 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1814 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1815 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1816 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1817 reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[3]->daddr);
1818 reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[3]->daddr);
1819 reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[2]->daddr);
1820 reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[2]->daddr);
1821 reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[1]->daddr);
1822 reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[1]->daddr);
1823 reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[0]->daddr);
1824 reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[0]->daddr);
1825 if (ring->id == RCS) {
1826 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1827 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
1828 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
1831 kunmap_atomic(reg_state);
1834 set_page_dirty(page);
1835 i915_gem_object_unpin_pages(ctx_obj);
1841 * intel_lr_context_free() - free the LRC specific bits of a context
1842 * @ctx: the LR context to free.
1844 * The real context freeing is done in i915_gem_context_free: this only
1845 * takes care of the bits that are LRC related: the per-engine backing
1846 * objects and the logical ringbuffer.
1848 void intel_lr_context_free(struct intel_context *ctx)
1852 for (i = 0; i < I915_NUM_RINGS; i++) {
1853 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1856 struct intel_ringbuffer *ringbuf =
1857 ctx->engine[i].ringbuf;
1858 struct intel_engine_cs *ring = ringbuf->ring;
1860 if (ctx == ring->default_context) {
1861 intel_unpin_ringbuffer_obj(ringbuf);
1862 i915_gem_object_ggtt_unpin(ctx_obj);
1864 WARN_ON(ctx->engine[ring->id].pin_count);
1865 intel_destroy_ringbuffer_obj(ringbuf);
1867 drm_gem_object_unreference(&ctx_obj->base);
1872 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1876 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
1880 if (INTEL_INFO(ring->dev)->gen >= 9)
1881 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
1883 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1889 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1896 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
1897 struct drm_i915_gem_object *default_ctx_obj)
1899 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1901 /* The status page is offset 0 from the default context object
1903 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
1904 ring->status_page.page_addr =
1905 kmap(sg_page(default_ctx_obj->pages->sgl));
1906 ring->status_page.obj = default_ctx_obj;
1908 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1909 (u32)ring->status_page.gfx_addr);
1910 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1914 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1915 * @ctx: LR context to create.
1916 * @ring: engine to be used with the context.
1918 * This function can be called more than once, with different engines, if we plan
1919 * to use the context with them. The context backing objects and the ringbuffers
1920 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1921 * the creation is a deferred call: it's better to make sure first that we need to use
1922 * a given ring with the context.
1924 * Return: non-zero on error.
1926 int intel_lr_context_deferred_create(struct intel_context *ctx,
1927 struct intel_engine_cs *ring)
1929 const bool is_global_default_ctx = (ctx == ring->default_context);
1930 struct drm_device *dev = ring->dev;
1931 struct drm_i915_gem_object *ctx_obj;
1932 uint32_t context_size;
1933 struct intel_ringbuffer *ringbuf;
1936 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1937 WARN_ON(ctx->engine[ring->id].state);
1939 context_size = round_up(get_lr_context_size(ring), 4096);
1941 ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
1942 if (IS_ERR(ctx_obj)) {
1943 ret = PTR_ERR(ctx_obj);
1944 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
1948 if (is_global_default_ctx) {
1949 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1951 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1953 drm_gem_object_unreference(&ctx_obj->base);
1958 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1960 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1963 goto error_unpin_ctx;
1966 ringbuf->ring = ring;
1968 ringbuf->size = 32 * PAGE_SIZE;
1969 ringbuf->effective_size = ringbuf->size;
1972 ringbuf->last_retired_head = -1;
1973 intel_ring_update_space(ringbuf);
1975 if (ringbuf->obj == NULL) {
1976 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1979 "Failed to allocate ringbuffer obj %s: %d\n",
1981 goto error_free_rbuf;
1984 if (is_global_default_ctx) {
1985 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1988 "Failed to pin and map ringbuffer %s: %d\n",
1990 goto error_destroy_rbuf;
1996 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1998 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2002 ctx->engine[ring->id].ringbuf = ringbuf;
2003 ctx->engine[ring->id].state = ctx_obj;
2005 if (ctx == ring->default_context)
2006 lrc_setup_hardware_status_page(ring, ctx_obj);
2007 else if (ring->id == RCS && !ctx->rcs_initialized) {
2008 if (ring->init_context) {
2009 ret = ring->init_context(ring, ctx);
2011 DRM_ERROR("ring init context: %d\n", ret);
2012 ctx->engine[ring->id].ringbuf = NULL;
2013 ctx->engine[ring->id].state = NULL;
2018 ctx->rcs_initialized = true;
2024 if (is_global_default_ctx)
2025 intel_unpin_ringbuffer_obj(ringbuf);
2027 intel_destroy_ringbuffer_obj(ringbuf);
2031 if (is_global_default_ctx)
2032 i915_gem_object_ggtt_unpin(ctx_obj);
2033 drm_gem_object_unreference(&ctx_obj->base);
2037 void intel_lr_context_reset(struct drm_device *dev,
2038 struct intel_context *ctx)
2040 struct drm_i915_private *dev_priv = dev->dev_private;
2041 struct intel_engine_cs *ring;
2044 for_each_ring(ring, dev_priv, i) {
2045 struct drm_i915_gem_object *ctx_obj =
2046 ctx->engine[ring->id].state;
2047 struct intel_ringbuffer *ringbuf =
2048 ctx->engine[ring->id].ringbuf;
2049 uint32_t *reg_state;
2055 if (i915_gem_object_get_pages(ctx_obj)) {
2056 WARN(1, "Failed get_pages for context obj\n");
2059 page = i915_gem_object_get_page(ctx_obj, 1);
2060 reg_state = kmap_atomic(page);
2062 reg_state[CTX_RING_HEAD+1] = 0;
2063 reg_state[CTX_RING_TAIL+1] = 0;
2065 kunmap_atomic(reg_state);