kernel/drivers/gpu/drm/i915/i915_suspend.c

   1 /*
   2  *
   3  * Copyright 2008 (c) Intel Corporation
   4  *   Jesse Barnes <jbarnes@virtuousgeek.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include <drm/drmP.h>
  28 #include <drm/i915_drm.h>
  29 #include "intel_drv.h"
  30 #include "i915_reg.h"
  31
  32 static void i915_save_display(struct drm_device *dev)
  33 {
  34         struct drm_i915_private *dev_priv = dev->dev_private;
  35
  36         /* Display arbitration control */
  37         if (INTEL_INFO(dev)->gen <= 4)
  38                 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
  39
  40         /* LVDS state */
  41         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  42                 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
  43         else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
  44                 dev_priv->regfile.saveLVDS = I915_READ(LVDS);
  45
  46         /* Panel power sequencer */
  47         if (HAS_PCH_SPLIT(dev)) {
  48                 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
  49                 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
  50                 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
  51                 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
  52         } else if (!IS_VALLEYVIEW(dev)) {
  53                 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
  54                 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
  55                 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
  56                 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
  57         }
  58
  59         /* save FBC interval */
  60         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
  61                 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
  62 }
  63
  64 static void i915_restore_display(struct drm_device *dev)
  65 {
  66         struct drm_i915_private *dev_priv = dev->dev_private;
  67         u32 mask = 0xffffffff;
  68
  69         /* Display arbitration */
  70         if (INTEL_INFO(dev)->gen <= 4)
  71                 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
  72
  73         mask = ~LVDS_PORT_EN;
  74
  75         /* LVDS state */
  76         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  77                 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
  78         else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
  79                 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
  80
  81         /* Panel power sequencer */
  82         if (HAS_PCH_SPLIT(dev)) {
  83                 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
  84                 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
  85                 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
  86                 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
  87         } else if (!IS_VALLEYVIEW(dev)) {
  88                 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
  89                 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
  90                 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
  91                 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
  92         }
  93
  94         /* only restore FBC info on the platform that supports FBC*/
  95         intel_fbc_disable(dev);
  96
  97         /* restore FBC interval */
  98         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
  99                 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
 100
 101         i915_redisable_vga(dev);
 102 }
 103
 104 int i915_save_state(struct drm_device *dev)
 105 {
 106         struct drm_i915_private *dev_priv = dev->dev_private;
 107         int i;
 108
 109         mutex_lock(&dev->struct_mutex);
 110
 111         i915_save_display(dev);
 112
 113         if (IS_GEN4(dev))
 114                 pci_read_config_word(dev->pdev, GCDGMBUS,
 115                                      &dev_priv->regfile.saveGCDGMBUS);
 116
 117         /* Cache mode state */
 118         if (INTEL_INFO(dev)->gen < 7)
 119                 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 120
 121         /* Memory Arbitration state */
 122         dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 123
 124         /* Scratch space */
 125         for (i = 0; i < 16; i++) {
 126                 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
 127                 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
 128         }
 129         for (i = 0; i < 3; i++)
 130                 dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 131
 132         mutex_unlock(&dev->struct_mutex);
 133
 134         return 0;
 135 }
 136
 137 int i915_restore_state(struct drm_device *dev)
 138 {
 139         struct drm_i915_private *dev_priv = dev->dev_private;
 140         int i;
 141
 142         mutex_lock(&dev->struct_mutex);
 143
 144         i915_gem_restore_fences(dev);
 145
 146         if (IS_GEN4(dev))
 147                 pci_write_config_word(dev->pdev, GCDGMBUS,
 148                                       dev_priv->regfile.saveGCDGMBUS);
 149         i915_restore_display(dev);
 150
 151         /* Cache mode state */
 152         if (INTEL_INFO(dev)->gen < 7)
 153                 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
 154                            0xffff0000);
 155
 156         /* Memory arbitration state */
 157         I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
 158
 159         for (i = 0; i < 16; i++) {
 160                 I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
 161                 I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
 162         }
 163         for (i = 0; i < 3; i++)
 164                 I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
 165
 166         mutex_unlock(&dev->struct_mutex);
 167
 168         intel_i2c_reset(dev);
 169
 170         return 0;
 171 }